200828803 九、發明說明： 【發明所屬之技術領域】 本發明涉及一種時序改善電路，尤指一種可使主機 板上晶片組輸出控制電腦休眠狀態之信號時序與輸入 輸出控制晶片内控制電腦休眠狀態信號時序一致之時 序改善電路。 【先前技術】 晶片組係主機板之重要組成部分，幾乎影響著主機 板之全部功能。當電腦進入休眠狀態時，要求晶片組輸 出控制休眠狀態之信號時序與輸入輸出控制晶片中控 制休眠狀態之信號時序相一致，然而，由於生產晶片組 之廠商與生產輸入輸出控制晶片之廠商會不同，難免存 在主機板上晶片組之信號時序與輸入輸出控制晶片之 信號時序不能相容之狀況，而影響電腦正常運行。 【發明内容】 鑒於以上内容，有必要提供一種可使主機板上晶片 組輸出控制電腦休眠狀態之信號時序與輸入輸出控制晶 片内控制休眠狀態之信號時序一致之時序改善電路。 一種時序改善電路，可將一晶片組輸出控制電腦休 眠狀態之控制信號轉換為與一輸入輸出控制晶片中用於 控制電腦休眠狀態之第一休眠狀態控制信號及第二休眠 狀態控制信號時序一致之信號，該時序改善電路包括一 控制電路及一開關電路，該控制電路包括一高通低斷之 第一開關元件及一高通低斷之第二開關元件，該第一開 200828803 關元件之輸入端與一節點相連，該節點電壓在開機時為 高電平，關機及休眠時為低電平，該第一開關元件之輸 出端分別與該晶片組輸出之控制信號端及該第二開關元 件之輸入端相連，該第二開關元件之輸出端與該輸入輸 出控制晶片相連，該開關電路之輸入端與該節點相連， 該開關電路之輸出端與該輸入輸出控制晶片相連並輸出 一開機時為高電平、關機與休眠時為低電平之信號至該 輸入輸出控制晶片。 相對習知技術，本發明時序改善電路借助該主機板 輔助電源端、該電源輸入端及該電源啟動信號端，將晶 片組輸出之用於控制電腦休眠狀態之控制信號轉換為與 輸入輸出控制晶片内用於控制電腦休眠狀態之第一休眠 狀態控制信號及第二休眠狀態控制信號時序一致之兩信 號，使該晶片組與該輸入輸出控制晶片之信號時序相 容，保證電腦能夠正常運行。 【實施方式】 請參閱圖1，本發明時序改善電路用於當電腦進入休 眠狀態時，可將一晶片組輸出之用於控制電腦休眠狀態 之控制信號S3’轉換為一信號31及一信號51，使該兩 信號31、51與一輸入輸出控制晶片10内之第一休眠狀 態控制信號S3及第二休眠狀態控制信號S4之時序一 致。該第一休眠狀態控制信號S3用於將電腦運行之程式 保存於記憶體中，其在電腦關機時處於低電平，開機時 處於高電平，第一休眠狀態及第二休眠狀態時處於低電 200828803 平’該第二休眠狀態控制信號S4用於將電腦運行之程式 保存於硬碟機中，其在電腦關機時處於低電平，開機及 第一休眠狀態時處於高電平，第二休眠狀態時處於低電 平；該控制信號S3，在電腦關機及開機時處於高電平， 第一休眠狀態時處於低電平，第二休眠狀態時處於高電 平。 該時序改善電路包括一主機板輔助電源端1〇〇、_ 電源輪入端300、一電源啟動信號端500、一比較器20、 一開關元件、一開關電路3〇、一控制電路50及該控制 信號S3’輸入端。該控制電路50包括一高通低斷之第 一開關元件及一高通低斷之第二開關元件，該開關電路 30包括一第三開關元件及一第四開關元件。在本實施方 式中，該開關元件為一第一場效應電晶體Q1，該第一開 關元件及該第二開關元件為一場效應電晶體Q4及一電 晶體Q5，該第一開關元件之輸入端及輸出端分別為該場 效應電晶體Q4之閘極及汲極，該第二開關元件之輪入 端及輪出端分別為該電晶體Q5之基極及集極，第三開 關元件及第四開關元件分別為一第二場效應電晶體Q2 及一第三場效應電晶體Q3。 該主機板輔助電源端1〇〇與一電阻R2之一端相 連，該電阻R2之另一端藉由一節點21與比較器2〇之 反向輪入端相連，該電源輸入端3〇〇與一電阻R3之一 端相連，該電阻R3之另一端藉由一節點23與比較器20 之正向輸入端相連，該節點21藉由一電阻R1接地，該 200828803 節點23藉由一電阻R4接地，該節點23還藉由一電容 C1接地。該比較器20之其中一端接一電源供電端700， 一端接地，其輸出端藉由一節點11連接該第一場效應電 晶體Q1之汲極，該第一場效應電晶體Q1之閘極與該電 源啟動信號端500相連，其閘極還藉由一電容C2接地， 其源極接地。該節點11藉由一電阻R5與該電源供電端 700相連，該節點11與該開關電路30中第二場效應電 晶體Q2之閘極相連，該第二場效應電晶體Q2之汲極藉 由一電阻R6連接該電源供電端700，其源極接地。該第 三場效應電晶體Q3之閘極與該第二場效應電晶體Q2之 汲極相連，該第三場效應電晶體Q3之汲極藉由一電阻 R7連接該電源供電端700，其源極接地。該第三場效應 電晶體Q3之汲極即該信號31之輸出端與該輸入輸出控 制晶片10之第一休眠狀態控制信號S3端相連。 該控制信號S3’端藉由一電阻R8與該控制電路50 中場效應電晶體Q4之汲極相連，該場效應電晶體Q4之 閘極連接該節點11，其源極接地。該電晶體Q5之基極 與該場效應電晶體Q4之汲極相連，該電晶體Q5之集極 藉由一電阻R9連接該電源供電端，其射極接地。該電 晶體Q5之集極即該信號51之輸出端與該輸入輸出控制 晶片10之第二休眠狀態控制信號S4端相連。 請參閱圖2,圖2為該輸入輸出控制晶片10中第一 休眠狀態控制信號S3及第二休眠狀態控制信號S4之時 序圖。當電腦處於關機狀態時，該第一休眠狀態控制信 11 200828803 號S3及該第二休眠狀態控制信號S4均為低電平；當電 腦開機後，該第一休眠狀態控制信號s3及該第二休眠狀 悲控制信號S4變為高電平；當電腦進入第一休眠狀態 時’該第一休眠狀態控制信號S3變為低電平，該第二休 眠狀態控制信號S4仍然保持高電平；當電腦進入第二休 眠狀態時，該第一休眠狀態控制信號S3保持低電平不 變’該第二休眠狀態控制信號S4變為低電平。 請繼續參閱圖3，圖3為該晶片組輸出之控制信號 S3’時序圖，當電腦處於關機狀態時，該控制信號S3’ 為高電平；當電腦開機後，該控制信號S3’保持高電平 不變；當電腦進入第一休眠狀態時，該控制信號S3，變 為低電平；當電腦進入第二休眠狀態時，該控制信號 S3’變為高電平。 下面詳細介紹本發明時序改善電路之工作過程。 該主機板輔助電源端1〇〇輸入+5V電壓至主機板， 用於給主機板上元件供電，該電源輸入端300輸入+ 12V 主電壓供電腦運行，當關機時，該主機板輔助電源端100 及該電源輸入端300均為低電平輸入，因此該節點11 之電壓為一低電平，只有當開機時，待該節點23之電壓 高於該節點21之電壓時，該節點11之電壓才為一高電 平。該電源啟動信號端500之信號為一低電平有效信 號，即當電腦處於開機狀態時，該電源啟動信號端5〇〇 為一低電平輸入，當電腦處於關機及休眠狀態時，該電 源啟動信號端500為一高電平輸入。 12 200828803 當電腦處於關機狀態時，該電源啟動信號端500為 一高電平輸入，該第一場效應電晶體Q1導通，其汲極 輸出低電平，因此該節點11之電壓為一低電平，該第二 場效應電晶體Q2截止，其汲極輸出高電平至該第三場 效應電晶體Q3之閘極，該第三場效應電晶體Q3導通， 其汲極輸出低電平，即該信號31為一低電平；該控制信 號S3’為一高電平，該節點11之電壓為一低電平，該 場效應電晶體Q4截止，其汲極輸出一高電平至該晶體 管Q5之基極，因此該電晶體Q5導通，其集極輸出低電 平，即該信號51為一低電平。 當電腦處於開機狀態時，該主機板辅助電源端100 及該電源輸入端300均為高電平輸入，該電源啟動信號 端500為一低電平輸入，當該節點23之電壓高於該節點 21之電壓時，該比較器20輸出一高電平，即該節點11 之電壓為一高電平，由於該第一場效應電晶體Q1截止， 該節點11之高電平輸入至該第二場效應電晶體Q2之閘 極，該第二場效應電晶體Q2導通，其汲極輸出低電平 至該第三場效應電晶體Q3之閘極，該第三場效應電晶 體Q3截止，其汲極輸出高電平，即該信號31為一高電 平；由於該節點11之電壓為一高電平，因此該場效應電 晶體Q4導通，其汲極輸出低電平至該電晶體Q5之基 極，該電晶體Q5截止，其集極輸出高電平，即該信號 51為一高電平。 當電腦處於第一休眠狀態時，該電源輸入端300輸 13 200828803 入一低電平，該節點π之電壓為低電平，因此該第三場 效應電晶體Q3之》及極輸出低電平’即該信號31為一低 電平；由於該控制信號S3’為低電平，該電晶體Q5截 止，其集極輸出高電平，即該信號51為一高電平。 當電腦處於第二休眠狀態時，該電源輸入端300輸 入一低電平，該節點11之電壓為低電平，因此該第三場 效應電晶體Q3之没極輸出低電平，即該信號31為一低 電平；由於該控制信號S3’為高電平，且該場效應電晶 體Q4截止，因此該電晶體Q5導通，其集極輸出低電平， 即該信號51為一低電平。 在本發明時序改善電路中，可藉由其他電路來實現 該信號31之時序與該第一休眠狀態控制信號S3之時序 一致。 本發明時序改善電路借助該主機板輔助電源端 100、該電源輸入端300及該電源啟動信號端500，將晶 片組輸出之控制信號S3’轉換為與該輸入輸出控制晶 片10内用於控制電腦休眠狀態之第一休眠狀態控制信 號S3及第二休眠狀態控制信號S4時序一致之兩信號 31、51，使該晶片組與該輸入輸出控制晶片10之時序相 容，則電腦能夠正常運行。 【圖式簡單說明】 圖1為本發明時序改善電路較佳實施方式之電路 圖。 圖2為圖1中輸入輸出控制晶片之信號時序圖。 14 200828803 圖3為一晶片組輪出之控制信號時序圖。 【主要元件符號說明】 輸入輸出控制晶片 10節點 11 比較器 20 即點 23 信號 31 信號 51 電源輸入端 300 電源供電端 700 電阻 R2 電阻 R4 電阻 R6 電阻 R8 電容 C1 第一場效應電晶體 Q1 第三場效應電晶體 Q3 電晶體 Q5 第二休眠狀態控制信號 S4 節點 21 開關電路 30 控制電路 50 主機板辅助電源端 100 電源啟動信號端 500 電阻 R1 電阻 R3 電阻 R5 電阻 R7 電阻 R9 電容 C2 第二場效應電晶體 Q2 場效應電晶體 第一休眠狀態控制信號 S3 控制信號 ^ 15200828803 IX. Description of the Invention: [Technical Field] The present invention relates to a timing improvement circuit, and more particularly to a signal timing and an input/output control chip to control a computer sleep state signal on a chipset output on a motherboard. Timing-consistent timing improvement circuit. [Prior Art] The chipset is an important part of the motherboard, which affects almost all functions of the motherboard. When the computer enters the sleep state, the signal timing of the chipset output control sleep state is consistent with the signal timing of controlling the sleep state in the input/output control chip. However, since the manufacturer of the chipset is different from the manufacturer who manufactures the input/output control chip. It is inevitable that the signal timing of the chipset on the motherboard is incompatible with the signal timing of the input/output control chip, which affects the normal operation of the computer. SUMMARY OF THE INVENTION In view of the above, it is necessary to provide a timing improvement circuit that can match the signal timing of the chipset output on the motherboard to control the sleep state of the computer and the signal timing of the sleep control state in the input/output control wafer. A timing improving circuit capable of converting a control signal of a chipset output control computer sleep state into a timing corresponding to a first sleep state control signal and a second sleep state control signal for controlling a sleep state of an IC in an input/output control chip The timing improvement circuit includes a control circuit and a switch circuit, the control circuit includes a high-pass low-break first switch component and a high-pass low-break second switch component, and the first open 200828803 component input terminal A node is connected, the node voltage is high when the power is turned on, and is low when the power is turned off and when the sleep is low. The output end of the first switching element is respectively connected to the control signal end of the chip group and the input of the second switching element. The output end of the second switching element is connected to the input/output control chip, and the input end of the switch circuit is connected to the node, and the output end of the switch circuit is connected to the input/output control chip and outputs a high when the power is turned on. A low level signal at level, shutdown, and sleep to the input and output control chip. Compared with the prior art, the timing improvement circuit of the present invention converts the control signal outputted by the chipset for controlling the sleep state of the computer into the input and output control chip by means of the auxiliary power supply end of the motherboard, the power input end and the power start signal end. The two signals for controlling the sleep state of the first sleep state control signal and the second sleep state control signal of the computer sleep state are compatible with the signal timing of the chip set and the input/output control chip to ensure normal operation of the computer. [Embodiment] Please refer to FIG. 1. The timing improvement circuit of the present invention is configured to convert a control signal S3' outputted by a chipset for controlling a sleep state of a computer into a signal 31 and a signal 51 when the computer enters a sleep state. The timings of the two signals 31, 51 and the first sleep state control signal S3 and the second sleep state control signal S4 in the input/output control wafer 10 are matched. The first sleep state control signal S3 is used to save the program running in the computer in the memory, which is at a low level when the computer is turned off, at a high level when the computer is turned on, and at a low level in the first sleep state and the second sleep state. Electric 200828803 flat 'The second sleep state control signal S4 is used to save the computer running program in the hard disk machine, which is at a low level when the computer is turned off, and is at a high level when the computer is turned on and the first sleep state, second The sleep state is at a low level; the control signal S3 is at a high level when the computer is turned off and turned on, at a low level in the first sleep state, and at a high level in the second sleep state. The timing improvement circuit includes a motherboard auxiliary power terminal 1 , _ power wheel terminal 300 , a power source signal terminal 500 , a comparator 20 , a switching element , a switching circuit 3 , a control circuit 50 , and the like Control signal S3' input. The control circuit 50 includes a high-pass low-break first switching element and a high-pass low-break second switching element. The switching circuit 30 includes a third switching element and a fourth switching element. In this embodiment, the switching element is a first field effect transistor Q1, and the first switching element and the second switching element are a field effect transistor Q4 and a transistor Q5, and the input end of the first switching element And the output end is the gate and the drain of the field effect transistor Q4, respectively, and the wheel end and the wheel end of the second switching element are respectively the base and the collector of the transistor Q5, and the third switching element and the first The four switching elements are a second field effect transistor Q2 and a third field effect transistor Q3, respectively. The auxiliary power terminal 1 of the motherboard is connected to one end of a resistor R2, and the other end of the resistor R2 is connected to the reverse wheel terminal of the comparator 2 through a node 21, and the power input terminal 3 One end of the resistor R3 is connected, and the other end of the resistor R3 is connected to the forward input terminal of the comparator 20 by a node 23, the node 21 is grounded by a resistor R1, and the node 2828 is grounded by a resistor R4. Node 23 is also grounded by a capacitor C1. One end of the comparator 20 is connected to a power supply terminal 700, one end of which is grounded, and the output end of which is connected to the drain of the first field effect transistor Q1 by a node 11, and the gate of the first field effect transistor Q1 is The power start signal terminal 500 is connected, and its gate is also grounded by a capacitor C2, and its source is grounded. The node 11 is connected to the power supply terminal 700 via a resistor R5. The node 11 is connected to the gate of the second field effect transistor Q2 of the switch circuit 30. The drain of the second field effect transistor Q2 is A resistor R6 is connected to the power supply terminal 700, and its source is grounded. The gate of the third field effect transistor Q3 is connected to the drain of the second field effect transistor Q2, and the drain of the third field effect transistor Q3 is connected to the power supply terminal 700 by a resistor R7. Extremely grounded. The drain of the third field effect transistor Q3, i.e., the output of the signal 31, is coupled to the first sleep state control signal S3 of the input and output control chip 10. The control signal S3' is connected to the drain of the field effect transistor Q4 in the control circuit 50 via a resistor R8. The gate of the field effect transistor Q4 is connected to the node 11, and its source is grounded. The base of the transistor Q5 is connected to the drain of the field effect transistor Q4. The collector of the transistor Q5 is connected to the power supply terminal by a resistor R9, and the emitter is grounded. The collector of the transistor Q5, i.e., the output of the signal 51, is coupled to the second sleep state control signal S4 of the input and output control chip 10. Referring to FIG. 2, FIG. 2 is a timing chart of the first sleep state control signal S3 and the second sleep state control signal S4 in the input/output control chip 10. When the computer is in the off state, the first sleep state control signal 11 200828803 S3 and the second sleep state control signal S4 are both low; when the computer is turned on, the first sleep state control signal s3 and the second The sleepy sad control signal S4 becomes a high level; when the computer enters the first sleep state, the first sleep state control signal S3 becomes a low level, and the second sleep state control signal S4 remains at a high level; When the computer enters the second sleep state, the first sleep state control signal S3 remains at a low level. The second sleep state control signal S4 becomes a low level. Please continue to refer to FIG. 3, which is a timing diagram of the control signal S3' outputted by the chipset. When the computer is in the off state, the control signal S3' is high; when the computer is turned on, the control signal S3' remains high. The level is unchanged; when the computer enters the first sleep state, the control signal S3 changes to a low level; when the computer enters the second sleep state, the control signal S3' becomes a high level. The operation of the timing improvement circuit of the present invention will be described in detail below. The auxiliary power supply terminal of the motherboard inputs +5V voltage to the motherboard, and is used for supplying power to the components on the motherboard. The power input terminal 300 inputs +12V main voltage for the computer to operate, and when the power is turned off, the auxiliary power terminal of the motherboard 100 and the power input terminal 300 are both low level inputs, so the voltage of the node 11 is a low level, and only when the voltage of the node 23 is higher than the voltage of the node 21 when the power is turned on, the node 11 The voltage is a high level. The signal of the power-on signal terminal 500 is an active-low signal, that is, when the computer is turned on, the power-on signal terminal 5 is a low-level input, and when the computer is in a shutdown state and a sleep state, the power source is The enable signal terminal 500 is a high level input. 12 200828803 When the computer is in the off state, the power start signal terminal 500 is a high level input, the first field effect transistor Q1 is turned on, and the drain output is low level, so the voltage of the node 11 is a low power. Ping, the second field effect transistor Q2 is turned off, and the drain thereof outputs a high level to the gate of the third field effect transistor Q3, the third field effect transistor Q3 is turned on, and the drain of the third field effect transistor is low level. That is, the signal 31 is a low level; the control signal S3' is a high level, the voltage of the node 11 is a low level, the field effect transistor Q4 is turned off, and the drain output is a high level to the The base of the transistor Q5, so that the transistor Q5 is turned on, and its collector outputs a low level, that is, the signal 51 is a low level. When the computer is in the power-on state, the motherboard auxiliary power terminal 100 and the power input terminal 300 are both high-level inputs, and the power-on signal terminal 500 is a low-level input, when the voltage of the node 23 is higher than the node. When the voltage of 21 is 21, the comparator 20 outputs a high level, that is, the voltage of the node 11 is a high level. Since the first field effect transistor Q1 is turned off, the high level of the node 11 is input to the second The gate of the field effect transistor Q2, the second field effect transistor Q2 is turned on, and the drain thereof outputs a low level to the gate of the third field effect transistor Q3, and the third field effect transistor Q3 is turned off. The drain output is high, that is, the signal 31 is a high level; since the voltage of the node 11 is a high level, the field effect transistor Q4 is turned on, and the drain output low level to the transistor Q5. The base of the transistor Q5 is turned off, and its collector output is high, that is, the signal 51 is at a high level. When the computer is in the first sleep state, the power input terminal 300 inputs 13 200828803 into a low level, and the voltage of the node π is a low level, so the third field effect transistor Q3 and the pole output low level That is, the signal 31 is a low level; since the control signal S3' is at a low level, the transistor Q5 is turned off, and its collector outputs a high level, that is, the signal 51 is at a high level. When the computer is in the second sleep state, the power input terminal 300 inputs a low level, and the voltage of the node 11 is a low level, so the third field effect transistor Q3 has a low level output low level, that is, the signal 31 is a low level; since the control signal S3' is at a high level, and the field effect transistor Q4 is turned off, the transistor Q5 is turned on, and its collector outputs a low level, that is, the signal 51 is a low power. level. In the timing improvement circuit of the present invention, the timing of the signal 31 can be made coincident with the timing of the first sleep state control signal S3 by other circuits. The timing improvement circuit of the present invention converts the control signal S3' outputted by the chipset into and out of the input/output control chip 10 by using the motherboard auxiliary power supply terminal 100, the power input terminal 300, and the power activation signal terminal 500. The two signals 31, 51 in which the first sleep state control signal S3 and the second sleep state control signal S4 in the sleep state coincide with each other, so that the timing of the chip set and the input/output control chip 10 are compatible, the computer can operate normally. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram of a preferred embodiment of a timing improving circuit of the present invention. 2 is a signal timing diagram of the input/output control chip of FIG. 1. 14 200828803 Figure 3 is a timing diagram of the control signals for a chipset turn-off. [Main component symbol description] Input/output control chip 10 node 11 Comparator 20 point 23 signal 31 signal 51 power input terminal 300 power supply terminal 700 resistor R2 resistor R4 resistor R6 resistor R8 capacitor C1 first field effect transistor Q1 third Field effect transistor Q3 transistor Q5 second sleep state control signal S4 node 21 switch circuit 30 control circuit 50 motherboard auxiliary power terminal 100 power start signal terminal 500 resistor R1 resistor R3 resistor R5 resistor R7 resistor R9 capacitor C2 second field effect Transistor Q2 field effect transistor first sleep state control signal S3 control signal ^ 15