TWI421910B - 半導體元件基板、其製造方法及半導體裝置 - Google Patents

半導體元件基板、其製造方法及半導體裝置 Download PDF

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TWI421910B
TWI421910B TW99108277A TW99108277A TWI421910B TW I421910 B TWI421910 B TW I421910B TW 99108277 A TW99108277 A TW 99108277A TW 99108277 A TW99108277 A TW 99108277A TW I421910 B TWI421910 B TW I421910B
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Taiwan
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metal plate
semiconductor element
outer frame
connection terminal
frame portion
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TW99108277A
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TW201044441A (en
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Junko Toda
Susumu Maniwa
Takehito Tsukamoto
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Toppan Printing Co Ltd
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Publication of TW201044441A publication Critical patent/TW201044441A/zh
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Description

半導體元件基板、其製造方法及半導體裝置
本發明係關於適合於半導體元件之安裝的半導體封裝基板的技術。尤其是關於半導體元件基板、半導體元件基板之製造方法、及使用半導體元件基板的半導體裝置。
在使用QFP(Quad Flat Package)所代表之導線架的半導體封裝體中，用來與印刷電路板連接之外部導線，係配置於半導體封裝體之側面。導線架係於金屬板之兩面形成所需的光阻圖案，從兩面進行蝕刻。藉此，可獲得作為半導體元件搭載部與半導體元件電極之連接部的內部導線、外部導線及固定此等要素之外框部。
另外，除蝕刻加工法以外，導線架還可藉加壓之沖孔加工法來獲得。作為半導體封裝體之組裝步驟，係在將半導體元件黏晶於半導體元件搭載部上之後，使用金線等將半導體元件之電極與內部導線電性連接。然後，對包含內部導線部的半導體元件的附近進行樹脂密封，裁切外框部，並根據需要對外部導線進行彎曲加工。
如此，設置於側面之外部導線，從微細化之加工能力的角度考慮，在30mm方形程度之封裝體尺寸中，其極限為200～300個接腳。
近年來，隨著半導體元件之電極數的增加，在側面具有外部導線之導線架型的半導體封裝體中，端子數已變得無法因應，一部分逐漸替換成與BGA(Ball Grid Aray)或LGA(Land Grid Aray)型等的印刷電路板連接之外部連接端子在封裝體基板底面配置成陣列狀的半導體封裝體。使用於此等封裝體之基板，一般係於兩面貼銅之玻璃環氧基板上以鑚頭開孔，並對孔內進行電鍍使其導通，在一面形成用來與半導體元件之電極連接的端子，而在另一面形成呈陣列狀排列之外部連接端子。
然而，此等基板之製造，其步驟複雜，成本高，並且於基板內之配線連接使用電鍍，所以，與導線架型之封裝體比較，具有可靠性差的問題。
針對此情況，揭示一種利用從兩面蝕刻導線架的步驟，而使用導線架的BGA型半導體封裝體構造(例如，參照專利文獻1)。
這是在改變表面和背面之光阻圖案，同時進行蝕刻或對單側進行蝕刻之後，於蝕刻面表層形成電鍍聚醯亞胺樹脂層後、或塗布預成型封裝樹脂後，從另一面施以蝕刻，藉此，於一面形成半導體元件電極之連接端子，於另一面形成陣列狀之外部連接端子的方法。
第11及第12圖顯示習知之半導體元件基板。半導體元件基板包含：配線110、外部連接端子111、外框部112、聚醯亞胺樹脂層116、半導體元件搭載部118及半導體元件電極連接端子119。如第11及第12圖所示，在BGA型之導線架中，當外部連接端子111之數量增加時，半導體元件電極連接端子119側的配線110的長度會變長。此配線110係將金屬板半蝕刻而製作者，其無論是寬度還是厚度均較小，在蝕刻以後之步驟中會產生折斷或彎曲，而有產率變得非常差的問題。
在專利文獻1中揭示有首先僅在外部連接端子111側進行半蝕刻，而於蝕刻面形成電鍍聚醯亞胺層後，以蝕刻形成半導體元件電極連接端子119側的方法。藉此，微細之配線110雖為薄膜，但被聚醯亞胺樹脂層116所支撐，可以避免導線架之製作時的配線之折斷或彎曲。
然而，於本構造之半導體元件基板上搭載半導體元件，並藉由引線接合來連接半導體元件電極與連接端子119時，連接端子119之下部成為中空，引線連接沒有著力點，而有產生連接不良，組裝產率明顯降低的問題。
在專利文獻1中推測，藉由取代電鍍聚醯亞胺層而充填預成型封裝樹脂，可某種程度地避免接合不良的問題。但是，當充填於凹部之預成型封裝樹脂硬化時，樹脂收縮，使得樹脂與外框部之密接力輸給樹脂之收縮力，而恐有產生剝離之問題。
(專利文獻)
[專利文獻1]特許第3642911號公報
本發明提供一種可因應半導體元件之電極數的增加，且可靠性高，並能穩定進行製作及半導體封裝體之組裝的半導體元件基板、其製造方法及半導體裝置。
本發明之第一態樣，係一種半導體元件基板之製造方法，其包含：形成第1光阻圖案的步驟，係用來於金屬板之第1面形成半導體元件搭載部、半導體元件電極連接端子、配線、外框部、及以使該外框部之四個角部與屬該金屬板的一部分之金屬片相連的方式貫通該金屬板之該第1面及不同於該第1面的第2面之狹縫；形成第2光阻圖案的步驟，係於該金屬板之該第2面形成外部連接端子、該外框部及該狹縫；以該金屬片與該外框部之四個角部相連的方式，藉由半蝕刻形成該狹縫之步驟；於該金屬板之該第2面形成複數個凹部的步驟；以不會進入該狹縫之方式朝該複數個凹部注入樹脂且使其硬化而形成樹脂層的步驟；及對該金屬板之該第1面進行蝕刻而形成該半導體元件搭載部、與該外部連接端子電性連接之該半導體元件電極連接端子及該外框部的步驟。
本發明之第二態樣，係一種半導體元件基板，其包含：金屬板；半導體元件搭載部，係形成於該金屬板之第1面；連接端子，係形成於該金屬板之該第1面，且與半導體元件電極連接；配線，係形成於該金屬板之該第1面；外框部，係形成於該金屬板；連結片，係連結該外框部之四個角部與該金屬板之一部分的金屬片；外部連接端子，係形成於不同於該金屬板之該第1面的第2面；複數個凹部，係形成於該金屬板之該第2面；及樹脂層，係充填於該複數個凹部內。
本發明之第三態樣，係一種半導體裝置，其包含半導體元件基板及半導體元件，其中該半導體元件基板具備：金屬板；半導體元件搭載部，係形成於該金屬板之該第1面；連接端子，係形成於該金屬板之該第1面，且與半導體元件電極連接；配線，係形成於該金屬板之該第1面；外框部，係形成於該金屬板；連結片，係連結作為該外框部之四個角部與該金屬板之一部分的金屬片；外部連接端子，係形成於不同於該金屬板之該第1面的第2面；複數個凹部，係形成於該金屬板之該第2面；及樹脂層，係充填於該複數個凹部內；而半導體元件係搭載於該半導體元件基板之該半導體元件搭載部，且與該半導體元件基板電性連接。
根據本發明，可將用來與印刷電路板連接之外部連接端子呈陣列狀地配置於半導體元件基板之整個背面，從而可因應半導體元件之多端子化。
另外，根據本發明，係主要以導線架製成之基板，不需使用電鍍配線，所以，可確保對熱應力之可靠性。又，根據本發明，在製作本基板時，不會發生配線之折斷或彎曲等的不良情形，在進行屬半導體封裝體組裝步驟的引線接合時，因設有狹縫，在預成型封裝樹脂充填於於凹部內後，可緩和硬化時產生之預成型封裝樹脂的應力，可防止預成型封裝樹脂從金屬板被剝離的情況。
因此，根據本發明，可因應半導體元件之電極數的增加，且可靠性高，並能穩定進行製作及半導體封裝體之組裝。
以下，參照圖面，詳細說明本發明之實施形態。
(實施形態1)
第1至第6圖為用來說明本發明之實施形態1的半導體元件基板之製造方法的步驟之示意剖視圖。
如第1及第2圖所示，在使用於導線架之金屬板1的上面形成光阻之第1光阻圖案2a，於金屬板1之下面形成第2光阻圖案2b。金屬板1上面之第1光阻圖案2a係用來於金屬板1上面形成半導體元件搭載部8、半導體元件電極連接端子9、配線10、外框部5及狹縫4者(參照第6圖)。狹縫4雖貫通於金屬板1之下面，但外框部5之周圍及金屬片17，至少以該外框部5之四個角部連接。
金屬板1下面之第2光阻圖案2b係用來於金屬板1下面形成外部連接端子11、外框部5及狹縫4者(參照第6圖)。狹縫4雖貫通於金屬板1之上面，但外框部5之周圍及金屬片17，至少以該外框部5之四個角部連接。
作為金屬板1，只要具有作為導線架之蝕刻加工性、機械強度、熱傳導性、膨脹係數等，則可使用任何材料，但普遍使用以42合金為代表之鐵一鎳系合金、或為了提高機械強度而添加各種金屬元素之銅系合金等。
其次，使用氯化亞鐵液等之溶解金屬板1的蝕刻液，從金屬板1之下面進行蝕刻，形成凹部3(參照第3圖)。因金屬板1之剩餘部最終會成為配線，所以，凹部3之深度係以在進行下一步之上面側的蝕刻時能形成微細配線的方式殘留約10 μm～50 μm的厚度較為適宜。
接著，以凹部3不會貫通之方式由覆膜進行被覆之後，從上面側進行蝕刻，藉以在外框部5形成狹縫4(參照第3圖)。藉由於外框部5形成狹縫4，於外框部5至少形成連結該外框部5之四個角部及該外框部5的金屬片17之連結片18(參照第7及第8圖)。
然後，將蝕刻加工後之金屬板1的上下面翻轉，於金屬板1之上面，以不會進入狹縫4之方式注入由液狀的預成型封裝樹脂構成之樹脂層6(參照第4圖)。
藉由於外框部5之周圍設置狹縫4，可緩和充填於凹部3內之由預成型封裝樹脂構成之樹脂層6在硬化時產生的應力，可防止樹脂層6從金屬板1剝離的情況。
又，在將金屬板1的上下面翻轉而返回原樣後，對金屬板1之上面進行蝕刻，形成有半導體搭載部8、半導體元件電極連接端子9及配線10，而製成半導體元件基板7(參照第5及第6圖)。
第7圖為顯示本發明之實施形態1的半導體元件基板之一部分的部分缺口俯視圖。第8圖為顯示本發明之實施形態1的半導體元件基板之其他部分的部分缺口俯視圖。如第7及第8圖所示，可將外部連接端子11配置成陣列狀，使得可因應半導體元件之多接腳化。另外，藉由形成狹縫4，外框部5之至少四個角部，成為藉由連結片18而與金屬片17相連的狀態。
(實施形態2)
以下，參照圖面，說明本發明之實施形態2。第9圖為用來說明本發明之實施形態2的半導體裝置之製造方法的步驟之示意剖視圖。第10圖為用來說明本發明之實施形態2的半導體裝置之製造方法的步驟之示意剖視圖。在本發明之實施形態2中，對與本發明之實施形態1相同的構成要素，賦予相同之元件符號，並省略其說明。
如第9圖所示，於半導體元件基板7之半導體元件搭載部8上，藉由黏晶材14搭載半導體元件12，半導體元件12係以金線13與半導體元件電極連接端子9連接。根據需要，於半導體元件電極連接端子9實施鎳-金電鍍、鍍錫、鍍銀或鎳-鈀-金電鍍。於進行引線接合時，將本導線架型之半導體元件基板7放置於加熱塊體上，一面加熱一面進行接合，但於半導體元件電極連接端子9之下部存在有位於同一水平面之樹脂層6，而不會成為中空構造，所以，可在不會引起接合不良的情況下進行組裝。
最後，如第10圖所示，藉由轉注成型或接合將半導體元件基板7側密封，以金剛石刀片等使外框部5分離而形成小片化。若為BGA型的話，將銲球搭載於外部連接端子11，可獲得使用半導體元件基板7之半導體裝置(半導體封裝體)。
(實施例1)
其次，參照圖面，詳細說明本發明之實施例1。本發明之實施例1，係以製造LGA(Land Grid Aray)型之半導體元件基板為例進行說明者。
製造之LGA封裝體係尺寸為10mm之方形，於封裝體下面具有168接腳之陣列狀的外部連接端子11。
首先，如第1圖所示，準備寬度為150mm且厚度為200μm之長帶狀銅合金製金屬板1(古河電工製：EFTEC64T)。然後，如第2圖所示，於該金屬板1之兩面以滾筒式塗布器塗布厚度為5μm之光阻(東京應化(股)製：OFPR4000)後，在溫度90℃下進行預烘烤(pre-bake)。
其次，透過具有所需圖案之光罩，從兩面進行圖案曝光，然後，以1%之碳酸鈉水溶液進行顯像處理後，進行水洗及後烘烤(post-bake)，如第2圖所示，獲得第1光阻圖案2a及第2光阻圖案2b。
金屬板1上面(第1面)之第1光阻圖案2a，係用來形成半導體元件搭載部8、與半導體元件電極連接之連接端子9、配線10、外框部5及狹縫4者(參照第6圖)。狹縫4雖貫通於金屬板1之第2面，但外框部5之周圍及金屬片17，至少以該外框部5之四個角部連接。
金屬板1下面(第2面)之第2光阻圖案2b，係用來於金屬板1之第2面形成外部連接端子11、外框部5及狹縫4者(參照第6圖)。狹縫4雖貫通於金屬板1之第1面，但外框部5之周圍及金屬片17，至少以該外框部5之四個角部連接。
然後，在以背膜(back sheet)被覆並保護金屬板1之第1面側後(未圖示)，使用氯化亞鐵溶液，從金屬板之第2面進行第1次之蝕刻處理，將從第2面側之光阻圖案2b露出的金屬板1之部位減薄至厚度為30μm而形成凹部3(參照第3圖)。氯化亞鐵溶液之比重，在50℃之液溫下為1.38。
然後，在以凹部3不會貫通之方式利用覆膜(cover film)保護後(未圖示)，使用氯化亞鐵溶液進行第2次之蝕刻處理，形成貫穿至第1面的狹縫4(參照第3圖)。氯化亞鐵溶液之比重，在50℃之液溫下為1.38。
然後，將已蝕刻第2面之金屬板1於30℃、50g/L之過硫酸氨水溶液中浸漬5分鐘，使利用第1次及第2次之蝕刻處理所形成的蝕刻面的表面粗化(未圖示)。再將金屬板1浸漬於既定之氫氧化鈉水溶液系剝離液中，剝離第2面之光阻(未圖示)。
然後，在利用第1次及第2次之蝕刻處理所形成的金屬板1之第2面，以不會進入狹縫4之部分的方式，注入液狀之熱硬化性樹脂(信越化學工業製SMC-376KF1)，在180℃之溫度下進行3小時的主硬化，形成樹脂層6(參照第4圖)。
熱硬化樹脂之樹脂層6的埋入性良好，並未觀察到有空隙等的不良情形。在外部連接端子11、外框部5未被蝕刻的面上，幾乎未殘留有熱硬化樹脂之樹脂層6，在兼用於表面洗淨的同時，在60℃之高錳酸鉀之鹼水溶液(40g/L之高錳酸鉀+20g/L之氫氧化鈉)中進行3分鐘左右之浸漬處理。
然後，在除去金屬板1之第1面側的背膜後，藉由氯化亞鐵溶液，從金屬板1之第1面側進行第3次之蝕刻處理，將從光阻圖案2a露出的金屬板1之部位溶解除去，形成半導體元件搭載部8、半導體元件電極連接端子9及配線10(參照第5圖)。外部連接端子11係從半導體元件電極連接端子9延伸。又，雖未圖示，但較佳為於第3次蝕刻處理時將背膜等貼附於金屬板1之第2面側，以使得不會在金屬板1之第2面側進行不需要的蝕刻。
然後，進行金屬板1之第1面的光阻圖案2a之剝離，獲得作為所需之導線架型LGA基板的半導體元件基板7(參照第6圖)。
接著，在剝離光阻圖案2a、2b之後，對露出之金屬板1的面實施電解鎳-金電鍍。鎳之厚度為5μm，金之厚度為0.1μm(未圖示)。
接著，於作為導線架型LGA基板的半導體元件基板7上，使用黏晶材14搭載半導體元件12，在150℃之溫度下對黏晶材14進行1小時的硬化。然後，使用直徑30μm之金線，對半導體元件12之電極與半導體元件電極之連接端子9進行引線接合(參照第9圖)。引線接合之加熱溫度係在200℃下進行，測定半導體元件電極之連接端子9側的引線的拉伸強度時，為9g以上，可獲得良好之連接。
然後，如第10圖所示，藉由轉注成型樹脂15將包含半導體元件12、半導體元件電極之連接端子9的區域密封，裁切成小片，而獲得使用半導體元件基板7之半導體裝置(半導體封裝體)。
本發明可減低製造時之不良情形及半導體封裝體組裝時之不良情形，可獲得提高對熱應力之可靠性的導線架型基板，尤其可適用於在導線架型半導體封裝體中無法因應之多腳端封裝基板。
以上，雖針對本發明之較佳實施例舉例說明，但此等實施例只能認為是發明之例示而已，並不受此侷限，只要在未超出本發明之範圍內，皆可作追加、刪除、置換及其他的變更。亦即，本發明不受前述實施例所限定，而是由申請專利範圍所限定。
(產業上之可利用性)
根據本發明，可將用來與印刷電路板連接之外部連接端子呈陣列狀地配置於半導體元件基板之整個背面，從而可因應半導體元件之多端子化。
另外，根據本發明，係主要以導線架製成之基板，不需使用電鍍配線，所以，可確保對熱應力之可靠性。又，根據本發明，在製作本基板時，不會發生配線之折斷或彎曲等的不良情形，在進行屬半導體封裝體組裝步驟的引線接合時，因設有狹縫，在預成型封裝樹脂充填於凹部後，可緩和硬化時產生之預成型封裝樹脂的應力，可防止預成型封裝樹脂從金屬板被剝離的情況。
因此，根據本發明，可因應半導體元件之電極數的增加，且可靠性高，並能穩定進行製作及半導體封裝體之組裝。
1．．．金屬板
2a．．．第1光阻圖案
2b．．．第2光阻圖案
3．．．凹部
4．．．狹縫
5．．．外框部
6．．．樹脂層
7．．．半導體元件基板
8．．．半導體元件搭載部
9．．．半導體元件電極連接端子
10．．．配線
11．．．外部連接端子
12．．．半導體元件
13．．．金線
14．．．黏晶材
15．．．轉注成型樹脂
16．．．電鍍聚醯亞胺層
17．．．金屬片
18．．．連結片
110．．．配線
111．．．外部連接端子
112．．．外框部
116．．．聚醯亞胺樹脂層
118．．．半導體元件搭載部
119．．．半導體元件電極連接端子
第1圖為用來說明本發明之實施形態1的半導體元件基板之製造方法的步驟之示意剖視圖。
第2圖為用來說明本發明之實施形態1的半導體元件基板之製造方法的步驟之示意剖視圖。
第3圖為用來說明本發明之實施形態1的半導體元件基板之製造方法的步驟之示意剖視圖。
第4圖為用來說明本發明之實施形態1的半導體元件基板之製造方法的步驟之示意剖視圖。
第5圖為用來說明本發明之實施形態1的半導體元件基板之製造方法的步驟之示意剖視圖。
第6圖為用來說明本發明之實施形態1的半導體元件基板之製造方法的步驟之示意剖視圖。
第7圖為顯示本發明之實施形態1的半導體元件基板之一部分的部分缺口俯視圖。
第8圖為顯示本發明之實施形態1的半導體元件基板之其他部分的部分缺口俯視圖。
第9圖為用來說明本發明之實施形態2的半導體裝置之製造方法的步驟之示意剖視圖。
第10圖為用來說明本發明之實施形態2的半導體裝置之製造方法的其他步驟之示意剖視圖。
第11圖為用來說明習知之半導體元件基板之製造方法的步驟之示意剖視圖。
第12圖為用來說明習知之半導體元件基板之製造方法的步驟之示意剖視圖。
5．．．外框部
6．．．樹脂層
7．．．半導體元件基板
8．．．半導體元件搭載部
9．．．半導體元件電極連接端子
11．．．外部連接端子
12．．．半導體元件
13．．．金線
15．．．轉注成型樹脂

Claims (3)

  1. 一種半導體元件基板之製造方法，其包含：形成第1光阻圖案的步驟，係用來於金屬板之第1面形成半導體元件搭載部、半導體元件電極連接端子、配線、外框部、及以使該外框部之四個角部與屬該金屬板的一部分之金屬片相連的方式貫通該金屬板之該第1面及不同於該第1面的第2面之狹縫；形成第2光阻圖案的步驟，係用來於該金屬板之該第2面形成外部連接端子、該外框部及該狹縫；以該金屬片與該外框部之四個角部相連的方式，藉由半蝕刻形成該狹縫之步驟；於該金屬板之該第2面形成複數個凹部的步驟；以不會進入該狹縫之方式朝該複數個凹部注入樹脂且使其硬化而形成樹脂層的步驟；及對該金屬板之該第1面進行蝕刻而形成該半導體元件搭載部、與該外部連接端子電性連接之該半導體元件電極連接端子及該外框部的步驟。
  2. 一種半導體元件基板，其包含：金屬板，具有第1面及不同於該第1面之第2面；半導體元件搭載部，係形成於該金屬板之該第1面；連接端子，係形成於該金屬板之該第1面，且與半導體元件電極連接；配線，係形成於該金屬板之該第1面；外框部，係形成於該金屬板；連結片，係連結該外框部之四個角部與該金屬板之一部分的金屬片；外部連接端子，係形成於該金屬板之該第2面；複數個凹部，係形成於該金屬板之該第2面；及樹脂層，係充填於該複數個凹部內。
  3. 一種半導體裝置，其包含半導體元件基板及半導體元件，其中該半導體元件基板具備：金屬板，具有第1面及不同於該第1面之第2面；半導體元件搭載部，係形成於該金屬板之該第1面；連接端子，係形成於該金屬板之該第1面，且與半導體元件電極連接；配線，係形成於該金屬板之該第1面；外框部，係形成於該金屬板；連結片，係連結該外框部之四個角部與該金屬板之一部分的金屬片；外部連接端子，係形成於該金屬板之該第2面；複數個凹部，係形成於該金屬板之該第2面；及樹脂層，係充填於該複數個凹部內；而該半導體元件係搭載於該半導體元件基板之該半導體元件搭載部，且與該半導體元件基板電性連接。
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Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8404524B2 (en) * 2010-09-16 2013-03-26 Stats Chippac Ltd. Integrated circuit packaging system with paddle molding and method of manufacture thereof
CN102324413B (zh) * 2011-09-13 2013-03-06 江苏长电科技股份有限公司 有基岛预填塑封料先刻后镀引线框结构及其生产方法
KR101478509B1 (ko) 2013-06-27 2015-01-02 앰코 테크놀로지 코리아 주식회사 반도체 패키지 제조용 원 레이어 기판 제조 방법
CN103400771B (zh) * 2013-08-06 2016-06-29 江阴芯智联电子科技有限公司 先蚀后封芯片倒装三维***级金属线路板结构及工艺方法
CN103456645B (zh) * 2013-08-06 2016-06-01 江阴芯智联电子科技有限公司 先蚀后封三维***级芯片正装堆叠封装结构及工艺方法
CN103413766B (zh) * 2013-08-06 2016-08-10 江阴芯智联电子科技有限公司 先蚀后封芯片正装三维***级金属线路板结构及工艺方法
CN104766832B (zh) 2014-01-03 2020-07-14 海成帝爱斯株式会社 制造半导体封装基板的方法及用其制造的半导体封装基板
KR102111730B1 (ko) * 2014-01-03 2020-05-15 해성디에스 주식회사 반도체 패키지 기판 제조방법 및 이를 이용하여 제조된 반도체 패키지 기판
KR102130757B1 (ko) * 2014-01-03 2020-07-08 해성디에스 주식회사 반도체 패키지 기판 제조방법 및 이를 이용하여 제조된 반도체 패키지 기판
KR101686349B1 (ko) * 2015-10-19 2016-12-13 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그의 제조 방법
JP6537144B2 (ja) * 2016-03-16 2019-07-03 大口マテリアル株式会社 多列型リードフレーム及びその製造方法
US9595455B1 (en) * 2016-06-09 2017-03-14 Nxp B.V. Integrated circuit module with filled contact gaps
CN106409696A (zh) * 2016-10-24 2017-02-15 上海凯虹科技电子有限公司 封装方法及封装体
US11244876B2 (en) 2019-10-09 2022-02-08 Microchip Technology Inc. Packaged semiconductor die with micro-cavity
JP7113461B2 (ja) * 2020-08-28 2022-08-05 株式会社バンダイ 金属シートの製造方法及び金属シート

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW381326B (en) * 1996-11-20 2000-02-01 Hitachi Ltd Semiconductor device and lead frame therefor
US7816187B2 (en) * 2003-01-21 2010-10-19 Siliconware Precision Industries Co., Ltd. Method for fabricating semiconductor package free of substrate
US8063470B1 (en) * 2008-05-22 2011-11-22 Utac Thai Limited Method and apparatus for no lead semiconductor package

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07273250A (ja) * 1994-03-31 1995-10-20 Hitachi Ltd 半導体装置
JPH09307043A (ja) * 1996-05-10 1997-11-28 Dainippon Printing Co Ltd リードフレーム部材とその製造方法、および該リードフレーム部材を用いた半導体装置
JP3642911B2 (ja) * 1997-02-05 2005-04-27 大日本印刷株式会社 リードフレーム部材とその製造方法
JP4547086B2 (ja) * 2000-12-25 2010-09-22 ルネサスエレクトロニクス株式会社 半導体装置
US6841854B2 (en) * 2002-04-01 2005-01-11 Matsushita Electric Industrial Co., Ltd. Semiconductor device
US20040080025A1 (en) * 2002-09-17 2004-04-29 Shinko Electric Industries Co., Ltd. Lead frame, method of manufacturing the same, and semiconductor device manufactured with the same
KR101298225B1 (ko) * 2005-06-30 2013-08-27 페어차일드 세미컨덕터 코포레이션 반도체 다이 패키지 및 그의 제조 방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW381326B (en) * 1996-11-20 2000-02-01 Hitachi Ltd Semiconductor device and lead frame therefor
US7816187B2 (en) * 2003-01-21 2010-10-19 Siliconware Precision Industries Co., Ltd. Method for fabricating semiconductor package free of substrate
US8063470B1 (en) * 2008-05-22 2011-11-22 Utac Thai Limited Method and apparatus for no lead semiconductor package

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