TWI419272B

TWI419272B - Semiconductor chip assembly with post/base heat spreader and signal post

Info

Publication number: TWI419272B
Application number: TW099142570A
Authority: TW
Inventors: Charles W C Lin; Chia Chung Wang
Original assignee: Bridge Semiconductor Corp
Priority date: 2009-12-19
Filing date: 2010-12-07
Publication date: 2013-12-11
Also published as: CN102130084A; CN102130084B; TW201130095A

Description

具有凸柱/基座之散熱座及訊號凸柱之半導體晶片組體Semiconductor wafer package with bump/base heat sink and signal bump

本發明係關於半導體晶片組體，更詳而言之，係關於一種由半導體元件、導線、黏著層及散熱座組成之半導體晶片組體及其製造方法。The present invention relates to a semiconductor wafer package, and more particularly to a semiconductor wafer package comprising a semiconductor component, a wire, an adhesive layer, and a heat sink, and a method of fabricating the same.

【相關申請案之相互參照】[Reciprocal reference of related applications]

本申請案為2009年11月11日提出申請之第12/616,773號美國專利申請案之部分延續案，該案之內容以引用之方式併入本文。本申請案亦為2009年11月11日提出申請之第12/616,775號美國專利申請案之部分延續案，該案之內容同樣以引用之方式併入本文。本申請案另主張2009年11月3日提出申請之第61/257,830號美國臨時專利申請案之優先權，該案之內容亦以引用之方式併入本文。This application is a continuation-in-part of U.S. Patent Application Serial No. 12/616,773, filed on Nov. 11, 2009, the content of which is hereby incorporated by reference. This application is also a continuation of the U.S. Patent Application Serial No. 12/616,775, filed on Nov. 11, 2009, the content of which is hereby incorporated by reference. The present application claims priority to U.S. Provisional Patent Application Serial No. 61/257,830, filed on Jan. 3, 2009, the content of which is hereby incorporated by reference.

前開於2009年11月11日提出申請之第12/616,773號美國專利申請案及前開於2009年11月11日提出申請之第12/616,775號美國專利申請案均為2009年9月11日提出申請之第12/557,540號美國專利申請案之部分延續案，且亦均為2009年9月11日提出申請之第12/557,541號美國專利申請案之部分延續案。U.S. Patent Application No. 12/616,773, filed on November 11, 2009, and U.S. Patent Application Serial No. 12/616,775, filed on Nov. 11, 2009, filed on Sep. 11, 2009 Part of the continuation of U.S. Patent Application Serial No. 12/557,540, filed on Sep. 11, 2009.

前開於2009年9月11日提出申請之第12/557,540號美國專利申請案及前開於2009年9月11日提出申請之第12/557,541號美國專利申請案均為2009年3月18日提出申請之第12/406,510號美國專利申請案之部分延續案。該第12/406,510號美國專利申請案主張2008年5月7日提出申請之第61/071,589號美國臨時專利申請案、2008年5月7日提出申請之第61/071,588號美國臨時專利申請案、2008年4月11日提出申請之第61/071,072號美國臨時專利申請案及2008年3月25日提出申請之第61/064,748號美國臨時專利申請案之優先權，上述各案之內容均以引用之方式併入本文。前開於2009年9月11日提出申請之第12/557,540號美國專利申請案及前開於2009年9月11日提出申請之第12/557,541號美國專利申請案亦主張2009年2月9日提出申請之第61/150,980號美國臨時專利申請案之優先權，其內容以引用之方式併入本文。U.S. Patent Application Serial No. 12/557,540, filed on Sep. 11, 2009, and filed No. 12/557,541, filed on Sep. 11, 2009, filed on March 18, 2009 Partial continuation of U.S. Patent Application Serial No. 12/406,510. U.S. Patent Application Serial No. 61/071,588, filed on May 7, 2008, and U.S. Provisional Patent Application No. 61/071,588, filed on May 7, 2008. Priority of US Provisional Patent Application No. 61/071,072, filed on Apr. 11, 2008, and U.S. Provisional Patent Application No. 61/064,748, filed on March 25, 2008, the content of each of This is incorporated herein by reference. U.S. Patent Application Serial No. 12/557,540, filed on Sep. 11, 2009, and filed on Sep. 11, 2009, filed on Sep. 11, 2009. Priority is claimed in US Provisional Patent Application Serial No. 61/150,980, the disclosure of which is incorporated herein by reference.

諸如經封裝與未經封裝之半導體晶片等半導體元件可提供高電壓、高頻率及高效能之應用；該些應用為執行特定功能，所需消耗之功率甚高，然功率愈高則半導體元件生熱愈多。此外，在封裝密度提高及尺寸縮減後，可供散熱之表面積縮小，更導致生熱加劇。Semiconductor components such as packaged and unpackaged semiconductor wafers can provide high voltage, high frequency, and high performance applications; these applications require a very high amount of power to perform a particular function, but the higher the power, the higher the semiconductor component More heat. In addition, after the package density is increased and the size is reduced, the surface area available for heat dissipation is reduced, which further increases heat generation.

半導體元件在高溫操作下易產生效能衰退及使用壽命縮短等問題，甚至可能立即故障。高熱不僅影響晶片效能，亦可能因熱膨脹不匹配而對晶片及其週遭元件產生熱應力作用。因此，必須使晶片迅速有效散熱方能確保其操作之效率與可靠度。一條高導熱性路徑通常係將熱能傳導並發散至一表面積較晶片或晶片所在之晶粒座更大之區域。Semiconductor components are prone to performance degradation and shortened service life under high temperature operation, and may even malfunction immediately. High heat not only affects wafer performance, but may also cause thermal stress on the wafer and its surrounding components due to thermal expansion mismatch. Therefore, the wafer must be quickly and efficiently dissipated to ensure the efficiency and reliability of its operation. A high thermal conductivity path typically conducts and dissipates thermal energy to a region of greater surface area than the die pad in which the wafer or wafer is located.

發光二極體(LED)近來已普遍成為白熾光源、螢光光源與鹵素光源之替代光源。LED可為醫療、軍事、招牌、訊號、航空、航海、車輛、可攜式設備、商用與住家照明等應用領域提供高能源效率及低成本之長時間照明。例如，LED可為燈具、手電筒、車頭燈、探照燈、交通號誌燈及顯示器等設備提供光源。Light-emitting diodes (LEDs) have recently become an alternative source of incandescent, fluorescent, and halogen sources. LEDs provide high energy efficiency and low cost long-term illumination for medical, military, signage, signal, aerospace, marine, vehicle, portable, commercial and residential lighting applications. For example, LEDs can provide light sources for fixtures, flashlights, headlights, searchlights, traffic lights, and displays.

LED中之高功率晶片在提供高亮度輸出之同時亦產生大量熱能。然而，在高溫操作下，LED會發生色偏、亮度降低、使用壽命縮短及立即故障等問題。此外，LED在散熱方面有其限制，進而影響其光輸出與可靠度。因此，LED格外突顯市場對於具有良好散熱效果之高功率晶片之需求。The high power chips in the LEDs also produce a large amount of thermal energy while providing high brightness output. However, under high temperature operation, LEDs may suffer from color shift, brightness reduction, shortened service life, and immediate failure. In addition, LEDs have limitations in terms of heat dissipation, which in turn affects their light output and reliability. Therefore, LEDs highlight the market's need for high-power chips with good heat dissipation.

LED封裝體通常包含一LED晶片、一基座、電接點及一熱接點。所述基座係熱連結至LED晶片並用以支撐該LED晶片。電接點則電性連結至LED晶片之陽極與陰極。熱接點經由該基座熱連結至LED晶片，其下方載具可充分散熱以預防LED晶片過熱。The LED package typically includes an LED chip, a pedestal, electrical contacts, and a thermal contact. The pedestal is thermally coupled to the LED wafer and used to support the LED wafer. The electrical contacts are electrically connected to the anode and cathode of the LED chip. The thermal contacts are thermally coupled to the LED wafer via the pedestal, and the underlying carrier is sufficiently thermally dissipated to prevent overheating of the LED wafer.

業界積極以各種設計及製造技術投入高功率晶片封裝體與導熱板之研發，以期在此極度成本競爭之環境中滿足效能需求。The industry is actively investing in the development of high-power chip packages and thermal boards with various design and manufacturing technologies in order to meet performance requirements in this extremely cost-competitive environment.

塑膠球柵陣列(PBGA)封裝係將一晶片與一層壓基板包裹於一塑膠外殼中，然後再以錫球黏附於一印刷電路板(PCB)之上。所述層壓基板包含一通常由玻璃纖維構成之介電層。晶片產生之熱能可經由塑膠及介電層傳至錫球，進而傳至印刷電路板。然而，由於塑膠與介電層之導熱性低，PBGA之散熱效果不佳。A plastic ball grid array (PBGA) package encloses a wafer and a laminate substrate in a plastic case and then adheres to a printed circuit board (PCB) with solder balls. The laminate substrate comprises a dielectric layer typically composed of glass fibers. The heat generated by the wafer can be transferred to the solder ball via the plastic and dielectric layers and transferred to the printed circuit board. However, due to the low thermal conductivity of the plastic and dielectric layers, the PBGA has a poor heat dissipation effect.

方形扁平無引腳(QFN)封裝係將晶片設置在一焊接於印刷電路板之銅質晶粒座上。晶片產生之熱能可經由晶粒座傳至印刷電路板。然而，由於其導線架中介層之路由能力有限，使得QFN封裝無法適用於高輸入/輸出(I/O)晶片或被動元件。A quad flat no-lead (QFN) package places the wafer on a copper die pad that is soldered to a printed circuit board. The thermal energy generated by the wafer can be transferred to the printed circuit board via the die pad. However, due to the limited routing capabilities of its leadframe interposer, QFN packages are not suitable for high input/output (I/O) chips or passive components.

導熱板為半導體元件提供電性路由、熱管理與機械性支撐等功能。導熱板通常包含一用於訊號路由之基板、一提供熱去除功能之散熱座或散熱裝置、一可供電性連結至半導體元件之焊墊，以及一可供電性連結至下一層組體之端子。該基板可為一具有單層或多層路由電路系統及一或多層介電層之層壓結構。該散熱座可為一金屬基座、金屬塊或埋設金屬層。The heat conducting plate provides electrical routing, thermal management, and mechanical support for the semiconductor components. The heat conducting board usually comprises a substrate for signal routing, a heat sink or heat sink for providing heat removal function, a solder pad electrically connectable to the semiconductor component, and a terminal electrically connectable to the next layer assembly. The substrate can be a laminate structure having a single or multi-layer routing circuitry and one or more dielectric layers. The heat sink can be a metal base, a metal block or a buried metal layer.

導熱板接合下一層組體。例如，下一層組體可為一具有印刷電路板及散熱裝置之燈座。在此範例中，一LED封裝體係安設於導熱板上，該導熱板則安設於散熱裝置上，導熱板/散熱裝置次組體與印刷電路板又安設於燈座中。此外，導熱板經由導線電性連結至該印刷電路板。該基板將電訊號自該印刷電路板導向LED封裝體，而該散熱座則將LED封裝體之熱能發散並傳遞至該散熱裝置。因此，該導熱板可為LED晶片提供一重要之熱路徑。The heat conducting plate engages the next layer of the body. For example, the next layer of the body can be a lamp holder having a printed circuit board and a heat sink. In this example, an LED package system is disposed on the heat conducting plate, and the heat conducting plate is disposed on the heat dissipating device, and the heat conducting plate/heat dissipating device sub-group and the printed circuit board are further disposed in the lamp holder. In addition, the heat conducting plate is electrically connected to the printed circuit board via wires. The substrate directs the electrical signal from the printed circuit board to the LED package, and the heat sink scatters and transfers the thermal energy of the LED package to the heat sink. Therefore, the heat conducting plate can provide an important thermal path for the LED wafer.

授予Juskey等人之第6,507,102號美國專利揭示一種組體，其中一由玻璃纖維與固化之熱固性樹脂所構成之複合基板包含一中央開口。一具有類似前述中央開口正方或長方形狀之散熱塊係黏附於該中央開口側壁因而與該基板結合。上、下導電層分別黏附於該基板之頂部及底部，並透過貫穿該基板之電鍍導孔互為電性連結。一晶片係設置於散熱塊上並打線接合至上導電層，一封裝材料係模設成形於晶片上，而下導電層則設有錫球。U.S. Patent No. 6,507,102 to the disclosure of U.S. Pat. A heat dissipating block having a square or rectangular shape similar to the central opening is adhered to the central opening side wall and thus joined to the substrate. The upper and lower conductive layers are respectively adhered to the top and bottom of the substrate, and are electrically connected to each other through the plating vias penetrating the substrate. A wafer is disposed on the heat dissipation block and wire bonded to the upper conductive layer, a package material is molded on the wafer, and a lower conductive layer is provided with a solder ball.

製造時，該基板原為一置於下導電層上之乙階(B-stage)樹脂膠片。散熱塊係插設於中央開口，因而位於下導電層上，並與該基板以一間隙相隔。上導電層則設於該基板上。上、下導電層經加熱及彼此壓合後，使樹脂熔化並流入前述間隙中固化。上、下導電層形成圖案，因而在該基板上形成電路佈線，並使樹脂溢料顯露於散熱塊上。然後去除樹脂溢料，使散熱塊露出。最後再將晶片安置於散熱塊上並進行打線接合與封裝。When manufactured, the substrate was originally a B-stage resin film placed on the lower conductive layer. The heat dissipating block is inserted in the central opening so as to be located on the lower conductive layer and separated from the substrate by a gap. The upper conductive layer is disposed on the substrate. After the upper and lower conductive layers are heated and pressed together, the resin is melted and flows into the gap to be solidified. The upper and lower conductive layers are patterned, thereby forming circuit wiring on the substrate and exposing the resin flash to the heat sink. The resin flash is then removed to expose the heat sink. Finally, the wafer is placed on the heat sink block and bonded and packaged.

因此，晶片產生之熱能可經由散熱塊傳至印刷電路板。然而在量產時，以手工方式將散熱塊放置於中央開口內之作業極為費工，且成本高昂。再者，由於側向之安裝容差小，散熱塊不易精確定位於中央開口中，導致基板與散熱塊之間易出現間隙以及打線不均之情形。如此一來，該基板僅部分黏附於散熱塊，無法自散熱塊獲得足夠支撐力，且容易脫層。此外，用於去除部分導電層以顯露樹脂溢料之化學蝕刻液亦將去除部分未被樹脂溢料覆蓋之散熱塊，使散熱塊不平且不易結合，最終導致組體之良率降偏低、可靠度不足且成本過高。Therefore, the thermal energy generated by the wafer can be transferred to the printed circuit board via the heat slug. However, in mass production, the manual placement of the heat sink in the central opening is labor intensive and costly. Moreover, since the mounting tolerance of the lateral direction is small, the heat dissipating block is not easily positioned in the central opening, which may cause a gap between the substrate and the heat dissipating block and uneven wiring. As a result, the substrate is only partially adhered to the heat dissipation block, and sufficient support force cannot be obtained from the heat dissipation block, and the layer is easily delaminated. In addition, the chemical etching solution for removing part of the conductive layer to expose the resin flash will also remove some of the heat-dissipating block which is not covered by the resin flash, so that the heat-dissipating block is not flat and difficult to combine, and finally the yield of the group is lowered, Insufficient reliability and high cost.

授予Ding等人之第6,528,882號美國專利揭露一種高散熱球柵陣列封裝體，其基板包含一金屬芯層，而晶片則安置於金屬芯層頂面之晶粒座區域。一絕緣層係形成於金屬芯層之底面。盲孔貫穿絕緣層直通金屬芯層，且孔內填有散熱錫球，另在該基板上設有與散熱錫球相對應之錫球。晶片產生之熱能可經由金屬芯層流向散熱錫球，再流向印刷電路板。然而，夾設於金屬芯層與印刷電路板間之絕緣層卻對流向印刷電路板之熱流造成限制。US Patent No. 6,528,882 to Ding et al. discloses a high heat dissipation ball grid array package having a substrate comprising a metal core layer and a wafer disposed in a die pad region on the top surface of the metal core layer. An insulating layer is formed on the bottom surface of the metal core layer. The blind hole penetrates the insulating layer through the metal core layer, and the hole is filled with the heat-dissipating solder ball, and the solder ball corresponding to the heat-dissipating solder ball is further disposed on the substrate. The thermal energy generated by the wafer can flow through the metal core to the heat sink balls and then to the printed circuit board. However, the insulating layer sandwiched between the metal core layer and the printed circuit board limits the heat flow to the printed circuit board.

授予Lee等人之第6,670,219號美國專利教示一種凹槽向下球柵陣列(CDBGA)封裝體，其中一具有中央開口之接地板係設置於一散熱座上以構成一散熱基板。一具有中央開口之基板透過一具有中央開口之黏著層設置於該接地板上。一晶片係安裝於該散熱座上由接地板中央開口所形成之一凹槽內，且該基板上設有錫球。然而，由於錫球係位於基板上，散熱座並無法接觸印刷電路板，導致該散熱座之散熱作用僅限熱對流而非熱傳導，因而大幅限縮其散熱效果。U.S. Patent No. 6,670,219 to Lee et al., the disclosure of which is incorporated herein by reference. A substrate having a central opening is disposed on the ground plate through an adhesive layer having a central opening. A chip is mounted on the heat sink in a recess formed by the central opening of the ground plate, and the substrate is provided with a solder ball. However, since the solder ball is located on the substrate, the heat sink cannot contact the printed circuit board, and the heat dissipation effect of the heat sink is limited to heat convection instead of heat conduction, thereby greatly reducing the heat dissipation effect.

授予Woodall等人之第7,038,311號美國專利提供一種高散熱BGA封裝體，其散熱裝置為倒T形且包含一柱部與一寬基底。一設有窗型開口之基板係安置於寬基底上，一黏著層則將柱部與寬基底黏附於該基板。一晶片係安置於柱部上並打線接合至該基板，一封裝材料係模製成形於晶片上，該基板上則設有錫球。柱部延伸穿過該窗型開口，並由寬基底支撐該基板，至於錫球則位於寬基底與基板周緣之間。晶片產生之熱能可經由柱部傳至寬基底，再傳至印刷電路板。然而，由於寬基底上必須留有容納錫球之空間，寬基底僅在對應於中央窗口與最內部錫球之間的位置突伸於該基板下方。如此一來，該基板在製造過程中便不平衡，且容易晃動及彎曲，進而導致晶片之安裝、打線接合以及封裝材料之模製成形均十分困難。此外，該寬基底可能因封裝材料之模製成形而彎折，且一旦錫球崩塌，便可能使該封裝體無法焊接至下一層組體。是以，此封裝體之良率偏低、可靠度不足且成本過高。U.S. Patent No. 7,038,311 to Woodall et al. provides a high-heat-dissipating BGA package having a heat sink that is inverted T-shaped and includes a post portion and a wide base. A substrate having a window-shaped opening is disposed on the wide substrate, and an adhesive layer adheres the pillar portion and the wide substrate to the substrate. A wafer system is disposed on the pillar portion and wire bonded to the substrate, and a packaging material is molded on the wafer, and the substrate is provided with a solder ball. A post extends through the window opening and supports the substrate by a wide substrate, with the solder ball being between the wide substrate and the periphery of the substrate. The thermal energy generated by the wafer can be transferred to the wide substrate via the post and then to the printed circuit board. However, since a space for accommodating the solder balls must be left on the wide substrate, the wide substrate protrudes below the substrate only at a position corresponding to the central window and the innermost tin ball. As a result, the substrate is unbalanced during the manufacturing process, and is easily shaken and bent, thereby causing difficulty in mounting, wire bonding, and molding of the package material. In addition, the wide substrate may be bent due to the molding of the encapsulating material, and once the solder ball collapses, the package may not be soldered to the next layer. Therefore, the yield of the package is low, the reliability is insufficient, and the cost is too high.

Erchak等人之美國專利申請公開案第2007/0267642號提出一種發光裝置組體，其中一倒T形之基座包含一基板、一突出部及一具有通孔之絕緣層，絕緣層上並設有電接點。一具有通孔與透明上蓋之封裝體係設置於電接點上。一LED晶片係設置於突出部並以打線連接該基板。該突出部係鄰接該基板並延伸穿過絕緣層與封裝體上之通孔，進入封裝體內。絕緣層係設置於該基板上，且絕緣層上設有電接點。封裝體係設置於該等電接點上並與絕緣層保持間距。該晶片產生之熱能可經由突出部傳至該基板，進而到達一散熱裝置。然而，該等電接點不易設置於絕緣層上，難以與下一層組體電性連結，且無法提供多層路由。U.S. Patent Application Publication No. 2007/0267642 to Erchak et al., which is incorporated herein by reference in its entirety, the entire entire entire entire entire entire entire entire entire entire entire entire entire contents There are electrical contacts. A packaging system having a through hole and a transparent upper cover is disposed on the electrical contact. An LED chip is disposed on the protruding portion and connected to the substrate by wire bonding. The protrusion is adjacent to the substrate and extends through the insulating layer and the through hole on the package to enter the package. An insulating layer is disposed on the substrate, and an electrical contact is disposed on the insulating layer. The packaging system is disposed on the electrical contacts and spaced apart from the insulating layer. The heat generated by the wafer can be transferred to the substrate via the protrusions to reach a heat sink. However, the electrical contacts are not easily disposed on the insulating layer, and are difficult to electrically connect with the next layer of the assembly, and cannot provide multilayer routing.

習知封裝體與導熱板具有重大缺點。舉例而言，諸如環氧樹脂等低導熱性之電絕緣材料對散熱效果造成限制，然而，以陶瓷或碳化矽填充之環氧樹脂等具有較高導熱性之電絕緣材料則具有黏著性低且量產成本過高之缺點。該電絕緣材料可能在製作過程中或在操作初期即因受熱而脫層。該基板若為單層電路系統則路由能力有限，但若該基板為多層電路系統，則其過厚之介電層將降低散熱效果。此外，前案技術尚有散熱座效能不足、體積過大或不易熱連結至下一層組體等問題。前案技術之製造工序亦不適於低成本之量產作業。Conventional packages and thermally conductive plates have major drawbacks. For example, an electrically insulating material having a low thermal conductivity such as an epoxy resin limits the heat dissipation effect, however, an electrically insulating material having a high thermal conductivity such as an epoxy resin filled with ceramic or tantalum carbide has low adhesion. The disadvantage of high production cost. The electrically insulating material may be delaminated by heat during the manufacturing process or at the beginning of the operation. If the substrate is a single-layer circuit system, the routing capability is limited. However, if the substrate is a multi-layer circuit system, the excessively thick dielectric layer will reduce the heat dissipation effect. In addition, the previous case technology still has problems such as insufficient heat sink performance, excessive volume or difficulty in thermally connecting to the next layer. The manufacturing process of the prior art is also not suitable for low-cost mass production operations.

有鑑於現有高功率半導體元件封裝體及導熱板之種種發展情形及相關限制，業界實需一種具成本效益、效能可靠、適於量產、多功能、可靈活調整訊號路由且具有優異散熱性之半導體晶片組體。In view of the various developments and related limitations of the existing high-power semiconductor device packages and heat-conducting plates, the industry needs a cost-effective, reliable, mass-produced, multi-functional, flexible signal routing and excellent heat dissipation. Semiconductor wafer assembly.

本發明提供一種半導體晶片組體，其至少包含一半導體元件、一散熱座、一導線與一黏著層。該半導體元件係電性連結至該導線並熱連結至該散熱座。該散熱座至少包含一導熱凸柱與一基座。該導熱凸柱自該基座向上延伸並進入該黏著層之一第一開口，該基座則自該導熱凸柱側向延伸。該導線至少包含一焊墊、一端子與一訊號凸柱。該訊號凸柱自該端子向上延伸並進入該黏著層之一第二開口。The invention provides a semiconductor wafer package comprising at least a semiconductor component, a heat sink, a wire and an adhesive layer. The semiconductor component is electrically connected to the wire and thermally coupled to the heat sink. The heat sink includes at least a heat conducting stud and a base. The thermally conductive stud extends upwardly from the base and into a first opening of the adhesive layer, the base extending laterally from the thermally conductive stud. The wire includes at least one pad, a terminal and a signal stud. The signal stud extends upward from the terminal and enters a second opening of the adhesive layer.

根據本發明之一樣式，一半導體晶片組體至少包含一半導體元件、一黏著層、一散熱座與一導線。該黏著層至少具有第一及第二開口。該散熱座至少包含一導熱凸柱及一基座，其中該導熱凸柱係鄰接該基座並沿一向上方向延伸於該基座上方，該基座則沿一與該向上方向相反之向下方向延伸於該導熱凸柱下方，並沿垂直於該向上及向下方向之側面方向從該導熱凸柱側向延伸而出。該導線至少包含一焊墊、一端子與一訊號凸柱，其中該訊號凸柱係延伸於該焊墊下方及該端子上方，且該焊墊與該端子間之一導電路徑包含該訊號凸柱。According to one aspect of the invention, a semiconductor wafer package includes at least a semiconductor component, an adhesive layer, a heat sink and a wire. The adhesive layer has at least first and second openings. The heat sink includes at least a heat conducting stud and a base, wherein the heat conducting stud is adjacent to the base and extends upwardly in the upward direction of the base, the base is opposite to the upward direction The direction extends below the thermally conductive stud and extends laterally from the thermally conductive stud in a direction perpendicular to the upward and downward directions. The wire is at least The device includes a solder pad, a terminal and a signal stud, wherein the signal stud extends below the solder pad and above the terminal, and a conductive path between the pad and the terminal includes the signal stud.

該半導體元件係位於該導熱凸柱上方並重疊於該導熱凸柱。該半導體元件係電性連結至該焊墊，從而電性連結至該端子；並且熱連結至該導熱凸柱，從而熱連結至該基座。該黏著層係設置於該基座上，延伸於該基座上方，並從該導熱凸柱側向延伸至該端子或越過該端子。該焊墊係延伸於該黏著層上方，而該端子則延伸於該黏著層下方。該導熱凸柱延伸進入該第一開口，該訊號凸柱則延伸進入該第二開口。此外，該導熱凸柱及該訊號凸柱具有相同厚度且彼此共平面，該基座與該端子亦具有相同厚度且彼此共平面。The semiconductor component is located above the thermally conductive stud and overlaps the thermally conductive stud. The semiconductor component is electrically connected to the pad to be electrically connected to the terminal; and thermally coupled to the thermally conductive stud to be thermally coupled to the susceptor. The adhesive layer is disposed on the base, extends above the base, and extends laterally from the thermally conductive stud to the terminal or over the terminal. The pad extends over the adhesive layer and the terminal extends below the adhesive layer. The thermally conductive stud extends into the first opening, and the signal stud extends into the second opening. In addition, the thermally conductive stud and the signal stud have the same thickness and are coplanar with each other, and the base and the terminal also have the same thickness and are coplanar with each other.

該導線可包含該焊墊、該端子、該訊號凸柱及一路由線。該路由線可鄰接該焊墊。該訊號凸柱可鄰接該路由線與該端子，延伸於該焊墊與該路由線下方，且延伸於該端子上方。該焊墊與該路由線可重疊於該黏著層。該端子可被該黏著層重疊。該訊號凸柱可延伸貫穿該黏著層。該焊墊、該端子、該訊號凸柱與該路由線可接觸該黏著層。一位於該焊墊與該端子間之導電路徑可包含該訊號凸柱與該路由線。The wire can include the pad, the terminal, the signal stud, and a routing wire. The routing line can abut the pad. The signal stud may abut the routing line and the terminal, extend below the solder pad and the routing line, and extend above the terminal. The pad and the routing line may overlap the adhesive layer. The terminal can be overlapped by the adhesive layer. The signal studs extend through the adhesive layer. The solder pad, the terminal, the signal stud and the routing line can contact the adhesive layer. A conductive path between the pad and the terminal can include the signal stud and the routing line.

根據本發明之另一樣式，一半導體晶片組體至少包含一半導體元件、一黏著層、一散熱座、一基板與一導線。該黏著層至少具有第一及第二開口。該散熱座至少包含一導熱凸柱及一基座，其中該導熱凸柱係鄰接該基座並沿一向上方向延伸於該基座上方，該基座則沿一與該向上方向相反之向下方向延伸於該導熱凸柱下方，並沿垂直於該向上及向下方向之側面方向從該導熱凸柱側向延伸而出。該基板至少包含一焊墊與一介電層，且第一及第二通孔延伸穿過該基板。該導線至少包含該焊墊、一端子與一訊號凸柱，其中該訊號凸柱係延伸於該焊墊下方及該端子上方，且該焊墊與該端子間之一導電路徑包含該訊號凸柱。According to another aspect of the invention, a semiconductor wafer package includes at least a semiconductor component, an adhesive layer, a heat sink, a substrate and a wire. The adhesive layer has at least first and second openings. The heat sink includes at least one a thermally conductive stud and a base, wherein the thermally conductive stud is adjacent to the base and extends above the base in an upward direction, the base extending in the downward direction opposite the upward direction to the thermally conductive convex Below the column, and extending laterally from the thermally conductive stud in a direction perpendicular to the upward and downward directions. The substrate includes at least one pad and a dielectric layer, and the first and second vias extend through the substrate. The wire includes at least the pad, a terminal and a signal stud, wherein the signal stud extends below the solder pad and above the terminal, and a conductive path between the pad and the terminal includes the signal stud .

該半導體元件係位於該導熱凸柱上方並重疊於該導熱凸柱。該半導體元件係電性連結至該焊墊，從而電性連結至該端子；並且熱連結至該導熱凸柱，從而熱連結至該基座。該黏著層係設置於該基座上，延伸於該基座上方，且延伸進入該第一通孔中一介於該導熱凸柱與該基板間之第一缺口，同時延伸進入該第二通孔中一介於該訊號凸柱與該基板間之第二缺口，並於該等缺口中延伸跨越該介電層。該黏著層從該導熱凸柱側向延伸至該端子或越過該端子，且係介於該導熱凸柱與該介電層之間、該訊號凸柱與該介電層之間以及該基座與該介電層之間。該基板係設置於該黏著層上，並延伸於該基座上方。該導熱凸柱延伸進入該第一開口及該第一通孔，該訊號凸柱則延伸進入該第二開口及該第二通孔。此外，該導熱凸柱及該訊號凸柱具有相同厚度且彼此共平面，該基座與該端子亦具有相同厚度且彼此共平面。The semiconductor component is located above the thermally conductive stud and overlaps the thermally conductive stud. The semiconductor component is electrically connected to the pad to be electrically connected to the terminal; and thermally coupled to the thermally conductive stud to be thermally coupled to the susceptor. The adhesive layer is disposed on the pedestal and extends over the pedestal and extends into the first through hole, a first gap between the heat conducting stud and the substrate, and extends into the second through hole The second gap between the signal stud and the substrate and extends across the dielectric layer in the gaps. The adhesive layer extends laterally from the thermally conductive stud to the terminal or over the terminal, between the thermally conductive stud and the dielectric layer, between the signal stud and the dielectric layer, and the pedestal Between the dielectric layer and the dielectric layer. The substrate is disposed on the adhesive layer and extends above the base. The heat conducting stud extends into the first opening and the first through hole, and the signal stud extends into the second opening and the second through hole. In addition, the thermally conductive stud and the signal stud have the same thickness and are coplanar with each other, and the base and the terminal also have the same thickness and are coplanar with each other.

該散熱座可包含一蓋體，該蓋體係位於該導熱凸柱之頂部上方，鄰接該導熱凸柱之頂部，同時從上方覆蓋該導熱凸柱之頂部，並沿該等側面方向從該導熱凸柱之頂部側向延伸而出。例如，該蓋體可為矩形或正方形，而該導熱凸柱之頂部可為圓形。在此例中，該蓋體之尺寸及形狀可經過設計，以配合該半導體元件之熱接觸表面，至於該導熱凸柱頂部之尺寸及形狀則未依該半導體元件之熱接觸表面而設計。該蓋體亦可接觸並覆蓋該黏著層一鄰接該導熱凸柱並與該導熱凸柱共平面之部分。該蓋體亦可在該介電層上方與該焊墊共平面。此外，該導熱凸柱可熱連結該基座與該蓋體。該散熱座可由該導熱凸柱與該基座組成，或由該導熱凸柱、該基座與該蓋體組成。該散熱座亦可由銅、鋁或銅/鎳/鋁合金組成。無論採用任一組成方式，該散熱座皆可提供散熱作用，將該半導體元件之熱能擴散至下一層組體。The heat sink can include a cover body, and the cover system is located at the heat conducting stud The top of the top portion abuts the top of the thermally conductive stud while covering the top of the thermally conductive stud from above and extending laterally from the top of the thermally conductive stud in the lateral direction. For example, the cover may be rectangular or square, and the top of the thermally conductive stud may be circular. In this case, the cover may be sized and shaped to match the thermal contact surface of the semiconductor component, and the top and bottom of the thermally conductive stud are not designed according to the thermal contact surface of the semiconductor component. The cover may also contact and cover the adhesive layer, a portion adjacent to the thermally conductive stud and coplanar with the thermally conductive stud. The cover may also be coplanar with the pad above the dielectric layer. In addition, the thermally conductive stud can thermally join the base and the cover. The heat sink can be composed of the heat conducting stud and the base, or the heat conducting stud, the base and the cover. The heat sink can also be composed of copper, aluminum or copper/nickel/aluminum alloy. Regardless of any composition, the heat sink can provide heat dissipation to diffuse the thermal energy of the semiconductor component to the next layer.

該半導體元件可設置於該散熱座上。例如，該半導體元件可設置於該散熱座及該基板上，重疊於該導熱凸柱與該焊墊，透過一第一焊錫電性連結至該焊墊，並透過一第二焊錫熱連結至該散熱座。或者，該半導體元件可設置於該散熱座而非該基板上，重疊於該導熱凸柱而非該基板，透過一打線電性連結至該焊墊，並透過一固晶材料熱連結至該散熱座。The semiconductor component can be disposed on the heat sink. For example, the semiconductor device can be disposed on the heat sink and the substrate, and is superposed on the heat conducting stud and the solder pad, electrically connected to the solder pad through a first solder, and thermally coupled to the solder via a second solder. Heat sink. Alternatively, the semiconductor device may be disposed on the heat sink instead of the substrate, and overlap the heat conducting stud instead of the substrate, electrically connected to the pad through a wire, and thermally coupled to the heat through a die bonding material. seat.

該半導體元件可為一經封裝或未經封裝之半導體晶片。例如，該半導體元件可為一包含LED晶片之LED封裝體，其係設置於該散熱座與該基板上，重疊於該導熱凸柱與該焊墊，經由一第一焊錫電性連結至該焊墊，且經由一第二焊錫熱連結至該散熱座。或者，該半導體元件可為一半導體晶片，其係設置於該散熱座而非該基板上，重疊於該導熱凸柱而非該基板，經由一打線電性連結至該焊墊，且經由一固晶材料熱連結至該散熱座。The semiconductor component can be a packaged or unpackaged semiconductor wafer. For example, the semiconductor component can be an LED package including an LED chip disposed on the heat sink and the substrate, overlapping the thermally conductive stud and The pad is electrically connected to the pad via a first solder and thermally coupled to the heat sink via a second solder. Alternatively, the semiconductor device can be a semiconductor wafer disposed on the heat sink instead of the substrate, overlapping the heat conducting stud instead of the substrate, electrically connected to the pad via a wire, and via a solid The crystalline material is thermally coupled to the heat sink.

該黏著層可在該第一缺口中接觸該導熱凸柱及該介電層，並在該第二缺口中接觸該訊號凸柱及該介電層，且於該等缺口之外接觸該基座、該端子及該介電層。該黏著層亦可於該等側面方向覆蓋及環繞該導熱凸柱及該訊號凸柱，且同形被覆於該導熱凸柱及該訊號凸柱之側壁。該黏著層尚可與該導熱凸柱及該訊號凸柱之頂部及底部共平面。The adhesive layer contacts the thermal conductive stud and the dielectric layer in the first notch, and contacts the signal stud and the dielectric layer in the second notch, and contacts the pedestal outside the notches The terminal and the dielectric layer. The adhesive layer can also cover and surround the heat conducting stud and the signal stud in the lateral direction, and is similarly coated on the sidewall of the heat conducting stud and the signal stud. The adhesive layer is still coplanar with the heat conducting stud and the top and bottom of the signal stud.

該黏著層可自該導熱凸柱側向延伸至該端子或越過該端子。例如，該黏著層與該端子可延伸至該組體之外圍邊緣；在此例中，該黏著層係從該導熱凸柱側向延伸至該端子。或者，該黏著層可延伸至該組體之外圍邊緣，而該端子則與該組體之外圍邊緣保持距離；在此情況下，該黏著層係從該導熱凸柱側向延伸且越過該端子。The adhesive layer may extend laterally from the thermally conductive stud to the terminal or across the terminal. For example, the adhesive layer and the terminal can extend to the peripheral edge of the assembly; in this example, the adhesive layer extends laterally from the thermally conductive stud to the terminal. Alternatively, the adhesive layer may extend to a peripheral edge of the set, and the terminal is spaced from a peripheral edge of the set; in this case, the adhesive layer extends laterally from the thermally conductive stud and over the terminal .

該導熱凸柱可與該基座一體成形。例如，該導熱凸柱與該基座可為單一金屬體或於其介面包含單一金屬體，其中該單一金屬體可為銅。該導熱凸柱亦可延伸貫穿該第一通口。該導熱凸柱亦可在該介電層上方與該黏著層共平面。該導熱凸柱亦可為平頂錐柱形，其直徑係從該基座處朝其鄰接該蓋體之平坦頂部向上遞減。The thermally conductive stud can be integrally formed with the base. For example, the thermally conductive stud and the pedestal may be a single metal body or comprise a single metal body in its interface, wherein the single metal body may be copper. The thermally conductive stud can also extend through the first port. The thermally conductive stud may also be coplanar with the adhesive layer above the dielectric layer. The thermally conductive stud may also be a flat-topped tapered cylinder having a diameter that decreases upwardly from the base toward its flat top adjacent the cover.

該訊號凸柱可與該端子一體成形。例如，該訊號凸柱與該端子可為單一金屬體或於其介面包含單一金屬體，其中該單一金屬體可為銅。該訊號凸柱亦可延伸貫穿該第二通口。該訊號凸柱亦可在該介電層上方與該黏著層共平面。該訊號凸柱亦可為平頂錐柱形，其直徑係從該端子處朝其鄰接該路由線之平坦頂部向上遞減。The signal stud can be integrally formed with the terminal. For example, the signal stud The terminal may be a single metal body or comprise a single metal body in its interface, wherein the single metal body may be copper. The signal stud can also extend through the second port. The signal studs may also be coplanar with the adhesive layer above the dielectric layer. The signal stud may also be a flat-topped tapered cylinder having a diameter that decreases upwardly from the terminal toward its flat top adjacent the routing line.

該基座可從下方覆蓋該導熱凸柱，同時支撐該基板，並與該組體之外圍邊緣保持距離。The pedestal can cover the thermally conductive stud from below while supporting the substrate and maintaining a distance from the peripheral edge of the group.

該基板可與該導熱凸柱及該基座保持距離。該基板亦可為一層壓結構。The substrate can be spaced from the thermally conductive stud and the base. The substrate can also be a laminated structure.

該導線可與該散熱座保持距離。該焊墊可接觸該介電層，該端子可接觸該黏著層，而該訊號凸柱則可接觸該黏著層與該介電層。此外，該端子可鄰接該訊號凸柱，延伸於該訊號凸柱下方，並從該訊號凸柱側向延伸。The wire can be spaced from the heat sink. The pad can contact the dielectric layer, the terminal can contact the adhesive layer, and the signal stud can contact the adhesive layer and the dielectric layer. In addition, the terminal is adjacent to the signal stud, extends below the signal stud, and extends laterally from the signal stud.

該焊墊可作為該半導體元件之一電接點，該端子可作為下一層組體之一電接點，且該焊墊與該端子可在該半導體元件與該下一層組體之間提供垂直訊號路由。The pad can serve as an electrical contact of the semiconductor component, the terminal can serve as an electrical contact of the next layer, and the pad and the terminal can provide a vertical between the semiconductor component and the next layer Signal routing.

該組體可為一第一級或第二級單晶或多晶裝置。例如，該組體可為一包含單一晶片或多枚晶片之第一級封裝體。或者，該組體可為一包含單一LED封裝體或多個LED封裝體之第二級模組，其中各該LED封裝體可包含單一LED晶片或多枚LED晶片。The group can be a first or second stage single crystal or polycrystalline device. For example, the group can be a first level package containing a single wafer or multiple wafers. Alternatively, the group may be a second-level module comprising a single LED package or a plurality of LED packages, wherein each of the LED packages may comprise a single LED chip or a plurality of LED chips.

本發明提供一種製作一半導體晶片組體之方法，其包含：提供一導熱凸柱、一訊號凸柱及一基座；設置一黏著層於該基座上，此步驟包含將該導熱凸柱***該黏著層之一第一開口，並將該訊號凸柱***該黏著層之一第二開口；設置一導電層於該黏著層上，此步驟包含將該導熱凸柱對準該導電層之一第一通孔，並將該訊號凸柱對準該導電層之一第二通孔；使該黏著層向上流入該第一通孔內一介於該導熱凸柱與該導電層間之第一缺口以及該第二通孔內一介於該訊號凸柱與該導電層間之第二缺口；固化該黏著層；提供一導線，該導線至少包含一焊墊、一端子、該訊號凸柱與該導電層之一選定部分；設置一半導體元件於一散熱座上，其中該散熱座至少包含該導熱凸柱及該基座；電性連結該半導體元件至該導線；以及熱連結該半導體元件至該散熱座。The present invention provides a method of fabricating a semiconductor wafer package, comprising: providing a thermal conductive stud, a signal stud and a pedestal; and providing an adhesive layer on the pedestal, the step comprising inserting the thermally conductive stud Adhesive layer a first opening, and inserting the signal stud into a second opening of the adhesive layer; and providing a conductive layer on the adhesive layer, the step comprising aligning the thermally conductive stud with the first through hole of the conductive layer Aligning the signal stud with a second through hole of the conductive layer; causing the adhesive layer to flow upward into the first through hole, a first gap between the heat conducting stud and the conductive layer, and the second pass a second gap between the signal stud and the conductive layer; curing the adhesive layer; providing a wire comprising at least a pad, a terminal, the signal stud and a selected portion of the conductive layer; A semiconductor device is disposed on a heat sink, wherein the heat sink includes at least the heat conductive stud and the base; electrically connecting the semiconductor component to the wire; and thermally bonding the semiconductor component to the heat sink.

根據本發明之一樣式，一種製作一半導體晶片組體之方法包含：(1)提供一導熱凸柱、一訊號凸柱、一基座、一黏著層及一導電層，其中(a)該導熱凸柱係鄰接該基座，沿一向上方向延伸於該基座上方，延伸進入該黏著層之一第一開口，並對準該導電層之一第一通孔，(b)該訊號凸柱係鄰接該基座，沿該向上方向延伸於該基座上方，延伸進入該黏著層之一第二開口，並對準該導電層之一第二通孔，(c)該基座係沿一與該向上方向相反之向下方向延伸於該導熱凸柱及該訊號凸柱下方，並沿垂直於該向上及向下方向之側面方向自該導熱凸柱及該訊號凸柱側向延伸而出，(d)該黏著層係設置於該基座上，延伸於該基座上方，並位於該基座與該導電層之間，且未固化，此外，(e)該導電層係設置於該黏著層上，並延伸於該黏著層上方；(2)使該黏著層向上流入該第一通孔內一介於該導熱凸柱與該導電層間之第一缺口以及該第二通孔內一介於該訊號凸柱與該導電層間之第二缺口；(3)固化該黏著層；(4)提供一導線，該導線至少包含一焊墊、一端子、該訊號凸柱與該導電層之一選定部分；(5)設置一半導體元件於一至少包含該導熱凸柱與該基座之散熱座上，其中該半導體元件重疊於該導熱凸柱；(6)電性連結該半導體元件至該焊墊，藉此電性連結該半導體元件至該端子，其中該焊墊與該端子間之一導電路徑包含該訊號凸柱；以及(7)熱連結該半導體元件至該導熱凸柱，藉此熱連結該半導體元件至該基座。According to one aspect of the present invention, a method of fabricating a semiconductor wafer package includes: (1) providing a thermally conductive stud, a signal stud, a pedestal, an adhesive layer, and a conductive layer, wherein (a) the thermal conduction a stud is adjacent to the pedestal, extends upwardly above the pedestal in an upward direction, extends into a first opening of the adhesive layer, and is aligned with a first through hole of the conductive layer, and (b) the signal stud Adjoining the susceptor, extending in the upward direction above the pedestal, extending into a second opening of the adhesive layer, and aligning with a second through hole of the conductive layer, (c) the pedestal is along a a downward direction opposite to the upward direction extending below the heat conducting stud and the signal stud, and extending laterally from the heat conducting stud and the signal stud in a direction perpendicular to the upward and downward directions (d) the adhesive layer is disposed on the pedestal, extends over the pedestal, and is located between the pedestal and the conductive layer, and is not cured. Further, (e) the conductive layer is disposed on the pedestal Adhesive layer and extending over the adhesive layer; (2) making the adhesion The layer flows upward into the first through hole, a first gap between the heat conducting stud and the conductive layer, and a second gap between the signal stud and the conductive layer in the second through hole; (3) curing the layer (4) providing a wire, the wire comprising at least a pad, a terminal, the signal stud and a selected portion of the conductive layer; (5) providing a semiconductor component at least comprising the thermally conductive stud and a heat sink of the pedestal, wherein the semiconductor component is overlapped with the heat conducting stud; (6) electrically connecting the semiconductor component to the solder pad, thereby electrically connecting the semiconductor component to the terminal, wherein the solder pad One of the conductive paths between the terminals includes the signal stud; and (7) thermally bonding the semiconductor component to the thermally conductive stud, thereby thermally bonding the semiconductor component to the pedestal.

根據本發明之另一樣式，一種製作一半導體晶片組體之方法包含：(1)提供一導熱凸柱、一訊號凸柱與一基座，其中該導熱凸柱係鄰接且一體成形於該基座，並沿一向上方向延伸於該基座上方，該訊號凸柱係鄰接且一體成形於該基座，並沿該向上方向延伸於該基座上方，且該基座係沿一與該向上方向相反之向下方向延伸於該導熱凸柱及該訊號凸柱下方，並自該導熱凸柱及該訊號凸柱沿垂直於該向上及向下方向之側面方向側向延伸而出；(2)提供一黏著層，其中第一及第二開口延伸貫穿該黏著層；(3)提供一導電層，其中第一及第二通孔延伸貫穿該導電層；(4)設置該黏著層於該基座上，此步驟包含將該導熱凸柱***該第一開口，並將該訊號凸柱***該第二開口，其中該黏著層係延伸於該基座上方，該導熱凸柱延伸進入該第一開口，而該訊號凸柱則延伸進入該第二開口；(5)設置該導電層於該黏著層上，此步驟包含將該導熱凸柱對準該第一通孔，並將該訊號凸柱對準該第二通孔，其中該導電層係延伸於該黏著層上方，該黏著層係介於該基座與該導電層之間且未固化；(6)加熱熔化該黏著層；(7)使該基座與該導電層彼此靠合，藉此使該導熱凸柱在該第一通孔內向上移動，並使該訊號凸柱在該第二通孔內向上移動，同時對該基座與該導電層間之熔化黏著層施加壓力，該壓力迫使該熔化黏著層向上流入該第一通孔內一介於該導熱凸柱與該導電層間之第一缺口以及該第二通孔內一介於該訊號凸柱與該導電層間之第二缺口；(8)加熱固化該熔化黏著層，藉此將該導熱凸柱及該訊號凸柱及該基座機械性黏附至該導電層；(9)提供一導線，該導線至少包含一焊墊、一端子、一路由線與該訊號凸柱，其中該導線包含該導電層之一選定部分，且一位於該焊墊與該端子間之導電路徑包含該路由線與該訊號凸柱；(10)設置一半導體元件於一散熱座上，該散熱座至少包含該導熱凸柱與該基座，其中該半導體元件重疊於該導熱凸柱；(11)電性連結該半導體元件至該焊墊，藉此電性連結該半導體元件至該端子；以及(12)熱連結該半導體元件至該導熱凸柱，藉此熱連結該半導體元件至該基座。According to another aspect of the present invention, a method of fabricating a semiconductor wafer package includes: (1) providing a thermally conductive stud, a signal stud, and a pedestal, wherein the thermally conductive stud is adjacent and integrally formed on the base And extending in an upward direction above the base, the signal studs are adjacent and integrally formed on the base, and extend upward in the upward direction on the base, and the base is along the upward direction The opposite direction extends downwardly from the heat conducting stud and the signal stud, and extends laterally from the heat conducting stud and the signal stud in a direction perpendicular to the upward and downward directions; (2 Providing an adhesive layer, wherein the first and second openings extend through the adhesive layer; (3) providing a conductive layer, wherein the first and second through holes extend through the conductive layer; (4) the adhesive layer is disposed thereon The step of inserting the thermal conductive stud into the first opening and inserting the signal stud into the second opening, wherein the adhesive layer extends over the base, the thermally conductive stud extending into the first An opening, and the signal stud extends into A second opening; (5) disposed on the conductive layer On the adhesive layer, the step of aligning the thermal conductive post to the first through hole and aligning the signal stud to the second through hole, wherein the conductive layer extends over the adhesive layer, the adhesive layer Between the susceptor and the conductive layer and uncured; (6) heating and melting the adhesive layer; (7) causing the pedestal and the conductive layer to abut each other, thereby making the thermally conductive stud at the first The inside of the through hole moves upward, and the signal stud is moved upward in the second through hole, and a pressure is applied to the molten adhesive layer between the base and the conductive layer, and the pressure forces the molten adhesive layer to flow upward into the first a first gap between the heat conducting stud and the conductive layer and a second gap between the signal stud and the conductive layer in the through hole; (8) heat curing the molten adhesive layer, The conductive post and the signal stud and the base are mechanically adhered to the conductive layer; (9) providing a wire, the wire comprising at least a pad, a terminal, a routing line and the signal stud, Wherein the wire comprises a selected portion of the conductive layer, and one of the pads is located The conductive path between the terminals includes the routing line and the signal stud; (10) a semiconductor component is disposed on a heat sink, the heat sink includes at least the heat conducting stud and the base, wherein the semiconductor component overlaps the heat conducting a bump; (11) electrically connecting the semiconductor device to the pad, thereby electrically connecting the semiconductor device to the terminal; and (12) thermally bonding the semiconductor device to the thermally conductive stud, thereby thermally bonding the semiconductor Components to the base.

設置該導電層可包含：將該導電層單獨設置於該黏著層上，或者，先將該導電層黏附於一載體，再將該導電層與該載體一同設置於該黏著層上，以使該載體重疊於該導電層，而該導電層則接觸該黏著層且介於該黏著層與該載體之間，接著在該黏著層固化後，先去除該載體，再提供該導線。The conductive layer may include: the conductive layer is separately disposed on the adhesive layer, or the conductive layer is first adhered to a carrier, and the conductive layer is disposed on the adhesive layer together with the carrier, so that the conductive layer The carrier is overlapped with the conductive layer, and the conductive layer contacts the adhesive layer and is interposed between the adhesive layer and the carrier, and then after the adhesive layer is cured, the carrier is first removed and then provided The wire.

根據本發明之另一樣式，一種製作一半導體晶片組體之方法包含：(1)提供一導熱凸柱、一訊號凸柱、一基座、一黏著層及一基板，其中(a)該基板至少包含一導電層與一介電層，(b)該導熱凸柱係鄰接該基座，沿一向上方向延伸於該基座上方，延伸穿過該黏著層之一第一開口，並延伸進入該基板之一第一通孔，(c)該訊號凸柱係鄰接該基座，沿該向上方向延伸於該基座上方，延伸穿過該黏著層之一第二開口，並延伸進入該基板之一第二通孔，(d)該基座係沿一與該向上方向相反之向下方向延伸於該導熱凸柱及該訊號凸柱下方，並沿垂直於該向上及向下方向之側面方向自該導熱凸柱及該訊號凸柱側向延伸而出，(e)該黏著層係設置於該基座上，延伸於該基座上方，並位於該基座與該基板之間，且未固化，(f)該基板係設置於該黏著層上，延伸於該黏著層上方，且該導電層係延伸於該介電層上方，(g)一第一缺口係位於該第一通孔內，且介於該導熱凸柱與該基板之間，此外，(h)一第二缺口係位於該第二通孔內，且介於該訊號凸柱與該基板之間；(2)使該黏著層向上流入該等缺口；(3)固化該黏著層；(4)設置一半導體元件於一至少包含該導熱凸柱與該基座之散熱座上，其中該半導體元件重疊於該導熱凸柱，一導線至少包含一焊墊、一端子、該訊號凸柱及該導電層之一選定部分，且該焊墊與該端子間之一導電路徑包含該訊號凸柱；(5)電性連結該半導體元件至該焊墊，藉此電性連結該半導體元件至該端子；以及 (6)熱連結該半導體元件至該導熱凸柱，藉此熱連結該半導體元件至該基座。According to another aspect of the present invention, a method of fabricating a semiconductor wafer package includes: (1) providing a thermally conductive stud, a signal stud, a pedestal, an adhesive layer, and a substrate, wherein (a) the substrate Having at least a conductive layer and a dielectric layer, (b) the thermally conductive stud is adjacent to the pedestal, extends upwardly above the pedestal in an upward direction, extends through a first opening of the adhesive layer, and extends into a first through hole of the substrate, (c) the signal stud is adjacent to the base, extends upward in the upward direction above the base, extends through a second opening of the adhesive layer, and extends into the substrate a second through hole, (d) the base extends in a downward direction opposite to the upward direction below the thermally conductive stud and the signal stud, and along a side perpendicular to the upward and downward directions The direction extends laterally from the heat conducting stud and the signal stud, and (e) the adhesive layer is disposed on the base, extends above the base, and is located between the base and the substrate, and Uncured, (f) the substrate is disposed on the adhesive layer and extends over the adhesive layer, and The conductive layer extends over the dielectric layer, and (g) a first gap is located in the first via hole and between the heat conductive stud and the substrate, and (h) a second gap system Located in the second through hole and between the signal stud and the substrate; (2) causing the adhesive layer to flow upward into the gap; (3) curing the adhesive layer; (4) providing a semiconductor component a heat sink having at least the heat conducting stud and the base, wherein the semiconductor component is overlapped with the heat conducting stud, and a wire includes at least a solder pad, a terminal, the signal stud, and a selected portion of the conductive layer And the conductive path between the pad and the terminal includes the signal stud; (5) electrically connecting the semiconductor component to the pad, thereby electrically connecting the semiconductor component to the terminal; (6) thermally bonding the semiconductor component to the thermally conductive stud, thereby thermally bonding the semiconductor component to the pedestal.

根據本發明之又一樣式，一種製作一半導體晶片組體之方法包含：(1)提供一導熱凸柱、一訊號凸柱與一基座，其中該導熱凸柱係鄰接且一體成形於該基座，並沿一向上方向延伸於該基座上方，該訊號凸柱係鄰接且一體成形於該基座，並沿該向上方向延伸於該基座上方，該基座係沿一與該向上方向相反之向下方向延伸於該導熱凸柱及該訊號凸柱下方，並自該導熱凸柱及該訊號凸柱沿垂直於該向上及向下方向之側面方向側向延伸而出；(2)提供一黏著層，其中第一及第二開口延伸貫穿該黏著層；(3)提供一至少包含一導電層與一介電層之基板，其中第一及第二通孔延伸貫穿該基板；(4)設置該黏著層於該基座上，此步驟包含將該導熱凸柱穿過該第一開口，並將該訊號凸柱穿過該第二開口，其中該黏著層係延伸於該基座上方，該導熱凸柱延伸貫穿該第一開口，該訊號凸柱則延伸貫穿該第二開口；(5)設置該基板於該黏著層上，此步驟包含將該導熱凸柱***該第一通孔，並將該訊號凸柱***該第二通孔，其中該基板延伸於該黏著層上方，該導電層延伸於該介電層上方，該導熱凸柱延伸貫穿該第一開口並進入該第一通孔，該訊號凸柱延伸貫穿該第二開口並進入該第二通孔，該黏著層係介於該基座與該基板之間且未固化，一第一缺口係位於該第一通孔內且介於該導熱凸柱與該基板之間，此外，一第二缺口係位於該第二通孔內且介於該訊號凸柱與該基板之間；(6)加熱熔化該黏著層；(7)使該基座與該基板彼此靠合，藉此使該導熱凸柱在該第一通孔內向上移動，並使該訊號凸柱在該第二通孔內向上移動，同時對該基座與該基板間之熔化黏著層施加壓力，其中該壓力迫使該熔化黏著層向上流入該等缺口，且該導熱凸柱及該訊號凸柱與該熔化黏著層係延伸於該介電層上方；(8)加熱固化該熔化黏著層，藉此將該導熱凸柱及該訊號凸柱及該基座機械性黏附至該基板；(9)設置一半導體元件於一散熱座上，該散熱座至少包含該導熱凸柱與該基座，其中該半導體元件重疊於該凸柱，一導線至少包含一焊墊、一端子、該訊號凸柱及該導電層之一選定部分，且該焊墊與該端子間之一導電路徑包含該訊號凸柱；(10)電性連結該半導體元件至該焊墊，藉此電性連結該半導體元件至該端子；以及(11)熱連結該半導體元件至該導熱凸柱，藉此熱連結該半導體元件至該基座。According to still another aspect of the present invention, a method for fabricating a semiconductor wafer package includes: (1) providing a thermally conductive stud, a signal stud, and a pedestal, wherein the thermally conductive stud is adjacent and integrally formed on the base And extending in an upward direction above the base, the signal studs are adjacent and integrally formed on the base, and extend in the upward direction above the base, the base is along an upward direction The opposite direction extends downwardly from the heat conducting stud and the signal stud, and extends laterally from the heat conducting stud and the signal stud in a direction perpendicular to the upward and downward directions; (2) Providing an adhesive layer, wherein the first and second openings extend through the adhesive layer; (3) providing a substrate including at least one conductive layer and a dielectric layer, wherein the first and second through holes extend through the substrate; 4) disposing the adhesive layer on the pedestal, the step of passing the thermal conductive stud through the first opening, and passing the signal stud through the second opening, wherein the adhesive layer extends over the pedestal Above, the heat conducting stud extends through the first opening, The signal stud extends through the second opening; (5) the substrate is disposed on the adhesive layer, the step of inserting the thermal conductive post into the first through hole, and inserting the signal stud into the second through hole The substrate extends above the adhesive layer, and the conductive layer extends above the dielectric layer, the heat conductive protrusion extends through the first opening and enters the first through hole, and the signal protrusion extends through the second opening And entering the second through hole, the adhesive layer is between the pedestal and the substrate and is not cured, a first notch is located in the first through hole and between the thermal conductive stud and the substrate In addition, a second gap is located in the second through hole and is between the signal protrusion and the (6) heating and melting the adhesive layer; (7) causing the base and the substrate to abut each other, thereby moving the thermally conductive stud upward in the first through hole, and causing the signal stud Moving upward in the second through hole while applying pressure to the molten adhesive layer between the base and the substrate, wherein the pressure forces the molten adhesive layer to flow upward into the gap, and the thermally conductive stud and the signal stud And the molten adhesive layer extends over the dielectric layer; (8) heat curing the molten adhesive layer, thereby mechanically adhering the thermally conductive stud and the signal stud and the base to the substrate; (9) A semiconductor device is disposed on a heat sink, the heat sink includes at least the heat conducting stud and the base, wherein the semiconductor component is overlapped with the stud, and a wire includes at least a solder pad, a terminal, the signal stud and a selected portion of the conductive layer, and a conductive path between the pad and the terminal includes the signal stud; (10) electrically connecting the semiconductor component to the pad, thereby electrically connecting the semiconductor component to the a terminal; and (11) thermally bonding the semiconductor component to Thermally conductive boss, whereby the semiconductor element is thermally coupled to the base.

提供該導熱凸柱、該訊號凸柱與該基座可包含：提供一金屬板；於該金屬板上形成一圖案化之蝕刻阻層，其選擇性曝露該金屬板；蝕刻該金屬板，使其形成該圖案化之蝕刻阻層所定義之圖案，藉此於該金屬板上形成一凹槽，其延伸進入但未貫穿該金屬板；而後去除該圖案化之蝕刻阻層，其中該導熱凸柱包含該金屬板之一第一未受蝕刻部分，該第一未受蝕刻部分係突出於該基座上方，且被該凹槽側向環繞，該訊號凸柱則包含該金屬板之一第二未受蝕刻部分，該第二未受蝕刻部分係突出於該基座上方，且被該凹槽側向環繞，該基座亦為該金屬板之一未受蝕刻部分，此未受蝕刻部分係位於該導熱凸柱及該訊號凸柱與該凹槽下方。Providing the thermal conductive stud, the signal stud and the base may include: providing a metal plate; forming a patterned etch stop layer on the metal plate, selectively exposing the metal plate; etching the metal plate to Forming a pattern defined by the patterned etch stop layer, thereby forming a recess on the metal plate that extends into but not through the metal plate; and then removes the patterned etch stop layer, wherein the thermal conductive convex The pillar includes a first unetched portion of the metal plate, the first unetched portion protrudes above the pedestal and is laterally surrounded by the groove, and the signal stud includes one of the metal plates a second unetched portion protruding above the pedestal and being The recess is laterally surrounded, and the base is also an unetched portion of the metal plate. The unetched portion is located under the thermally conductive stud and the signal stud and the recess.

提供該黏著層可包含：提供一未固化環氧樹脂之膠片。使該黏著層流動可包含：熔化該未固化環氧樹脂；並擠壓該基座與該基板間之該未固化環氧樹脂。固化該黏著層可包含：固化該熔化之未固化環氧樹脂。Providing the adhesive layer can comprise: providing a film of uncured epoxy. Flowing the adhesive layer can include: melting the uncured epoxy resin; and pressing the uncured epoxy resin between the susceptor and the substrate. Curing the adhesive layer can include curing the melted uncured epoxy resin.

提供該散熱座可包含：在固化該黏著層之後與設置該半導體元件之前，於該導熱凸柱上提供一蓋體，該蓋體位於該導熱凸柱之一頂部上方，鄰接該導熱凸柱之頂部，同時從上方覆蓋該導熱凸柱之頂部，且自該導熱凸柱之頂部沿該等側面方向側向延伸而出。Providing the heat sink can include: providing a cover on the heat conducting stud after curing the adhesive layer and before disposing the semiconductor component, the cover being located above a top of one of the heat conducting studs, adjacent to the heat conducting stud The top portion covers the top of the thermally conductive stud from above and extends laterally from the top of the thermally conductive stud in the lateral direction.

提供該焊墊可包含：在固化該黏著層之後，去除該導電層之選定部分。Providing the bond pad can include removing selected portions of the conductive layer after curing the adhesive layer.

提供該焊墊亦可包含：在固化該黏著層之後，研磨該導熱凸柱、該訊號凸柱、該黏著層及該導電層，以使該導熱凸柱、該訊號凸柱、該黏著層及該導電層在一面向該向上方向之上側表面係彼此側向齊平；而後去除該導電層之選定部分，以使該焊墊包含該導電層之選定部分。所述研磨可包含：研磨該黏著層而不研磨該導熱凸柱及該訊號凸柱；而後研磨該導熱凸柱、該訊號凸柱、該黏著層及該導電層。所述去除可包含：利用一可定義該焊墊之圖案化蝕刻阻層對該導電層進行濕式化學蝕刻。The bonding pad may further include: after curing the adhesive layer, grinding the thermal conductive stud, the signal stud, the adhesive layer and the conductive layer to make the thermal conductive stud, the signal stud, the adhesive layer and The conductive layers are laterally flush with each other on a side surface facing the upward direction; and then selected portions of the conductive layer are removed such that the pads comprise selected portions of the conductive layer. The polishing may include: grinding the adhesive layer without grinding the thermal conductive stud and the signal stud; and then grinding the thermally conductive stud, the signal stud, the adhesive layer and the conductive layer. The removing may include: wet chemical etching the conductive layer with a patterned etch stop layer defining the pad.

提供該焊墊亦可包含：在研磨完成後，於該導熱凸柱、該訊號凸柱、該黏著層與該導電層上沉積導電金屬以形成一第二導電層；然後去除該導電層及該第二導電層之選定部分，以使該焊墊包含該導電層及該第二導電層之選定部分。沉積導電金屬以形成該第二導電層可包含：將一第一被覆層以無電鍍被覆之方式設於該導熱凸柱、該訊號凸柱、該黏著層與該導電層上；而後將一第二被覆層以電鍍方式設於該第一被覆層上。所述去除可包含：利用可定義該焊墊之圖案化蝕刻阻層對該導電層及該第二導電層進行濕式化學蝕刻。Providing the bonding pad may also include: after the polishing is completed, the thermal conductive stud Depositing a conductive metal on the conductive pillar, the adhesive layer and the conductive layer to form a second conductive layer; then removing the conductive layer and selected portions of the second conductive layer, so that the solder pad comprises the conductive layer and a selected portion of the second conductive layer. Depositing the conductive metal to form the second conductive layer may include: disposing a first coating layer on the thermally conductive stud, the signal stud, the adhesive layer and the conductive layer in an electroless plating manner; The second coating layer is electroplated on the first coating layer. The removing may include: performing wet chemical etching on the conductive layer and the second conductive layer by using a patterned etch stop layer defining the pad.

提供該端子可包含：在固化該黏著層之後，去除該基座之選定部分。所述去除可包含：利用可定義該端子之圖案化蝕刻阻層對該基座進行濕式化學蝕刻，以使該端子包含該基座之一未受蝕刻部分，此未受蝕刻部分鄰接該訊號凸柱，且與該基座分離，彼此隔開，故已非該基座之一部分。如此一來，該焊墊與該端子便可於同一濕式化學蝕刻步驟中利用不同之圖案化蝕刻阻層同時形成。Providing the terminal can include removing a selected portion of the susceptor after curing the adhesive layer. The removing may include wet chemical etching the susceptor with a patterned etch stop layer defining the terminal such that the terminal includes an unetched portion of the pedestal, the unetched portion abutting the signal The studs are separated from the base and spaced apart from each other and are therefore not part of the base. In this way, the pad and the terminal can be simultaneously formed by using different patterned etching resist layers in the same wet chemical etching step.

提供該蓋體可包含：去除該第二導電層之選定部分。提供該蓋體亦可包含：先完成前述研磨，然後利用可定義該蓋體之圖案化蝕刻阻層去除該第二導電層之選定部分，以使該蓋體包含該第二導電層之選定部分。如此一來，該焊墊與該蓋體便可透過同一研磨工序，並於同一濕式化學蝕刻步驟中利用同一圖案化蝕刻阻層同時形成。Providing the cover can include removing selected portions of the second conductive layer. Providing the cover may further comprise: first performing the grinding, and then removing a selected portion of the second conductive layer by using a patterned etch stop layer defining the cover such that the cover includes a selected portion of the second conductive layer . In this way, the pad and the cover can pass through the same polishing process and are simultaneously formed by the same patterned etching resist in the same wet chemical etching step.

使該黏著層流動可包含：以該黏著層填滿該等缺口。使該黏著層流動亦可包含：擠壓該黏著層，使其通過該等缺口，到達該導熱凸柱、該訊號凸柱與該基板上方，並及於該導熱凸柱及該訊號凸柱頂面與該基板頂面鄰接該等缺口之部分。Flowing the adhesive layer can include filling the gaps with the adhesive layer. Flowing the adhesive layer may also include: pressing the adhesive layer to pass the same The notch reaches the heat conducting stud, the signal stud and the upper portion of the substrate, and the heat conducting stud and the top surface of the signal stud are adjacent to the top surface of the substrate.

固化該黏著層可包含：將該導熱凸柱、該訊號凸柱與該基座機械性結合於該基板。Curing the adhesive layer can include mechanically bonding the thermally conductive stud, the signal stud, and the base to the substrate.

設置該半導體元件可包含：將該半導體元件設置於該蓋體上。設置該半導體元件亦可包含：將該半導體元件設置於該導熱凸柱、該蓋體、該第一開口與該第一通孔上方，並使該半導體元件重疊於該導熱凸柱、該蓋體、該第一開口與該第一通孔，但不重疊於該訊號凸柱、該第二開口與該第二通孔。Providing the semiconductor device may include disposing the semiconductor element on the cover. The semiconductor device may further include: the semiconductor device is disposed on the heat conducting stud, the cover, the first opening and the first through hole, and the semiconductor element is overlapped with the heat conducting stud, the cover The first opening and the first through hole do not overlap the signal post, the second opening and the second through hole.

設置該半導體元件可包含：提供一第一焊錫與一第二焊錫，其中該第一焊錫位於一包含LED晶片之LED封裝體與該焊墊之間，該第二焊錫則位於該LED封裝體與該蓋體之間。電性連結該半導體元件可包含：在該LED封裝體與該焊墊之間提供該第一焊錫。熱連結該半導體元件可包含：在該LED封裝體與該蓋體之間提供該第二焊錫。The disposing the semiconductor device may include: providing a first solder and a second solder, wherein the first solder is located between an LED package including an LED chip and the bonding pad, and the second solder is located in the LED package Between the covers. Electrically connecting the semiconductor component can include providing the first solder between the LED package and the pad. Thermally bonding the semiconductor component can include providing the second solder between the LED package and the cover.

設置該半導體元件可包含：在一半導體晶片與該蓋體之間提供一固晶材料。電性連結該半導體元件可包含：在該晶片與該焊墊之間提供一打線。熱連結該半導體元件可包含：在該晶片與該蓋體之間提供該固晶材料。Providing the semiconductor device can include providing a die bond material between a semiconductor wafer and the cover. Electrically bonding the semiconductor component can include providing a wire between the wafer and the pad. Thermally bonding the semiconductor component can include providing the die attach material between the wafer and the cover.

該黏著層可接觸該導熱凸柱、該訊號凸柱、該基座、該蓋體與該介電層，從下方覆蓋該基板，於該等側面方向覆蓋並環繞該導熱凸柱及該訊號凸柱，並延伸至該組體製造完成後與同批生產之其他組體分離所形成之外圍邊緣。The adhesive layer can contact the heat conducting stud, the signal stud, the base, the cover and the dielectric layer, covering the substrate from below, covering and surrounding the heat conducting stud and the signal convex in the side directions Column and extend to the group system After the completion of the fabrication, the peripheral edges formed by separation from other groups produced in the same batch are formed.

當該組體製造完成且與同批生產之其他組體分離後，該基座可從下方覆蓋該半導體元件、該導熱凸柱與該蓋體，同時支撐該基板，並與該組體之外圍邊緣保持距離。After the assembly is manufactured and separated from other groups of the same batch, the pedestal can cover the semiconductor element, the thermally conductive stud and the cover from below, while supporting the substrate and surrounding the group Keep the distance at the edge.

本發明具有多項優點。該散熱座可提供優異之散熱效果，並使熱能不流經該黏著層。因此，該黏著層可為低導熱性之低成本電介質且不易脫層。該導熱凸柱與該基座可一體成形以提高可靠度。該蓋體可為該半導體元件量身訂做以提升熱連結之效果。該黏著層可介於該導熱凸柱及該訊號凸柱與該基板之間以及該基座與該基板之間，藉以在該散熱座與該基板之間提供堅固之機械性連結。該導線可形成簡單之電路圖案以提供訊號路由，或形成複雜之電路圖案以實現具彈性之多層訊號路由。該導線亦可在該介電層上方之該焊墊與該黏著層下方之該端子之間提供垂直訊號路由。該基座可為該基板提供機械性支撐，防止其彎曲變形。該組體可利用低溫工序製造，不僅降低應力，亦提高可靠度。該組體亦可利用電路板、導線架與捲帶式基板製造廠可輕易實施之高控制工序加以製造。The invention has several advantages. The heat sink provides excellent heat dissipation and allows thermal energy to flow through the adhesive layer. Therefore, the adhesive layer can be a low-cost dielectric with low thermal conductivity and is not easily delaminated. The thermally conductive stud can be integrally formed with the base to improve reliability. The cover body can be tailored to the semiconductor component to enhance the effect of thermal bonding. The adhesive layer can be interposed between the heat conducting stud and the signal stud and the substrate and between the base and the substrate, thereby providing a strong mechanical connection between the heat sink and the substrate. The wires can form a simple circuit pattern to provide signal routing or to form complex circuit patterns for flexible multilayer signal routing. The wire can also provide a vertical signal routing between the pad above the dielectric layer and the terminal below the adhesive layer. The pedestal provides mechanical support for the substrate to prevent it from bending and deforming. The assembly can be manufactured by a low temperature process, which not only reduces stress but also improves reliability. The assembly can also be fabricated using high control procedures that can be easily implemented by circuit boards, lead frames, and tape and roll substrate manufacturers.

本發明之上述及其他特徵與優點將於下文中藉由各種實施例進一步加以說明。The above and other features and advantages of the present invention will be further described hereinafter by way of various embodiments.

圖1A至圖1D為剖視圖，繪示本發明之一實施例中一種製作一導熱凸柱22、一訊號凸柱24與一基座26之方法，圖1E及圖1F分別為圖1D之俯視圖及仰視圖。1A to 1D are cross-sectional views showing a method of fabricating a thermally conductive stud 22, a signal stud 24 and a pedestal 26 in accordance with an embodiment of the present invention, and FIGS. 1E and 1F are top views of FIG. 1D, respectively. Bottom view.

圖1A為金屬板10之剖視圖，金屬板10包含相背之主要表面12及14。圖示之金屬板10係一厚度為330微米之銅板。銅具有導熱性高、結合性良好與低成本等優點。金屬板10可由多種金屬製成，如銅、鋁、鐵鎳合金42、鐵、鎳、銀、金、其混合物及其合金。1A is a cross-sectional view of a metal plate 10 that includes opposing major surfaces 12 and 14. The illustrated metal plate 10 is a copper plate having a thickness of 330 microns. Copper has the advantages of high thermal conductivity, good bonding and low cost. The metal plate 10 can be made of a variety of metals such as copper, aluminum, iron-nickel alloy 42, iron, nickel, silver, gold, mixtures thereof, and alloys thereof.

圖1B為一剖視圖，顯示金屬板10上形成有一圖案化之蝕刻阻層16與一全面覆蓋之蝕刻阻層18。圖示之圖案化之蝕刻阻層16與全面覆蓋之蝕刻阻層18係沉積於金屬板10上之光阻層，其製作方式係利用壓模技術以熱滾輪同時將光阻層分別壓合於表面12及14。濕性旋塗法及淋幕塗佈法亦為適用之光阻形成技術。將一光罩(圖未示)靠合於光阻層，然後依照習知技術，令光線選擇性通過光罩，使受光之光阻部分變為不可溶解；之後再以顯影液去除未受光且仍可溶解之光阻部分，使光阻層形成圖案。因此，圖案化之蝕刻阻層16具有一可選擇性曝露表面12之圖案，而全面覆蓋之蝕刻阻層18則無圖案且覆蓋表面14。1B is a cross-sectional view showing a patterned etch stop layer 16 and a etch stop layer 18 overlying the metal plate 10. The patterned etch stop layer 16 and the over-etched etch stop layer 18 are deposited on the metal plate 10 in a photoresist layer. The photoresist layer is used to simultaneously press the photoresist layer with a hot roller. Surfaces 12 and 14. Wet spin coating and curtain coating are also suitable photoresist forming techniques. A reticle (not shown) is placed on the photoresist layer, and then light is selectively passed through the reticle to make the light-receiving portion of the light-receivable portion insoluble according to conventional techniques; The photoresist portion, which is still soluble, forms a pattern of the photoresist layer. Thus, the patterned etch stop layer 16 has a pattern of selectively exposed surface 12, while the overlying etch stop layer 18 is unpatterned and covers the surface 14.

圖1C為一剖視圖，顯示金屬板10形成有掘入但未穿透金屬板10之凹槽20。凹槽20係以蝕刻金屬板10之方式形成，以使金屬板10形成由圖案化之蝕刻阻層16所定義之圖案。圖示之蝕刻方式為正面濕式化學蝕刻。例如，可將結構體反轉，使圖案化之蝕刻阻層16朝下，而全面覆蓋之蝕刻阻層18朝上，然後利用一面向圖案化蝕刻阻層16之底部噴嘴(圖未示)將化學蝕刻液朝上噴灑於金屬板10及圖案化之蝕刻阻層16，在此同時，一面向全面覆蓋之蝕刻阻層18之頂部噴嘴(圖未示)則不予啟動，如此一來便可借助重力去除蝕刻之副產物。或者，利用全面覆蓋之蝕刻阻層18提供背面保護，亦可將結構體浸入化學蝕刻液中以形成凹槽20。所述化學蝕刻液對銅具有高度針對性，且可刻入金屬板10達300微米。因此，凹槽20自表面12延伸進入但未穿透金屬板10，與表面14距離30微米，深度則為300微米。化學蝕刻液亦對圖案化之蝕刻阻層16下方之金屬板10造成側向蝕入。適用之化學蝕刻液可為含鹼氨之溶液或硝酸與鹽酸之稀釋混合物。換言之，所述化學蝕刻液可為酸性或鹼性。足以形成凹槽20而不致使金屬板10過度曝露於化學蝕刻液之理想蝕刻時間可由試誤法決定。1C is a cross-sectional view showing the metal plate 10 formed with a recess 20 which is dug but does not penetrate the metal plate 10. The recess 20 is formed by etching the metal plate 10 such that the metal plate 10 forms a pattern defined by the patterned etch stop layer 16. The etching method shown is a front wet chemical etching. For example, the structure can be reversed such that the patterned etch stop layer 16 faces downward, while the overlying etch stop layer 18 faces upward, and then a bottom nozzle (not shown) that faces the patterned etch stop layer 16 The chemical etching solution is sprayed upward on the metal plate 10 and the patterned etching resist layer 16, while at the same time, an etching is provided for the full coverage. The top nozzle (not shown) of the resist layer 18 is not activated, so that the by-product of the etching can be removed by gravity. Alternatively, the backside protection can be provided by a fully covered etch stop layer 18, and the structure can also be immersed in a chemical etchant to form the recess 20. The chemical etchant is highly targeted to copper and can be engraved into the metal sheet 10 up to 300 microns. Thus, the recess 20 extends from the surface 12 but does not penetrate the metal sheet 10, 30 microns from the surface 14, and 300 microns deep. The chemical etchant also causes lateral etch in the metal plate 10 beneath the patterned etch stop layer 16. Suitable chemical etching solutions can be alkaline ammonia-containing solutions or diluted mixtures of nitric acid and hydrochloric acid. In other words, the chemical etching solution can be acidic or alkaline. The ideal etching time sufficient to form the recess 20 without causing the metal plate 10 to be excessively exposed to the chemical etchant can be determined by trial and error.

圖1D、圖1E及圖1F分別為去除圖案化之蝕刻阻層16及全面覆蓋之蝕刻阻層18後之金屬板10之剖視圖、俯視圖及仰視圖，其中案化之蝕刻阻層16與全面覆蓋之蝕刻阻層18已經溶劑處理去除。例如，所用溶劑可為pH為14之強鹼性氫氧化鉀溶液。1D, FIG. 1E, and FIG. 1F are respectively a cross-sectional view, a top view, and a bottom view of the metal plate 10 after the patterned etch stop layer 16 and the etch stop layer 18 are completely covered, wherein the etched resist layer 16 and the full cover are respectively covered. The etch stop layer 18 has been removed by solvent treatment. For example, the solvent used may be a strong alkaline potassium hydroxide solution having a pH of 14.

蝕刻後之金屬板10因此包含導熱凸柱22、訊號凸柱24及基座26。The etched metal plate 10 thus includes a thermally conductive stud 22, a signal stud 24, and a pedestal 26.

導熱凸柱22為金屬板10受圖案化之蝕刻阻層16保護之一第一未受蝕刻部分。導熱凸柱22係鄰接基座26，與基座26形成一體，且突伸於基座26上方，並由凹槽20從側向包圍。導熱凸柱22高300微米(等於凹槽20之深度)，其頂面(表面12之圓形部分)之直徑為1000微米，而底部(鄰接基座26之圓形部分)之直徑則為1100微米。因此，導熱凸柱22呈平頂錐柱形(類似一平截頭體)，其側壁漸縮，直徑則自基座26處朝其平坦圓形頂面向上遞減。該漸縮側壁係因化學蝕刻液側向蝕入圖案化之蝕刻阻層16下方而形成。該頂面與該底部之圓周同心(如圖1E所示)。The thermally conductive studs 22 are one of the first unetched portions of the metal plate 10 protected by the patterned etch stop layer 16. The thermally conductive stud 22 is adjacent to the base 26 and is integral with the base 26 and projects above the base 26 and is laterally surrounded by the recess 20. The thermally conductive stud 22 is 300 microns high (equal to the depth of the groove 20), the top surface (the circular portion of the surface 12) having a diameter of 1000 microns, and the bottom portion (the circular portion adjacent the pedestal 26) having a diameter of 1100. Micron. Therefore, heat conduction The stud 22 has a flat-topped tapered cylindrical shape (like a frustum) with its side walls tapered and the diameter decreasing from the base 26 toward its flat circular top surface. The tapered sidewalls are formed by lateral etching of the chemical etchant into the patterned etch stop layer 16. The top surface is concentric with the circumference of the bottom (as shown in Figure 1E).

訊號凸柱24為金屬板10受圖案化之蝕刻阻層16保護之一第二未受蝕刻部分。訊號凸柱24係鄰接基座26，與基座26形成一體，且突伸於基座26上方，並由凹槽20從側向包圍。訊號凸柱24高300微米(等於凹槽20之深度)，其頂面(表面12之圓形部分)之直徑為300微米，而底部(鄰接基座26之圓形部分)之直徑則為400微米。因此，訊號凸柱24呈平頂錐柱形(類似一平截頭體)，其側壁漸縮，直徑則自基座26處朝其平坦圓形頂面向上遞減。該漸縮側壁係因化學蝕刻液側向蝕入圖案化之蝕刻阻層16下方而形成。該頂面與該底部之圓周同心(如圖1E所示)。The signal studs 24 are one of the second unetched portions of the metal plate 10 protected by the patterned etch stop layer 16. The signal stud 24 is adjacent to the base 26 and is integral with the base 26 and projects above the base 26 and is laterally surrounded by the recess 20. The signal stud 24 is 300 microns high (equal to the depth of the groove 20), the top surface (the circular portion of the surface 12) has a diameter of 300 microns, and the bottom portion (the circular portion adjacent the pedestal 26) has a diameter of 400. Micron. Thus, the signal studs 24 are in the form of a flat-topped conical cylinder (like a frustum) with the side walls tapered and the diameter decreasing from the base 26 toward its flat circular top surface. The tapered sidewalls are formed by lateral etching of the chemical etchant into the patterned etch stop layer 16. The top surface is concentric with the circumference of the bottom (as shown in Figure 1E).

基座26為金屬板10在導熱凸柱22與訊號凸柱24下方之一未受蝕刻部分，並自導熱凸柱22、訊號凸柱24沿一側向平面(如左、右等側面方向)側向延伸，厚度為30微米(即330微米減去300微米)。The pedestal 26 is an unetched portion of the metal plate 10 below the heat conducting stud 22 and the signal stud 24, and is laterally oriented from the heat conducting stud 22 and the signal stud 24 (such as the left and right sides). Laterally extending, the thickness is 30 microns (ie 330 microns minus 300 microns).

導熱凸柱22、訊號凸柱24與基座26可經處理以加強與環氧樹脂及焊料之結合度。例如，導熱凸柱22、訊號凸柱24與基座26可經化學氧化或微蝕刻以產生較粗糙之表面。The thermally conductive studs 22, signal posts 24 and pedestal 26 can be treated to enhance bonding to epoxy and solder. For example, the thermally conductive studs 22, the signal studs 24, and the pedestal 26 can be chemically oxidized or microetched to create a rougher surface.

導熱凸柱22、訊號凸柱24與基座26在圖式中為透過削減法形成之單一金屬(銅)體。此外，亦可利用一接觸件沖壓金屬板10，其中該接觸件具有可定義導熱凸柱22之第一凹槽或孔洞以及可定義訊號凸柱24之第二凹槽或孔洞，俾使導熱凸柱22、訊號凸柱24與基座26成為沖壓成型之單一金屬體。或者，可利用增添法形成導熱凸柱22、訊號凸柱24，其作法係透過電鍍、化學氣相沉積(CVD)、物理氣相沉積(PVD)等技術，將導熱凸柱22、訊號凸柱24沉積於基座26上。例如，可於銅質基座26上電鍍焊料導熱凸柱22及焊料訊號凸柱24；在此情況下，導熱凸柱22與基座26係以冶金介面相接，彼此鄰接但並非一體成形，訊號凸柱24與基座26係以冶金介面相接，彼此鄰接但並非一體成形。或者，可利用半增添法形成導熱凸柱22、訊號凸柱24，例如可於導熱凸柱22、訊號凸柱24其蝕刻形成之下部上方分別沉積導熱凸柱22、訊號凸柱24之上部。此外，導熱凸柱22、訊號凸柱24與基座26亦可同時以半增添法形成，例如可在導熱凸柱22、訊號凸柱24與基座26其蝕刻形成之下部上方分別沉積導熱凸柱22、訊號凸柱24與基座26之同形上部。導熱凸柱22、訊號凸柱24亦可燒結於基座26。The thermally conductive studs 22, the signal studs 24 and the pedestal 26 are in the form of a single metal (copper) body formed by a reduction process. In addition, you can also use a contact to punch Pressing the metal plate 10, wherein the contact member has a first groove or hole defining a heat conducting stud 22 and a second groove or hole defining the signal stud 24, so that the heat conducting stud 22 and the signal stud 24 are The susceptor 26 is a single metal body that is stamped and formed. Alternatively, the thermally conductive studs 22 and the signal studs 24 may be formed by an additive method, and the thermally conductive studs 22 and the signal studs may be passed through electroplating, chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. 24 is deposited on the susceptor 26. For example, the solder thermally conductive studs 22 and the solder signal studs 24 can be plated on the copper pedestal 26; in this case, the thermally conductive studs 22 and the pedestal 26 are joined by a metallurgical interface, adjacent to each other but not integrally formed. The signal studs 24 and the pedestal 26 are joined by a metallurgical interface, adjacent to each other but not integrally formed. Alternatively, the thermally conductive studs 22 and the signal studs 24 can be formed by a semi-additive method. For example, the thermally conductive studs 22 and the upper portions of the signal studs 24 can be respectively deposited on the lower portions of the thermally conductive studs 22 and the signal studs 24. In addition, the heat conducting studs 22, the signal studs 24 and the pedestal 26 can also be formed by a semi-additive method. For example, thermal conductive bumps can be respectively deposited on the lower portions of the thermally conductive studs 22, the signal studs 24 and the pedestals 26. The column 22, the signal stud 24 and the base 26 have the same upper portion. The thermally conductive studs 22 and the signal studs 24 can also be sintered to the pedestal 26.

圖2A及圖2B為剖視圖，說明本發明之一實施例中一種製作黏著層28之方法。圖2C及圖2D分別為根據圖2B所繪製之俯視圖及仰視圖。2A and 2B are cross-sectional views illustrating a method of making an adhesive layer 28 in accordance with one embodiment of the present invention. 2C and 2D are a plan view and a bottom view, respectively, according to FIG. 2B.

圖2A為黏著層28之剖視圖，其中黏著層28為乙階(B-stage)未固化環氧樹脂之膠片，其為一未經固化且無圖案之片體，厚180微米。2A is a cross-sectional view of the adhesive layer 28 in which the adhesive layer 28 is a B-stage uncured epoxy film which is an uncured and unpatterned sheet having a thickness of 180 microns.

黏著層28可為多種有機或無機電性絕緣體製成之各種介電膜或膠片。例如，黏著層28起初可為一膠片，其中樹脂型態之熱固性環氧樹脂浸入一加強材料後部分固化至中期。所述環氧樹脂可為FR-4，但亦可使用諸如多官能與雙馬來醯亞胺-三氮雜苯(BT)樹脂等其他環氧樹脂。在特定應用中，氰酸酯、聚醯亞胺及聚四氟乙烯(PTFE)亦為可用之環氧樹脂。所述加強材料可為電子級玻璃，亦可為其他加強材料，如高強度玻璃、低誘電率玻璃、石英、克維拉纖維(kevlar aramid)及紙等。所述加強材料也可為織物、不織布或無方向性微纖維。可將諸如矽(研粉熔融石英)等填充物加入膠片中以提升導熱性、熱衝擊阻抗力與熱膨脹匹配性。可利用市售預浸漬體，如美國威斯康辛州奧克萊W.L.Gore & Associates之SPEEDBOARD C膠片即為一例。Adhesive layer 28 can be a variety of dielectric films or films made from a variety of organic or inorganic electrical insulators. For example, the adhesive layer 28 may initially be a film in which the resin-type thermosetting epoxy resin is partially cured to a medium stage after being immersed in a reinforcing material. The epoxy resin may be FR-4, but other epoxy resins such as polyfunctional and bismaleimide-triazabenzene (BT) resins may also be used. Cyanate esters, polyimine and polytetrafluoroethylene (PTFE) are also useful epoxy resins in certain applications. The reinforcing material may be an electronic grade glass, or may be other reinforcing materials such as high-strength glass, low-induced glass, quartz, kevlar aramid, and paper. The reinforcing material may also be a woven fabric, a non-woven fabric or a non-directional microfiber. Fillers such as enamel (melt fused silica) can be added to the film to improve thermal conductivity, thermal shock resistance and thermal expansion matching. Commercially available prepregs can be utilized, such as the SPEEDBOARD C film from W. L. Gore & Associates of Oakley, Wisconsin, USA.

圖2B、圖2C及圖2D分別為具有開口30、32之黏著層28的剖視圖、俯視圖及仰視圖。開口30貫穿黏著層28且直徑為1150微米。開口32貫穿黏著層28且直徑為450微米。開口30、32係以機械方式鑽透該膠片而形成，但亦可以其他技術製作，如沖製及沖壓等。2B, 2C, and 2D are cross-sectional, top, and bottom views, respectively, of the adhesive layer 28 having openings 30,32. The opening 30 extends through the adhesive layer 28 and has a diameter of 1150 microns. Opening 32 extends through adhesive layer 28 and has a diameter of 450 microns. The openings 30, 32 are formed by mechanically drilling through the film, but may be fabricated by other techniques, such as stamping and stamping.

圖3A及圖3B為剖視圖，說明本發明之一實施例中一種製作基板34之方法，而圖3C及圖3D則分別為根據圖3B繪製之俯視圖及仰視圖。3A and 3B are cross-sectional views illustrating a method of fabricating a substrate 34 in accordance with an embodiment of the present invention, and FIGS. 3C and 3D are a plan view and a bottom view, respectively, according to FIG. 3B.

圖3A係基板34之剖視圖。基板34包含導電層36與介電層38。導電層36為電性導體，其接觸介電層38且延伸於介電層38上方。介電層38則為電性絕緣體。例如，導電層36係一無圖案且厚度為30微米之銅板，而介電層38則為厚度為150微米之環氧樹脂。3A is a cross-sectional view of the substrate 34. The substrate 34 includes a conductive layer 36 and a dielectric layer 38. Conductive layer 36 is an electrical conductor that contacts dielectric layer 38 and extends over dielectric layer 38. Dielectric layer 38 is an electrical insulator. E.g, The conductive layer 36 is a copper plate having a pattern of 30 micrometers in thickness, and the dielectric layer 38 is an epoxy resin having a thickness of 150 micrometers.

圖3B、圖3C及圖3D分別為具有通孔40、42之基板34之剖視圖、俯視圖及仰視圖。通孔40貫穿基板34且直徑為1150微米。通孔42貫穿基板34且直徑為450微米。通孔40、42係以機械方式鑽透導電層36與介電層38而形成，但亦可以其他技術製作，如沖製及沖壓等。較佳者，開口30與通孔40具有相同直徑，且係以相同之鑽頭在同一鑽台上透過相同方式形成；而開口32與通孔42亦具有相同直徑，且係以相同之鑽頭在同一鑽台上透過相同方式形成。3B, 3C, and 3D are a cross-sectional view, a plan view, and a bottom view, respectively, of the substrate 34 having the through holes 40, 42. The through hole 40 penetrates the substrate 34 and has a diameter of 1150 μm. The through hole 42 penetrates the substrate 34 and has a diameter of 450 μm. The through holes 40, 42 are formed by mechanically drilling through the conductive layer 36 and the dielectric layer 38, but may be fabricated by other techniques such as punching and stamping. Preferably, the opening 30 has the same diameter as the through hole 40 and is formed in the same manner on the same drill floor by the same drill bit; and the opening 32 and the through hole 42 also have the same diameter and are the same drill bit in the same The drill floor is formed in the same way.

基板34在此繪示為一層壓結構，但基板34亦可為其他電性相連體，如陶瓷板或印刷電路板。同樣地，基板34可另包含複數個內嵌電路之層體。The substrate 34 is illustrated as a laminate structure, but the substrate 34 can also be other electrically connected bodies, such as ceramic plates or printed circuit boards. Similarly, the substrate 34 can further comprise a plurality of layers of embedded circuits.

圖4A至圖4L為剖視圖，說明本發明之一實施例中一種製作導熱板74之方法，該導熱板74包含導熱凸柱22、訊號凸柱24、基座26、黏著層28及基板34。圖4M及圖4N分別為圖4L之俯視圖及仰視圖。4A-4L are cross-sectional views illustrating a method of fabricating a thermally conductive plate 74 that includes a thermally conductive stud 22, a signal stud 24, a pedestal 26, an adhesive layer 28, and a substrate 34, in accordance with an embodiment of the present invention. 4M and 4N are a plan view and a bottom view, respectively, of FIG. 4L.

圖4A為黏著層28設置於基座26上之剖視圖。黏著層28係下降至基座26上，使導熱凸柱22向上***並貫穿開口30，而訊號凸柱24則向上***並貫穿開口32，最終則使黏著層28接觸並定位於基座26。較佳者，導熱凸柱22在***及貫穿開口30後係對準開口30且位於開口30內之中央位置但不接觸黏著層28；而訊號凸柱24在***及貫穿開口32後亦對準開口32且位於開口32內之中央位置但不接觸黏著層28。4A is a cross-sectional view showing the adhesive layer 28 disposed on the susceptor 26. The adhesive layer 28 is lowered onto the base 26 such that the thermally conductive studs 22 are inserted upwardly through the opening 30, and the signal studs 24 are inserted upwardly through the opening 32, and finally the adhesive layer 28 is contacted and positioned on the base 26. Preferably, the thermally conductive stud 22 is aligned with the opening 30 after being inserted into and through the opening 30 and is located at a central position within the opening 30 but does not contact the adhesive layer 28; and the signal stud 24 is inserted and penetrated The opening 32 is also aligned with the opening 32 and is located centrally within the opening 32 but does not contact the adhesive layer 28.

在圖4B所示結構中，基板34係設置於黏著層28上。基板34係下降至黏著層28上，使導熱凸柱22向上***通孔40，而訊號凸柱24則向上***通孔42，最終則使基板34接觸並定位於黏著層28。In the structure shown in FIG. 4B, the substrate 34 is disposed on the adhesive layer 28. The substrate 34 is lowered onto the adhesive layer 28 such that the thermally conductive studs 22 are inserted upwardly into the through holes 40, and the signal studs 24 are inserted upwardly into the through holes 42 to ultimately contact and position the substrate 34 to the adhesive layer 28.

導熱凸柱22在***(但並未貫穿)通孔40後係對準通孔40且位於通孔40內之中央位置而不接觸基板34。因此，缺口44係位於通孔40內且介於導熱凸柱22與基板34之間。缺口44側向環繞導熱凸柱22，同時被基板34側向包圍。此外，開口30與通孔40係相互對齊且具有相同直徑。The thermally conductive stud 22 is aligned with the through hole 40 after being inserted (but not penetrating) through the through hole 40 and located at a central position within the through hole 40 without contacting the substrate 34. Therefore, the notch 44 is located in the through hole 40 and between the thermally conductive stud 22 and the substrate 34. The notch 44 laterally surrounds the thermally conductive stud 22 while being laterally surrounded by the substrate 34. Further, the opening 30 and the through hole 40 are aligned with each other and have the same diameter.

訊號凸柱24在***(但並未貫穿)通孔42後係對準通孔42且位於通孔42內之中央位置而不接觸基板34。因此，缺口46係位於通孔42內且介於訊號凸柱24與基板34之間。缺口46側向環繞訊號凸柱24，同時被基板34側向包圍。此外，開口32與通孔42係相互對齊且具有相同直徑。The signal stud 24 is aligned with the through hole 42 after insertion (but not through) the through hole 42 and is located at a central position within the through hole 42 without contacting the substrate 34. Therefore, the notch 46 is located in the through hole 42 and between the signal stud 24 and the substrate 34. The notch 46 laterally surrounds the signal stud 24 while being laterally surrounded by the substrate 34. Further, the opening 32 and the through hole 42 are aligned with each other and have the same diameter.

此時，基板34係安置於黏著層28上並與之接觸，且延伸於黏著層28上方。導熱凸柱22延伸通過開口30後，進入通孔40且到達介電層38。導熱凸柱22較導電層36之頂面低60微米，並經由通孔40朝一向上方向外露。訊號凸柱24延伸通過開口32後，進入通孔42且到達介電層38。訊號凸柱24較導電層36之頂面低60微米，並經由通孔 42朝該向上方向外露。黏著層28接觸基座26與基板34且介於該兩者之間。黏著層28接觸介電層38但與導電層36保持距離。在此階段，黏著層28仍為乙階(B-stage)未固化環氧樹脂之膠片，而缺口44、46中則為空氣。At this time, the substrate 34 is disposed on and in contact with the adhesive layer 28 and extends over the adhesive layer 28. After extending through the opening 30, the thermally conductive studs 22 enter the vias 40 and reach the dielectric layer 38. The thermally conductive studs 22 are 60 microns lower than the top surface of the conductive layer 36 and are exposed in an upward direction via the vias 40. After the signal studs 24 extend through the openings 32, they enter the vias 42 and reach the dielectric layer 38. The signal stud 24 is 60 microns lower than the top surface of the conductive layer 36 and passes through the through hole 42 is exposed in the upward direction. Adhesive layer 28 contacts pedestal 26 and substrate 34 and is interposed therebetween. Adhesive layer 28 contacts dielectric layer 38 but is at a distance from conductive layer 36. At this stage, the adhesive layer 28 is still a film of B-stage uncured epoxy, while the gaps 44, 46 are air.

圖4C繪示黏著層28經加熱加壓後流入缺口44、46。在此圖中，迫使黏著層28流入缺口44、46之方法係對導電層36施以向下壓力及/或對基座26施以向上壓力，亦即將基座26與基板34相對壓合，藉以對黏著層28施壓；在此同時亦對黏著層28加熱。受熱之黏著層28可在壓力下任意成形。因此，位於基座26與基板34間之黏著層28受到擠壓後，改變其原始形狀並向上流入缺口44、46。基座26與基板34持續朝彼此壓合，直到黏著層28填滿缺口44、46為止。此外，在基座26與基板34間之間隙縮小後，黏著層28仍舊填滿此一縮小之間隙內。4C illustrates the adhesive layer 28 flowing into the gaps 44, 46 after being heated and pressurized. In this figure, the method of forcing the adhesive layer 28 into the gaps 44, 46 is to apply downward pressure to the conductive layer 36 and/or apply upward pressure to the susceptor 26, that is, to press the susceptor 26 against the substrate 34, Thereby, the adhesive layer 28 is pressed; at the same time, the adhesive layer 28 is also heated. The heated adhesive layer 28 can be arbitrarily shaped under pressure. Therefore, after the adhesive layer 28 between the susceptor 26 and the substrate 34 is pressed, its original shape is changed and flows upward into the notches 44, 46. The susceptor 26 and the substrate 34 are continuously pressed against each other until the adhesive layer 28 fills the notches 44, 46. In addition, after the gap between the susceptor 26 and the substrate 34 is reduced, the adhesive layer 28 still fills the reduced gap.

例如，可將基座26及導電層36設置於一壓合機之上、下壓台(圖未示)之間。此外，可將一上擋板及上緩衝紙(圖未示)夾置於導電層36與上壓台之間，並將一下擋板及下緩衝紙(圖未示)夾置於基座26與下壓台之間。以此構成之疊合體由上到下依次為上壓台、上擋板、上緩衝紙、基板34、黏著層28、基座26、下緩衝紙、下擋板及下壓台。此外，可利用從下壓台向上延伸並穿過基座26對位孔(圖未示)之工具接腳(圖未示)將此疊合體定位於下壓台上。For example, the susceptor 26 and the conductive layer 36 can be disposed between a press machine and a lower pressing table (not shown). In addition, an upper baffle and an upper buffer paper (not shown) may be interposed between the conductive layer 36 and the upper pressing table, and the lower baffle and the lower cushioning paper (not shown) are placed on the base 26 . Between the lower pressing table. The stacked body thus constructed is, in order from top to bottom, an upper pressing table, an upper baffle plate, an upper baffle paper, a substrate 34, an adhesive layer 28, a susceptor 26, a lower cushioning paper, a lower baffle plate, and a lower pressing table. In addition, the stacking body can be positioned on the lower pressing table by means of a tool pin (not shown) extending upward from the lower pressing table and passing through a counter hole (not shown) of the base 26.

而後將上、下壓台加熱並相互推進，藉此對黏著層28加熱並施壓。擋板可將壓台之熱分散，使熱均勻施加於基座26與基板34乃至於黏著層28。緩衝紙則將壓台之壓力分散，使壓力均勻施加於基座26與基板34乃至於黏著層28。起初，介電層38接觸並壓合於黏著層28。隨著壓台持續動作與持續加熱，基座26與基板34間之黏著層28受到擠壓並開始熔化，因而向上流入缺口44、46，並於通過介電層38後抵達導電層36。例如，未固化環氧樹脂遇熱熔化後，被壓力擠入缺口44、46中，但加強材料及填充物仍留在基座26與基板34之間。黏著層28在通孔40內上升之速度大於導熱凸柱22，終至填滿缺口44。黏著層28在通孔42內上升之速度亦大於訊號凸柱24，終至填滿缺口46。黏著層28亦上升至稍高於缺口44、46之位置，並在壓台停止動作前，溢流至導熱凸柱22頂面及導電層36頂面鄰接缺口44處，以及訊號凸柱24頂面及導電層36頂面鄰接缺口46處。若膠片厚度略大於實際所需便可能發生此一情形。如此一來，黏著層28便在導熱凸柱22頂面及訊號凸柱24頂面形成一覆蓋薄層。壓台在觸及導熱凸柱22及訊號凸柱24後停止動作，但仍持續對黏著層28加熱。The upper and lower press tables are then heated and pushed into each other, whereby the adhesive layer 28 is heated and pressed. The baffle can disperse the heat of the pressing table to uniformly apply heat to the base. The holder 26 and the substrate 34 are as an adhesive layer 28. The cushioning paper disperses the pressure of the platen so that the pressure is uniformly applied to the susceptor 26 and the substrate 34 or even the adhesive layer 28. Initially, the dielectric layer 38 contacts and is pressed against the adhesive layer 28. As the platen continues to operate and continues to heat, the adhesive layer 28 between the susceptor 26 and the substrate 34 is squeezed and begins to melt, thereby flowing upward into the notches 44, 46 and after reaching the conductive layer 36 after passing through the dielectric layer 38. For example, the uncured epoxy resin is melted into the gaps 44, 46 after being melted by heat, but the reinforcing material and the filler remain between the susceptor 26 and the substrate 34. The adhesive layer 28 rises faster in the through hole 40 than the thermally conductive stud 22, and finally fills the notch 44. The adhesive layer 28 also rises faster in the through hole 42 than the signal stud 24, and finally fills the notch 46. The adhesive layer 28 also rises slightly above the notches 44, 46 and overflows to the top surface of the thermally conductive stud 22 and the top surface of the conductive layer 36 adjacent the notch 44 and the top of the signal stud 24 before the platen stops operating. The top surface of the surface and conductive layer 36 abuts the notch 46. This can happen if the film thickness is slightly larger than actually needed. As a result, the adhesive layer 28 forms a thin layer of cover on the top surface of the heat conducting stud 22 and the top surface of the signal stud 24 . The platen stops after touching the thermally conductive studs 22 and the signal studs 24, but continues to heat the adhesive layer 28.

黏著層28於缺口44、46中向上流動之方向如圖中向上粗箭號所示，導熱凸柱22、訊號凸柱24與基座26相對於基板34之向上移動如向上細箭號所示，而基板34相對於導熱凸柱22、訊號凸柱24與基座26之向下移動則如向下細箭號所示。The direction in which the adhesive layer 28 flows upward in the notches 44, 46 is as shown by the upward bold arrow in the figure, and the thermal conductive post 22, the signal stud 24 and the pedestal 26 move upward relative to the substrate 34 as indicated by the upward arrow. The downward movement of the substrate 34 relative to the thermally conductive studs 22, the signal studs 24 and the pedestal 26 is as indicated by the downwardly thin arrows.

圖4D中之黏著層28已經固化。The adhesive layer 28 in Figure 4D has cured.

例如，壓台停止移動後仍持續夾合導熱凸柱22、訊號凸柱24與基座26並供熱，藉此將已熔化之乙階(B-stage)環氧樹脂轉換為丙階(C-stage)固化或硬化之環氧樹脂。因此，環氧樹脂係以類似習知多層壓合之方式固化。環氧樹脂固化後，壓台分離，以便將結構體從壓合機中取出。For example, after the platen stops moving, the heat conducting stud 22 and the signal are continuously clamped. The studs 24 are heated with the susceptor 26, thereby converting the melted B-stage epoxy to a C-stage cured or hardened epoxy. Therefore, the epoxy resin is cured in a manner similar to conventional lamination. After the epoxy resin is cured, the platen is separated to remove the structure from the press.

固化之黏著層28在導熱凸柱22與基板34之間、訊號凸柱24與基板34之間以及基座26與基板34之間提供牢固之機械性連結。黏著層28可承受一般操作壓力而不致變形損毀，遇過大壓力時則僅暫時扭曲。再者，黏著層28可吸收導熱凸柱22與基板34之間、訊號凸柱24與基板34之間以及基座26與基板34之間的熱膨脹不匹配。The cured adhesive layer 28 provides a secure mechanical bond between the thermally conductive stud 22 and the substrate 34, between the signal studs 24 and the substrate 34, and between the pedestal 26 and the substrate 34. The adhesive layer 28 can withstand normal operating pressure without deformation and damage, and is only temporarily distorted when excessive pressure is applied. Furthermore, the adhesive layer 28 can absorb the thermal expansion mismatch between the thermally conductive studs 22 and the substrate 34, between the signal studs 24 and the substrate 34, and between the pedestal 26 and the substrate 34.

在此階段，導熱凸柱22、訊號凸柱24與導電層36大致共平面，而黏著層28與導電層36則延伸至一面朝該向上方向之頂面。例如，基座26與介電層38間之黏著層28厚120微米，較其初始厚度180微米減少60微米；亦即導熱凸柱22在通孔40中升高60微米，訊號凸柱24在通孔42中升高60微米，而基板34則相對於導熱凸柱22、訊號凸柱24下降60微米。導熱凸柱22及訊號凸柱24之高度300微米基本上等同於導電層36(30微米)、介電層38(150微米)與下方黏著層28(120微米)之結合高度。此外，導熱凸柱22仍位於開口30與通孔40內之中央位置並與基板34保持距離，訊號凸柱24仍位於開口32與通孔42內之中央位置並與基板34保持距離，而黏著層28則填滿基座26與基板34間之空間並填滿缺口44、46。例如，缺口44(以及導熱凸柱22與基板34間之黏著層28)在導熱凸柱22頂面處寬75微米(即1150微米減去1000微米後除以2)，缺口46(以及訊號凸柱24與基板34間之黏著層28)在訊號凸柱24頂面處寬75微米((450 300)/2)。黏著層28在缺口44、46內延伸跨越介電層38。換言之，缺口44中之黏著層28係沿該向上方向及一向下方向延伸並跨越缺口44外側壁之介電層38厚度，而缺口46中之黏著層28則沿該向上方向及該向下方向延伸並跨越缺口46外側壁之介電層38厚度。黏著層28亦包含缺口44、46上方之薄頂部分，其接觸導熱凸柱22、訊號凸柱24之頂面與導電層36之頂面並在導熱凸柱22、訊號凸柱24上方延伸10微米。At this stage, the thermally conductive studs 22, signal posts 24 and the conductive layer 36 are substantially coplanar, and the adhesive layer 28 and the conductive layer 36 extend to a top surface of the upward direction. For example, the adhesive layer 28 between the pedestal 26 and the dielectric layer 38 is 120 microns thicker, and is 60 microns smaller than its initial thickness of 180 microns; that is, the thermally conductive stud 22 is raised 60 microns in the through hole 40, and the signal studs 24 are The via 42 is raised by 60 microns, and the substrate 34 is lowered by 60 microns with respect to the thermally conductive stud 22 and the signal stud 24. The height of the thermally conductive studs 22 and the signal studs 24 is substantially equal to the combined height of the conductive layer 36 (30 microns), the dielectric layer 38 (150 microns) and the underlying adhesive layer 28 (120 microns). In addition, the heat conducting stud 22 is still located at a central position in the opening 30 and the through hole 40 and is spaced apart from the substrate 34. The signal stud 24 is still located at a central position in the opening 32 and the through hole 42 and is spaced apart from the substrate 34, and adhered. Layer 28 fills the space between pedestal 26 and substrate 34 and fills gaps 44,46. For example, the notch 44 (and the adhesive layer 28 between the thermally conductive stud 22 and the substrate 34) is on the top surface of the thermally conductive stud 22 At a width of 75 microns (i.e., 1150 microns minus 1000 microns divided by 2), the notch 46 (and the adhesion layer 28 between the signal studs 24 and the substrate 34) is 75 microns wider at the top surface of the signal studs 24 (450 300 )/2). Adhesive layer 28 extends across dielectric layer 38 within indentations 44,46. In other words, the adhesive layer 28 in the notch 44 extends along the upward direction and a downward direction and across the thickness of the dielectric layer 38 of the outer sidewall of the notch 44, and the adhesive layer 28 in the notch 46 is along the upward direction and the downward direction. The thickness of the dielectric layer 38 extends and spans the outer sidewall of the notch 46. The adhesive layer 28 also includes a thin top portion above the notches 44, 46 that contacts the top surface of the thermally conductive stud 22, the signal post 24 and the top surface of the conductive layer 36 and extends over the thermally conductive stud 22 and the signal studs 24 Micron.

在圖4E所示結構中，導熱凸柱22、訊號凸柱24、黏著層28及導電層36之頂部皆已去除。In the structure shown in FIG. 4E, the tops of the thermally conductive studs 22, the signal studs 24, the adhesive layer 28, and the conductive layer 36 have been removed.

導熱凸柱22、訊號凸柱24、黏著層28及導電層36之頂部係以研磨方式去除，例如以旋轉鑽石砂輪及蒸餾水處理結構體之頂部。起初，鑽石砂輪僅磨去黏著層28。持續研磨，則黏著層28因受磨表面下移而變薄。鑽石砂輪終將接觸導熱凸柱22、訊號凸柱24與導電層36(不必然同時)，因而開始研磨導熱凸柱22、訊號凸柱24與導電層36。持續研磨後，導熱凸柱22、訊號凸柱24、黏著層28及導電層36均因受磨表面下移而變薄。研磨持續至去除所需厚度為止。之後，以蒸餾水沖洗結構體去除污物。The tops of the thermally conductive studs 22, signal posts 24, adhesive layer 28, and conductive layer 36 are removed by grinding, such as by rotating the diamond wheel and the top of the structured water. Initially, the diamond wheel only scratches the adhesive layer 28. With continuous grinding, the adhesive layer 28 becomes thinner as the surface to be worn is moved downward. The diamond wheel will eventually contact the thermally conductive stud 22, the signal stud 24 and the conductive layer 36 (not necessarily simultaneously), thus beginning to polish the thermally conductive stud 22, the signal stud 24 and the conductive layer 36. After continuous grinding, the thermally conductive studs 22, the signal studs 24, the adhesive layer 28, and the conductive layer 36 are all thinned by the worn surface being moved down. The grinding continues until the desired thickness is removed. Thereafter, the structure was rinsed with distilled water to remove dirt.

上述研磨步驟將黏著層28之頂部磨去25微米，將導熱凸柱22之頂部磨去15微米，將訊號凸柱24之頂部磨去15微米，並將導電層36之頂部磨去15微米。厚度減少對導熱凸柱22、訊號凸柱24或黏著層28均無明顯影響，但導電層36之厚度卻從30微米大幅縮減至15微米。The grinding step removes the top of the adhesive layer 28 by 25 microns, the top of the thermally conductive stud 22 by 15 microns, the top of the signal stud 24 by 15 microns, and the top of the conductive layer 36 by 15 microns. Thickness reduction The thermally conductive studs 22, the signal studs 24, or the adhesive layer 28 have no significant effect, but the thickness of the conductive layer 36 is greatly reduced from 30 microns to 15 microns.

至此，導熱凸柱22、訊號凸柱24、黏著層28及導電層36係共同位於介電層38上方一面朝該向上方向之平滑拼接側頂面上。同樣地，導熱凸柱22、訊號凸柱24與黏著層28在基座26處係彼此共平面。At this point, the thermally conductive studs 22, the signal studs 24, the adhesive layer 28, and the conductive layer 36 are collectively located above the dielectric layer 38 toward the smooth splicing side top surface of the upward direction. Similarly, the thermally conductive studs 22, signal posts 24, and adhesive layer 28 are coplanar with each other at the pedestal 26.

圖4F所示之結構體具有導電層50，其係沉積於導熱凸柱22、訊號凸柱24、黏著層28及導電層36上。The structure shown in FIG. 4F has a conductive layer 50 deposited on the thermally conductive studs 22, the signal studs 24, the adhesive layer 28, and the conductive layer 36.

導電層50接觸導熱凸柱22、訊號凸柱24、黏著層28及導電層36，並從上方覆蓋此四者。例如，可將結構體浸入一活化劑溶液中，因而使黏著層28可與無電鍍銅產生觸媒反應，接著將一第一銅層以無電鍍被覆之方式設於導熱凸柱22、訊號凸柱24、黏著層28及導電層36上，然後將一第二銅層以電鍍方式設於該第一銅層上。第一銅層厚約2微米，第二銅層厚約13微米，故導電層50之總厚度約為15微米。如此一來，導電層36之厚度便增為約30微米(15+15)。導電層50係作為導熱凸柱22與訊號凸柱24之一覆蓋層及導電層36之一加厚層。為便於說明，導熱凸柱22、訊號凸柱24與導電層50以及導電層36與50均以單層顯示。由於銅為同質被覆，導熱凸柱22與導電層50間之界線、訊號凸柱24與導電層50間之界線以及導電層36與50間之界線(均以虛線繪示)可能不易察覺甚至無法察覺。然而，黏著層28與導電層50間之界線則清楚可見。The conductive layer 50 contacts the thermally conductive studs 22, the signal studs 24, the adhesive layer 28, and the conductive layer 36, and covers the four from above. For example, the structure can be immersed in an activator solution, so that the adhesive layer 28 can react with the electroless copper to generate a catalyst, and then a first copper layer is provided on the thermally conductive stud 22 and the signal convex in an electroless plating manner. On the pillar 24, the adhesive layer 28 and the conductive layer 36, a second copper layer is then electroplated on the first copper layer. The first copper layer is about 2 microns thick and the second copper layer is about 13 microns thick, so the total thickness of the conductive layer 50 is about 15 microns. As a result, the thickness of the conductive layer 36 is increased to about 30 microns (15 + 15). The conductive layer 50 serves as a thickening layer of the thermal conductive stud 22 and the signal bump 24 and the conductive layer 36. For convenience of description, the thermal conductive studs 22, the signal studs 24 and the conductive layer 50, and the conductive layers 36 and 50 are all shown in a single layer. Since the copper is a homogeneous coating, the boundary between the heat conducting stud 22 and the conductive layer 50, the boundary between the signal stud 24 and the conductive layer 50, and the boundary between the conductive layers 36 and 50 (both shown by dashed lines) may be difficult to detect or even aware. However, the boundary between the adhesive layer 28 and the conductive layer 50 is clearly visible.

圖4G所示結構體之上、下表面分別設有圖案化之蝕刻阻層52與圖案化之蝕刻阻層54。圖示之圖案化之蝕刻阻層52、54均為類似於圖案化之蝕刻阻層16之光阻層。圖案化之蝕刻阻層52設有可選擇性曝露導電層50之圖案，而圖案化之蝕刻阻層54則設有可選擇性曝露基座26之圖案。A patterned etching is provided on the upper surface and the lower surface of the structure shown in FIG. 4G. The resist layer 52 and the patterned etch stop layer 54. The illustrated patterned etch stop layers 52, 54 are all photoresist layers similar to the patterned etch stop layer 16. The patterned etch stop layer 52 is provided with a pattern that selectively exposes the conductive layer 50, and the patterned etch stop layer 54 is provided with a pattern that selectively exposes the pedestal 26.

在圖4H所示之結構體中，導電層36、50已經由蝕刻去除其選定部分以形成圖案化之蝕刻阻層52所定義之圖案，而基座26也已經由蝕刻去除其選定部分以形成圖案化之蝕刻阻層54所定義之圖案。所述蝕刻係雙面濕式化學蝕刻，其與施用於金屬板10者相仿。例如，利用一頂部噴嘴(圖未示)及一底部噴嘴(圖未示)將化學蝕刻液分別噴灑於結構體之頂面及底面，或者將結構體浸入化學蝕刻液中。化學蝕刻液可蝕透導電層36、50以露出黏著層28及介電層38，因而將原本無圖案之導電層36、50轉變為圖案層。化學蝕刻液亦蝕透基座26以露出黏著層28。In the structure shown in FIG. 4H, the conductive layers 36, 50 have been removed by etching to select portions thereof to form a pattern defined by the patterned etch stop layer 52, and the pedestal 26 has also been removed by etching to select selected portions thereof. A pattern defined by the patterned etch stop layer 54. The etching is a two-sided wet chemical etching similar to that applied to the metal plate 10. For example, a top nozzle (not shown) and a bottom nozzle (not shown) are used to spray the chemical etching solution on the top and bottom surfaces of the structure, respectively, or to immerse the structure in the chemical etching solution. The chemical etchant etches through the conductive layers 36, 50 to expose the adhesive layer 28 and the dielectric layer 38, thereby converting the originally unpatterned conductive layers 36, 50 into a patterned layer. The chemical etchant also erodes the susceptor 26 to expose the adhesive layer 28.

在圖4I中，結構體上之圖案化蝕刻阻層52、54均已去除。去除圖案化之蝕刻阻層52、54之方式可與去除圖案化之蝕刻阻層16、全面覆蓋之蝕刻阻層18之方式相同。In Figure 4I, the patterned etch stop layers 52, 54 on the structure have been removed. The manner in which the patterned etch stop layers 52, 54 are removed may be the same as the manner in which the patterned etch stop layer 16 is removed and the etch stop layer 18 is completely covered.

蝕刻後之導電層36、50包含焊墊56與路由線58，而蝕刻後之導電層50則包含蓋體60。焊墊56與路由線58係導電層36、50受圖案化之蝕刻阻層52保護而未被蝕刻之部分，蓋體60則為導電層50受圖案化之蝕刻阻層52保護而未被蝕刻之部分。如此一來，導電層36、50便成為圖案層，其包含焊墊56與路由線58但不包含蓋體60。此外，路由線58為一銅導線，其接觸介電層38並延伸於其上方，同時鄰接且電性連結訊號凸柱24與焊墊56。The etched conductive layers 36, 50 include pads 56 and routing lines 58, and the etched conductive layer 50 includes a cover 60. The pad 56 and the routing line 58 are electrically protected layers 36, 50 protected by the patterned etch stop layer 52, and the cover 60 is protected by the patterned etch stop layer 52. Part of it. As such, the conductive layers 36, 50 become patterned layers that include the pads 56 and routing lines 58 but do not include the cover 60. In addition, routing line 58 is a copper wire that contacts dielectric layer 38 and extends above it. At the same time, the signal bumps 24 and the pads 56 are electrically connected adjacent to each other.

蝕刻後之基座26包含基座26(僅剩其中央部分)及端子62。基座26係原基座26受圖案化之蝕刻阻層54保護而未被蝕刻之部分，其沿側向延伸且於側面方向超出導熱凸柱22之外1000微米。端子62係原基座26受圖案化之蝕刻阻層54保護而未被蝕刻之部分，其鄰接訊號凸柱24，延伸於訊號凸柱24下方，且自訊號凸柱24側向延伸而出，同時接觸黏著層28並延伸於黏著層28下方。基座26仍為一無圖案層，但在基座26周緣之外則形成一包含端子62且與基座26保持側向間距之圖案層。因此，端子62與基座26係彼此分離，且端子62已非基座26之一部分。此外，訊號凸柱24鄰接路由線58與端子62並在路由線58與端子62之間形成電性連結。The etched susceptor 26 includes a pedestal 26 (only the central portion remains) and a terminal 62. The pedestal 26 is the portion of the original pedestal 26 that is protected by the patterned etch stop layer 54 and that is not etched, extending laterally and 1000 microns beyond the thermally conductive studs 22 in the lateral direction. The terminal 62 is a portion of the original pedestal 26 that is protected by the patterned etch stop layer 54 and is not etched. The adjacent signal post 24 extends below the signal stud 24 and extends laterally from the signal stud 24 . At the same time, the adhesive layer 28 is contacted and extends below the adhesive layer 28. The pedestal 26 is still a non-patterned layer, but a patterned layer comprising terminals 62 and laterally spaced from the pedestal 26 is formed outside the periphery of the pedestal 26. Therefore, the terminal 62 and the base 26 are separated from each other, and the terminal 62 is not part of the base 26. In addition, the signal studs 24 abut the routing line 58 and the terminal 62 and form an electrical connection between the routing line 58 and the terminal 62.

訊號凸柱24、焊墊56、路由線58及端子62共同形成導線64。訊號凸柱24及路由線58係焊墊56與端子62間之一導電路徑。導線64提供從焊墊56至端子62之垂直(由上至下)路由。導線64並不限於此一構型。舉例而言，上述導電路徑尚可包含貫穿介電層38之導電孔、額外之路由線(其位於介電層38之上方及/或下方)及被動元件(如設置於其他焊墊上之電阻與電容)。Signal bumps 24, pads 56, routing lines 58, and terminals 62 collectively form wires 64. The signal studs 24 and routing lines 58 are one of the conductive paths between the pads 56 and the terminals 62. Wire 64 provides a vertical (top to bottom) routing from pad 56 to terminal 62. The wire 64 is not limited to this configuration. For example, the conductive path may further include conductive vias through the dielectric layer 38, additional routing lines (which are above and/or below the dielectric layer 38), and passive components (such as resistors disposed on other pads). capacitance).

散熱座66包含導熱凸柱22、基座26及蓋體60。導熱凸柱22與基座26係一體成形。蓋體60位於導熱凸柱22之頂部上方，鄰接導熱凸柱22之頂部，同時從上方覆蓋導熱凸柱22之頂部，並由導熱凸柱22之頂部往側向延伸。設置蓋體60後，導熱凸柱22係坐落於蓋體60圓周內之中央區域。蓋體60亦接觸並從上方覆蓋其下方黏著層28之一部分，黏著層28之該部分係與導熱凸柱22共平面，鄰接導熱凸柱22，且側向包圍導熱凸柱22。The heat sink 66 includes a heat conductive stud 22, a base 26 and a cover 60. The thermally conductive stud 22 is integrally formed with the base 26. The cover 60 is located above the top of the thermally conductive stud 22 adjacent to the top of the thermally conductive stud 22 while covering the top of the thermally conductive stud 22 from above and extending laterally from the top of the thermally conductive stud 22. After the cover 60 is disposed, the thermally conductive studs 22 are located in a central region within the circumference of the cover 60. The cover 60 also contacts and covers a portion of the adhesive layer 28 therebelow from above. The portion of the adhesive layer 28 is coplanar with the thermally conductive studs 22, abuts the thermally conductive studs 22, and laterally surrounds the thermally conductive studs 22.

散熱座66實質上為一倒T形之散熱塊，其包含柱部(導熱凸柱22)、翼部(基座26自柱部側向延伸之部分)以及一導熱墊(蓋體60)。The heat sink 66 is substantially an inverted T-shaped heat sink block including a post portion (thermal conductive stud 22), a wing portion (a portion of the base 26 extending laterally from the post portion), and a thermal pad (cover 60).

圖4J之結構體在黏著層28、介電層38、導電層50及蓋體60上設有防焊綠漆68，並且在基座26、黏著層28及端子62上設有防焊綠漆70。The structure of FIG. 4J is provided with a solder resist green paint 68 on the adhesive layer 28, the dielectric layer 38, the conductive layer 50 and the cover 60, and the solder resist green paint is provided on the base 26, the adhesive layer 28 and the terminal 62. 70.

防焊綠漆68為一電性絕緣層，其可依吾人之選擇形成圖案以曝露焊墊56與蓋體60，並從上方覆蓋路由線58、黏著層28之外露部分及介電層38之外露部分。防焊綠漆68在焊墊56與蓋體60上方之厚度為25微米，且防焊綠漆68於介電層38上方延伸55微米(30+25)。The solder resist green paint 68 is an electrical insulating layer which can be patterned to expose the solder pad 56 and the cover 60, and covers the routing line 58, the exposed portion of the adhesive layer 28 and the dielectric layer 38 from above. Exposed part. The solder resist green lacquer 68 has a thickness of 25 microns above the pad 56 and the cover 60, and the solder resist green lacquer 68 extends 55 microns (30+25) above the dielectric layer 38.

防焊綠漆70為一電性絕緣層，其可依吾人之選擇形成圖案以曝露基座26與端子62，並從下方覆蓋黏著層28之外露部分。防焊綠漆70在基座26與端子62下方之厚度為25微米，且防焊綠漆70於黏著層28下方延伸55微米(30+25)。The solder resist green paint 70 is an electrically insulating layer that can be patterned to expose the pedestal 26 and the terminal 62 and to cover the exposed portion of the adhesive layer 28 from below. The solder resist green lacquer 70 has a thickness of 25 microns below the pedestal 26 and the terminal 62, and the solder resist green lacquer 70 extends 55 microns (30+25) below the adhesive layer 28.

防焊綠漆68、70起初為塗佈於結構體上之一光顯像型液態樹脂。之後再於防焊綠漆68、70上形成圖案，其作法係令光線選擇性透過光罩(圖未示)，使受光之部分防焊綠漆變為不可溶解，然後利用一顯影溶液去除未受光且仍可溶解之部分防焊綠漆，最後再進行硬烤，以上步驟乃習知技藝。The solder resist green paints 68 and 70 were originally coated with a light-developing liquid resin on the structure. Then, a pattern is formed on the solder resist green paints 68 and 70. The method is to selectively pass light through the mask (not shown), so that the portion of the light-shielded green paint becomes insoluble, and then removes the solution by using a developing solution. Light and still soluble Part of the anti-weld green paint is solved, and finally hard baking is performed. The above steps are known techniques.

圖4K所示結構體之基座26、焊墊56、蓋體60與端子62上設有被覆接點72。The base 26, the pad 56, the cover 60, and the terminal 62 of the structure shown in Fig. 4K are provided with covered contacts 72.

被覆接點72為一多層金屬鍍層，其接觸基座26與端子62並從下方覆蓋其外露之部分，同時接觸焊墊56與蓋體60並從上方覆蓋其外露之部分。例如，一鎳層係以無電鍍被覆之方式設於基座26、焊墊56、蓋體60與端子62上，而後再將一金層以無電鍍被覆之方式設於該鎳層上，其中內部鎳層厚約3微米，表面金層厚約0.5微米，故被覆接點72之厚度約為3.5微米。The coated contact 72 is a multi-layer metal coating that contacts the pedestal 26 and the terminal 62 and covers the exposed portion thereof from below while contacting the pad 56 and the cover 60 and covering the exposed portion thereof from above. For example, a nickel layer is provided on the susceptor 26, the pad 56, the cover 60 and the terminal 62 in an electroless plating manner, and then a gold layer is provided on the nickel layer in an electroless plating manner, wherein The inner nickel layer is about 3 microns thick and the surface gold layer is about 0.5 microns thick, so the thickness of the coated contact 72 is about 3.5 microns.

以被覆接點72作為基座26、焊墊56、蓋體60與端子62之表面處理具有幾項優點。內部鎳層提供主要之機械性與電性連結及/或熱連結，而表面金層則提供一可濕性表面以利焊料迴焊。被覆接點72亦保護基座26、焊墊56、蓋體60與端子62不受腐蝕。被覆接點72可包含各種金屬以符合外部連結媒介之需要。例如，一被覆在鎳層上之銀層可搭配焊錫或打線。The surface treatment with the covered contacts 72 as the pedestal 26, the pads 56, the cover 60 and the terminals 62 has several advantages. The inner nickel layer provides primary mechanical and electrical bonding and/or thermal bonding, while the surface gold layer provides a wettable surface for solder reflow. The covered contacts 72 also protect the susceptor 26, the pads 56, the cover 60 and the terminals 62 from corrosion. The coated contacts 72 can contain a variety of metals to meet the needs of externally coupled media. For example, a layer of silver coated on a nickel layer can be soldered or wired.

為便於說明，設有被覆接點72之基座26、焊墊56、蓋體60與端子62均以單一層體方式顯示。被覆接點72與基座26、焊墊56、蓋體60及端子62間之界線(圖未示)為銅/鎳介面。For convenience of explanation, the susceptor 26 provided with the covered contacts 72, the pads 56, the cover 60 and the terminals 62 are all displayed in a single layer. The boundary (not shown) between the covered contact 72 and the susceptor 26, the pad 56, the cover 60 and the terminal 62 is a copper/nickel interface.

至此完成導熱板74之製作。The fabrication of the heat conducting plate 74 is thus completed.

圖4L、圖4M及圖4N分別為導熱板74之剖視圖、俯視圖及仰視圖，圖中導熱板74之邊緣已沿切割線而與支撐架及/或同批生產之相鄰導熱板分離。4L, 4M, and 4N are cross-sectional views of the heat conducting plate 74, respectively. View and bottom view, the edges of the heat conducting plate 74 in the figure have been separated along the cutting line from the support frame and/or the adjacent heat transfer plates produced in the same batch.

導熱板74包含黏著層28、基板34、導線64、散熱座66及防焊綠漆68、70。基板34包含介電層38。導線64包含訊號凸柱24、焊墊56、路由線58及端子62。散熱座66包含導熱凸柱22、基座26及蓋體60。The heat conducting plate 74 includes an adhesive layer 28, a substrate 34, a wire 64, a heat sink 66, and solder resist green paints 68, 70. Substrate 34 includes a dielectric layer 38. Wire 64 includes signal studs 24, pads 56, routing lines 58, and terminals 62. The heat sink 66 includes a heat conductive stud 22, a base 26 and a cover 60.

導熱凸柱22延伸貫穿開口30並進入通孔40後，仍位於開口30與通孔40內之中央位置。導熱凸柱22之頂部係與黏著層28位於介電層38上方之一相鄰部分共平面，而導熱凸柱22之底部則與黏著層28其接觸基座26之一相鄰部分共平面。導熱凸柱22保持平頂錐柱形，其漸縮側壁使其直徑自基座26朝導熱凸柱22鄰接蓋體60之平坦圓頂向上遞減。After the heat conducting stud 22 extends through the opening 30 and enters the through hole 40, it is still located at a central position within the opening 30 and the through hole 40. The top of the thermally conductive stud 22 is coplanar with an adjacent portion of the adhesive layer 28 above the dielectric layer 38, and the bottom of the thermally conductive stud 22 is coplanar with an adjacent portion of the adhesive layer 28 that contacts the pedestal 26. The thermally conductive studs 22 maintain a flat-topped tapered cylindrical shape with tapered side walls that decrease in diameter from the base 26 toward the flattened dome of the thermally conductive stud 22 adjacent the cover 60.

訊號凸柱24延伸貫穿開口32並進入通孔42後，仍位於開口32與通孔42內之中央位置。訊號凸柱24之頂部係與黏著層28位於介電層38上方之一相鄰部分共平面，而訊號凸柱24之底部則與黏著層28其接觸端子62之一相鄰部分共平面。訊號凸柱24保持平頂錐柱形，其漸縮側壁使其直徑自端子62朝訊號凸柱24鄰接路由線58之平坦圓頂向上遞減。After the signal stud 24 extends through the opening 32 and enters the through hole 42, it is still located at a central position within the opening 32 and the through hole 42. The top of the signal stud 24 is coplanar with an adjacent portion of the adhesive layer 28 above the dielectric layer 38, and the bottom of the signal stud 24 is coplanar with an adjacent portion of the adhesive layer 28 that contacts the terminal 62. The signal studs 24 maintain a flat-topped tapered cylindrical shape with tapered side walls that decrease in diameter from the terminal 62 toward the flat dome of the signal post 24 adjacent the routing line 58.

基座26從下方覆蓋導熱凸柱22與蓋體60，且與導熱板74之外圍邊緣保持距離。The pedestal 26 covers the thermally conductive stud 22 and the cover 60 from below and is spaced from the peripheral edge of the thermally conductive plate 74.

蓋體60位於導熱凸柱22上方，與之鄰接並為熱連結。蓋體60同時從上方覆蓋導熱凸柱22之頂部，並自導熱凸柱22頂部沿側向延伸。蓋體60亦從上方接觸並覆蓋黏著層28之一部分，黏著層28之該部分係鄰接導熱凸柱22，與導熱凸柱22共平面，且側向環繞導熱凸柱22。蓋體60亦與焊墊56共平面。The cover 60 is located above the thermally conductive stud 22 adjacent thereto and is thermally coupled. The cover body 60 simultaneously covers the top of the heat conducting stud 22 from above and is self-conducting The top of the stud 22 extends laterally. The cover 60 also contacts and covers a portion of the adhesive layer 28 from above, the portion of the adhesive layer 28 abutting the thermally conductive studs 22, coplanar with the thermally conductive studs 22, and laterally surrounding the thermally conductive studs 22. The cover 60 is also coplanar with the pads 56.

黏著層28係設置於基座26上並於其上方延伸。黏著層28在缺口44內接觸且介於導熱凸柱22與介電層38之間，並填滿導熱凸柱22與介電層38間之空間。黏著層28在缺口46內接觸且介於訊號凸柱24與介電層38之間，並填滿訊號凸柱24與介電層38間之空間。黏著層28在缺口44、46外則接觸且介於基座26與介電層38之間，並填滿基座26與介電層38間之空間。黏著層28係從導熱凸柱22側向延伸並越過端子62，重疊於端子62，並從上方覆蓋基座26位於導熱凸柱22周緣外之一部分，同時沿側面方向覆蓋且環繞導熱凸柱22與訊號凸柱24。黏著層28亦填滿基板34與散熱座66間之絕大部分空間。此時黏著層28已固化。The adhesive layer 28 is disposed on the base 26 and extends above it. The adhesive layer 28 contacts the gap between the thermally conductive studs 22 and the dielectric layer 38 and fills the space between the thermally conductive studs 22 and the dielectric layer 38. The adhesive layer 28 contacts the gap 46 between the signal stud 24 and the dielectric layer 38 and fills the space between the signal studs 24 and the dielectric layer 38. Adhesive layer 28 contacts outside of gaps 44, 46 and is interposed between susceptor 26 and dielectric layer 38 and fills the space between pedestal 26 and dielectric layer 38. The adhesive layer 28 extends laterally from the thermally conductive stud 22 and over the terminal 62, overlying the terminal 62, and covers the pedestal 26 from above with a portion outside the periphery of the thermally conductive stud 22 while covering in the lateral direction and surrounding the thermally conductive stud 22 And the signal studs 24. Adhesive layer 28 also fills most of the space between substrate 34 and heat sink 66. At this point the adhesive layer 28 has cured.

基板34係設置於黏著層28上並與之接觸。此外，基板34延伸於其下方黏著層28之上方，且延伸於基座26上方。導電層36(以及焊墊56與路由線58)接觸介電層38並延伸於其上方，而介電層38則接觸且介於黏著層28與導電層36之間。The substrate 34 is disposed on and in contact with the adhesive layer 28. In addition, the substrate 34 extends above the underlying adhesive layer 28 and over the susceptor 26. Conductive layer 36 (and pad 56 and routing line 58) contact dielectric layer 38 and extend thereover, while dielectric layer 38 contacts and is between adhesive layer 28 and conductive layer 36.

導熱凸柱22與訊號凸柱24具有相同厚度且彼此共平面。基座26與端子62具有相同厚度且彼此共平面。此外，導熱凸柱22、訊號凸柱24之頂部及底部均與黏著層28 共平面。The thermally conductive studs 22 have the same thickness as the signal studs 24 and are coplanar with each other. The pedestal 26 has the same thickness as the terminals 62 and is coplanar with each other. In addition, the thermal conductive studs 22, the top and bottom of the signal studs 24 and the adhesive layer 28 Coplanar.

導熱凸柱22、訊號凸柱24、基座26、蓋體60及端子62均與基板34保持距離。因此，基板34與散熱座66係機械性連接且彼此電性隔離。The thermally conductive studs 22, the signal studs 24, the pedestal 26, the cover 60, and the terminals 62 are all spaced from the substrate 34. Therefore, the substrate 34 is mechanically coupled to the heat sink 66 and electrically isolated from each other.

同批製作之導熱板74經裁切後，其黏著層28、介電層38及防焊綠漆68、70均延伸至裁切而成之垂直邊緣。After the same batch of thermally conductive plates 74 are cut, the adhesive layer 28, the dielectric layer 38 and the solder resist green paints 68, 70 extend to the cut vertical edges.

焊墊56係一專為LED封裝體或半導體晶片等半導體元件量身訂做之電性介面，該半導體元件將於後續製程中設置於蓋體60上。端子62係一專為下一層組體(例如來自一印刷電路板之可焊接線)量身訂做之電性介面。蓋體60係一專為該半導體元件量身訂做之熱介面。基座26係一專為下一層組體(例如前述印刷電路板或一電子設備之散熱裝置)量身訂做之熱介面。此外，蓋體60係經由導熱凸柱22而熱連結至基座26。The pad 56 is an electrical interface tailored to a semiconductor component such as an LED package or a semiconductor wafer, and the semiconductor component is disposed on the cover 60 in a subsequent process. Terminal 62 is an electrical interface tailored to the next layer of components (e.g., solderable wires from a printed circuit board). The cover 60 is a thermal interface tailored to the semiconductor component. The pedestal 26 is a thermal interface tailored to the next layer of components, such as the aforementioned printed circuit board or a heat sink for an electronic device. Further, the cover 60 is thermally coupled to the susceptor 26 via the thermally conductive studs 22 .

焊墊56與端子62在垂直方向上彼此錯位，且分別外露於導熱板74之頂面及底面，藉此提供該半導體元件與下一層組體間之垂直路由。The pad 56 and the terminal 62 are offset from each other in the vertical direction, and are respectively exposed on the top surface and the bottom surface of the heat conducting plate 74, thereby providing a vertical route between the semiconductor element and the next layer assembly.

焊墊56與蓋體60兩者之頂面於介電層38上方為共平面，而基座26與端子62兩者之底面則於黏著層28下方為共平面。The top surface of both the pad 56 and the cover 60 is coplanar above the dielectric layer 38, and the bottom surfaces of both the pedestal 26 and the terminal 62 are coplanar below the adhesive layer 28.

為便於說明，導線64於剖視圖中係繪示為一連續電路跡線。然而，導線64通常同時提供X與Y方向之水平訊號路由，亦即焊墊56與端子62彼此在X與Y方向形成側向錯位，而路由線58則構成X與Y方向之路徑。For ease of illustration, the wire 64 is depicted as a continuous circuit trace in cross-sectional view. However, the wires 64 typically provide horizontal signal routing in the X and Y directions, i.e., the pads 56 and the terminals 62 are laterally offset from each other in the X and Y directions, and the routing lines 58 form the path in the X and Y directions.

散熱座66可將隨後設置於蓋體60上之半導體元件所產生之熱能擴散至導熱板74所連接之下一層組體。該半導體元件產生之熱能流入蓋體60，自蓋體60進入導熱凸柱22，並經由導熱凸柱22進入基座26。熱能從基座26沿該向下方向散出，例如擴散至一下方散熱裝置。The heat sink 66 can diffuse the thermal energy generated by the semiconductor component subsequently disposed on the cover 60 to a lower group to which the heat conducting plate 74 is connected. The thermal energy generated by the semiconductor component flows into the cover 60, enters the thermally conductive stud 22 from the cover 60, and enters the susceptor 26 via the thermally conductive stud 22. Thermal energy is dissipated from the susceptor 26 in the downward direction, for example, to a lower heat sink.

導熱板74之導熱凸柱22、訊號凸柱24與路由線58均未外露，其中導熱凸柱22被蓋體60覆蓋，訊號凸柱24及路由線58係由防焊綠漆68覆蓋，而黏著層28則同時由防焊綠漆68、70覆蓋。為便於說明，圖4M以虛線繪示導熱凸柱22、訊號凸柱24、黏著層28與路由線58。The heat conducting studs 22, the signal studs 24 and the routing wires 58 of the heat conducting plate 74 are not exposed, wherein the heat conducting studs 22 are covered by the cover 60, and the signal studs 24 and the routing wires 58 are covered by the solder resist green paint 68. The adhesive layer 28 is simultaneously covered by the solder resist green paints 68, 70. For convenience of description, FIG. 4M shows the heat conducting stud 22, the signal stud 24, the adhesive layer 28 and the routing line 58 in broken lines.

導熱板74亦包含其他導線64，該些導線64基本上係由訊號凸柱24、焊墊56、路由線58與端子62所構成。為便於說明，在此僅說明並繪示單一導線64。於導線64中，訊號凸柱24、焊墊56及端子62通常具有相同之形狀及尺寸，而路由線58則通常採用不同之路由構型。例如，部分導線64設有間距，彼此分離，且為電性隔離，而部分導線64則彼此交錯或導向同一焊墊56、路由線58或端子62且彼此電性連結。同樣地，部分焊墊56可用以接收獨立訊號，而部分焊墊56則共用一訊號、電源或接地端。The heat conducting plate 74 also includes other wires 64 that are substantially comprised of signal posts 24, pads 56, routing lines 58, and terminals 62. For ease of explanation, only a single wire 64 is illustrated and illustrated herein. In the wire 64, the signal posts 24, pads 56 and terminals 62 generally have the same shape and size, while the routing wires 58 are typically of a different routing configuration. For example, portions of the wires 64 are spaced apart from each other and electrically isolated, and the partial wires 64 are staggered or directed to the same pad 56, routing line 58 or terminal 62 and electrically coupled to each other. Similarly, a portion of the pads 56 can be used to receive independent signals, while a portion of the pads 56 share a signal, power supply, or ground.

導熱板74可適用於具有藍、綠及紅色LED晶片之LED封裝體，其中各LED晶片包含一陽極與一陰極，且各LED封裝體包含對應之陽極端子與陰極端子。在此例中，導熱板74可包含六個焊墊56與四個端子62，以便將每一陽極從一獨立焊墊56導向一獨立端子62，並將每一陰極從一獨立焊墊56導向一共同之接地端子62。The heat conducting plate 74 can be applied to an LED package having blue, green, and red LED chips, wherein each LED chip includes an anode and a cathode, and each LED package includes a corresponding anode terminal and cathode terminal. In this example, the thermally conductive plate 74 can include six pads 56 and four terminals 62 to direct each anode from a separate pad 56 to a separate terminal 62, and each cathode is A separate pad 56 is directed to a common ground terminal 62.

在各製造階段均可利用一簡易清潔步驟去除外露金屬上之氧化物與殘留物，例如可對本案結構體施行一短暫之氧電漿清潔步驟。或者，可利用一過錳酸鉀溶液對本案結構體進行一短暫之濕式化學清潔步驟。同樣地，亦可利用蒸餾水淋洗本案結構體以去除污物。此清潔步驟可清潔所需表面而不對結構體造成明顯之影響或破壞。A simple cleaning step can be used at each stage of manufacture to remove oxides and residues from the exposed metal. For example, a short oxygen plasma cleaning step can be applied to the structure of the present invention. Alternatively, the structure of the present invention can be subjected to a brief wet chemical cleaning step using a potassium permanganate solution. Similarly, the structure can be rinsed with distilled water to remove dirt. This cleaning step cleans the desired surface without causing significant damage or damage to the structure.

本案之優點在於導線64形成後不需從中分離或分割出匯流點或相關電路系統。匯流點可於形成焊墊56、路由線58、蓋體60與端子62之濕式化學蝕刻步驟中分離。The advantage of this case is that there is no need to separate or separate the confluence points or associated circuitry from the wires 64 after they are formed. The sink point can be separated during the wet chemical etching step of forming pad 56, routing line 58, cover 60 and terminal 62.

導熱板74可包含鑽透或切通黏著層28、基板34與防焊綠漆68、70而形成之對位孔(圖未示)。如此一來，當導熱板74需於後續製程中設置於一下方載體時，便可將工具接腳***對位孔中，藉以將導熱板74置於定位。The heat conducting plate 74 may include a counter hole (not shown) formed by drilling or cutting through the adhesive layer 28, the substrate 34 and the solder resist green paint 68, 70. In this way, when the heat conducting plate 74 needs to be disposed on a lower carrier in a subsequent process, the tool pin can be inserted into the alignment hole to position the heat conducting plate 74.

導熱板74可略去蓋體60。欲達此一目的，可調整圖案化之蝕刻阻層52，使整個通孔40上方之導電層50均曝露於用以形成焊墊56及路由線58之化學蝕刻液中。略去蓋體60之另一作法係不設導電層50。The cover 60 can be omitted from the heat conducting plate 74. To achieve this, the patterned etch stop layer 52 can be adjusted such that the conductive layer 50 over the entire via 40 is exposed to the chemical etchant used to form the pads 56 and routing lines 58. Another method of omitting the cover 60 is to provide no conductive layer 50.

導熱板74可容納多個半導體元件而非僅容納單一半導體元件。欲達此一目的，可調整圖案化之蝕刻阻層16以定義更多導熱凸柱22與訊號凸柱24，調整黏著層28以包含更多開口30、32，調整基板34以包含更多通孔40、42，調整圖案化之蝕刻阻層52以定義更多焊墊56、路由線58與蓋體60，並調整防焊綠漆68以包含更多開口。端子62 以外之元件可改變側向位置以便為四個半導體元件提供一2x2陣列。此外，部分但非所有元件之剖面形狀及高低(即側面形狀)亦可有所調整。例如，焊墊56、蓋體60與端子62可保持相同之側面形狀，而路由線58則具有不同之路由構型。The heat conducting plate 74 can accommodate a plurality of semiconductor components instead of only a single semiconductor component. To achieve this, the patterned etch stop layer 16 can be modified to define more thermally conductive posts 22 and signal posts 24, the adhesive layer 28 can be adjusted to include more openings 30, 32, and the substrate 34 can be adjusted to include more passes. The holes 40, 42 are patterned to etch the etch stop layer 52 to define more pads 56, routing lines 58 and cover 60, and to adjust the solder resist green lacquer 68 to include more openings. Terminal 62 Components other than the ones can change the lateral position to provide a 2x2 array for the four semiconductor components. In addition, the cross-sectional shape and height (ie, side shape) of some but not all components may be adjusted. For example, pad 56, cover 60 and terminal 62 may maintain the same side shape, while routing line 58 has a different routing configuration.

圖5A、圖5B及圖5C分別為本發明一實施例中一導熱板76之剖視圖、俯視圖及仰視圖，該導熱板76在其黏著層28上設有一導線64。5A, 5B, and 5C are respectively a cross-sectional view, a top view, and a bottom view of a heat conducting plate 76 according to an embodiment of the present invention. The heat conducting plate 76 is provided with a wire 64 on the adhesive layer 28.

本實施例省略介電層38，且導線64係與黏著層28接觸。為求簡明，凡導熱板74之相關說明適用於此實施例者均併入此處，相同之說明不予重覆。同樣地，本實施例導熱板76之元件與導熱板74之元件相仿者，均採對應之參考標號。In this embodiment, the dielectric layer 38 is omitted and the wires 64 are in contact with the adhesive layer 28. For the sake of brevity, the description of the heat conducting plate 74 is applicable to this embodiment, and the same description will not be repeated. Similarly, the components of the heat conducting plate 76 of this embodiment are similar to those of the heat conducting plate 74, and corresponding reference numerals are used.

導熱板76包含黏著層28、導線64、散熱座66與防焊綠漆68、70。導線64包含訊號凸柱24、焊墊56、路由線58與端子62。散熱座66包含導熱凸柱22、基座26與蓋體60。The thermally conductive plate 76 includes an adhesive layer 28, wires 64, heat sinks 66 and solder resist green paints 68,70. Wire 64 includes signal studs 24, pads 56, routing lines 58, and terminals 62. The heat sink 66 includes a heat conductive stud 22, a base 26 and a cover 60.

本實施例之導電層36較前一實施例為厚。例如，導電層36之厚度由前一實施例中之30微米增為130微米，如此一來，導電層36便不至於在搬動時彎曲晃動。焊墊56與路由線58之厚度也因此增加，且焊墊56與路由線58均接觸並重疊於黏著層28。導熱板76並無對應於介電層38之介電層。The conductive layer 36 of this embodiment is thicker than the previous embodiment. For example, the thickness of the conductive layer 36 is increased from 30 micrometers to 130 micrometers in the previous embodiment, so that the conductive layer 36 does not bend and sway during handling. The thickness of pad 56 and routing line 58 is also increased, and pad 56 and routing line 58 both contact and overlap the adhesive layer 28. Thermally conductive plate 76 does not have a dielectric layer corresponding to dielectric layer 38.

導熱板76之製作方式與導熱板74類似，但必須為導熱凸柱22、訊號凸柱24與導電層36進行適當調整。例如將金屬板10之厚度由330微米改為280微米，以使導熱凸柱22、訊號凸柱24之高度由300微米降為250微米。縮短蝕刻時間即可達成此一目的。然後依前文所述之方式，將黏著層28設置於基座26上，再將導電層36單獨設置於黏著層28上；對黏著層28加熱及加壓，使黏著層28流動並固化；接著以研磨方式使結構體之頂面成為平面，再將導電層50沉積於該頂面。然後蝕刻導電層36、50以形成焊墊56與路由線58，蝕刻導電層50以形成蓋體60，蝕刻基座26以形成端子62，再將防焊綠漆68設置於該頂面以選擇性曝露焊墊56與蓋體60，並將防焊綠漆70設置於結構體之底面以選擇性曝露基座26與端子62，最後再以披覆接點72為基座26、焊墊56、蓋體60與端子62進行表面處理。The heat conducting plate 76 is fabricated in a manner similar to the heat conducting plate 74, but must be a guide The heat studs 22, the signal studs 24 and the conductive layer 36 are appropriately adjusted. For example, the thickness of the metal plate 10 is changed from 330 micrometers to 280 micrometers, so that the height of the heat conducting studs 22 and the signal studs 24 is reduced from 300 micrometers to 250 micrometers. This can be achieved by shortening the etching time. Then, the adhesive layer 28 is disposed on the susceptor 26 in the manner described above, and the conductive layer 36 is separately disposed on the adhesive layer 28; the adhesive layer 28 is heated and pressurized to cause the adhesive layer 28 to flow and solidify; The top surface of the structure is planarized by grinding, and the conductive layer 50 is deposited on the top surface. The conductive layers 36, 50 are then etched to form the pads 56 and routing lines 58, the conductive layer 50 is etched to form the cover 60, the pedestal 26 is etched to form the terminals 62, and the solder resist green lacquer 68 is placed over the top surface to select The pad 56 and the cover 60 are exposed, and the solder resist green paint 70 is disposed on the bottom surface of the structure to selectively expose the pedestal 26 and the terminal 62. Finally, the lap joint 72 is used as the pedestal 26 and the pad 56. The cover 60 and the terminal 62 are surface-treated.

圖6A、圖6B及圖6C分別為本發明一實施例中一半導體晶片組體100之剖視圖、俯視圖及仰視圖，該半導體晶片組體100包含一導熱板74及一具有背面接點之LED封裝體102。6A, FIG. 6B and FIG. 6C are respectively a cross-sectional view, a top view and a bottom view of a semiconductor wafer package 100 according to an embodiment of the present invention. The semiconductor wafer package 100 includes a heat conducting plate 74 and an LED package having a back contact. Body 102.

半導體晶片組體100包含導熱板74、LED封裝體102及焊錫104、106。LED封裝體102包含LED晶片108、基座110、打線112、電接點114、熱接點116與透明封裝材料118。LED晶片108之一電極(圖未示)係經由打線112電性連結至基座110中之一導電孔(圖未示)，藉以將LED晶片108電性連結至電接點114。LED晶片108係透過一固晶材料(圖未示)設置於基座110上，使LED晶片108熱連結且機械性黏附於基座110，藉此將LED晶片108熱連結至熱接點116。基座110為一具有低導電性及高導熱性之陶瓷塊，電接點114、熱接點116係被覆於基座110背部並自基座110背部向下突伸。The semiconductor wafer package 100 includes a heat conductive plate 74, an LED package 102, and solders 104 and 106. The LED package 102 includes an LED wafer 108, a pedestal 110, a wire 112, electrical contacts 114, thermal contacts 116, and a transparent encapsulation material 118. An electrode (not shown) of the LED chip 108 is electrically connected to one of the conductive holes (not shown) of the susceptor 110 via the wire 112 to electrically connect the LED chip 108 to the electrical contact 114. LED chip 108 is transmitted through a solid crystal A material (not shown) is disposed on the susceptor 110 to thermally bond and mechanically adhere the LED wafer 108 to the susceptor 110, thereby thermally bonding the LED wafer 108 to the thermal junction 116. The susceptor 110 is a ceramic block having low conductivity and high thermal conductivity. The electrical contact 114 and the thermal contact 116 are covered on the back of the pedestal 110 and protrude downward from the back of the pedestal 110.

LED封裝體102係設置於基板34與散熱座66上，電性連結至基板34，並熱連結至散熱座66。詳而言之，LED封裝體102係設置於焊墊56與蓋體60上，重疊於導熱凸柱22，且經由焊錫104電性連結至基板34，並經由焊錫106熱連結至散熱座66。例如，焊錫104接觸且位於焊墊56與電接點114之間，同時電性連結且機械性黏合焊墊56與電接點114，藉此將LED晶片108電性連結至端子62。同樣地，焊錫106接觸且位於蓋體60與熱接點116之間，同時熱連結且機械性黏合蓋體60與熱接點116，藉此將LED晶片108熱連結至基座26。焊墊56上設有鎳/金之被覆金屬接墊以利與焊錫104穩固結合，且焊墊56之形狀及尺寸均配合電接點114，藉此改善自基板34至LED封裝體102之訊號傳導。同樣地，蓋體60上設有鎳/金之被覆金屬接墊以利與焊錫106穩固結合，且蓋體60之形狀及尺寸均配合熱接點116，藉此改善自LED封裝體102至散熱座66之熱傳遞。至於導熱凸柱22之形狀及尺寸則並未且亦不需配合熱接點116而設計。The LED package 102 is disposed on the substrate 34 and the heat sink 66 , electrically connected to the substrate 34 , and thermally coupled to the heat sink 66 . In detail, the LED package 102 is disposed on the pad 56 and the lid 60 , overlaps the heat conducting stud 22 , is electrically connected to the substrate 34 via the solder 104 , and is thermally coupled to the heat sink 66 via the solder 106 . For example, the solder 104 contacts and is located between the pad 56 and the electrical contact 114 , and electrically and mechanically bonds the pad 56 and the electrical contact 114 , thereby electrically connecting the LED chip 108 to the terminal 62 . Similarly, the solder 106 contacts and is located between the cover 60 and the thermal contact 116 while thermally bonding and mechanically bonding the cover 60 to the thermal contact 116, thereby thermally bonding the LED wafer 108 to the pedestal 26. The pad 56 is provided with a nickel/gold coated metal pad for stable bonding with the solder 104, and the pad 56 is shaped and sized to match the electrical contact 114, thereby improving the signal from the substrate 34 to the LED package 102. Conduction. Similarly, the cover 60 is provided with a nickel/gold coated metal pad for stable bonding with the solder 106, and the shape and size of the cover 60 are matched with the thermal contact 116, thereby improving the self-LED package 102 to heat dissipation. Heat transfer from seat 66. The shape and size of the thermally conductive studs 22 are not and do not need to be designed in conjunction with the thermal contacts 116.

透明封裝材料118為一固態電性絕緣保護性塑膠包覆體，其可為LED晶片108及打線112提供諸如抗潮溼及防微粒等環境保護。LED晶片108與打線112係埋設於透明封裝材料118中。The transparent encapsulating material 118 is a solid electrically insulating protective plastic covering, which can provide anti-moisture and anti-micro for the LED chip 108 and the wire 112. Environmental protection such as grain. The LED chip 108 and the wire 112 are embedded in the transparent encapsulation material 118.

若欲製造半導體晶片組體100，可將一焊料沉積於焊墊56及蓋體60上，然後將接點114與116分別放置於焊墊56及蓋體60上方之焊料上，繼而使該焊料迴焊以形成接著之焊錫104、106。If the semiconductor wafer package 100 is to be fabricated, a solder may be deposited on the pad 56 and the cover 60, and then the contacts 114 and 116 are placed on the pads 56 and the solder over the cover 60, respectively. Reflow is performed to form subsequent solders 104,106.

例如，先以網版印刷之方式將錫膏選擇性印刷於焊墊56及蓋體60上，而後利用一抓取頭與一自動化圖案辨識系統以步進重複之方式將LED封裝體102放置於導熱板74上。迴焊機之抓取頭將電接點114、熱接點116分別放置於焊墊56及蓋體60上方之錫膏上。接著加熱錫膏，使其以相對較低之溫度(如190ºC)迴焊，然後移除熱源，靜待錫膏冷卻並固化以形成硬化焊錫104、106。或者，可於焊墊56與蓋體60上放置錫球，然後將電接點114、熱接點116分別放置於焊墊56與蓋體60上方之錫球上，接著加熱錫球使其迴焊以形成接著之焊錫104、106。For example, the solder paste is selectively printed on the pad 56 and the cover 60 by screen printing, and then the LED package 102 is placed in a step-and-repeat manner by using a grab head and an automated pattern recognition system. On the heat conducting plate 74. The grabbing head of the reflow machine places the electric contact 114 and the hot contact 116 on the solder paste 56 and the solder paste above the cover 60, respectively. The solder paste is then heated to reflow at a relatively low temperature (e.g., 190oC), then the heat source is removed, and the solder paste is allowed to cool and solidify to form hardened solders 104,106. Alternatively, a solder ball may be placed on the pad 56 and the cover 60, and then the electrical contact 114 and the hot contact 116 are respectively placed on the solder ball 56 and the solder ball above the cover 60, and then the solder ball is heated to be returned. Soldering to form subsequent solders 104,106.

焊料起初可經由被覆或印刷或佈置技術沉積於導熱板74或LED封裝體102上，使其位於導熱板74與LED封裝體102之間，並使其迴焊。焊料亦可置於端子62上以供下一層組體使用。此外，尚可利用一導電黏著劑(例如填充銀之環氧樹脂)或其他連結媒介取代焊料，且焊墊56、蓋體60與端子62上之連接媒介不必相同。The solder may initially be deposited on the thermally conductive plate 74 or the LED package 102 via coating or printing or placement techniques between the thermally conductive plate 74 and the LED package 102 and reflowed. Solder can also be placed on terminal 62 for use by the next layer of the assembly. In addition, the solder may be replaced by a conductive adhesive (for example, a silver-filled epoxy) or other bonding medium, and the bonding pads 56, the cover 60 and the connecting medium on the terminal 62 are not necessarily the same.

該半導體晶片組體100為一第二級單晶模組。The semiconductor wafer package 100 is a second-level single crystal module.

圖7A、圖7B與圖7C分別為本發明一實施例中一半導體晶片組體200之剖視圖、俯視圖及仰視圖，其中該半導體晶片組體200包含一導熱板74及一具有側引腳之LED封裝體202。7A, 7B and 7C are respectively a half guide according to an embodiment of the present invention. The semiconductor wafer package 200 includes a heat conducting plate 74 and an LED package 202 having side pins.

於此實施例中，該LED封裝體202具有側引腳而不具有背面接點。為求簡明，凡半導體晶片組體100之相關說明適用於此實施例者均併入此處，相同之說明不予重覆。同樣地，本實施例組體之元件與組體100之元件相仿者，均採對應之參考標號，但其編碼之基數由100改為200。例如，LED晶片208對應於LED晶片108，而基座210則對應於基座110，以此類推。In this embodiment, the LED package 202 has side pins and no back contacts. For the sake of brevity, the description of the semiconductor wafer package 100 is applicable to this embodiment, and the same description will not be repeated. Similarly, the components of the assembly of this embodiment are similar to those of the component 100, and the corresponding reference numerals are used, but the base number of the coding is changed from 100 to 200. For example, LED die 208 corresponds to LED die 108, while pedestal 210 corresponds to pedestal 110, and so on.

半導體晶片組體200包含導熱板74、LED封裝體202與焊錫204、206。LED封裝體202包含LED晶片208、基座210、打線212、引腳214與透明封裝材料218。LED晶片208係經由打線212電性連結至引腳214。基座210背面包含熱接觸表面216，此外，基座210係窄於基座110且與熱接點116具有相同之側向尺寸及形狀。LED晶片208係經由一固晶材料(圖未示)設置於於基座210上，使LED晶片208熱連結且機械性黏附於基座210，藉此將LED晶片208熱連結至熱接觸表面216。引腳214自基座210往側向延伸，而熱接觸表面216則面朝下。The semiconductor wafer package 200 includes a heat conductive plate 74, an LED package 202, and solders 204, 206. The LED package 202 includes an LED wafer 208, a pedestal 210, a wire 212, a pin 214, and a transparent encapsulation material 218. The LED chip 208 is electrically coupled to the pin 214 via the wire 212. The back side of the susceptor 210 includes a thermal contact surface 216. Further, the pedestal 210 is narrower than the pedestal 110 and has the same lateral dimensions and shape as the thermal junction 116. The LED chip 208 is disposed on the susceptor 210 via a die bonding material (not shown) to thermally bond and mechanically adhere the LED chip 208 to the susceptor 210, thereby thermally bonding the LED chip 208 to the thermal contact surface 216. . Pin 214 extends laterally from pedestal 210 while thermal contact surface 216 faces downward.

LED封裝體202係設置於基板34與散熱座66上，電性連結至基板34，且熱連結至散熱座66。詳而言之，LED封裝體202係設置於焊墊56與蓋體60上，重疊於導熱凸柱22，且經由焊錫204電性連結至基板34，並經由焊錫 206熱連結至散熱座66。例如，焊錫204接觸且位於焊墊56與引腳214之間，同時電性連結且機械性黏合焊墊56與引腳214，藉此將LED晶片208電性連結至端子62。同樣地，焊錫206接觸且位於蓋體60與熱接觸表面216之間，同時熱連結且機械性黏合蓋體60與熱接觸表面216，藉此將LED晶片208熱連結至基座26。The LED package 202 is disposed on the substrate 34 and the heat sink 66 , electrically connected to the substrate 34 , and thermally coupled to the heat sink 66 . In detail, the LED package 202 is disposed on the pad 56 and the cover 60, overlaps the heat conducting stud 22, and is electrically connected to the substrate 34 via the solder 204, and is soldered via the solder. 206 is thermally coupled to the heat sink 66. For example, the solder 204 contacts and is located between the pad 56 and the pin 214 , and electrically and mechanically bonds the pad 56 and the pin 214 , thereby electrically connecting the LED chip 208 to the terminal 62 . Similarly, the solder 206 contacts and is positioned between the cover 60 and the thermal contact surface 216 while thermally bonding and mechanically bonding the cover 60 to the thermal contact surface 216, thereby thermally bonding the LED wafer 208 to the pedestal 26.

若欲製造半導體晶片組體200，可將一焊料置於焊墊56與蓋體60上，然後分別在焊墊56與蓋體60上方之焊料上放置引腳214與熱接觸表面216，繼而使該焊料迴焊以形成接著之焊錫204、206。If the semiconductor wafer package 200 is to be fabricated, a solder may be placed on the pad 56 and the cover 60, and then the pins 214 and the thermal contact surface 216 are placed on the solder over the pads 56 and the cover 60, respectively. The solder is reflowed to form the next solder 204, 206.

該半導體晶片組體200為一第二級單晶模組。The semiconductor wafer package 200 is a second-level single crystal module.

圖8A、圖8B及圖8C分別為本發明一實施例中一半導體晶片組體300之剖視圖、俯視圖及仰視圖，其中該半導體晶片組體300包含一導熱板74及一半導體晶片302。8A, 8B, and 8C are respectively a cross-sectional view, a top view, and a bottom view of a semiconductor wafer assembly 300 in accordance with an embodiment of the present invention, wherein the semiconductor wafer assembly 300 includes a thermally conductive plate 74 and a semiconductor wafer 302.

於此實施例中，該半導體元件為一晶片而非一封裝體，且該晶片302係設置於前述散熱座66而非前述基板34上。此外，該晶片302係重疊於前述導熱凸柱22而非前述基板34，且該晶片302係經由一打線電性連結至前述焊墊56，並利用一固晶材料306熱連結至前述蓋體60。In this embodiment, the semiconductor component is a wafer instead of a package, and the wafer 302 is disposed on the heat sink 66 instead of the substrate 34. In addition, the wafer 302 is superposed on the heat conducting stud 22 instead of the substrate 34, and the wafer 302 is electrically connected to the pad 56 via a wire and thermally bonded to the cover 60 by a die bonding material 306. .

半導體晶片組體300包含導熱板74、晶片302、打線304、固晶材料306及封裝材料308。晶片302包含頂面310、底面312與打線接墊314。頂面310為活性表面且包含打線接墊314，而底面312則為熱接觸表面。The semiconductor wafer package 300 includes a heat conducting plate 74, a wafer 302, a wire bonding 304, a die bonding material 306, and an encapsulating material 308. The wafer 302 includes a top surface 310, a bottom surface 312, and a wire bonding pad 314. The top surface 310 is an active surface and includes a wire bond pad 314, while the bottom surface 312 is a thermal contact surface.

晶片302係設置於散熱座66上，電性連結至基板34，且熱連結至散熱座66。詳而言之，晶片302係設置於蓋體60上，位於蓋體60之周緣內，重疊於導熱凸柱22但未重疊於基板34。此外，晶片302係經由打線304電性連結至基板34，同時經由固晶材料306熱連結且機械性黏附於散熱座66。例如，打線304係連接於並電性連結焊墊56及打線接墊314，藉此將晶片302電性連結至端子62。同樣地，固晶材料306接觸且位於蓋體60與熱接觸表面312之間，同時熱連結且機械性黏合蓋體60與熱接觸表面312，藉此將晶片302熱連結至基座26。焊墊56上設有鎳/銀之被覆金屬接墊以利與打線304穩固接合，藉此改善自基板34至晶片302之訊號傳送。此外，蓋體60之形狀及尺寸係與熱接觸表面312配適，藉此改善自晶片302至散熱座66之熱傳送。至於導熱凸柱22之形狀及尺寸則並未且亦不需配合熱接觸表面312而設計。The chip 302 is disposed on the heat sink 66 and electrically connected to the substrate 34. And thermally coupled to the heat sink 66. In detail, the wafer 302 is disposed on the cover 60 and is located in the periphery of the cover 60 and overlaps the thermally conductive stud 22 but does not overlap the substrate 34. In addition, the wafer 302 is electrically connected to the substrate 34 via the bonding wires 304 while being thermally coupled via the die bonding material 306 and mechanically adhered to the heat sink 66. For example, the wire 304 is connected to the electrically conductive pad 56 and the wire bonding pad 314, thereby electrically connecting the wafer 302 to the terminal 62. Similarly, the die bond material 306 contacts and is positioned between the cover 60 and the thermal contact surface 312 while thermally bonding and mechanically bonding the cover 60 to the thermal contact surface 312, thereby thermally bonding the wafer 302 to the pedestal 26. The pad 56 is provided with a nickel/silver coated metal pad for secure bonding with the wire 304, thereby improving signal transmission from the substrate 34 to the wafer 302. In addition, the shape and size of the cover 60 is adapted to the thermal contact surface 312, thereby improving heat transfer from the wafer 302 to the heat sink 66. The shape and size of the thermally conductive studs 22 are not and do not need to be designed in conjunction with the thermal contact surface 312.

封裝材料308為一固態電性絕緣保護性塑膠包覆體，其可為晶片302及打線304提供抗潮溼及防微粒等環境保護。晶片302與打線304係埋設於封裝材料308中。此外，若晶片302係一諸如LED之光學晶片，則封裝材料308可為透明狀。封裝材料308在圖8B中呈透明狀係為方便圖示說明。The encapsulating material 308 is a solid electrically insulating protective plastic covering body, which can provide environmental protection against moisture and anti-particles for the wafer 302 and the wire bonding 304. The wafer 302 and the wire 304 are embedded in the encapsulation material 308. Additionally, if wafer 302 is an optical wafer such as an LED, encapsulation material 308 can be transparent. The encapsulating material 308 is transparent in FIG. 8B for ease of illustration.

若欲製造半導體晶片組體300，可利用固晶材料306將晶片302設置於蓋體60上，接著將焊墊56及打線接墊314以打線接合，而後形成封裝材料308。If the semiconductor wafer assembly 300 is to be fabricated, the wafer 302 can be placed on the cover 60 by using the die bonding material 306, and then the bonding pads 56 and the bonding pads 314 are bonded by wire bonding, and then the sealing material 308 is formed.

例如，固晶材料306原為一具有高導熱性之含銀環氧樹脂膏，並以網版印刷之方式選擇性印刷於蓋體60上。然後利用一抓取頭及一自動化圖案辨識系統以步進重複之方式將晶片302放置於該環氧樹脂銀膏上。繼而加熱該環氧樹脂銀膏，使其於相對低溫(如190ºC)下硬化以完成固晶。打線304為金線，其隨即以熱超音波連接焊墊56及打線接墊314。最後再將封裝材料308轉移模製於結構體上。For example, the solid crystal material 306 is originally a silver-containing epoxy having high thermal conductivity. The resin paste is selectively printed on the cover 60 by screen printing. The wafer 302 is then placed on the epoxy silver paste in a step-and-repeat manner using a pick-up head and an automated pattern recognition system. The epoxy silver paste is then heated and allowed to harden at a relatively low temperature (e.g., 190 ° C) to complete the solid crystal. The wire 304 is a gold wire which is then connected to the bonding pad 56 and the wire bonding pad 314 by thermal ultrasonic waves. Finally, the encapsulation material 308 is transferred onto the structure.

晶片302可透過多種連結媒介電性連結至焊墊56，利用多種熱黏著劑熱連結並機械性黏附於散熱座66，並以多種封裝材料封裝。The wafer 302 can be electrically connected to the bonding pad 56 through a plurality of bonding media, thermally bonded by a plurality of thermal adhesives and mechanically adhered to the heat sink 66, and packaged in a plurality of packaging materials.

該半導體晶片組體300為一第一級單晶封裝體。The semiconductor wafer package 300 is a first-level single crystal package.

上述之半導體晶片組體與導熱板僅為說明範例，本發明尚可透過其他多種實施例實現。此外，上述實施例可依設計及可靠度之考量，彼此混合搭配使用或與其他實施例混合搭配使用。例如，該基板可包含複數組單層導線與複數組多層導線。該導熱板可包含多個凸柱，且該些凸柱係排成一陣列以供多個半導體元件使用，此外，該導熱板為配合額外之半導體元件，可包含更多導線。同樣地，該半導體元件可為一具有多枚LED晶片之LED封裝體，而該導熱板則可包含更多導線以配合額外之LED晶片。該半導體元件與該蓋體可重疊於該基板，並從上方覆蓋該導熱凸柱。The semiconductor wafer package and the heat conductive plate described above are merely illustrative examples, and the present invention can be implemented by other various embodiments. In addition, the above embodiments may be used in combination with other embodiments or in combination with other embodiments in consideration of design and reliability. For example, the substrate can comprise a complex array of single layer conductors and a complex array of multilayer conductors. The heat conducting plate may comprise a plurality of studs, and the studs are arranged in an array for use by a plurality of semiconductor components. Further, the heat conducting plate may be configured to accommodate additional semiconductor components and may include more wires. Similarly, the semiconductor component can be an LED package having a plurality of LED chips, and the thermally conductive plate can include more wires to accommodate additional LED chips. The semiconductor element and the cover may overlap the substrate and cover the thermally conductive stud from above.

該半導體元件可獨自使用該散熱座或與其他半導體元件共用該散熱座。例如，可將單一半導體元件設置於該散熱座上，或將多個半導體元件設置於該散熱座上。舉例而言，可將四枚排列成2x2陣列之小型晶片黏附於該導熱凸柱，而該基板則可包含額外之導線以配合該些晶片之電性連接。此一作法遠較為每一晶片設置一微小導熱凸柱更具經濟效益。The semiconductor element can use the heat sink alone or share the heat sink with other semiconductor elements. For example, a single semiconductor component can be disposed on the heat sink or a plurality of semiconductor components can be disposed on the heat sink. For example That is, four small wafers arranged in a 2x2 array can be attached to the thermally conductive studs, and the substrate can include additional wires to match the electrical connections of the wafers. This practice is far more economical than setting a tiny thermally conductive stud on each wafer.

該半導體晶片可為光學性或非光學性。例如，該晶片可為一LED、一太陽能電池、一微處理器、一控制器或一射頻(RF)功率放大器。同樣地，該半導體封裝體可為一LED封裝體或一射頻模組。因此，該半導體元件可為一經封裝或未經封裝之光學或非光學晶片。此外，吾人可利用多種連結媒介將該半導體元件機械性連結、電性連結及熱連結至該導熱板，包括利用焊接及使用導電及/或導熱黏著劑等方式達成。The semiconductor wafer can be optical or non-optical. For example, the wafer can be an LED, a solar cell, a microprocessor, a controller, or a radio frequency (RF) power amplifier. Similarly, the semiconductor package can be an LED package or a radio frequency module. Thus, the semiconductor component can be a packaged or unpackaged optical or non-optical wafer. In addition, the semiconductor element can be mechanically, electrically and thermally bonded to the heat conducting plate by a plurality of connecting media, including by soldering and using an electrically conductive and/or thermally conductive adhesive.

該散熱座可將該半導體元件所產生之熱能迅速、有效且均勻散發至下一層組體而不需使熱流通過該黏著層、該基板或該導熱板之他處。如此一來便可使用導熱性較低之黏著層，進而大幅降低成本。該散熱座可包含一體成形之導熱凸柱與基座，以及與該導熱凸柱為冶金連結及熱連結之一蓋體，藉此提高可靠度並降低成本。該蓋體可與該焊墊共平面，以便與該半導體元件形成電性、熱能及機械性連結。此外，該蓋體可依該半導體元件量身訂做，而該基座則可依下一層組體量身訂做，藉此加強自該半導體元件至下一層組體之熱連結。例如，該導熱凸柱在一側向平面上可呈圓形，該蓋體在一側向平面上可呈正方形或矩形，且該蓋體之側面形狀與該半導體元件熱接點之側面形狀相同或相似。The heat sink can quickly, efficiently and uniformly dissipate the thermal energy generated by the semiconductor component to the next layer assembly without passing heat through the adhesive layer, the substrate or the heat conducting plate elsewhere. In this way, an adhesive layer having a lower thermal conductivity can be used, thereby greatly reducing the cost. The heat sink can include an integrally formed thermally conductive stud and a base, and a cover body that is metallurgically bonded and thermally coupled to the thermally conductive stud, thereby improving reliability and reducing cost. The cover can be coplanar with the pad to form electrical, thermal, and mechanical bonds with the semiconductor component. In addition, the cover may be tailored to the semiconductor component, and the pedestal may be tailored to the next layer of the body to enhance thermal bonding from the semiconductor component to the next layer. For example, the thermally conductive stud may be circular in a lateral plane, the cover may be square or rectangular in a lateral plane, and the side shape of the cover may be opposite to the side shape of the thermal junction of the semiconductor component. Same or similar.

該散熱座可與該半導體元件及該基板為電性連結或電性隔離。例如，位於研磨後之表面上之該第二導電層可包含一路由線，該路由線係於該基板與該蓋體之間延伸通過該黏著層，藉以將該半導體元件電性連結至該散熱座。之後，該散熱座可電性接地，藉以將該半導體元件電性接地。The heat sink can be electrically or electrically isolated from the semiconductor component and the substrate. For example, the second conductive layer on the polished surface may include a routing line extending between the substrate and the cover through the adhesive layer, thereby electrically connecting the semiconductor element to the heat dissipation. seat. Thereafter, the heat sink can be electrically grounded to electrically ground the semiconductor component.

該散熱座可為銅質、鋁質、銅/鎳/鋁合金或其他導熱金屬結構。The heat sink can be copper, aluminum, copper/nickel/aluminum alloy or other thermally conductive metal structure.

該導熱凸柱可沉積於該基座上或與該基座一體成形。該導熱凸柱可與該基座一體成形，因而成為單一金屬體(如銅或鋁)。該導熱凸柱亦可與該基座一體成形，使該兩者之介面包含單一金屬體(例如銅)，至於他處則包含其他金屬(例如凸柱之上部為焊料，凸柱之下部及基座則為銅質)。該導熱凸柱亦可與該基座一體成形，使該兩者之介面包含多層單一金屬體(例如在一鋁核心外設有一鎳緩衝層，而該鎳緩衝層上則設有一銅層)。The thermally conductive stud can be deposited on the base or integrally formed with the base. The thermally conductive stud can be integrally formed with the base and thus become a single metal body (such as copper or aluminum). The thermally conductive stud can also be integrally formed with the base such that the interface between the two comprises a single metal body (for example, copper), and other portions include other metals (for example, the upper portion of the stud is solder, the lower portion of the stud and the base) The seat is made of copper). The thermally conductive stud can also be integrally formed with the base such that the interface between the two comprises a plurality of layers of a single metal body (eg, a nickel buffer layer on an aluminum core peripheral and a copper layer on the nickel buffer layer).

該訊號凸柱可沉積於該端子上或與該端子一體成形。該訊號凸柱可與該端子一體成形，因而成為單一金屬體(如銅或鋁)。該訊號凸柱亦可與該端子一體成形，使該兩者之介面包含單一金屬體(例如銅)，至於他處則包含其他金屬(例如凸柱之上部為焊料，凸柱之下部及端子則為銅質)。該訊號凸柱亦可與該端子一體成形，使該兩者之介面包含多層單一金屬體(例如在一鋁核心外設有一鎳緩衝層，而該鎳緩衝層上則設有一銅層)。The signal stud can be deposited on the terminal or integrally formed with the terminal. The signal stud can be integrally formed with the terminal and thus becomes a single metal body (such as copper or aluminum). The signal stud can also be integrally formed with the terminal such that the interface between the two comprises a single metal body (for example, copper), and other portions include other metals (for example, the upper portion of the stud is solder, the lower portion of the stud and the terminal For copper). The signal stud can also be integrally formed with the terminal such that the interface between the two comprises a plurality of single metal bodies (for example, a nickel buffer layer is disposed on an aluminum core peripheral, and the nickel A buffer layer is provided on the buffer layer).

該導熱凸柱可包含一平坦之頂面，且該頂面係與該黏著層共平面。例如，該導熱凸柱可與該黏著層共平面，或者該導熱凸柱可在該黏著層固化後接受蝕刻，因而在該導熱凸柱上方之黏著層形成一凹穴。吾人亦可選擇性蝕刻該導熱凸柱，藉以在該導熱凸柱中形成一延伸至其頂面下方之凹穴。在上述任一情況下，該半導體元件均可設置於該導熱凸柱上並位於該凹穴中，而該打線則可從該凹穴內之該半導體元件延伸至該凹穴外之該焊墊。在此情況下，該半導體元件可為一LED晶片，並由該凹穴將LED光線朝該向上方向聚焦。The thermally conductive stud may include a flat top surface and the top surface is coplanar with the adhesive layer. For example, the thermally conductive stud may be coplanar with the adhesive layer, or the thermally conductive stud may be etched after the adhesive layer is cured, such that the adhesive layer over the thermally conductive stud forms a recess. The thermally conductive stud can also be selectively etched to form a recess extending into the thermally conductive stud below its top surface. In any of the above cases, the semiconductor component may be disposed on the thermally conductive stud and located in the recess, and the bonding wire may extend from the semiconductor component in the recess to the pad outside the recess . In this case, the semiconductor component can be an LED wafer and the LED light is focused by the recess toward the upward direction.

該基座可為該基板提供機械性支撐。例如，該基座可防止該基板在金屬研磨、晶片設置、打線接合及模製封裝材料之過程中彎曲變形。此外，該基座之背部可包含沿該向下方向突伸之鰭片。例如，可利用一鑽板機切削該基座之底面以形成側向溝槽，而此等側向溝槽即為鰭片。在此例中，該基座之厚度可為500微米，該等溝槽之深度可為300微米，亦即該等鰭片之高度可為300微米。該等鰭片可增加該基座之表面積，若該等鰭片係曝露於空氣中而非設置於一散熱裝置上，則可提升該基座經由熱對流之導熱性。The pedestal provides mechanical support for the substrate. For example, the susceptor can prevent the substrate from being bent and deformed during metal grinding, wafer placement, wire bonding, and molding of the packaging material. Additionally, the back of the base may include fins that project in the downward direction. For example, a rig can be used to cut the bottom surface of the pedestal to form lateral grooves, and the lateral grooves are fins. In this case, the pedestal may have a thickness of 500 microns, and the depth of the grooves may be 300 microns, that is, the height of the fins may be 300 microns. The fins may increase the surface area of the susceptor, and if the fins are exposed to the air rather than being disposed on a heat sink, the thermal conductivity of the susceptor via thermal convection may be enhanced.

該蓋體可於該黏著層固化後，該焊墊及/或該端子形成之前、中或後，以多種沉積技術製成，包括以電鍍、無電鍍被覆、蒸發及噴濺等技術形成單層或多層結構。該蓋體可採用與該導熱凸柱相同之金屬材質，或採用與鄰接該蓋體之導熱凸柱頂部相同之金屬材質。此外，該蓋體可跨越該通孔並延伸至該基板，或坐落於該通孔之周緣內。因此，該蓋體可接觸該基板或與該基板保持距離。在上述任一情況下，該蓋體均係從該導熱凸柱之頂部沿側面方向側向延伸而出。The cover may be formed by various deposition techniques, including electroplating, electroless plating, evaporation, and sputtering, before, during, or after the bonding of the bonding layer, including forming a single layer by electroplating, electroless plating, evaporation, and sputtering. Or multilayer structure. The cover It can be made of the same metal material as the thermal conductive stud or the same metal material as the top of the thermal conductive stud adjacent to the cover. In addition, the cover may span the through hole and extend to the substrate or be located within the periphery of the through hole. Thus, the cover can contact or be spaced from the substrate. In either case, the cover extends laterally from the top of the thermally conductive stud in the lateral direction.

該黏著層可在該散熱座與該基板之間提供堅固之機械性連結。例如，該黏著層可自該導熱凸柱側向延伸並越過該導線到達該組體之外圍邊緣，該黏著層可填滿該散熱座與該基板間之空間，且該黏著層可為一具有均勻分佈之結合線之無孔洞結構。該黏著層亦可吸收該散熱座與該基板間因熱膨脹所產生之不匹配現象。此外，該黏著層可為一低成本電介質，且不需具備高導熱性。再者，該黏著層不易脫層。The adhesive layer provides a strong mechanical bond between the heat sink and the substrate. For example, the adhesive layer may extend laterally from the heat conducting stud and pass the wire to the peripheral edge of the group. The adhesive layer may fill the space between the heat sink and the substrate, and the adhesive layer may have A non-porous structure of a uniformly distributed bond line. The adhesive layer can also absorb the mismatch caused by thermal expansion between the heat sink and the substrate. In addition, the adhesive layer can be a low cost dielectric and does not require high thermal conductivity. Furthermore, the adhesive layer is not easily delaminated.

吾人可調整該黏著層之厚度，使該黏著層實質填滿該等缺口，並使幾乎所有黏著劑在固化及/或研磨後均位於結構體內。例如，理想之膠片厚度可由試誤法決定。同樣地，吾人亦可調整該介電層之厚度以達此一效果。We can adjust the thickness of the adhesive layer so that the adhesive layer substantially fills the gaps and allows almost all of the adhesive to be located within the structure after curing and/or grinding. For example, the ideal film thickness can be determined by trial and error. Similarly, we can also adjust the thickness of the dielectric layer to achieve this effect.

該基板可為一低成本之層壓結構，且不需具備高導熱性。此外，該基板可包含單一導電層或複數層導電層。再者，該基板可包含該導電層或由該導電層組成。The substrate can be a low cost laminate structure and does not require high thermal conductivity. Additionally, the substrate can comprise a single conductive layer or a plurality of conductive layers. Furthermore, the substrate may comprise or consist of the conductive layer.

該導電層可單獨設置於該黏著層上。例如，可先在該導電層上形成該等通孔，然後將該導電層設置於該黏著層上，使該導電層接觸該黏著層，並朝該向上方向外露，在此同時，該導熱凸柱及該訊號凸柱則延伸進入該等通孔，並透過該等通孔朝該向上方向外露。在此例中，該導電層之厚度可為100至200微米，例如125微米，此厚度一方面夠厚，故搬運時不致彎曲晃動，一方面則夠薄，故不需過度蝕刻即可形成圖案。The conductive layer can be separately disposed on the adhesive layer. For example, the through holes may be formed on the conductive layer, and then the conductive layer is disposed on the adhesive layer, so that the conductive layer contacts the adhesive layer and is exposed in the upward direction. At the same time, the heat conducting stud and the signal stud extend into the through holes and are exposed through the through holes in the upward direction. In this case, the conductive layer may have a thickness of 100 to 200 micrometers, for example, 125 micrometers. The thickness is thick enough on the one hand, so that it does not bend when transported, and is thin enough on the one hand, so that the pattern can be formed without excessive etching. .

亦可將該導電層與該介電層一同設置於該黏著層上。例如，可先將該導電層設置於該介電層上，然後在該導電層及該介電層上形成該等通孔，接著將該導電層及該介電層設置於該黏著層上，使該導電層朝該向上方向外露，並使該介電層接觸且介於該導電層與該黏著層之間，因而將該導電層與該黏著層隔開，在此同時，該導熱凸柱及該訊號凸柱則延伸進入該等通孔，並透過該等通孔朝該向上方向外露。在此例中，該導電層之厚度可為10至50微米，例如30微米，此厚度一方面夠厚，足以提供可靠之訊號傳導，一方面則夠薄，可降低重量及成本。此外，該介電層恆為該導熱板之一部分。The conductive layer may also be disposed on the adhesive layer together with the dielectric layer. For example, the conductive layer may be disposed on the dielectric layer, and then the via holes are formed on the conductive layer and the dielectric layer, and then the conductive layer and the dielectric layer are disposed on the adhesive layer. Exposing the conductive layer toward the upward direction and contacting the dielectric layer between the conductive layer and the adhesive layer, thereby separating the conductive layer from the adhesive layer, and at the same time, the thermally conductive stud And the signal studs extend into the through holes and are exposed through the through holes in the upward direction. In this case, the conductive layer may have a thickness of 10 to 50 microns, such as 30 microns, which is thick enough on the one hand to provide reliable signal transmission and, on the other hand, thin enough to reduce weight and cost. Furthermore, the dielectric layer is always part of the heat conducting plate.

亦可將該導電層與一載體同時設置於該黏著層上。例如，可先利用一薄膜將該導電層黏附於一諸如雙定向聚對苯二甲酸乙二酯膠膜(Mylar)之載體，然後僅在該導電層而非該載體上形成該等通孔，接著將該導電層及該載體設置於該黏著層上，使該載體覆蓋該導電層，且朝該向上方向外露，並使該薄膜接觸且介於該載體與該導電層之間，至於該導電層則接觸且介於該薄膜與該黏著層之間，在此同時，該導熱凸柱及該訊號凸柱則對準該等通孔，並由該載體從上方覆蓋。該黏著層固化後，可利用紫外光分解該薄膜，以便將該載體從該導電層上剝除，從而使該導電層朝該向上方向外露，之後便可研磨及圖案化該導電層以形成該導線。在此例中，該導電層之厚度可為10至50微米，例如30微米，此厚度一方面夠厚，足以提供可靠之訊號傳導，一方面則夠薄，可降低重量及成本；至於該載體之厚度可為300至500微米，此厚度一方面夠厚，故搬運時不致彎曲晃動，一方面又夠薄，有助於減少重量及成本。該載體僅為一暫時固定物，並非永久屬於該導熱板之一部分。The conductive layer may also be disposed on the adhesive layer simultaneously with a carrier. For example, the conductive layer may be adhered to a carrier such as a bi-directional polyethylene terephthalate film (Mylar) by using a film, and then the via holes are formed only on the conductive layer instead of the carrier. And then the conductive layer and the carrier are disposed on the adhesive layer, the carrier covers the conductive layer, and is exposed in the upward direction, and the film is contacted and interposed between the carrier and the conductive layer, as for the conductive The layer is in contact with and between the film and the adhesive layer, and at the same time, the heat conducting stud and the signal stud are aligned with the through holes, and the load is The body is covered from above. After the adhesive layer is cured, the film may be decomposed by ultraviolet light to strip the carrier from the conductive layer, thereby exposing the conductive layer toward the upward direction, and then the conductive layer may be ground and patterned to form the conductive layer. wire. In this case, the conductive layer may have a thickness of 10 to 50 micrometers, for example 30 micrometers, which is thick enough on the one hand to provide reliable signal transmission, and on the other hand thin enough to reduce weight and cost; The thickness can be 300 to 500 micrometers, and the thickness is thick enough on the one hand, so that it does not bend and shake when transported, and is thin enough on the one hand to help reduce weight and cost. The carrier is only a temporary fixture and is not permanently part of the heat conducting plate.

該焊墊與該端子可視該半導體元件與下一層組體之需要而採用多種封裝形式。The pad and the terminal can be in various package forms depending on the needs of the semiconductor component and the next layer assembly.

該焊墊之頂面與該蓋體之頂面可為共平面，如此一來便可藉由控制錫球之崩塌程度，強化該半導體元件與該導熱板間之焊接。The top surface of the solder pad and the top surface of the cover may be coplanar, so that the soldering between the semiconductor component and the heat conducting plate can be strengthened by controlling the degree of collapse of the solder ball.

位於該介電層上之該焊墊與該路由線可在該基板尚未或已然設置於該黏著層上時，以多種沉積技術製成，包括以電鍍、無電鍍被覆、蒸發及噴濺等技術形成單層或多層結構。例如，可在該基板尚未設置於該黏著層上時、或在該基板已藉由該黏著層而黏附於該導熱凸柱及該訊號凸柱與該基座後，於該基板上形成該導電層之圖案。The pad and the routing line on the dielectric layer can be fabricated by various deposition techniques, including electroplating, electroless plating, evaporation, and sputtering, when the substrate is not yet or already disposed on the adhesive layer. A single layer or a multilayer structure is formed. For example, the conductive layer may be formed on the substrate when the substrate is not disposed on the adhesive layer, or after the substrate has been adhered to the heat conductive stud and the signal stud and the base by the adhesive layer. The pattern of the layers.

以所述被覆接點進行表面處理之工序可於該焊墊及該端子形成之前或之後為之。例如，該被覆層可沉積於該基座及該第二導電層上，然後利用圖案化之蝕刻阻層定義該焊墊與該端子並進行蝕刻，以使該被覆層具有圖案。The step of surface treatment with the covered contacts may be performed before or after the formation of the pads and the terminals. For example, the coating layer may be deposited on the pedestal and the second conductive layer, and then the patterned etch stop layer is used to define the The pad is etched with the terminal to have a pattern of the cover layer.

該導線可包含額外之焊墊、端子、導電孔、訊號凸柱、路由線以及被動元件，且可為不同構型。該導線可作為一訊號層、一功率層或一接地層，端視其相應半導體元件焊墊之目的而定。該導線亦可包含各種導電金屬，例如銅、金、鎳、銀、鈀、錫、其混合物及其合金。理想之組成既取決於外部連結媒介之性質，亦取決於設計及可靠度方面之考量。此外，精於此技藝之人士應可瞭解，在該半導體晶片組體中所用之銅可為純銅，但通常係以銅為主之合金，如銅-鋯(99.9%銅)、銅-銀-磷-鎂(99.7%銅)及銅-錫-鐵-磷(99.7%銅)，藉以提高如抗張強度與延展性等機械性能。The wire may include additional pads, terminals, conductive vias, signal posts, routing wires, and passive components, and may be of different configurations. The wire can be used as a signal layer, a power layer or a ground layer depending on the purpose of the corresponding semiconductor component pads. The wire may also comprise various conductive metals such as copper, gold, nickel, silver, palladium, tin, mixtures thereof, and alloys thereof. The ideal composition depends both on the nature of the externally connected medium and on the design and reliability considerations. In addition, those skilled in the art will appreciate that the copper used in the semiconductor wafer package may be pure copper, but is typically a copper-based alloy such as copper-zirconium (99.9% copper), copper-silver- Phosphorus-magnesium (99.7% copper) and copper-tin-iron-phosphorus (99.7% copper) to improve mechanical properties such as tensile strength and ductility.

在一般情況下，最好在前述研磨後之表面上設有該蓋體、介電層、防焊綠漆、被覆接點及第二導電層，但於某些實施例中則可省略之。例如，若該開口及通孔係以衝孔而非鑽孔之方式產生，因而使該導熱凸柱頂部之形狀及尺寸均與該半導體元件之熱接觸表面相配適，則可省略該蓋體與該第二導電層以降低成本。同樣地，可省略該介電層以降低成本。In general, it is preferable to provide the cover, the dielectric layer, the solder resist green lacquer, the coated contact and the second conductive layer on the surface after the grinding, but in some embodiments, it may be omitted. For example, if the opening and the through hole are formed by punching instead of drilling, so that the shape and size of the top of the heat conducting stud are matched with the thermal contact surface of the semiconductor element, the cover and the cover may be omitted. The second conductive layer reduces cost. As such, the dielectric layer can be omitted to reduce cost.

該導熱板可包含一導熱孔，該導熱孔係與該導熱凸柱及該訊號凸柱保持距離，並於該等開口及該等通孔外延伸穿過該介電層與該黏著層，同時鄰接且熱連結該基座與該蓋體，藉此提升自該蓋體至該基座之散熱效果，並促進熱能在該基座內擴散。The heat conducting plate may include a heat conducting hole, the heat conducting hole is spaced apart from the heat conducting stud and the signal stud, and extends through the dielectric layer and the adhesive layer outside the openings and the through holes. The base and the cover are adjacently and thermally coupled, thereby enhancing the heat dissipation effect from the cover to the base and promoting thermal energy diffusion in the base.

本案之組體可提供水平或垂直之單層或多層訊號路由。The group of this case can provide single or multi-layer signal routing horizontally or vertically. .

林文強等人於2009年11月11日提出申請之第12/616,773號美國專利申請案：「具有凸柱/基座之散熱座及基板之半導體晶片組體」即揭露一種具有水平單層訊號路由之結構，其中焊墊、端子與路由線均位於介電層上方，此一美國專利申請案之內容在此以引用之方式併入本文。U.S. Patent Application Serial No. 12/616,773, filed on Jan. The structure of the pad, the terminal and the routing line are all located above the dielectric layer, the contents of which are incorporated herein by reference.

林文強等人於2009年11月11日提出申請之第12/616,775號美國專利申請案：「具有凸柱/基座之散熱座及導線之半導體晶片組體」則揭露另一種具有水平單層訊號路由之結構，其中焊墊、端子與路由線係位於黏著層上方，且該結構未設置介電層，此一美國專利申請案之內容在此以引用之方式併入本文。U.S. Patent Application Serial No. 12/616,775, filed on Nov. 11, 2009, the disclosure of which is incorporated herein in The structure of the routing in which the pads, terminals and routing wires are located above the adhesive layer, and the structure is not provided with a dielectric layer, the contents of which are incorporated herein by reference.

王家忠等人於2009年9月11日提出申請之第12/557,540號美國專利申請案：「具有凸柱/基座之散熱座及水平訊號路由之半導體晶片組體」揭露一種具有水平多層訊號路由之結構，其中介電層上方之焊墊與端子係利用穿過該介電層之第一及第二導電孔以及該介電層下方之路由線達成電性連結，此一美國專利申請案之內容在此以引用之方式併入本文。U.S. Patent Application Serial No. 12/557,540, the entire disclosure of which is incorporated herein by reference to the entire entire entire entire entire entire entire entire entire entire entire entire content a routing structure in which pads and terminals above the dielectric layer are electrically connected by using first and second conductive vias through the dielectric layer and routing lines under the dielectric layer. US Patent Application The content is hereby incorporated by reference.

王家忠等人於2009年9月11日提出申請之第12/557,541號美國專利申請案：「具有凸柱/基座之散熱座及垂直訊號路由之半導體晶片組體」則揭露一種具有垂直多層訊號路由之結構，其中介電層上方之焊墊與黏著層下方之端子係利用穿過該介電層之第一導電孔、該介電層下方之路由線以及穿過該黏著層之第二導電孔達成電性連結，此一美國專利申請案之內容在此以引用之方式併入本文。U.S. Patent Application Serial No. 12/557,541, the entire disclosure of which is incorporated herein by reference to the entire entire entire entire entire entire entire entire entire entire entire entire content The structure of the signal routing, wherein the pads above the dielectric layer and the terminals under the adhesive layer utilize a first conductive via that passes through the dielectric layer, below the dielectric layer The routing line and the second conductive via through the adhesive layer are electrically connected. The contents of this U.S. Patent Application is incorporated herein by reference.

該導熱板之作業格式可為單一或多個導熱板，視製造設計而定。例如，可單獨製作單一導熱板。或者，可利用單一金屬板、單一黏著層、單一基板、單一頂部防焊綠漆及單一底部防焊綠漆同時批次製造多個導熱板，而後再行分離。同樣地，針對同一批次中之各導熱板，吾人亦可利用單一金屬板、單一黏著層、單一基板、單一頂部防焊綠漆與單一底部防焊綠漆同時批次製造多組分別供單一半導體元件使用之散熱座與導線。The heat shield can be operated in a single or multiple heat shield depending on the manufacturing design. For example, a single heat conducting plate can be fabricated separately. Alternatively, a plurality of thermally conductive plates can be fabricated in batches using a single metal sheet, a single adhesive layer, a single substrate, a single top solder mask green paint, and a single bottom solder resist green paint, and then separated. Similarly, for each thermal plate in the same batch, we can also use a single metal plate, a single adhesive layer, a single substrate, a single top anti-weld green paint and a single bottom anti-weld green paint to simultaneously manufacture multiple groups for a single batch. The heat sink and the wire used in the semiconductor component.

例如，可在一金屬板上蝕刻出多條凹槽以形成該基座、多個導熱凸柱與多個訊號凸柱；而後將一具有對應該等導熱凸柱及該等訊號凸柱之開口的未固化黏著層設置於該基座上，俾使每一導熱凸柱及訊號凸柱均延伸貫穿一對應開口；然後將一基板(其具有單一導電層、單一介電層以及對應該等導熱凸柱及該等訊號凸柱之通孔)設置於該黏著層上，俾使每一凸柱均延伸貫穿一對應開口並進入一對應通孔；而後利用壓台將該基座與該基板彼此靠合，迫使該黏著層進入該等通孔內介於該等導熱凸柱及該等訊號凸柱與該基板間之缺口；然後固化該黏著層，繼而研磨該等導熱凸柱、該等訊號凸柱、該黏著層及該第一導電層以形成一頂面；然後將第二導電層被覆設置於該等導熱凸柱、該等訊號凸柱、該黏著層及該第一導電層上；接著蝕刻該第一與第二導電層以形成多組分別對應該等訊號凸柱之焊墊及路由線，蝕刻該第二導電層以形成多個分別對應該等導熱凸柱之蓋體，並蝕刻該基座以形成多個對應該等導熱凸柱之基座以及多個對應該等訊號凸柱之端子；而後將頂部防焊綠漆設於結構體上，並使該頂部防焊綠漆產生圖案，藉以曝露該等焊墊及該等蓋體，另將底部防焊綠漆設於該結構體上，使該底部防焊綠漆產生圖案，藉以曝露該等基座及該等端子；而後以被覆接點對該等基座、該等焊墊、該等端子及該等蓋體進行表面處理；最後於該等導熱板外圍邊緣之適當位置切割或劈裂該基板、該黏著層及該等防焊綠漆，俾使個別之導熱板彼此分離。For example, a plurality of grooves may be etched on a metal plate to form the pedestal, the plurality of thermally conductive studs and the plurality of signal studs; and then an opening having a corresponding thermally conductive stud and the signal studs An uncured adhesive layer is disposed on the pedestal such that each of the thermal conductive posts and the signal studs extend through a corresponding opening; and then a substrate (having a single conductive layer, a single dielectric layer, and corresponding heat conduction) The through holes of the studs and the signal studs are disposed on the adhesive layer, so that each of the studs extends through a corresponding opening and enters a corresponding through hole; and then the base and the substrate are mutually connected by the pressing table Relying the adhesive layer into the through holes, the gap between the heat conducting studs and the signal studs and the substrate; then curing the adhesive layer, and then grinding the thermally conductive studs, the signals a pillar, the adhesive layer and the first conductive layer to form a top surface; and then a second conductive layer is disposed on the heat conducting studs, the signal bumps, the adhesive layer and the first conductive layer; Then etching the first and second conductive layers to form Group respectively correspond to the signal pads and the like of the boss and Routing a second conductive layer to form a plurality of caps respectively corresponding to the thermally conductive studs, and etching the pedestal to form a plurality of pedestals corresponding to the thermally conductive studs and a plurality of corresponding signal bumps a terminal of the column; and then the top solder resist green paint is disposed on the structure, and the top solder resist green paint is patterned to expose the solder pads and the cover body, and the bottom solder resist green paint is disposed on the bottom Structurally, the bottom solder resist green lacquer is patterned to expose the pedestals and the terminals; and then the pedestals, the pads, the terminals, and the covers are covered by the covered contacts Surface treatment; finally cutting or cleaving the substrate, the adhesive layer and the solder resist green paint at appropriate positions on the peripheral edge of the heat conducting plates to separate the individual heat conducting plates from each other.

該半導體晶片組體之作業格式可為單一組體或多個組體，取決於製造設計。例如，可單獨製造單一組體。或者，可同時批次製造多個組體，之後再將各導熱板一一分離。同樣地，亦可將多個半導體元件電性連結、熱連結及機械性連結至批次量產中之每一導熱板。The operational format of the semiconductor wafer package can be a single group or a plurality of groups, depending on the manufacturing design. For example, a single set can be manufactured separately. Alternatively, a plurality of groups can be manufactured in batches at the same time, and then the heat conducting plates are separated one by one. Similarly, a plurality of semiconductor elements may be electrically connected, thermally coupled, and mechanically coupled to each of the heat conducting plates in mass production.

例如，可將多個錫膏部分分別沉積於多個焊墊及蓋體上，而後將多個LED封裝體分別置於該等錫膏部分上，接著同時加熱該等錫膏部分以使其迴焊、硬化並形成多個焊接點，之後再將各導熱板一一分離。For example, a plurality of solder paste portions may be separately deposited on the plurality of pads and the cover, and then the plurality of LED packages are respectively placed on the solder paste portions, and then the solder paste portions are simultaneously heated to be returned. Welding, hardening and forming a plurality of solder joints, and then separating the heat conducting plates one by one.

在另一範例中係將多個固晶材料分別沉積於多個蓋體上，而後將多枚晶片分別放置於該等固晶材料上，之後再同時加熱該等固晶材料以使其硬化並形成多個固晶，而後將該等晶片打線接合至對應之焊墊，接著在該等晶片與打線上形成對應之封裝材料，最後再將各導熱板一一分離。In another example, a plurality of solid crystal materials are separately deposited on a plurality of covers, and then a plurality of wafers are respectively placed on the solid crystal materials, and then the solid crystal materials are simultaneously heated to harden them. A plurality of solid crystals are formed, and then the wafers are wire bonded to the corresponding pads, and then corresponding packaging materials are formed on the wafers and the wires, and finally the heat conducting plates are separated one by one.

吾人可透過單一步驟或多道步驟使各導熱板彼此分離。例如，可將多個導熱板批次製成一平板，接著將多個半導體元件設置於該平板上，然後再將該平板所構成之多個半導體晶片組體一一分離。或者，可將多個導熱板批次製成一平板，而後將該平板所構成之多個導熱板分切為多個導熱板條，接著將多個半導體元件分別設置於該等導熱板條上，最後再將各導熱板條所構成之多個半導體晶片組體分離為個體。此外，在分割導熱板時可利用機械切割、雷射切割、分劈或其他適用技術。We can separate the heat conducting plates from each other in a single step or in multiple steps. For example, a plurality of heat conducting plates can be batched into a flat plate, and then a plurality of semiconductor elements are disposed on the flat plate, and then the plurality of semiconductor wafer assemblies formed by the flat plates are separated one by one. Alternatively, a plurality of heat conducting plates can be batched into a flat plate, and then the plurality of heat conducting plates formed by the flat plate are slit into a plurality of heat conducting strips, and then a plurality of semiconductor elements are respectively disposed on the heat conducting strips. Finally, the plurality of semiconductor wafer assemblies formed by the heat conducting strips are separated into individual parts. In addition, mechanical cutting, laser cutting, bifurcation or other suitable techniques may be utilized in splitting the thermally conductive plates.

在本文中，「鄰接」一語意指元件係一體成形(形成單一個體)或相互接觸(彼此無間隔或未隔開)。例如，該導熱凸柱係鄰接該基座，此與形成該導熱凸柱時採用增添法或削減法無關。As used herein, the term "adjacent" means that the elements are integrally formed (forming a single individual) or in contact with one another (with or without separation from one another). For example, the thermally conductive stud is adjacent to the pedestal, which is independent of the addition or reduction method when forming the thermally conductive stud.

「重疊」一語意指位於上方並延伸於一下方元件之周緣內。「重疊」包含延伸於該周緣之內、外或坐落於該周緣內。例如，該半導體元件係重疊於該導熱凸柱，乃因一假想垂直線可同時貫穿該半導體元件與該導熱凸柱，不論該半導體元件與該導熱凸柱間是否存在有另一同為該假想垂直線貫穿之元件(如該蓋體)，且亦不論是否有另一假想垂直線僅貫穿該半導體元件而未貫穿該導熱凸柱(亦即位於該導熱凸柱之周緣外)。同樣地，該黏著層係重疊於該基座並被該焊墊重疊，而該基座則被該導熱凸柱重疊。同樣地，該導熱凸柱係重疊於該基座且位於其周緣內。此外，「重疊」與「位於上方」同義，「被重疊」則與「位於下方」同義。The term "overlapping" means located above and extending within the perimeter of a lower element. "Overlap" includes extending within, outside of, or within the circumference of the circumference. For example, the semiconductor component is overlapped with the thermally conductive stud because an imaginary vertical line can simultaneously penetrate the semiconductor component and the thermally conductive stud, regardless of whether there is another imaginary vertical between the semiconductor component and the thermally conductive stud. The element through which the wire runs, such as the cover, and whether or not another imaginary vertical line extends only through the semiconductor component does not extend through the thermally conductive stud (ie, outside the periphery of the thermally conductive stud). Similarly, the adhesive layer is overlaid on the pedestal and overlapped by the pads, and the pedestal is overlapped by the thermally conductive studs. Likewise, the thermally conductive stud is superposed on the base and is located within its circumference. In addition, "overlap" is synonymous with "below" and "overlap" is synonymous with "below".

「接觸」一語意指直接接觸。例如，該介電層接觸該焊墊但並未接觸該導熱凸柱或該基座。The term "contact" means direct contact. For example, the dielectric layer contacts the pad but does not contact the thermally conductive stud or the pedestal.

「覆蓋」一語意指從上方、從下方及/或從側面完全覆蓋。例如，該基座從下方覆蓋該導熱凸柱，但該導熱凸柱並未從上方覆蓋該基座。The term "covering" means completely covering from above, from below and/or from the side. For example, the pedestal covers the thermally conductive stud from below, but the thermally conductive stud does not cover the pedestal from above.

「層」字包含設有圖案或未設圖案之層體。例如，當該基板設置於該黏著層上時，該導電層可為該介電層上一空白無圖案之平板；而當該半導體元件設置於該散熱座上之後，該導電層可為該介電層上一具有間隔導線之電路圖案。此外，「層」可包含複數疊合層。The "layer" word contains a layer with or without a pattern. For example, when the substrate is disposed on the adhesive layer, the conductive layer may be a blank unpatterned flat plate on the dielectric layer; and after the semiconductor component is disposed on the heat sink, the conductive layer may be the dielectric layer A circuit pattern having spaced wires on the electrical layer. In addition, a "layer" may comprise a plurality of superposed layers.

「焊墊」一語與該導線搭配使用時係指一用於連接及/或接合外部連接媒介(如焊料或打線)之連結區域，而該外部連接媒介則可將該導線電性連結至該半導體元件。The term "pad" as used in connection with the conductor means a connection area for connecting and/or engaging an external connection medium (such as solder or wire), and the external connection medium electrically connects the wire to the Semiconductor component.

「端子」一語與該導線搭配使用時係指一連結區域，其可接觸及/或接合外部連結媒介(如焊料或打線)，而該外部連結媒介則可將該導線電性連結至與下一層組體相關之一外部設備(例如一印刷電路板或與其連接之一導線)。The term "terminal" as used in connection with the conductor means a connection area which is capable of contacting and/or engaging an external connection medium (such as solder or wire) which electrically connects the wire to the lower One layer of an external device (such as a printed circuit board or a wire connected to it).

「蓋體」一語與該散熱座搭配使用時係指一用於連接及/或接合外部連接媒介(如焊料或導熱黏著劑)之接觸區域，而該外部連接媒介則可將該散熱座熱連結至該半導體元件。The term "cover" when used in conjunction with the heat sink refers to a contact area for connecting and/or bonding an external connection medium (such as solder or a thermally conductive adhesive), and the external connection medium can heat the heat sink. Connected to the semiconductor component.

「開口」與「通孔」等語同指貫穿孔洞。例如，當該導熱凸柱***該黏著層之該開口時，該導熱凸柱係沿向上方向曝露於該黏著層。同樣地，當該導熱凸柱***該基板之該通孔時，該導熱凸柱係沿向上方向曝露於該基板。The words "opening" and "through hole" refer to the through hole. For example, when the thermally conductive stud is inserted into the opening of the adhesive layer, the thermally conductive stud is exposed to the adhesive layer in an upward direction. Similarly, when the thermally conductive stud is inserted into the substrate In the through hole, the thermally conductive stud is exposed to the substrate in an upward direction.

「***」一語意指元件間之相對移動。例如，「將該導熱凸柱***該通孔中」包含：該導熱凸柱固定不動而由該基板向該基座移動；該基板固定不動而由該導熱凸柱向該基板移動；以及該導熱凸柱與該基板兩者彼此靠合。又例如，「將該導熱凸柱***(或延伸至)該通孔內」包含：該導熱凸柱貫穿(穿入並穿出)該通孔；以及該導熱凸柱***但未貫穿(穿入但未穿出)該通孔。The term "insertion" means the relative movement between components. For example, "inserting the thermal conductive stud into the through hole" includes: the thermally conductive stud is fixed and moved by the substrate toward the base; the substrate is fixed and moved by the thermally conductive stud to the substrate; and the thermal conduction Both the stud and the substrate abut each other. For another example, “inserting (or extending into) the through-hole of the heat-conducting stud includes: the heat-conducting stud penetrating (passing in and penetrating) the through-hole; and the thermally-conductive stud is inserted but not penetrated (penetrated) But did not wear out the through hole.

「彼此靠合」一語亦指元件間之相對移動。例如，「該基座與該基板彼此靠合」包含：該基座固定不動而由該基板移往該基座；該基板固定不動而由該基座向該基板移動；以及該基座與該基板相互靠近。The phrase "together with each other" also refers to the relative movement between components. For example, "the pedestal and the substrate abut each other" includes: the pedestal is fixed and moved from the substrate to the pedestal; the substrate is fixed and moved by the pedestal to the substrate; and the pedestal and the pedestal The substrates are close to each other.

「對準」一語意指元件間之相對位置。例如，當該黏著層已設置於該基座上、該基板已設置於該黏著層上、該導熱凸柱已***並對準該開口，且該通孔已對準該開口時，無論該導熱凸柱係***該通孔或位於該通孔下方且與其保持距離，該導熱凸柱均已對準該通孔。The term "aligned" means the relative position between components. For example, when the adhesive layer is disposed on the pedestal, the substrate is disposed on the adhesive layer, the thermal conductive stud has been inserted and aligned with the opening, and the through hole has been aligned with the opening, regardless of the thermal conduction. The stud is inserted into or located below the through hole, and the thermally conductive stud is aligned with the through hole.

「設置於」一語包含與單一或多個支撐元件間之接觸與非接觸。例如，該半導體元件係設置於該散熱座上，不論該半導體元件係實際接觸該散熱座或係與該散熱座以一固晶材料相隔。同樣地，該半導體元件係設置於該散熱座上，不論該半導體元件係僅設置於該散熱座上或係同時設置於該散熱座與該基板上。The term "set in" encompasses contact and non-contact with a single or multiple support elements. For example, the semiconductor component is disposed on the heat sink, whether the semiconductor component is actually in contact with the heat sink or is separated from the heat sink by a solid crystal material. Similarly, the semiconductor component is disposed on the heat sink, and the semiconductor component is disposed only on the heat sink or on the heat sink and the substrate.

「黏著層…於該缺口之中」一語意指位於該缺口中之該黏著層。例如，「黏著層在該缺口中延伸跨越該介電層」意指該缺口內之該黏著層延伸跨越該介電層。同樣地，「黏著層於該缺口之中接觸且介於該導熱凸柱與該介電層之間」意指該缺口中之該黏著層接觸且介於該缺口內側壁之該導熱凸柱與該缺口外側壁之該介電層之間。The phrase "adhesive layer...in the gap" means located in the gap The adhesive layer. For example, "the adhesive layer extends across the dielectric layer in the gap" means that the adhesive layer within the gap extends across the dielectric layer. Similarly, "the adhesive layer contacts the gap and is between the thermal conductive stud and the dielectric layer" means that the adhesive layer in the notch contacts and the thermally conductive stud between the inner sidewall of the notch Between the dielectric layers of the outer sidewall of the gap.

「上方」一語意指向上延伸，且包含鄰接與非鄰接元件以及重疊與非重疊元件。例如，該導熱凸柱係延伸於該基座上方，同時鄰接、重疊於該基座並自該基座突伸而出。同樣地，該導熱凸柱係延伸至該介電層上方，即便該導熱凸柱並未鄰接或重疊於該介電層。The term "upper" is intended to mean an upward extension and encompasses contiguous and non-contiguous elements as well as overlapping and non-overlapping elements. For example, the thermally conductive stud extends above the pedestal while abutting, overlapping the pedestal and projecting from the pedestal. Similarly, the thermally conductive stud extends above the dielectric layer even if the thermally conductive stud does not abut or overlap the dielectric layer.

「下方」一語意指向下延伸，且包含鄰接與非鄰接元件以及重疊與非重疊元件。例如，該基座係延伸於該導熱凸柱下方，鄰接該導熱凸柱，被該導熱凸柱重疊，並自該導熱凸柱突伸而出。同樣地，該導熱凸柱係延伸於該介電層下方，即便該導熱凸柱並未鄰接該介電層或被該介電層重疊。The word "below" is intended to mean a downward extension and includes contiguous and non-contiguous elements as well as overlapping and non-overlapping elements. For example, the pedestal extends below the thermally conductive stud, adjacent to the thermally conductive stud, and is overlapped by the thermally conductive stud and protrudes from the thermally conductive stud. Similarly, the thermally conductive stud extends below the dielectric layer even if the thermally conductive stud is not adjacent to or overlapped by the dielectric layer.

所謂「向上」及「向下」之垂直方向並非取決於該半導體晶片組體(或該導熱板)之定向，凡熟悉此項技藝之人士可輕易瞭解其實際所指之方向。例如，該導熱凸柱係沿向上方向垂直延伸於該基座上方，而該黏著層則沿向下方向垂直延伸於該焊墊下方，此與該組體是否倒置及/或是否係設置於一散熱裝置上無關。同樣地，該基座係沿一側向平面自該導熱凸柱「側向」延伸而出，此與該組體是否倒置、旋轉或傾斜無關。因此，該向上及向下方向係彼此相對且垂直於側面方向，此外，側向對齊之元件係在一垂直於該向上與向下方向之側向平面上彼此共平面。The vertical direction of "upward" and "downward" does not depend on the orientation of the semiconductor wafer package (or the thermal plate), and those skilled in the art can easily understand the actual direction. For example, the thermally conductive stud extends vertically above the pedestal in an upward direction, and the adhesive layer extends vertically below the solder pad in a downward direction, whether the set is inverted and/or is disposed at a It has nothing to do with the heat sink. Similarly, the pedestal extends laterally from the thermally conductive stud along a lateral plane, regardless of whether the set is inverted, rotated or tilted. Therefore, the upward and downward directions are related to each other. Paired and perpendicular to the side direction, in addition, the laterally aligned elements are coplanar with one another in a lateral plane perpendicular to the upward and downward directions.

本發明之半導體晶片組體具有多項優點。該組體之可靠度高、價格平實且極適合量產。該組體尤其適用於易產生高熱且需優異散熱效果方可有效及可靠運作之高功率半導體元件，例如LED封裝體、大型半導體晶片以及多個同時使用之小型半導體元件(例如以陣列方式排列之多枚小形半導體晶片)。The semiconductor wafer package of the present invention has a number of advantages. The group's reliability is high, the price is flat and it is very suitable for mass production. The group is particularly suitable for high-power semiconductor components that are prone to high heat and require excellent heat dissipation to operate efficiently and reliably, such as LED packages, large semiconductor wafers, and multiple small semiconductor components used simultaneously (eg, arrayed) Multiple small semiconductor wafers).

本案之製造工序具有高度適用性，且係以獨特、進步之方式結合運用各種成熟之電性連結、熱連結及機械性連結技術。此外，本案之製造工序不需昂貴工具即可實施。因此，此製造工序可大幅提升傳統封裝技術之產量、良率、效能與成本效益。再者，本案之組體極適合於銅晶片及無鉛之環保要求。The manufacturing process of this case is highly applicable, and combines various mature electrical connections, thermal connections and mechanical joining technologies in a unique and progressive manner. In addition, the manufacturing process of this case can be implemented without expensive tools. As a result, this manufacturing process can significantly increase the yield, yield, performance and cost effectiveness of traditional packaging technologies. Furthermore, the group in this case is extremely suitable for copper wafers and lead-free environmental requirements.

在此所述之實施例係為例示之用，其中所涉及之本技藝習知元件或步驟或經簡化或有所省略以免模糊本發明之特點。同樣地，為使圖式清晰，圖式中重覆或非必要之元件及參考標號或有所省略。The embodiments described herein are illustrative, and the elements or steps of the present invention are either simplified or omitted to avoid obscuring the features of the present invention. Similarly, in the drawings, the repeated or non-essential elements and reference numerals may be omitted.

精於此項技藝之人士針對本文所述之實施例當可輕易思及各種變化及修改。例如，前述之材料、尺寸、形狀、大小、步驟之內容與步驟之順序皆僅為範例。上述人士可於不脫離本發明之精神與範圍之條件下從事此等改變、調整與均等技藝，其中本發明之範圍係由後附之申請專利範圍加以界定。Those skilled in the art can readily appreciate various changes and modifications to the embodiments described herein. For example, the foregoing materials, dimensions, shapes, sizes, steps, and order of steps are merely examples. The above-mentioned persons can make such changes, adjustments and equals without departing from the spirit and scope of the invention, and the scope of the invention is defined by the scope of the appended claims.

10‧‧‧金屬板10‧‧‧Metal plates

12、14‧‧‧表面12, 14‧‧‧ surface

16、52、54‧‧‧圖案化之蝕刻阻層16, 52, 54‧‧‧ patterned etch stop

18‧‧‧全面覆蓋之蝕刻阻層18‧‧‧Full coverage of the etch stop

20‧‧‧凹槽20‧‧‧ Groove

22‧‧‧導熱凸柱22‧‧‧thermal pillar

24‧‧‧訊號凸柱24‧‧‧ Signal Stud

26‧‧‧基座26‧‧‧Base

28‧‧‧黏著層28‧‧‧Adhesive layer

30、32‧‧‧開口30, 32‧‧‧ openings

34‧‧‧基板34‧‧‧Substrate

36、50‧‧‧導電層36, 50‧‧‧ conductive layer

38‧‧‧介電層38‧‧‧Dielectric layer

40、42‧‧‧通孔40, 42‧‧‧through holes

44、46‧‧‧缺口44, 46‧‧ ‧ gap

56‧‧‧焊墊56‧‧‧ solder pads

58‧‧‧路由線58‧‧‧Route line

60‧‧‧蓋體60‧‧‧ cover

62‧‧‧端子62‧‧‧ terminals

64‧‧‧導線64‧‧‧Wire

66‧‧‧散熱座66‧‧‧ Heat sink

68、70‧‧‧防焊綠漆68, 70‧‧‧Protective green paint

72‧‧‧被覆接點72‧‧‧covered contacts

74、76‧‧‧導熱板74, 76‧‧‧ Thermal Conductive Plate

100、200、300‧‧‧半導體晶片組體100, 200, 300‧‧‧ semiconductor wafer assembly

102、202‧‧‧LED封裝體102, 202‧‧‧ LED package

104、106、204、206‧‧‧焊錫104, 106, 204, 206‧‧‧ solder

108、208‧‧‧LED晶片108, 208‧‧‧ LED chips

110、210‧‧‧基座110, 210‧‧‧ Pedestal

112、212、304‧‧‧打線112, 212, 304‧‧‧

114‧‧‧電接點114‧‧‧Electrical contacts

116‧‧‧熱接點116‧‧‧Hot junction

118、218‧‧‧透明封裝材料118, 218‧‧‧ Transparent packaging materials

214‧‧‧引腳214‧‧‧ pin

216‧‧‧熱接觸表面216‧‧‧ Thermal contact surface

302‧‧‧晶片302‧‧‧ wafer

306‧‧‧固晶材料306‧‧‧Solid crystal materials

308‧‧‧封裝材料308‧‧‧Packaging materials

310‧‧‧頂面310‧‧‧ top surface

312‧‧‧底面312‧‧‧ bottom

314‧‧‧打線接墊314‧‧‧Wire mat

圖1A至圖1D為剖視圖，說明本發明一實施例中用以製作一凸柱及一基座之方法；圖1E及圖1F分別為圖1D之俯視圖及仰視圖；圖2A及圖2B為剖視圖，說明本發明一實施例中用以製作一黏著層之方法；圖2C及圖2D分別為圖2B之俯視圖及仰視圖；圖3A及圖3B為剖視圖，說明本發明一實施例中用以製作一基板之方法；圖3C及圖3D分別為圖3B之俯視圖及仰視圖；圖4A至圖4L為剖視圖，說明本發明一實施例中用以製作一導熱板之方法，該導熱板在其黏著層上設有一基板；圖4M及圖4N分別為圖4L之俯視圖及仰視圖；圖5A、圖5B及圖5C分別為本發明一實施例中一導熱板之剖視圖、俯視圖及仰視圖，該導熱板在其黏著層上設有一導線；圖6A、圖6B及圖6C分別為本發明一實施例中一半導體晶片組體之剖視圖、俯視圖及仰視圖，該半導體晶片組體包含一導熱板及一具有背面接點之LED封裝體；圖7A、圖7B及圖7C分別為本發明一實施例中一半導體晶片組體之剖視圖、俯視圖及仰視圖，該半導體晶片組體包含一導熱板及一具有側引腳之LED封裝體；圖8A、圖8B及圖8C分別為本發明一實施例中一半導體晶片組體之剖視圖、俯視圖及仰視圖，該半導體晶片組體包含一導熱板及一半導體晶片。1A to 1D are cross-sectional views illustrating a method for fabricating a stud and a pedestal in accordance with an embodiment of the present invention; FIGS. 1E and 1F are a plan view and a bottom view, respectively, of FIG. 1D; FIGS. 2A and 2B are cross-sectional views. FIG. 2C and FIG. 2D are respectively a plan view and a bottom view of FIG. 2B; FIG. 3A and FIG. 3B are cross-sectional views illustrating an embodiment of the present invention for making an adhesive layer; FIG. FIG. 3C and FIG. 3D are respectively a top view and a bottom view of FIG. 3B; FIG. 4A to FIG. 4L are cross-sectional views illustrating a method for fabricating a heat conducting plate according to an embodiment of the present invention, wherein the heat conducting plate is adhered thereto 4M and FIG. 4N are respectively a top view and a bottom view of FIG. 4L; FIGS. 5A, 5B and 5C are respectively a cross-sectional view, a top view and a bottom view of a heat conducting plate according to an embodiment of the present invention, the heat conduction The board is provided with a wire on the adhesive layer. FIG. 6A, FIG. 6B and FIG. 6C are respectively a cross-sectional view, a top view and a bottom view of a semiconductor wafer assembly according to an embodiment of the present invention. The semiconductor chip assembly includes a heat conducting plate and a LED package having a back contact; 7A, 7B, and 7C are respectively a cross-sectional view, a top view, and a bottom view of a semiconductor wafer package including a heat conducting plate and an LED package having side pins; 8A, FIG. 8B and FIG. 8C are respectively half guides according to an embodiment of the present invention. A cross-sectional view, a top view, and a bottom view of the bulk wafer assembly, the semiconductor wafer package including a thermally conductive plate and a semiconductor wafer.

22．．．導熱凸柱twenty two. . . Thermal conductive stud

24．．．訊號凸柱twenty four. . . Signal stud

26．．．基座26. . . Pedestal

28．．．黏著層28. . . Adhesive layer

34．．．基板34. . . Substrate

38．．．介電層38. . . Dielectric layer

56．．．焊墊56. . . Solder pad

58．．．路由線58. . . Routing line

60．．．蓋體60. . . Cover

62．．．端子62. . . Terminal

64．．．導線64. . . wire

66．．．散熱座66. . . Heat sink

68、70．．．防焊綠漆68, 70. . . Anti-weld green paint

74．．．導熱板74. . . Thermal plate

100．．．半導體晶片組體100. . . Semiconductor wafer package

102．．．LED封裝體102. . . LED package

104、106．．．焊錫104, 106. . . Solder

108．．．LED晶片108. . . LED chip

110．．．基座110. . . Pedestal

112．．．打線112. . . Line

114．．．電接點114. . . Electric contact

116．．．熱接點116. . . Hot junction

118．．．透明封裝材料118. . . Transparent packaging material

Claims

一種半導體晶片組體，至少包含：一半導體元件；一黏著層，其至少具有第一及第二開口；一散熱座，其至少包含一導熱凸柱及一基座，其中該導熱凸柱係鄰接該基座並沿一向上方向延伸於該基座上方，該基座係沿一與該向上方向相反之向下方向延伸於該導熱凸柱下方，並沿垂直於該向上及向下方向之側面方向從該導熱凸柱側向延伸；及一導線，其至少包含一焊墊、一端子及一訊號凸柱，其中該訊號凸柱係延伸於該焊墊下方及該端子上方，且該焊墊與該端子間之一導電路徑包含該訊號凸柱；其中該半導體元件係位於該導熱凸柱上方並重疊於該導熱凸柱，該半導體元件係電性連結至該焊墊，從而電性連結至該端子，且該半導體元件係熱連結至該導熱凸柱，從而熱連結至該基座；其中該黏著層係設置於該基座上，延伸於該基座上方，並自該導熱凸柱側向延伸至該端子或越過該端子；其中該焊墊係延伸於該黏著層上方，而該端子則延伸於該黏著層下方；以及其中該導熱凸柱延伸進入該第一開口，該訊號凸柱延伸進入該第二開口，該導熱凸柱及該訊號凸柱具有相同厚度且彼此共平面，該基座與該端子具有相同厚度且彼此共平面。 A semiconductor wafer assembly comprising: at least: a semiconductor component; an adhesive layer having at least first and second openings; a heat sink comprising at least one thermally conductive stud and a pedestal, wherein the thermally conductive stud is adjacent The pedestal extends above the pedestal in an upward direction, the pedestal extending below the thermally conductive stud in a downward direction opposite the upward direction and along a side perpendicular to the upward and downward directions a direction extending laterally from the heat conducting stud; and a wire comprising at least one pad, a terminal and a signal stud, wherein the signal stud extends below the pad and above the terminal, and the pad The conductive path between the terminal and the terminal includes the signal stud; wherein the semiconductor component is located above the thermally conductive stud and overlaps the thermally conductive stud, and the semiconductor component is electrically connected to the pad to be electrically connected to the a terminal, and the semiconductor component is thermally coupled to the thermally conductive stud to be thermally coupled to the pedestal; wherein the adhesive layer is disposed on the pedestal, extending over the pedestal, and from the thermally conductive stud side Extending to or over the terminal; wherein the pad extends over the adhesive layer, and the terminal extends below the adhesive layer; and wherein the thermally conductive stud extends into the first opening, the signal post extends Entering the second opening, the thermally conductive stud and the signal stud have the same thickness and are coplanar with each other, the pedestal having the same thickness as the terminal and being coplanar with each other.

如申請專利範圍第1項所述之半導體晶片組體，其中該半導體元件為一包含LED晶片之LED封裝體。 The semiconductor wafer package of claim 1, wherein the semiconductor component is an LED package comprising an LED chip.

如申請專利範圍第2項所述之半導體晶片組體，其中該LED封裝體係利用一第一焊錫電性連結至該焊墊，並利用一第二焊錫熱連結至該散熱座。 The semiconductor wafer package of claim 2, wherein the LED package system is electrically connected to the pad by a first solder and thermally coupled to the heat sink by a second solder.

如申請專利範圍第1項所述之半導體晶片組體，其中該半導體元件為一半導體晶片。 The semiconductor wafer package of claim 1, wherein the semiconductor component is a semiconductor wafer.

如申請專利範圍第4項所述之半導體晶片組體，其中該晶片係利用一打線電性連結至該焊墊，並利用一固晶材料熱連結至該散熱座。 The semiconductor wafer package of claim 4, wherein the wafer is electrically connected to the pad by a wire and thermally bonded to the heat sink by a die bonding material.

如申請專利範圍第1項所述之半導體晶片組體，其中該黏著層接觸該導熱凸柱及該訊號凸柱、該基座、該焊墊與該端子。 The semiconductor wafer package of claim 1, wherein the adhesive layer contacts the thermally conductive stud and the signal stud, the base, the pad and the terminal.

如申請專利範圍第1項所述之半導體晶片組體，其中該黏著層於該等側面方向覆蓋且環繞該導熱凸柱及該訊號凸柱。 The semiconductor wafer package of claim 1, wherein the adhesive layer covers and surrounds the thermally conductive stud and the signal stud in the lateral direction.

如申請專利範圍第1項所述之半導體晶片組體，其中該黏著層同形被覆於該導熱凸柱及該訊號凸柱之側壁。 The semiconductor wafer assembly of claim 1, wherein the adhesive layer is isomorphously coated on the sidewalls of the thermally conductive stud and the signal stud.

如申請專利範圍第1項所述之半導體晶片組體，其中該黏著層與該導熱凸柱及該訊號凸柱之頂部及底部共平面。 The semiconductor wafer package of claim 1, wherein the adhesive layer is coplanar with the heat conducting stud and the top and bottom of the signal stud.

如申請專利範圍第1項所述之半導體晶片組體，其中該黏著層自該導熱凸柱側向延伸且越過該端子。 The semiconductor wafer package of claim 1, wherein the adhesive layer extends laterally from the thermally conductive stud and passes over the terminal.

如申請專利範圍第1項所述之半導體晶片組體，其中該黏著層延伸至該半導體晶片組體之外圍邊緣。 The semiconductor wafer package according to claim 1, wherein the The adhesive layer extends to the peripheral edge of the semiconductor wafer package.

如申請專利範圍第1項所述之半導體晶片組體，其中該導熱凸柱係與該基座一體成形，該訊號凸柱則與該端子一體成形。 The semiconductor wafer package of claim 1, wherein the thermally conductive stud is integrally formed with the base, and the signal stud is integrally formed with the terminal.

如申請專利範圍第1項所述之半導體晶片組體，其中該導熱凸柱為平頂錐柱形，其直徑自該基座至該導熱凸柱之一平坦頂部係呈向上遞減，且該訊號凸柱為平頂錐柱形，其直徑自該端子至該訊號凸柱之一平坦頂部係呈向上遞減。 The semiconductor wafer assembly of claim 1, wherein the thermally conductive stud is a flat-topped tapered column having a diameter that decreases upward from the base to a flat top of the thermally conductive stud, and the signal The stud is a flat-topped conical cylinder whose diameter decreases upward from the terminal to a flat top of one of the signal studs.

如申請專利範圍第1項所述之半導體晶片組體，其中該基座從下方覆蓋該導熱凸柱，支撐該黏著層，且與該半導體晶片組體之外圍邊緣保持距離。 The semiconductor wafer package of claim 1, wherein the pedestal covers the thermally conductive stud from below to support the adhesive layer and maintain a distance from a peripheral edge of the semiconductor wafer assembly.

如申請專利範圍第1項所述之半導體晶片組體，其中該導線係與該散熱座及該焊墊保持距離，該端子與該訊號凸柱則接觸該黏著層。 The semiconductor wafer package of claim 1, wherein the wire is spaced from the heat sink and the pad, and the terminal and the signal stud contact the adhesive layer.

如申請專利範圍第1項所述之半導體晶片組體，其中該端子係鄰接該訊號凸柱，延伸於該訊號凸柱下方，並沿該等側面方向自該訊號凸柱側向延伸。 The semiconductor wafer package of claim 1, wherein the terminal is adjacent to the signal stud, extends below the signal stud, and extends laterally from the signal stud along the lateral directions.

如申請專利範圍第1項所述之半導體晶片組體，其中該散熱座至少包含一蓋體，該蓋體位於該導熱凸柱之一頂部上方，鄰接該導熱凸柱之該頂部，並從上方覆蓋該導熱凸柱之該頂部，同時沿該等側面方向自該導熱凸柱之該頂部側向延伸。 The semiconductor wafer assembly of claim 1, wherein the heat sink comprises at least a cover, the cover is located above a top of one of the thermally conductive studs, adjacent to the top of the thermally conductive stud, and from above Covering the top of the thermally conductive stud while extending laterally from the top of the thermally conductive stud in the lateral direction.

如申請專利範圍第17項所述之半導體晶片組體，其中該蓋體與該焊墊於該黏著層上方為共平面。 The semiconductor wafer package of claim 17, wherein the semiconductor wafer assembly The cover and the pad are coplanar above the adhesive layer.

如申請專利範圍第17項所述之半導體晶片組體，其中該蓋體為矩形或正方形，該導熱凸柱之該頂部則為圓形。 The semiconductor wafer package of claim 17, wherein the cover is rectangular or square, and the top of the thermally conductive stud is circular.

如申請專利範圍第17項所述之半導體晶片組體，其中該蓋體之尺寸及形狀係配合該半導體元件之一熱接觸表面而設計，該導熱凸柱之該頂部之尺寸及形狀則並非配合該半導體元件之該熱接觸表面而設計。 The semiconductor wafer package of claim 17, wherein the size and shape of the cover are designed to match a thermal contact surface of the semiconductor component, and the size and shape of the top of the thermal conductive post are not matched. The thermal contact surface of the semiconductor component is designed.

一種半導體晶片組體，至少包含：一半導體元件；一黏著層，其至少具有第一及第二開口；一散熱座，其至少包含一導熱凸柱及一基座，其中該導熱凸柱係鄰接該基座並與該基座一體成形，且該導熱凸柱係沿一向上方向延伸於該基座上方，該基座係沿一與該向上方向相反之向下方向延伸於該導熱凸柱下方，並沿垂直於該向上及向下方向之側面方向自該導熱凸柱側向延伸；及一導線，其至少包含一焊墊、一端子、一路由線及一訊號凸柱，其中該路由線鄰接該焊墊，該訊號凸柱則鄰接該路由線與該端子，並延伸於該焊墊與該路由線下方，同時延伸於該端子上方，且該焊墊與該端子間之一導電路徑包含該路由線與該訊號凸柱；其中該半導體元件係設置於該散熱座上，重疊於該導熱凸柱但並未重疊於該訊號凸柱，該半導體元件係電性連結至該焊墊，從而電性連結至該端子，且該半導體元件係熱連結至該導熱凸柱，從而熱連結至該基座；其中該黏著層係設置於該基座上，延伸於該基座上方，並於該等側面方向覆蓋且環繞該導熱凸柱及該訊號凸柱，同時延伸至該半導體晶片組體之外圍邊緣；其中該焊墊延伸於該黏著層上方；以及其中該導熱凸柱延伸進入該第一開口，該訊號凸柱延伸進入該第二開口，該導熱凸柱及該訊號凸柱具有相同厚度，彼此共平面，且延伸穿過該黏著層，該基座與該端子具有相同厚度，彼此共平面，且延伸於該黏著層下方，該導熱凸柱及該訊號凸柱之頂部及底部係與該黏著層共平面。 A semiconductor wafer assembly comprising: at least: a semiconductor component; an adhesive layer having at least first and second openings; a heat sink comprising at least one thermally conductive stud and a pedestal, wherein the thermally conductive stud is adjacent The pedestal is integrally formed with the pedestal, and the thermally conductive stud extends above the pedestal in an upward direction, the pedestal extending below the thermally conductive stud in a downward direction opposite the upward direction And extending laterally from the thermally conductive stud in a direction perpendicular to the upward and downward directions; and a wire comprising at least a pad, a terminal, a routing line and a signal stud, wherein the routing line Adjacent to the solder pad, the signal stud is adjacent to the routing line and the terminal, and extends below the solder pad and the routing line, and extends above the terminal, and a conductive path between the pad and the terminal includes The routing line and the signal stud; wherein the semiconductor component is disposed on the heat sink, overlaps the heat conducting stud but does not overlap the signal stud, and the semiconductor component is electrically connected to the pad Electricity Coupled to the terminals, and the semiconductor The component is thermally coupled to the thermally conductive stud to be thermally coupled to the pedestal; wherein the adhesive layer is disposed on the pedestal, extends over the pedestal, and covers and surrounds the thermally conductive stud in the lateral directions And the signal stud extending to the peripheral edge of the semiconductor wafer assembly; wherein the bonding pad extends over the adhesive layer; and wherein the thermal conductive post extends into the first opening, the signal stud extending into the first a second opening, the thermally conductive stud and the signal stud have the same thickness, are coplanar with each other, and extend through the adhesive layer, the pedestal and the terminal have the same thickness, are coplanar with each other, and extend below the adhesive layer The thermally conductive stud and the top and bottom of the signal stud are coplanar with the adhesive layer.

如申請專利範圍第21項所述之半導體晶片組體，其中該半導體元件為一半導體晶片，且係利用一固晶材料設置於該散熱座上，並利用一打線電性連結至該焊墊，同時利用該固晶材料熱連結至該散熱座。 The semiconductor wafer assembly of claim 21, wherein the semiconductor component is a semiconductor wafer, and is disposed on the heat sink by a die bonding material, and is electrically connected to the pad by using a wire. At the same time, the solid crystal material is thermally bonded to the heat sink.

如申請專利範圍第21項所述之半導體晶片組體，其中該黏著層接觸該導熱凸柱、該訊號凸柱、該基座、該焊墊、該端子與該路由線。 The semiconductor wafer package of claim 21, wherein the adhesive layer contacts the thermally conductive stud, the signal stud, the pedestal, the pad, the terminal and the routing line.

如申請專利範圍第21項所述之半導體晶片組體，其中該導熱凸柱為平頂錐柱形，其直徑自該基座至該導熱凸柱之一平坦頂部係呈向上遞減，該導熱凸柱之該頂部為圓形，一蓋體係設置於該導熱凸柱之該頂部上，位於該導熱凸柱之該頂部上方，鄰接該導熱凸柱之該頂部，並從上方覆蓋該導熱凸柱之該頂部，同時沿該等側面方向自該導熱凸柱之該頂部側向延伸，該蓋體為矩形或正方形。 The semiconductor wafer assembly of claim 21, wherein the thermally conductive stud is a flat-topped tapered cylinder having a diameter that decreases upward from the pedestal to a flat top of the thermally conductive stud, the thermally conductive convex The top of the column is circular, and a cover system is disposed on the top of the thermally conductive stud, above the top of the thermally conductive stud, adjacent to the top of the thermally conductive stud, and covering the thermally conductive stud from above The top, at the same time along the sides The top of the thermally conductive stud extends laterally and the cover is rectangular or square.

如申請專利範圍第24項所述之半導體晶片組體，其中該蓋體與該焊墊於該黏著層上方為共平面。 The semiconductor wafer package of claim 24, wherein the cover and the bonding pad are coplanar above the adhesive layer.

一種半導體晶片組體，至少包含：一半導體元件；一黏著層，其至少具有第一及第二開口；一散熱座，其至少包含一導熱凸柱及一基座，其中該導熱凸柱係鄰接該基座，並沿一向上方向延伸於該基座上方，該基座係沿一與該向上方向相反之向下方向延伸於該導熱凸柱下方，並沿垂直於該向上及向下方向之側面方向從該導熱凸柱側向延伸；一基板，其至少包含一焊墊及一介電層，其中第一及第二通孔延伸貫穿該基板；及一導線，其至少包含該焊墊、一端子及一訊號凸柱，其中該訊號凸柱係延伸於該焊墊下方及該端子上方，且該焊墊與該端子間之一導電路徑包含該訊號凸柱；其中該半導體元件係位於該導熱凸柱上方並重疊於該導熱凸柱，該半導體元件係電性連結至該焊墊，從而電性連結至該端子，且該半導體元件係熱連結至該導熱凸柱，從而熱連結至該基座；其中該黏著層係設置於該基座上，延伸於該基座上方，延伸進入該第一通孔內一介於該導熱凸柱與該基板間之第一缺口，延伸進入該第二通孔內一介於該訊號凸柱與該基板間之第二缺口，並於該等缺口內延伸跨越該介電層，該黏著層自該導熱凸柱側向延伸至該端子或越過該端子，且該黏著層係介於該導熱凸柱與該介電層之間、該訊號凸柱與該介電層之間以及該基座與該介電層之間；其中該基板係設置於該黏著層上，且延伸於該基座上方；其中該焊墊係延伸於該介電層上方，而該端子則延伸於該黏著層下方；以及其中該導熱凸柱延伸進入該第一開口與該第一通孔，該訊號凸柱延伸進入該第二開口與該第二通孔，該導熱凸柱及該訊號凸柱具有相同厚度且彼此共平面，該基座與該端子具有相同厚度且彼此共平面。 A semiconductor wafer assembly comprising: at least: a semiconductor component; an adhesive layer having at least first and second openings; a heat sink comprising at least one thermally conductive stud and a pedestal, wherein the thermally conductive stud is adjacent The pedestal extends above the pedestal in an upward direction, the pedestal extending below the thermally conductive stud in a downward direction opposite the upward direction and perpendicular to the upward and downward directions a side surface extending laterally from the heat conducting stud; a substrate comprising at least one pad and a dielectric layer, wherein the first and second through holes extend through the substrate; and a wire including at least the pad a terminal and a signal stud, wherein the signal stud extends below the solder pad and above the terminal, and a conductive path between the pad and the terminal includes the signal stud; wherein the semiconductor component is located The semiconductor element is electrically connected to the solder pad to be electrically connected to the terminal, and the semiconductor component is thermally coupled to the heat conducting stud to be thermally coupled to the heat conducting stud. a pedestal; the adhesive layer is disposed on the pedestal and extends over the pedestal and extends into the first through hole, and a first gap between the thermally conductive stud and the substrate extends into the second Inside the through hole a second gap between the pillar and the substrate, and extending across the dielectric layer in the gap, the adhesive layer extending laterally from the heat conducting stud to the terminal or over the terminal, and the adhesive layer is interposed Between the thermal conductive stud and the dielectric layer, between the signal stud and the dielectric layer, and between the pedestal and the dielectric layer; wherein the substrate is disposed on the adhesive layer and extends over the base Above the seat; wherein the soldering pad extends above the dielectric layer, and the terminal extends below the adhesive layer; and wherein the thermally conductive stud extends into the first opening and the first through hole, the signal stud Extending into the second opening and the second through hole, the heat conducting stud and the signal stud have the same thickness and are coplanar with each other, the pedestal and the terminal having the same thickness and being coplanar with each other.

如申請專利範圍第26項所述之半導體晶片組體，其中該半導體元件為一包含LED晶片之LED封裝體。 The semiconductor wafer package of claim 26, wherein the semiconductor component is an LED package comprising an LED chip.

如申請專利範圍第27項所述之半導體晶片組體，其中該LED封裝體係利用一第一焊錫電性連結至該焊墊，並利用一第二焊錫熱連結至該散熱座。 The semiconductor wafer package of claim 27, wherein the LED package system is electrically connected to the pad by a first solder and thermally coupled to the heat sink by a second solder.

如申請專利範圍第26項所述之半導體晶片組體，其中該半導體元件為一半導體晶片。 The semiconductor wafer package of claim 26, wherein the semiconductor component is a semiconductor wafer.

如申請專利範圍第29項所述之半導體晶片組體，其中該晶片係利用一打線電性連結至該焊墊，並利用一固晶材料熱連結至該散熱座。 The semiconductor wafer package of claim 29, wherein the wafer is electrically connected to the pad by a wire and thermally bonded to the heat sink by a die bonding material.

如申請專利範圍第26項所述之半導體晶片組體，其中該黏著層於該第一缺口內接觸該導熱凸柱與該介電層，並於該第二缺口內接觸該訊號凸柱與該介電層，同時於該等缺口外接觸該基座、該端子與該介電層。 The semiconductor wafer package of claim 26, wherein the Adhesively contacting the thermal conductive stud and the dielectric layer in the first notch, and contacting the signal stud and the dielectric layer in the second notch, and contacting the pedestal and the terminal outside the notch With the dielectric layer.

如申請專利範圍第26項所述之半導體晶片組體，其中該黏著層於該等側面方向覆蓋且環繞該導熱凸柱及該訊號凸柱。 The semiconductor wafer package of claim 26, wherein the adhesive layer covers and surrounds the thermally conductive stud and the signal stud in the lateral direction.

如申請專利範圍第26項所述之半導體晶片組體，其中該黏著層同形被覆於該導熱凸柱及該訊號凸柱之側壁。 The semiconductor wafer package of claim 26, wherein the adhesive layer is isomorphously coated on the sidewalls of the thermally conductive stud and the signal stud.

如申請專利範圍第26項所述之半導體晶片組體，其中該黏著層與該導熱凸柱及該訊號凸柱之頂部及底部共平面。 The semiconductor wafer package of claim 26, wherein the adhesive layer is coplanar with the heat conducting stud and the top and bottom of the signal stud.

如申請專利範圍第26項所述之半導體晶片組體，其中該黏著層自該導熱凸柱側向延伸且越過該端子。 The semiconductor wafer package of claim 26, wherein the adhesive layer extends laterally from the thermally conductive stud and passes over the terminal.

如申請專利範圍第26項所述之半導體晶片組體，其中該黏著層延伸至該半導體晶片組體之外圍邊緣。 The semiconductor wafer package of claim 26, wherein the adhesive layer extends to a peripheral edge of the semiconductor wafer assembly.

如申請專利範圍第26項所述之半導體晶片組體，其中該導熱凸柱係與該基座一體成形，該訊號凸柱則與該端子一體成形。 The semiconductor wafer package of claim 26, wherein the thermally conductive stud is integrally formed with the base, and the signal stud is integrally formed with the terminal.

如申請專利範圍第26項所述之半導體晶片組體，其中該導熱凸柱為平頂錐柱形，其直徑自該基座至該導熱凸柱之一平坦頂部係呈向上遞減，且該訊號凸柱為平頂錐柱形，其直徑自該端子至該訊號凸柱之一平坦頂部係呈向上遞減。 The semiconductor wafer package of claim 26, wherein the thermally conductive stud is a flat-topped tapered cylinder having a diameter that decreases upward from the pedestal to a flat top of the thermally conductive stud, and the signal The stud is a flat-topped conical cylinder whose diameter decreases upward from the terminal to a flat top of one of the signal studs.

如申請專利範圍第26項所述之半導體晶片組體，其中該基座從下方覆蓋該導熱凸柱，支撐該基板，且與該半導體晶片組體之外圍邊緣保持距離。 The semiconductor wafer package of claim 26, wherein the The pedestal covers the thermally conductive stud from below to support the substrate and maintain a distance from a peripheral edge of the semiconductor wafer package.

如申請專利範圍第26項所述之半導體晶片組體，其中該導線係與該散熱座保持距離，該焊墊接觸該介電層，該端子接觸該黏著層，該訊號凸柱則接觸該黏著層與該介電層。 The semiconductor wafer package of claim 26, wherein the wire is kept at a distance from the heat sink, the pad contacts the dielectric layer, the terminal contacts the adhesive layer, and the signal post contacts the adhesive a layer and the dielectric layer.

如申請專利範圍第26項所述之半導體晶片組體，其中該端子係鄰接該訊號凸柱，延伸於該訊號凸柱下方，並沿該等側面方向自該訊號凸柱側向延伸。 The semiconductor wafer package of claim 26, wherein the terminal is adjacent to the signal stud, extends below the signal stud, and extends laterally from the signal stud in the lateral directions.

如申請專利範圍第26項所述之半導體晶片組體，其中該散熱座至少包含一蓋體，該蓋體位於該導熱凸柱之一頂部上方，鄰接該導熱凸柱之該頂部，並從上方覆蓋該導熱凸柱之該頂部，同時沿該等側面方向自該導熱凸柱之該頂部側向延伸。 The semiconductor wafer package of claim 26, wherein the heat sink comprises at least a cover, the cover is located above a top of one of the thermally conductive studs, adjacent to the top of the thermally conductive stud, and from above Covering the top of the thermally conductive stud while extending laterally from the top of the thermally conductive stud in the lateral direction.

如申請專利範圍第42項所述之半導體晶片組體，其中該蓋體與該焊墊於該介電層上方為共平面。 The semiconductor wafer package of claim 42, wherein the cover and the pad are coplanar above the dielectric layer.

如申請專利範圍第42項所述之半導體晶片組體，其中該蓋體為矩形或正方形，該導熱凸柱之該頂部則為圓形。 The semiconductor wafer package of claim 42, wherein the cover is rectangular or square, and the top of the thermally conductive stud is circular.

如申請專利範圍第42項所述之半導體晶片組體，其中該蓋體之尺寸及形狀係配合該半導體元件之一熱接觸表面而設計，該導熱凸柱之該頂部之尺寸及形狀則並非配合該半導體元件之該熱接觸表面而設計。 The semiconductor wafer package of claim 42, wherein the size and shape of the cover are designed to match a thermal contact surface of the semiconductor component, and the size and shape of the top of the thermal conductive post are not matched. The thermal contact surface of the semiconductor component is designed.

一種半導體晶片組體，至少包含：一半導體元件；一黏著層，其至少具有第一及第二開口，一散熱座，其至少包含一導熱凸柱、一基座及一蓋體，其中該導熱凸柱係鄰接該基座並與該基座一體成形，該導熱凸柱係沿一向上方向延伸於該基座上方，並為該基座與該蓋體提供熱連結，該基座係沿一與該向上方向相反之向下方向延伸於該導熱凸柱下方，並沿垂直於該向上及向下方向之側面方向自該導熱凸柱側向延伸，該蓋體位於該導熱凸柱之一頂部上方，鄰接該導熱凸柱之該頂部，並從上方覆蓋該導熱凸柱之該頂部，同時沿該等側面方向自該導熱凸柱之該頂部側向延伸；一基板，其至少包含一焊墊、一路由線及一介電層，其中第一及第二通孔延伸貫穿該基板；及一導線，其至少包含該焊墊、該路由線、一端子與一訊號凸柱，其中該路由線鄰接該焊墊，該訊號凸柱則鄰接該路由線與該端子，並延伸於該焊墊與該路由線下方，同時延伸於該端子上方，且該焊墊與該端子間之一導電路徑包含該路由線與該訊號凸柱；其中該半導體元件係設置於該蓋體上，重疊於該導熱凸柱但並未重疊於該訊號凸柱，該半導體元件係電性連結至該焊墊，從而電性連結至該端子，且該半導體元件係熱連結至該蓋體，從而熱連結至該基座；其中該黏著層係設置於該基座上，延伸於該基座上方，延伸進入該第一通孔內一介於該導熱凸柱與該基板間之第一缺口，延伸進入該第二通孔內一介於該訊號凸柱與該基板間之第二缺口，並於該等缺口內延伸跨越該介電層，該黏著層係介於該導熱凸柱與該介電層之間、該訊號凸柱與該介電層之間以及該基座與該介電層之間，該黏著層於該等側面方向覆蓋且環繞該導熱凸柱及該訊號凸柱，且延伸至該半導體晶片組體之外圍邊緣；其中該焊墊延伸於該介電層上方；以及其中該導熱凸柱延伸進入該第一開口與該第一通孔，該訊號凸柱延伸進入該第二開口與該第二通孔，該導熱凸柱及該訊號凸柱具有相同厚度，彼此共平面，且延伸穿過該黏著層與該介電層，該基座與該端子具有相同厚度，彼此共平面，且延伸於該黏著層與該介電層下方，該導熱凸柱及該訊號凸柱之頂部及底部係與該黏著層共平面。 A semiconductor wafer assembly comprising at least: a semiconductor component; An adhesive layer having at least first and second openings, a heat sink comprising at least one heat conducting stud, a base and a cover, wherein the heat conducting stud is adjacent to the base and integral with the base Forming, the heat conducting stud extending above the pedestal in an upward direction and providing thermal connection between the pedestal and the cover, the pedestal extending in the downward direction opposite to the upward direction Behind the studs and extending laterally from the thermally conductive studs in a direction perpendicular to the upward and downward directions, the cover is located above the top of one of the thermally conductive studs, adjoins the top of the thermally conductive studs, and Covering the top of the thermally conductive stud with the top portion extending laterally from the top of the thermally conductive stud; the substrate comprising at least one pad, a routing line and a dielectric layer, wherein the first And the second through hole extends through the substrate; and a wire comprising at least the pad, the routing line, a terminal and a signal stud, wherein the routing line is adjacent to the pad, and the signal stud is adjacent to the route a wire with the terminal and extending over the weld And the routing line is extended over the terminal, and a conductive path between the pad and the terminal includes the routing line and the signal stud; wherein the semiconductor component is disposed on the cover and overlaps the The heat conducting stud is not overlapped with the signal stud, the semiconductor component is electrically connected to the pad, electrically connected to the terminal, and the semiconductor component is thermally coupled to the cover, thereby thermally bonding to the a pedestal; the adhesive layer is disposed on the pedestal and extends over the pedestal and extends into the first through hole, and a first gap between the thermally conductive stud and the substrate extends into the second Inside the through hole a second gap between the pillar and the substrate, and extending across the dielectric layer in the gap, the adhesive layer is between the heat conducting stud and the dielectric layer, the signal stud and the dielectric layer Between and between the pedestal and the dielectric layer, the adhesive layer covers and surrounds the thermally conductive stud and the signal stud in the lateral direction and extends to a peripheral edge of the semiconductor wafer assembly; wherein the bonding a pad extending over the dielectric layer; and wherein the heat conducting stud extends into the first opening and the first through hole, the signal stud extending into the second opening and the second through hole, the thermally conductive stud and The signal studs have the same thickness, are coplanar with each other, and extend through the adhesive layer and the dielectric layer, the pedestal and the terminal have the same thickness, are coplanar with each other, and extend to the adhesive layer and the dielectric layer Below, the thermally conductive stud and the top and bottom of the signal stud are coplanar with the adhesive layer.

如申請專利範圍第46項所述之半導體晶片組體，其中該半導體元件為一半導體晶片，且係利用一固晶材料設置於該蓋體上，並利用一打線電性連結至該焊墊，同時利用該固晶材料熱連結至該蓋體。 The semiconductor wafer assembly of claim 46, wherein the semiconductor component is a semiconductor wafer, and is disposed on the cover by a die bonding material, and is electrically connected to the pad by a wire. At the same time, the solid crystal material is used to thermally bond to the cover.

如申請專利範圍第46項所述之半導體晶片組體，其中該黏著層於該等缺口內接觸該導熱凸柱、該訊號凸柱與該介電層，並於該等缺口外接觸該基座、該端子與該介電層，該介電層則接觸該焊墊與該路由線，並與該導熱凸柱、該訊號凸柱、該基座與該端子保持距離。 The semiconductor wafer package of claim 46, wherein the adhesive layer contacts the thermally conductive stud, the signal stud and the dielectric layer in the notches, and contacts the pedestal outside the notches. The terminal and the dielectric layer, the dielectric layer contacts the bonding pad and the routing line, and is spaced apart from the thermally conductive stud, the signal stud, and the base and the terminal.

如申請專利範圍第46項所述之半導體晶片組體，其中該導熱凸柱為平頂錐柱形，其直徑自該基座至該蓋體係呈向上遞減，該訊號凸柱為平頂錐柱形，其直徑自該端子至該路由線係呈向上遞減，該導熱凸柱之該頂部為圓形，該蓋體則為矩形或正方形。 The semiconductor wafer assembly of claim 46, wherein the thermally conductive stud is a flat-topped tapered cylinder having a diameter from the pedestal to the cover system Decreasing upward, the signal stud is a flat-topped tapered cylinder whose diameter decreases upward from the terminal to the routing line, the top of the thermally conductive stud is circular, and the cover is rectangular or square.

如申請專利範圍第46項所述之半導體晶片組體，其中該蓋體與該焊墊於該介電層上方為共平面。The semiconductor wafer package of claim 46, wherein the cover and the pad are coplanar above the dielectric layer.