TW201133729A

TW201133729A - Semiconductor chip assembly with post/base heat spreader and conductive trace

Info

Publication number: TW201133729A
Application number: TW99138653A
Authority: TW
Inventors: Charles W C Lin; Chia-Chung Wang
Original assignee: Bridge Semoconductor Corp
Priority date: 2009-11-11
Filing date: 2010-11-10
Publication date: 2011-10-01
Also published as: CN102074518A

Abstract

A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The semiconductor device is electrically connected to the conductive trace and thermally connected to the heat spreader. The heat spreader includes a post and a base. The post extends upwardly from the base into an opening in the adhesive, and the base extends laterally from the post. The adhesive extends between the post and the conductive trace and between the base and the conductive trace. The conductive trace provides signal routing between a pad and a terminal.

Description

201133729 六、發明說明：【發明所屬之技術領域】本發明係關於半導體晶片組體，更詳而言之，係關於一種由半導體元件、導線、黏著層及散熱座組成之半導體晶片組體及其製造方法。【先前技術】諸如經封裝與未經封裝之半導體晶片等半導體元件可提供尚電壓、高頻率及高效能之應用；該些應用為執行特疋功忐，所需消耗之功率甚高，然功率愈高則半導體元件生熱愈多。此外，在封裝密度提高及尺寸縮減後，可供散熱之表面積縮小，更導致生熱加劇。半導體元件在高溫操作下易產生效能衰退及使用壽命縮短等問題，甚至可能立即故障。高熱不僅影響晶片效能，亦可能因熱膨脹不匹配而對晶片及其週遭元件產生熱應力作用。因此，必須使晶片迅速有效散熱方能確保其操作之效率與可靠度…條高導熱性路徑通常係將熱能傳導並發散至一表面積較晶片或晶片所在之晶粒座更大之區域。發光二極體（LED)近來已普遍成為白熾光源、螢光光源與_素光源之替代光源。LED可為醫療、軍事、招牌、訊號、航空、航海、車柄、可攜式設備、商用與住家照明等應用領域提供尚能源效率及低成本 LED可為燈具、手電筒、車頭燈、之長時間照明。例如，探照燈、交通號誌燈及顯示器卓設備提供光源。 LED巾之高功率晶片在提供高亮度輸出之同時亦產生 201133729 大量熱能。然而，在高溫操作下，LED會發生色偏、亮度降低、使用壽命縮短及立即故障等問題。此外，LED在散BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer package, and more particularly to a semiconductor wafer package comprising a semiconductor component, a wire, an adhesive layer, and a heat sink. Production method. [Prior Art] Semiconductor components such as packaged and unpackaged semiconductor wafers can provide applications with voltage, high frequency, and high performance; these applications require a very high power for performing special functions. The higher the semiconductor component, the more heat it generates. In addition, after the package density is increased and the size is reduced, the surface area available for heat dissipation is reduced, resulting in an increase in heat generation. Semiconductor components are prone to performance degradation and shortened service life at high temperatures, and may even fail immediately. High heat not only affects wafer performance, but may also cause thermal stress on the wafer and its surrounding components due to thermal expansion mismatch. Therefore, the wafer must be dissipated quickly and efficiently to ensure the efficiency and reliability of its operation. A high thermal conductivity path typically conducts and dissipates thermal energy to a larger area than the die pad where the wafer or wafer is located. Light-emitting diodes (LEDs) have recently become the alternative source of incandescent light sources, fluorescent light sources, and light sources. LEDs can provide energy efficiency and low cost LEDs for medical, military, signage, signal, aviation, marine, handle, portable devices, commercial and residential lighting applications. LEDs can be used for lamps, flashlights, headlights, and long time. illumination. For example, searchlights, traffic lights, and display devices provide a light source. The high-power chip of the LED towel also generates a large amount of heat energy while providing high-intensity output. However, under high temperature operation, LEDs may suffer from color shift, brightness reduction, shortened life, and immediate failure. In addition, the LED is scattered

熱方面有其限制’進而影響其光輸出與可靠度。因此，LED 格外突顯市場對於具有良好散熱效果之高功率晶片之需求〇 led封裝體通常包含一 LED晶片、一基座、電接點及一熱接點。所述基座係熱連結至LED晶片並用以支撐該 LED晶片。電接點則電性連結至LED晶片之陽極與陰極。熱接點經由該基座熱連結至LED晶片，其下方載具可充分散熱以預防LED晶片過熱。業界積極以各種設計及製造技術投入高功率晶片封裝體與導熱板之研發，以期在此極度成本競爭之環境中滿足效能需求。塑膠球柵陣列（P B G A)封裝係將一晶片與一層壓基板包裹於一塑膠外殼中，然後再以錫球黏附於一印刷電路板 (PCB)之上。所述層壓基板包含一通常由玻璃纖維構成之介電層。晶片產生之熱能可經由塑膠及介電層傳至錫球，進而傳至印刷電路板。然而，由於塑膠與介電層之導熱性低 ’ PBGA之散熱效果不佳。方形扁平無引腳（qFN)封裝係將晶片設置在一焊接於印刷電路板之銅質晶粒座上。晶片產生之熱能可經由晶粒座傳至印刷電路板。然而，由於其導線架中介層之路由能力有限，使得QFN封裝無法適用於高輸入/輸出（1/〇)晶片或被動元件。 5 201133729 導熱板為半導體元件提供電性路由、熱管理與機械性支撑等功能。導熱板通常包含一用於訊號路由之基板、一提供熱去除功能之散熱座或散熱裝置、一可供電性連結至半導體元件之焊墊’以及一可供電性連結至下一層組體之端子。該基板可為一具有單層或多層路由電路系統及—或多層介電層之層壓結構。該散熱座可為一金屬基座、金屬塊或埋設金屬層。導熱板接合下一層組體。例如，下一層組體可為一具有印刷電路板及散熱裝置之燈座。在此範例中，一 led封裝體係安設於導熱板上，該導熱板則安設於散熱襞置上，導熱板/散熱裝置次組體與印刷電路板又安設於燈座中。此外，導熱板經由導線電性連結至該印刷電路板。該基板將電訊號自該印刷電路板導向LED封裝體，而該散熱座則將 led封裝體之熱能發散並傳遞至該散熱裝置。因此，該導熱板可為LED晶片提供一重要之熱路徑。授予Juskey等人之第6,5〇7，1〇2號美國專利揭示一種組體，其中一由玻璃纖維與固化之熱固性樹脂所構成之複合基板包含一中央開口。一具有類似前述中央開口正方或長方形狀之散熱塊係黏附於該中央開口側壁因而與該基板結合。上、下導電層分別黏附於該基板之頂部及底部，並透過貫穿該基板之電鍍導孔互為電性連結。一晶片係設置於散熱塊上並打線接合至上導電層，—封裝材料係模設成形於晶片上’而下導電層則設有錫球。製造時，該基板原為—置於下導電層上之乙階（Bstage) 201133729 樹脂膠片。散熱塊係插設於中央開口，因而位於下導電層上，並與該基板以一間隙相隔。上導電層則設於該基板上。上、下導電層經加熱及彼此壓合後，使樹脂熔化並流入前述間隙中固化。上、下導電層形成圖案，因而在該基板上形成電路佈線，並使樹脂溢料顯露於散熱塊上。然後去除樹脂溢料，使散熱塊露出。最後再將晶片安置於散熱塊上並進行打線接合與封裝。因此，晶片產生之熱能可經由散熱塊傳至印刷電路板。然而在量產時，以手工方式將散熱塊放置於中央開口内之作業極為費工，且成本高昂。再者，由於側向之安裝容差小，散熱塊不易精確定位於中央開口中，導致基板與散熱塊之間易出現間隙以及打線不均之情形。如此一來，該基板僅部分黏附於散熱塊，無法自散熱塊獲得足夠支撐力 ’且容易脫層。此外，用於去除部分導電層以顯露樹脂溢料之化學蝕刻液亦將去除部分未被樹脂溢料覆蓋之散熱塊，使散熱塊不平且不易結合，最終導致組體之良率降偏低、可靠度不足且成本過高。授予Ding等人之第6,528,882號美國專利揭露一種高散熱球柵陣列封裝體，其基板包含一金屬芯層，而晶片則安置於金屬芯層頂面之晶粒座區域^ 一絕緣層係形成於金屬芯層之底面。盲孔貫穿絕緣層直通金屬芯層，且孔内填有散熱錫球’另在該基板上設有與散熱錫球相對應之錫球。晶片產生之熱能可經由金屬芯層流向散熱錫球，再流向印刷電路板。然而，夾設於金屬芯層與印刷電路板間之絕 201133729 緣層卻對流向印刷電路板之熱流造成限制。授予Lee專人之第6,670,219號美國專利教示一種凹槽向下球栅陣列（CDBGA)封裝體，其中一具有中央開口之接地板係設置於一散熱座上以構成一散熱基板。一具有中央開口之基板透過一具有中央開口之黏著層設置於該接地板上。一晶片係安裝於該散熱座上由接地板中央開口所形成之凹槽内，且该基板上设有錫球。然而，由於錫球係位於基板上，散熱座並無法接觸印刷電路板，導致該散熱座之政熱作用僅限熱對流而非熱傳導，因而大幅限縮其散熱效果。授予Woodall等人之第7,038,311號美國專利提供一種高散熱BGA封裝體，其散熱裝置為倒τ形且包含一柱部與一寬基底。一設有窗型開口之基板係安置於寬基底上，一黏著層則將柱部與寬基底黏附於該基板。一晶片係安置於柱部上並打線接合至該基板，一封裝材料係模製成形於晶片上，s亥基板上則設有錫球。柱部延伸穿過該窗型開口，並由寬基底支撐該基板，至於錫球則位於寬基底與基板周緣之間》晶片產生之熱能可經由柱部傳至寬基底，再傳至印刷電路板。然而，由於寬基底上必須留有容納錫球之空間，寬基底僅在對應於中央窗口與最内部錫球之間的位置大伸於該基板下方。如此一來，該基板在製造過程中便不平衡，且容易晃動及彎曲，進而導致晶片之安裝、打線接合以及封裝材料之模製成形均十分困難。此外，該寬基底可月b因封裝材料之模製成形而彎折，且一旦錫球崩塌，便 201133729 可月b使該封裝體無法焊接至下一層組體。是以，此封裝體之良率偏低、可靠度不足且成本過高。There are limits in terms of heat' which in turn affects its light output and reliability. Therefore, LEDs highlight the market's need for high-power chips with good heat dissipation. 〇 led packages typically contain an LED chip, a pedestal, electrical contacts, and a hot junction. The pedestal is thermally coupled to the LED wafer and used to support the LED wafer. The electrical contacts are electrically connected to the anode and cathode of the LED chip. The thermal contacts are thermally bonded to the LED wafer via the pedestal, and the underlying carrier is sufficiently thermally dissipated to prevent overheating of the LED wafer. The industry is actively investing in high-power chip packages and thermal boards in a variety of design and manufacturing technologies to meet performance needs in this extremely cost-competitive environment. A plastic ball grid array (P B G A) package encloses a wafer and a laminate substrate in a plastic case and then adheres to a printed circuit board (PCB) with solder balls. The laminate substrate comprises a dielectric layer typically composed of glass fibers. The heat generated by the wafer can be transferred to the solder ball via the plastic and dielectric layers and then to the printed circuit board. However, due to the low thermal conductivity of the plastic and dielectric layers, the heat dissipation effect of PBGA is not good. A quad flat no-lead (qFN) package places the wafer on a copper die pad that is soldered to the printed circuit board. The thermal energy generated by the wafer can be transferred to the printed circuit board via the die. However, due to the limited routing capability of its leadframe interposer, QFN packages are not suitable for high input/output (1/〇) wafers or passive components. 5 201133729 Thermal pads provide electrical routing, thermal management and mechanical support for semiconductor components. The heat conducting plate usually comprises a substrate for signal routing, a heat sink or heat sink for providing heat removal, a solder pad electrically connectable to the semiconductor component, and a terminal electrically connectable to the next layer. The substrate can be a laminate having a single or multi-layer routing circuitry and/or a multilayer dielectric layer. The heat sink can be a metal base, a metal block or a buried metal layer. The heat conducting plate engages the next layer of the body. For example, the next layer of the body can be a lamp holder with a printed circuit board and a heat sink. In this example, a led package system is mounted on the heat conducting plate, and the heat conducting plate is mounted on the heat dissipating device, and the heat conducting plate/heat dissipating device sub-group and the printed circuit board are further disposed in the lamp holder. In addition, the heat conducting plate is electrically coupled to the printed circuit board via wires. The substrate directs the electrical signal from the printed circuit board to the LED package, and the heat sink scatters and transfers the thermal energy of the led package to the heat sink. Therefore, the heat shield can provide an important thermal path for the LED wafer. U.S. Patent No. 6,5,7,1,2, issued toJ.S.A. No. 6, the disclosure of which is incorporated herein by reference. A heat dissipating block having a square or rectangular shape similar to the central opening is adhered to the central opening side wall to be bonded to the substrate. The upper and lower conductive layers are respectively adhered to the top and bottom of the substrate, and are electrically connected to each other through the plating vias penetrating the substrate. A wafer is disposed on the heat slug and bonded to the upper conductive layer, the package material is patterned on the wafer, and the lower conductive layer is provided with solder balls. At the time of manufacture, the substrate was originally a Bstage 201133729 resin film placed on the lower conductive layer. The heat dissipating block is inserted in the central opening so as to be located on the lower conductive layer and spaced apart from the substrate by a gap. The upper conductive layer is disposed on the substrate. After the upper and lower conductive layers are heated and pressed against each other, the resin is melted and flows into the gap to be solidified. The upper and lower conductive layers are patterned, thereby forming circuit wiring on the substrate and exposing the resin flash to the heat sink. Then remove the resin flash to expose the heat sink. Finally, the wafer is placed on the heat slug and bonded and packaged. Therefore, the thermal energy generated by the wafer can be transferred to the printed circuit board via the heat slug. However, in mass production, the manual placement of the heat sink in the central opening is labor intensive and costly. Moreover, since the mounting tolerance of the lateral direction is small, the heat dissipating block is not easily positioned in the central opening, which causes a gap between the substrate and the heat radiating block and uneven wiring. As a result, the substrate is only partially adhered to the heat sink block, and sufficient support force is not obtained from the heat sink block and is easily delaminated. In addition, the chemical etching solution for removing part of the conductive layer to expose the resin flash will also remove some of the heat-dissipating block which is not covered by the resin flash, so that the heat-dissipating block is not flat and difficult to combine, and finally the yield of the group is lowered, Insufficient reliability and high cost. US Patent No. 6,528,882 to Ding et al. discloses a high heat dissipation ball grid array package having a substrate comprising a metal core layer and a wafer disposed on a top surface of the metal core layer. The bottom surface of the metal core layer. The blind hole penetrates the insulating layer through the metal core layer, and the hole is filled with a heat-dissipating solder ball. Further, a solder ball corresponding to the heat-dissipating solder ball is disposed on the substrate. The thermal energy generated by the wafer can flow through the metal core to the heat sink balls and then to the printed circuit board. However, the 201133729 edge layer sandwiched between the metal core layer and the printed circuit board limits the heat flow to the printed circuit board. U.S. Patent No. 6,670,219 issued to, the entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire all A substrate having a central opening is disposed on the ground plate through an adhesive layer having a central opening. A chip is mounted on the heat sink in a recess formed by the central opening of the ground plate, and the substrate is provided with a solder ball. However, since the solder ball is on the substrate, the heat sink cannot contact the printed circuit board, and the heat dissipation effect of the heat sink is limited to heat convection instead of heat conduction, thereby greatly reducing the heat dissipation effect. U.S. Pat. A substrate having a window-shaped opening is disposed on the wide substrate, and an adhesive layer adheres the pillar portion and the wide substrate to the substrate. A wafer system is disposed on the pillar portion and wire bonded to the substrate, a package material is molded on the wafer, and a solder ball is disposed on the substrate. The post extends through the window opening and supports the substrate by a wide substrate, and the solder ball is located between the wide substrate and the periphery of the substrate. The thermal energy generated by the wafer can be transferred to the wide substrate via the post and then to the printed circuit board. . However, since a space for accommodating the solder balls must be left on the wide substrate, the wide substrate extends only below the substrate at a position corresponding to the center window and the innermost tin ball. As a result, the substrate is unbalanced during the manufacturing process, and is easily shaken and bent, which in turn leads to difficulty in mounting the wafer, bonding the wire, and molding the package material. In addition, the wide substrate may be bent by the molding of the encapsulating material, and once the solder ball collapses, the 201133729 may make the package unweldable to the next layer. Therefore, the yield of the package is low, the reliability is insufficient, and the cost is too high.

Erchak等人之美國專利申請公開案第2〇〇7/〇267642號提X種發光裝置組體，其中一倒τ形之基座包含一基板、一突出部及-具有通孔之絕緣層，絕緣層上並設有電接八有通孔與透明上蓋之封裝體係設置於電接點上。 - LED日日日片係設置於突出部並以打線連接該基板。該突出部係鄰接該基板並延伸穿過絕緣層與封裝體上之通孔，進入封裝體^絕緣制設置於該基板上，且絕緣層上設有電接點。封裝體係設置於該等電接點上並與絕緣層保持間距。該晶片產生之熱能可經由突出部傳至該基板進而到達-散熱裝置。然而’該等電接點不易設置於絕緣層上，難以與下-層組體電性連結，且無法提供多層路由。 ^習知封裝體與導熱板具有重大缺點。舉例而言，諸如環氧樹脂等低導熱性之電絕緣材料對散熱效果造成限制，然而’以陶究或碳化石夕填充之環氧樹脂等具有較高導敎性之電絕緣材料則具有黏著性低且量產成本過高之缺點。該電、’、邑緣材料可此在製作過程中或在操作初期即因受熱而脫層。該基板若為單層電路系統則路由能板為剛路系統，則其過厚之介電層將降低散=基此外’則案技術尚有散熱座效能不足、體積過大或不易熱連結至下一層組體等問題。前案技術之製造工序亦不適於低成本之量產作業。有鑑於現有高功率半導體元件封裝體及導熱板之種種 201133729 f展情形及相關限制，f界實需__㈣成本效益、效能可罪、適於量產、多功能、可靈活調整訊號路由且具有優異散熱性之半導體晶片組體。【發明内容】相關申請案之相互參照：本申清案為⑽9年9月11日提出中請之第12/557,540 號美國專财請案之料延㈣，而該第12/557,⑽號美國專财請案則為2_年3月18日提出申請之第 12/406’51G號美國專利中請案之部分延續案。該第 :主2/406,510唬美國專利申請案主張2_年$月7曰提出申第/〇7丨，589唬美國臨時專利申請案、2〇〇8年5月7 日出申θ之第61/G71，588號美國臨時專利_請案、2〇〇8 年4月11日提出申請之第61/〇71，〇72號美國臨時專利申請案及2008年3月25日提出申請之第61編，州號美國臨時專利申請案之優先權，上述各案之内容以引用之方式併入本文° M第12/557’54G號美國專利中請案另主張2009 年2月9日提出申請之第61/15〇，號美國臨時專利申請案之優先冑，其内容以引用之方式併入本文。本申請案亦為2_年9月n曰提出申請之第 7,541號美國專利申請案之部分延續案而該第 12/557,541號美國專利中請案則為期年3月a日提出申請之第UMOWO號美國專利φ請案之部分延續案。該第 12/406,51G號美國專利中請案主張2_年$月7日提出申青之第61/071,589號美國臨時專利中請案、2_年$月7 10 201133729 2出^之第61/G71，588號美國臨時專利中請案、2008 月11日提出申請之第61/071，〇72號美國臨時專利申嗜 2雇年3月25日提出中請之第Μ編，748號美國臨時專利申請案之優先權，上述各案之内容以引用之方式併本文别開第12/557,541號美國專利申請案另主張2〇〇9 月9日提出申請之第61/15〇,98〇號美國臨時專利申請案之優先權，其内容以引用之方式併入本文。本發明提供一種半導體晶片組體，其至少包含一半導體το件、—散熱座、—導線與—黏著層。該半導體元件係 :性連結至該導線並熱連結至該散熱座。該散熱座至少包 :凸柱與-基座。該凸柱自該基座向上延伸並進入該黏 ^ 開口，該基座則自該凸柱側向延伸。該黏著層延伸於該凸柱與該導線之間以及該基座與該導線之間。該導線可在一焊墊與一端子之間提供訊號路由。一根據本發明之一樣式，一半導體晶片組體至少包含一，導體it件、一黏著層、一散熱座與一導線。該黏著層至 ▲少具有一開口。該散熱座至少包含一凸柱及一基座，其令該凸柱係鄰接該基座並沿一向上方向延伸於該基座上方，該基座則沿一與該向上方向相反之向下方向延伸於該凸柱方並/CF垂直於該向上及向下方向之側面方向從該凸柱側向延伸而出。該導線至少包含一焊墊與一端子。該半導體元件係位於該凸柱上方並重疊於該凸柱。該半導體元件係電性連結至該焊墊，從而電性連結至該端子 ’並且熱連結至該凸柱，從而熱連結至該基座。 11 3- 201133729 該黏著層係設置於該基座上，延伸於該基座上方，並伸入-位於該凸柱與該料間之缺σ。該黏著層自該凸柱側向延伸至該端子或越過該端子，且係介於該基座與該焊墊之間。該焊墊係設置於該黏著層上，且延伸於該基座上方。該凸柱延伸進入該開口，該基座則延伸於該半導體元件、該黏著層與該焊墊下方。該散熱座可包含一蓋體，該蓋體係位於該凸柱之頂部上方，鄰接該凸柱之頂部，同時從上方覆蓋該凸柱之頂部，並沿該等側面方向從該凸柱之頂部側向延伸而出。例如，該蓋體可為矩形或正方形，而該凸柱之頂部可為圓形。在此例中，該蓋體之尺寸及形狀可經過設計，以配合該半導體元件之熱接觸表面’至於該凸柱頂部之尺寸及形狀則未依該半導體元件之熱接觸表面而設計。該蓋體亦可接觸並覆蓋該黏著層一鄰接該凸柱並與該凸柱共平面之部分。該蓋體亦可在該黏著層上方與該料及/或該端子共平面。此外，該凸柱可熱連結該基座與該蓋體。該散熱座可由該凸柱與該基座組成，或由該凸柱、該基座與該蓋體組成。該散熱座亦可由鋼、㈣鋼/制呂合金組成。無論採用任— 組成方式，該散熱座皆可提供散熱作用，將該半導體元件之熱能擴散至下一層組體。該半導體元件可設置於該散熱座上。例如，該半導體元件可設置於該散熱座及該導線上，重疊於該凸柱與該焊墊’透過-第-焊錫電性連結至該烊塾，並透過一第二焊 12 201133729 錫熱連結至該散熱座。或者，該半導體元件可設置於該散熱座而非該導線上，重疊於該凸柱而非該導線，透過一打線電性連結至該焊墊，並透過一固晶材料熱連結至該散熱座。該半導體元件可為-經封裝或未經封裝之半導體晶片。例如，該半導體元件可為-包含LED晶片之LED封震體 ’其係設置於該散熱座與該導線上，重疊於該凸柱與該焊墊，經由一第一焊錫電性連結至該焊墊，且經由一第二焊錫熱連結至該散熱座。或者，該半導體元件可為一半導體晶片，其係設置於該散熱座而非該導線上，重疊於該凸柱而非該導線，經由一打線電性連結至該焊墊，且經由一固晶材料熱連結至該散熱座。該黏著層可在該缺口中接觸該凸柱，並在該缺口之外接觸該基座、該焊墊與該端子。該黏著層亦可從下方覆蓋該導線，並於該等側面方向覆蓋及環繞該凸柱，同時從上方覆蓋該基座位於該凸柱外之一部分。該黏著層亦可同形被覆於該凸柱之側壁以及該基座位於該凸柱外之一頂面。該黏著層尚可與該凸柱之一頂部共平面。該黏著層亦可填滿該基座與該導線間之一空間，且該黏著層被限制於該散熱座與該導線間之一空間内。該黏著層可自該凸柱側向延伸至該端子或越過該端子。例如，該黏著層與該端子可延伸至該組體之外圍邊緣. 在此例中，該黏著層係從該凸柱側向延伸至該端子。或者，該黏著層可延伸至該組體之外圍邊緣，而該端子則與該 13 201133729 該黏著廣係從該組體之外圍邊緣保持距離；在此情況下凸柱側向延伸且越過該端子。端子層可重疊於該端子或被該料重疊1如，該焊墊及黏著層上方，重#於該黏著層，同時與該 "盖體共平面；在此例中’該黏著層係被該端子重且去該組體則在料㈣該端子之㈣供水平訊號路由。 -者’該端子可延伸於該㈣層下方，並被該㈣層重叠 /時與該基座共平面；在此情況下，該黏著層係重疊於以端子’而該組體則在該蟬塾與該端子之間提供垂直訊號路由。該凸柱可與該基座一體成形。例如，該凸柱與該基座可為單-金屬體或於其介面包含單一金屬豸，其中該單一金屬體可為銅。該凸柱亦可延伸貫穿該開口。該凸柱亦可在該焊塾之—底面上方與該黏著層共平面。該凸柱亦可為平頂錐柱形，其直徑係從該基座處朝其鄰接該蓋體之平坦頂部向上遞減。該基座可從下方覆蓋該半導體元件、該凸柱、該蓋體、該黏著層及該導線，同時支#該黏著層與該導線，並延伸至該組體之外圍邊緣。該導線可與該凸柱及該基座保持距離。該導線亦可為一單層連續跡線，其係設置於該黏著層上並與之接觸，同時重疊於該黏著層且延伸於其上方^該導線亦可包含該焊墊 '該端子與一路由線，其中該焊墊與該端子間之一導電路徑包含該路由線。在上述任一情況下，該導線均可在該 14 201133729 焊墊與該端子之間提供訊號路由。 ,亥焊墊可作為該半導體元件之一電接點，該端子可作為下一層組體之-電接點，且該焊墊與該端子可在該半導體7G件與該下一層組體之間提供訊號路由。 ▲該組體可為-第-級或第二級單晶或多晶裝置。例如。玄組體可為-包含單—晶片或多牧晶片之第—級封裝體。或者’該組體可為-包含單—LED封裝體或多個LED封裝體之第二級模組，其中各該LED封裝體可包含單一· 晶片或多枚led晶片》本發明提供一種製作一半導體晶片組體之方法，其包含：提供一凸柱及一基座；設置一黏著層於該基座上此步驟包含將該凸柱***該黏著層之一開口；設置一導電層於該黏著層上，此步驟包含將該凸柱對準該導電層之一通孔；使該黏著層向上流入該通孔内一介於該凸柱與該導電層間之缺口；固化該黏著層；提供一導線，該導線至少包含一焊墊、一端子與該導電層之一選定部分；設置一半導體元件於一散熱座上，其中該散熱座至少包含該凸柱及該基座；電性連結該半導體元件至該導線；以及熱連結該半導體元件至該散熱座。根據本發明之一樣式，一種製作一半導體晶片組體之方法包含：（1)提供一凸柱、一基座、一黏著層及一導電層 ’其中（a)該凸柱係鄰接該基座，沿一向上方向延伸於該基座上方，延伸進入該黏著層之一開口，並對準該導電層之一通孔’（b)該基座係沿一與該向上方向相反之向下方向延 15 201133729 伸於該凸柱下方，並沿垂直於該向上及向下方向之側面方向自該凸柱側向延伸而出’（c)該黏著層係設置於該基座上，延伸於該基座上方，並位於該基座與該導電層之間，且未固化，此外’（d)該導電層係設置於該黏著層上，並延伸於該黏著層上方；（2)使該黏著層向上流入該通孔内一介於該凸柱與該導電層間之缺口；固化該黏著層；（句提供一導線，該導線至少包含一焊墊、一端子與該導電層之一選定部分；（5)設置一半導體元件於一至少包含該凸柱與該基座之散熱座上，其中該半導體元件重疊於該凸柱；（6)電性連結該半導體元件至該焊墊，藉此電性連結該半導體元件至該端子；以及（7)熱連結該半導體元件至該連結該半導體元件至該基座。種製作一半導體晶片組體 7 根據本發明之另一樣式之方法包含：⑴提供一凸柱與一基座’其中該凸柱係鄰接且-體成形於該基座，並沿—向上方向延伸於該基座上方 ’且該基座係沿-與該向上方向相反之向下方向延伸於1 凸柱下方’並自該凸柱沿垂直於該向上及向下方向之；面方向側向延伸而出；⑺提供-黏著層，其中_開〇延伸貫穿該黏著層；（3)提供-導電層’其中—通孔延伸貫穿電層；⑷設置該黏著層於該基座上，此步驟包含將該;;柱 ***該開口，其中該黏著層係延伸於該基座上方且該柱延伸進人該開口；（5)設置該導電層於該點著層上，2 驟包含將該凸柱對準該通孔，其中該導電層係：伸料黏者層上方’該黏著層係介於該基座與該導電層之間且未固 16 201133729 化；（6)加熱熔化該黏著層；（7)使該基座與該導電層彼此靠合’藉此使該凸柱在該通孔内向上移動，並對該基座與該導電層間之熔化黏著層施加壓力，該壓力迫使該熔化黏著層向上流入該通孔内一介於該凸柱與該導電層間之缺口； (8)加熱固化該熔化黏著層，藉此將該凸柱及該基座機械性黏附至該導電層；（9)提供一導線，該導線至少包含一焊墊、一端子與一路由線，其中該焊墊、該端子與該路由線包含该導電層之選定部分，且一位於該焊墊與該端子間之導電路徑包含該路由線，·（1〇)設置一半導體元件於一散熱座上，該散熱座至少包含該凸柱與該基座，其中該半導體元件重疊於該凸柱；（11)電性連結該半導體元件至該焊墊，藉此電性連結該半導體元件i該端以及（12)熱連結該半導體兀件至該凸柱，藉此熱連結該半導體元件至該基座。提供該凸柱與該基座可包含：提供一金屬板；於該金屬板上形成-圖案化之敍刻阻層’其選擇性曝露該金屬板截刻該金屬板，使其形成該圖案化之蚀刻阻層所定義之圖案，藉此於该金屬板上形成一凹槽，其延伸進入但未貫穿該金屬板；而後去除該圖案化之蝕刻阻層，其中該凸柱包含該金屬板之-未受姓刻部分’此未受姓刻部分突出於該基座上方，且被該凹槽側向環繞，該基座亦包含該金屬板之-未受蝕刻部分，此未受蝕刻部分位於該凸柱盥該凹槽下方。提供該黏著層可包含：提供一未固化環氧樹脂之W 使該黏著層流動可包含：炼化該未固化環氧樹脂；並擠 17 S- 201133729 壓該基座與該導電層間之該未固化環氧樹脂。固化該黏著層可包含：固化該熔化之未固化環氧樹脂。提供該散熱座可包含：在固化該黏著層之後與設置該半導體元件之前，於該凸柱上提供一蓋體，該蓋體位於該凸柱之一頂部上方，鄰接該凸柱之頂部，同時從上方覆蓋該凸柱之頂部，且自該凸柱頂部沿該等側面方向側向延伸而出。提供該焊墊、該端子與該路由線可包含：在固化該黏著層之後，去除該導電層之選定部分。提供該焊墊、該端子與該路由線亦可包含：在固化該黏著層之後，研磨該凸柱、該黏著層及該導電層，以使該凸柱、S亥黏著層及該導電層在一面向該向上方向之上側表面係彼此側向齊平；而後去除該導電層之選定部分以使該焊墊、該端子與該路由線包含該導電層之選定部分。所述研磨可包含：研磨該黏著層而不研磨該凸柱；而後研磨該凸柱、該黏著層及該導電層。所述去除可包含：利用一可定義该焊墊、該端子與該路由線之圖案化蝕刻阻層對該導電層進行濕式化學餘刻。提供該焊墊、該端子與該路由線亦可包含：在研磨完成後，於該凸柱、該黏著層與該導電層上沉積導電金屬以形成一第二導電層；然後去除該些導電層之選定部分以使該焊墊、該端子與該路由線包含該些導電層之選定部分。沉積導電金屬以形成該第二導電層可包含：將一第一被覆層以無電鍍被覆之方式設於該凸柱、該黏著層與該導電 18 201133729 層上’而後將一第二被霜被覆層以電鍍方式設於該第-被覆層上。所述去除可包含··刺田散復層用可疋義该焊墊、該端子盥該由線之圖案化蝕刻阻層Λ路層對該些導電層進行濕式化學蝕刻。提供該蓋體可包含.土a —结匕3 .去除该第二導電層之選定部分。提供該蓋體亦可包含：先+ 兀凡成刖返研磨，然後利用可該蓋體之圖案化蝕刻阻層去 W玄除及第一導電層之選定部分，以使該蓋體包含該第二導電層之敎部分。如此—來，該焊塾該端子、4路由線與該蓋體便可透過同—研磨，並於同一濕式化學飯岁丨牛干蝕刻步驟中利用同一圖案化蝕刻阻層同時形成。使該黏著層流動可0# 匕3 ·以該黏著層填滿該缺口。使該黏著層流動亦可包含：擠壓該黏著層，使其通過該缺口，到達該凸柱與該導電層上方，並及於該凸柱頂面與該導電層頂面鄰接該缺口之部分。固化#亥黏者層可句. qn t t 匕3 .將該凸柱與該基座機械性結合於該導電層。設置該導電層可包含：將該導電層單獨設置於該黏著層上，或者’先將該導電層黏附於一載體，然後將該導電層與該載體-同設置於該黏著層上，以使該載體重疊於該導電層，而該導電層則接觸該黏著層且介於該黏著層與該載體之間’接著在該黏著層固化後’先去除該載體，再提供該導線。設置該半導體元件可包含：將該半導體元件設置於該蓋體上。設置該半導體元件亦可包含：將該半導體元件設 19 201133729 置於該凸柱、該蓋體與該開口上方，並使該半導體元件重疊於該凸柱、該蓋體與該開口。設置該半導體元件可包含：提供-第-焊錫與-第二焊錫，其中該第-焊錫位於一包含LED晶片之led封裝體與該焊塾之間，該第二焊錫位於該LED封裝體與該蓋體之間。電性連結該半導體元件可包含：在該led封裝體與該焊塾之間提供該第H熱連結該半導體元件可包含：在該LED封裝體與該蓋體之間提供該第二焊錫。設置該半導體元件可包含：在一半導體晶片與該蓋體之間提供-固晶材料。電性連結該半導體元件可包含：在該晶片與該焊墊之間提供—打線。熱連結該半導體元件可包含：在該晶片與該蓋體之間提供該固晶材料。該黏著層可接觸該凸柱、該基座、該蓋體、該焊塾、該端子與該路由線’從下方覆蓋該導線，於該等側面方向覆蓋並環繞該凸柱’從上方覆蓋該基座位於該凸柱外之一部分，並延伸至該組體製造完成後與同批生產之其他組體分離所形成之外圍邊緣。當該組體製造完成且與同批生產之其他組體分離後，該基座可從下方覆蓋該半導體元件、該凸柱、該蓋體、該黏著層與該導線，同時支撐該黏著層與該導線，並延伸至該組體之外圍邊緣。本發明具有多項優點。該散熱座可提供優異之散熱效果，並使熱能不流經該黏著層。因此，該黏著層可為低導熱性之低成本電介質且不易脫|。該凸柱與該基座可一體 20 201133729 成形以提高可靠度。該蓋體可為該半導體元件量身訂做以提升熱連結之效果。該黏著層可介於該基座與該導線之間，藉以在該散熱座與該導線之間提供堅固之機械性連結。該導線可具有簡單之電路圖案，俾以低成本之方式提供水平向之單層減路由1基座可為料線提供機械性支樓，防止其彎曲變形。該組體可利用低溫工序製造，不僅降低應力’亦提高可靠度。該組體亦可利用電路板、導線架與捲帶式基板製造廠可輕易實施之高控制工序加以製造。本發明之上述及其他特徵與優點將於下文中藉由各種實施例進一步加以說明。【實施方式】第1A至1D圖為剖視圖，種製作一凸柱與一基座之方法，圖之俯視圖及仰視圖。續'示本發明之一實施例中一第1E及if圖分別為第m 第1A圖為金屬板10之剖視圖，金屬板ι〇包含相背之主要表面12及14。圖示之金屬板1〇係一厚度為5〇〇微米之銅板冑具有導熱性尚、結合性良好與低成本等優點。金屬板10可由多種金屬製成，如鋼、銘、鐵錄合金、鐵、鎳、銀、金、其混合物及其合金。第1B圖為一刮視圖，顯示金屬板1〇上形成有一圖案化之蝕刻阻層16與一全面覆蓋之蝕刻阻層】8。圖示之圖案刻阻層16與全面覆蓋之姓刻阻層18係沉積於金屬之光阻層’其製作方式係利用愿模技術以熱滚輪同時將光阻層分別塵合於表面12 & 14。濕性旋塗法及淋幕塗 21 气. 201133729 =亦=用之光阻形成技術。將一光罩(圖未示)靠合於光依照習知技術，令光線選擇性通過光罩，使受部分變為不可溶解，·之後再以顯影液去除未受光乃:溶解之光阻部分，使光阻層形成圖案，即形成圖案之刻阻層16。因此，光阻層（即圖案化之敍刻阻層16) 具有-可選擇性曝露表面12之圖案，而光阻層(即全面覆蓋之餘刻阻層18)則無圖案且覆蓋表面14。土第1C圖為—剖視圖，顯示金屬板1〇形成有一掘入伸金屬板10之凹槽20。凹槽20係以韻刻金屬板10之 :式形成，以使金屬板10形成由圖案化之姓刻阻層16所定義之圖案。圖示之姓刻方式為正面濕式化學钱刻。例如 ’：將結構體反轉，使圖案化之蝕刻阻層16朝下而全面覆蓋之姓刻阻層18朝上，然後利用—朝上且面向圖案化之 αΙΡ層16之底部噴嘴（圖未示）將化學蝕刻液噴灑至金屬板10及圖案化之蝕刻阻層16，在此同時，一面向全面覆蓋之姓刻阻層18之頂部噴嘴（圖未示）則不予啟動，如此—來便可借助重力去除钱刻之副產物。或者，利用全面覆蓋之姓刻阻層18提供背面保護，亦可將結構體浸人化學敍刻液中以形成凹槽20。所述化學蝕刻液對銅具有高度針對性，且可刻入金屬板10達200微米。因此，凹槽2〇自表面^ 延伸進入但未穿透金屬板1〇，與表面14距離3〇〇微米，深度則為200微米。化學蝕刻液亦對圖案化之蝕刻阻層μ下方之金屬板10造成側向蝕入。適用之化學蝕刻液可為含鹼氨之溶液或硝酸與鹽酸之稀釋混合物。換言之，所述化與 22 201133729 蝕刻液可為酸性或鹼性。。足以形成凹槽2〇過度曝露於化學姓刻液之理想蝕刻時間 20而不致使金屬板卜間可由試誤法決定In the U.S. Patent Application Publication No. 2/7/267,642 to Erchak et al., the X-ray device assembly comprises a substrate, a protrusion and an insulating layer having a through hole. A sealing system with an electrical connection of eight through holes and a transparent upper cover is disposed on the insulating layer. - The LED day and day film is placed on the protruding portion and connected to the substrate by wire bonding. The protruding portion is adjacent to the substrate and extends through the insulating layer and the through hole on the package body, and is inserted into the package body to be disposed on the substrate, and the insulating layer is provided with an electrical contact. A package system is disposed on the electrical contacts and spaced apart from the insulating layer. The thermal energy generated by the wafer can be transferred to the substrate via the projections to the heat sink. However, these electrical contacts are not easily disposed on the insulating layer, and are difficult to electrically connect with the lower-layer assembly, and cannot provide multilayer routing. ^The conventional package and the heat conducting plate have major drawbacks. For example, an electrically insulating material such as an epoxy resin that has low thermal conductivity limits the heat dissipation effect. However, an electrically insulating material having a high conductivity such as a ceramic or a carbonized stone-filled epoxy resin has adhesion. Low cost and high cost of mass production. The electric, or rim material can be delaminated by heat during the manufacturing process or at the beginning of the operation. If the substrate is a single-layer circuit system, the routing energy board is a rigid circuit system, and the excessively thick dielectric layer will reduce the bulk = base. In addition, the technology has insufficient heat sink performance, is too bulky, or is not easily thermally connected to the bottom. One layer group and other issues. The manufacturing process of the prior art is also not suitable for low-cost mass production operations. In view of the current situation and related limitations of the current high-power semiconductor package and heat-conducting plate, the f sector needs __(4) cost-effectiveness, performance guilty, suitable for mass production, multi-function, flexible adjustment of signal routing and A semiconductor wafer package with excellent heat dissipation. [CRITERIA] The cross-references of the relevant applications: The application for this application is (10) September 11th, 9th, and the request for the US special account No. 12/557, 540 is extended (4), and the 12th, 557, (10) The US special account request is part of the continuation of the US patent application No. 12/406'51G filed on March 18, 2nd. The first: The main 2/406,510 US patent application claims 2 years, 7 months, 7 days, 申7〇, 589唬 US provisional patent application, May 7th, 2nd, May 7th US Provisional Patent No. 61/G71,588_Request, No. 61/〇71, filed on April 11, 2008, US Provisional Patent Application No. 72 and Application No. on March 25, 2008 61, the priority of the state's US provisional patent application, the contents of the above cases are incorporated herein by reference. M US Patent No. 12/557'54G, and the other application is filed on February 9, 2009. Priority to U.S. Provisional Patent Application Serial No. 61/15, the disclosure of which is incorporated herein by reference. This application is also a continuation of the U.S. Patent Application No. 7,541, filed on Sep. 2, 2009, and the U.S. Patent Application Serial No. 12/557,541, the UMOWO application filed on March a. Part of the continuation of the US patent φ request. The US Patent No. 12/406, 51G claims that the US Patent Provision No. 61/071,589 of Shen Qing, No. 61/071,589, is filed in the US Patent No. 12/406, 51G. Proposal for US Provisional Patent No. 61/G71, 588, No. 61/071, No. 748, filed on March 11th, US Patent Application No. 61/071, No. 72 Priority of the U.S. Provisional Patent Application, the contents of each of which are incorporated by reference in its entirety in the U.S. Patent Application Serial No. 12/557,541, the entire disclosure of which is incorporated herein by reference. The priority of the U.S. Provisional Patent Application is hereby incorporated by reference. The present invention provides a semiconductor wafer package comprising at least one half of a conductor, a heat sink, a wire and an adhesive layer. The semiconductor component is sexually coupled to the wire and thermally coupled to the heat sink. The heat sink includes at least: a stud and a base. The stud extends upward from the base and into the viscous opening, the pedestal extending laterally from the stud. The adhesive layer extends between the stud and the wire and between the base and the wire. The wire provides signal routing between a pad and a terminal. According to one aspect of the invention, a semiconductor wafer package includes at least one of a conductor member, an adhesive layer, a heat sink and a wire. The adhesive layer has a small opening to ▲. The heat sink includes at least a stud and a base, the post is adjacent to the base and extends upwardly in the upward direction of the base, and the base is in a downward direction opposite to the upward direction Extending from the column side and /CF perpendicular to the lateral direction of the upward and downward directions, extending laterally from the stud. The wire includes at least one pad and one terminal. The semiconductor component is located above the pillar and overlaps the pillar. The semiconductor component is electrically connected to the pad to be electrically connected to the terminal ′ and thermally coupled to the stud to be thermally coupled to the pedestal. 11 3- 201133729 The adhesive layer is disposed on the base, extends above the base, and extends into the gap σ between the stud and the material. The adhesive layer extends laterally from the stud to the terminal or over the terminal and between the pedestal and the pad. The solder pad is disposed on the adhesive layer and extends above the base. The stud extends into the opening, and the pedestal extends over the semiconductor component, the adhesive layer and the pad. The heat sink can include a cover body located above the top of the stud, abutting the top of the stud, while covering the top of the stud from above, and from the top side of the stud in the side directions Extend out. For example, the cover may be rectangular or square, and the top of the stud may be circular. In this case, the cover may be sized and shaped to match the thermal contact surface of the semiconductor component. The size and shape of the top of the stud are not designed according to the thermal contact surface of the semiconductor component. The cover may also contact and cover the adhesive layer a portion adjacent to the co-column and coplanar with the stud. The cover may also be coplanar with the material and/or the terminal above the adhesive layer. In addition, the stud can thermally join the base and the cover. The heat sink may be composed of the pillar and the base, or the pillar, the base and the cover. The heat sink can also be composed of steel, (four) steel / Lu alloy. Regardless of the composition, the heat sink can provide heat dissipation to diffuse the thermal energy of the semiconductor component to the next layer. The semiconductor component can be disposed on the heat sink. For example, the semiconductor device can be disposed on the heat sink and the wire, and is electrically connected to the bump and the solder pad through the solder-first solder, and is electrically connected to the solder through a second solder 12 201133729 To the heat sink. Alternatively, the semiconductor component may be disposed on the heat sink instead of the wire, and overlap the bump and the wire, electrically connected to the pad through a wire, and thermally coupled to the heat sink through a die bonding material. . The semiconductor component can be a packaged or unpackaged semiconductor wafer. For example, the semiconductor component may be an LED sealing body comprising an LED chip, which is disposed on the heat sink and the wire, and is overlapped with the pillar and the pad, and is electrically connected to the solder via a first solder. The pad is thermally coupled to the heat sink via a second solder. Alternatively, the semiconductor device may be a semiconductor wafer disposed on the heat sink instead of the wire, overlapping the pillar and not the wire, electrically connected to the pad via a wire, and through a die bond The material is thermally bonded to the heat sink. The adhesive layer contacts the stud in the notch and contacts the pedestal, the pad and the terminal outside the notch. The adhesive layer may also cover the wire from below and cover and surround the protrusion in the lateral direction while covering the base from a portion of the protrusion outside the protrusion. The adhesive layer may also be coated in the same manner on the sidewall of the stud and the base is located on a top surface of the stud. The adhesive layer can still be coplanar with the top of one of the studs. The adhesive layer may also fill a space between the base and the wire, and the adhesive layer is confined in a space between the heat sink and the wire. The adhesive layer can extend laterally from the stud to the terminal or across the terminal. For example, the adhesive layer and the terminal can extend to the peripheral edge of the assembly. In this example, the adhesive layer extends laterally from the stud to the terminal. Alternatively, the adhesive layer may extend to a peripheral edge of the set, and the terminal is spaced from the peripheral edge of the set by the 13 201133729; in this case the stud extends laterally and over the terminal . The terminal layer may be overlapped with the terminal or overlapped by the material, for example, above the bonding pad and the adhesive layer, in the adhesive layer, and coplanar with the "cover; in this case, the adhesive layer is The terminal is heavy and goes to the group to be in the material (4) (4) of the terminal for horizontal signal routing. - the terminal may extend below the (four) layer and be coplanar with the pedestal by the (four) layer overlap/time; in this case, the adhesive layer is overlapped with the terminal ' and the set is at the 蝉Provide vertical signal routing between the terminal and the terminal. The stud can be integrally formed with the base. For example, the stud and the pedestal may be a single-metal body or comprise a single metal ruthenium in its interface, wherein the single metal body may be copper. The stud can also extend through the opening. The stud can also be coplanar with the adhesive layer above the bottom surface of the solder fillet. The stud may also be a flat-topped conical cylinder having a diameter that decreases upwardly from the base toward its flat top adjacent the cover. The pedestal can cover the semiconductor component, the stud, the cover, the adhesive layer and the wire from below, and simultaneously support the adhesive layer and the wire and extend to the peripheral edge of the set. The wire can be spaced from the stud and the base. The wire may also be a single-layer continuous trace disposed on and in contact with the adhesive layer while overlapping the adhesive layer and extending over the wire. The wire may also include the pad 'the terminal and the A routing line, wherein a conductive path between the pad and the terminal includes the routing line. In either case, the wire can provide signal routing between the 14 201133729 pad and the terminal. , the solder pad can be used as an electrical contact of the semiconductor component, the terminal can be used as an electrical contact of the next layer, and the pad and the terminal can be between the semiconductor 7G component and the next layer assembly Provide signal routing. ▲ The group can be a -stage or second stage single crystal or polycrystalline device. E.g . The squad can be a first-stage package containing a single-wafer or multi-grass wafer. Or the 'group can be - a second-level module comprising a single-LED package or a plurality of LED packages, wherein each of the LED packages can comprise a single wafer or a plurality of led wafers." The present invention provides a fabrication The method of the semiconductor wafer assembly includes: providing a stud and a pedestal; and providing an adhesive layer on the pedestal; the step of inserting the stud into an opening of the adhesive layer; and providing a conductive layer to the adhesive On the layer, the step comprises: aligning the stud with one of the through holes of the conductive layer; causing the adhesive layer to flow upward into the through hole; a gap between the stud and the conductive layer; curing the adhesive layer; providing a wire The wire includes at least one pad, a terminal and a selected portion of the conductive layer; a semiconductor component is disposed on a heat sink, wherein the heat sink comprises at least the pillar and the base; and the semiconductor component is electrically connected to The wire; and thermally bonding the semiconductor component to the heat sink. According to one aspect of the invention, a method of fabricating a semiconductor wafer package includes: (1) providing a stud, a pedestal, an adhesive layer, and a conductive layer, wherein (a) the stud is adjacent to the pedestal Extending in an upward direction above the pedestal, extending into one of the openings of the adhesive layer, and aligning one of the conductive layers with a through hole' (b) the pedestal is extended in a downward direction opposite to the upward direction 15 201133729 extends below the stud and extends laterally from the stud in a direction perpendicular to the upward and downward directions. ((c) the adhesive layer is disposed on the base and extends to the base Above the seat, between the base and the conductive layer, and uncured, in addition, '(d) the conductive layer is disposed on the adhesive layer and extends above the adhesive layer; (2) the adhesive layer Flowing upward into the through hole, a gap between the stud and the conductive layer; curing the adhesive layer; (providing a wire comprising at least one pad, a terminal and a selected portion of the conductive layer; (5) Configuring a semiconductor component to include at least the stud a heat sink of the pedestal, wherein the semiconductor component is overlapped with the stud; (6) electrically connecting the semiconductor component to the pad, thereby electrically connecting the semiconductor component to the terminal; and (7) thermally connecting The semiconductor device is connected to the semiconductor device to the pedestal. The method for fabricating a semiconductor wafer assembly 7 according to another aspect of the present invention comprises: (1) providing a stud and a pedestal 'where the stud is adjacent and Forming the body on the base and extending in an upward direction above the base 'and the base is extending in a downward direction opposite the upward direction from below the 1st post' and perpendicularly from the stud In the upward and downward directions; the surface direction extends laterally; (7) providing an adhesive layer, wherein the opening is extended through the adhesive layer; (3) providing a conductive layer 'where the through hole extends through the electrical layer; (4) providing the adhesive layer on the pedestal, the step comprising: inserting the column into the opening, wherein the adhesive layer extends over the pedestal and the post extends into the opening; (5) the conductive layer is disposed At the point of the layer, 2 steps will be included The protruding post is aligned with the through hole, wherein the conductive layer is: above the stretched adhesive layer, the adhesive layer is between the base and the conductive layer and is not solidified; (6) heating and melting Adhesive layer; (7) causing the pedestal and the conductive layer to abut each other', thereby moving the stud upward in the through hole, and applying pressure to the molten adhesive layer between the pedestal and the conductive layer, the pressure Forcing the molten adhesive layer to flow upward into the through hole and a gap between the protruding post and the conductive layer; (8) heating and curing the molten adhesive layer, thereby mechanically adhering the protruding post and the base to the conductive layer (9) providing a wire comprising at least one pad, a terminal and a routing line, wherein the pad, the terminal and the routing line comprise a selected portion of the conductive layer, and a pad is located between the pad and the pad The conductive path between the terminals includes the routing line, and a semiconductor component is disposed on a heat sink, the heat sink includes at least the pillar and the base, wherein the semiconductor component is overlapped with the pillar; Electrically connecting the semiconductor component to the pad, Electrically connecting the semiconductor element i, and the end (12) thermally coupled to the semiconductor Wu the boss member, whereby the semiconductor element is thermally coupled to the base. Providing the stud and the base may include: providing a metal plate; forming a patterned patterned resist layer on the metal plate to selectively expose the metal plate to engrave the metal plate to form the pattern Etching a pattern defined by the resist layer, thereby forming a recess on the metal plate that extends into but not through the metal plate; and then removes the patterned etch stop layer, wherein the stud includes the metal plate - an unexamined portion - the unexamined portion protrudes above the pedestal and is laterally surrounded by the recess, the pedestal also including an unetched portion of the metal plate, the unetched portion being located The stud is below the groove. Providing the adhesive layer may include: providing an uncured epoxy resin, and flowing the adhesive layer may include: refining and curing the uncured epoxy resin; and pressing 17 S-201133729 to press the susceptor between the pedestal and the conductive layer Curing epoxy resin. Curing the adhesive layer can comprise: curing the molten uncured epoxy resin. Providing the heat sink may include: providing a cover on the stud after curing the adhesive layer and before disposing the semiconductor component, the cover being located above the top of one of the studs, adjacent to the top of the stud, and simultaneously The top of the stud is covered from above and extends laterally from the top of the stud in the lateral directions. Providing the pad, the terminal and the routing line can include removing a selected portion of the conductive layer after curing the adhesive layer. Providing the solder pad, the terminal and the routing line may further include: after curing the adhesive layer, grinding the pillar, the adhesive layer and the conductive layer, so that the pillar, the S-adhesive layer and the conductive layer are A top side surface facing the upward direction is laterally flush with each other; and then a selected portion of the conductive layer is removed such that the pad, the terminal and the routing line comprise selected portions of the conductive layer. The grinding may include: grinding the adhesive layer without grinding the stud; and then grinding the stud, the adhesive layer, and the conductive layer. The removing may include: performing a wet chemical scavenging of the conductive layer with a patterned etch stop layer defining the pad, the terminal, and the routing line. Providing the solder pad, the terminal and the routing line may further include: depositing a conductive metal on the bump, the adhesive layer and the conductive layer to form a second conductive layer after the polishing is completed; and then removing the conductive layer The selected portion is such that the pad, the terminal and the routing line comprise selected portions of the conductive layers. Depositing the conductive metal to form the second conductive layer may include: disposing a first coating layer on the stud, the adhesive layer and the conductive layer 1833733729 in an electroless plating manner, and then coating a second frost layer The layer is provided on the first coating layer by electroplating. The removing may include a shattering layer of the shovel. The conductive layer is wet chemically etched using the pad, the terminal, and the patterned etch stop layer of the line. The cover is provided to include a soil a - a crucible 3. The selected portion of the second electrically conductive layer is removed. Providing the cover body may further include: first + 兀刖刖刖研磨, then using the patterned etching etch layer of the cover to remove the selected portion of the first conductive layer, so that the cover includes the first The second part of the two conductive layers. In this way, the terminal, the 4 routing wires and the cover body can be transparently ground and simultaneously formed by the same patterned etching resist layer in the same wet chemical yak dry etching step. The adhesive layer is allowed to flow 0# 匕3. The gap is filled with the adhesive layer. Flowing the adhesive layer may also include: pressing the adhesive layer through the notch to reach the stud and the conductive layer, and a portion of the top surface of the stud adjacent to the top surface of the conductive layer . The cured layer can be mechanically bonded to the conductive layer. qn t t 匕3. The providing the conductive layer may include: separately arranging the conductive layer on the adhesive layer, or 'adhering the conductive layer to a carrier, and then placing the conductive layer and the carrier on the adhesive layer, so that The carrier is overlaid on the conductive layer, and the conductive layer contacts the adhesive layer and is interposed between the adhesive layer and the carrier. Then, after the adhesive layer is cured, the carrier is removed first and then the wire is provided. Providing the semiconductor device may include disposing the semiconductor device on the cover. The disposing the semiconductor device may further include: placing the semiconductor device 19 201133729 over the stud, the cover and the opening, and overlapping the semiconductor element with the stud, the cover and the opening. The disposing the semiconductor device may include: providing a -th solder and a second solder, wherein the first solder is located between a led package including an LED chip and the solder pad, and the second solder is located in the LED package and the Between the covers. Electrically connecting the semiconductor component can include: providing the H-th thermal connection between the LED package and the solder fillet. The semiconductor component can include: providing the second solder between the LED package and the cover. Providing the semiconductor device can include providing a -solid crystal material between a semiconductor wafer and the cover. Electrically bonding the semiconductor component can include providing a wire between the wafer and the pad. Thermally bonding the semiconductor component can include providing the die bond material between the wafer and the cover. The adhesive layer may contact the protruding post, the base, the cover body, the soldering ring, the terminal and the routing line 'covering the wire from below, covering the surrounding side and surrounding the protruding column' from above The pedestal is located at a portion of the outer portion of the stud and extends to a peripheral edge formed by the separation of the other components of the same batch after the assembly is completed. After the assembly is manufactured and separated from other groups of the same batch, the pedestal can cover the semiconductor element, the stud, the cover, the adhesive layer and the wire from below, while supporting the adhesive layer and The wire extends to the peripheral edge of the set. The invention has several advantages. The heat sink provides excellent heat dissipation and allows thermal energy to flow through the adhesive layer. Therefore, the adhesive layer can be a low-cost dielectric with low heat conductivity and is not easily removed. The stud is integrally formed with the base 20 201133729 for improved reliability. The cover body can be tailored to the semiconductor component to enhance the effect of thermal bonding. The adhesive layer can be interposed between the base and the wire to provide a strong mechanical bond between the heat sink and the wire. The wire can have a simple circuit pattern and provide a horizontal single-layer de-routed pedestal at a low cost to provide a mechanical support for the wire to prevent bending deformation. This group can be manufactured by a low temperature process, which not only reduces stress but also improves reliability. The assembly can also be fabricated using high control procedures that can be easily implemented by circuit boards, lead frames, and tape and roll substrate manufacturers. The above and other features and advantages of the present invention will be further described hereinafter by way of various embodiments. [Embodiment] Figs. 1A to 1D are cross-sectional views showing a method of fabricating a stud and a pedestal, and a plan view and a bottom view. Continuing to show an embodiment of the present invention, the first and second figures are the mth, and the first and second views are a cross-sectional view of the metal plate 10, and the metal plate ι includes the opposite major surfaces 12 and 14. The illustrated metal plate 1 is a copper plate having a thickness of 5 μm and has the advantages of thermal conductivity, good bonding, and low cost. The metal sheet 10 can be made of a variety of metals such as steel, stellite, ferrous alloy, iron, nickel, silver, gold, mixtures thereof, and alloys thereof. Fig. 1B is a plan view showing that a patterned etch stop layer 16 and a etch stop layer 8 are formed on the metal plate. The illustrated pattern resistive layer 16 and the fully-covered surname resist layer 18 are deposited on the metal photoresist layer'. The fabrication method is to use the hot-rolling roller to simultaneously dust the photoresist layer on the surface 12 & 14. Wet spin coating and curtain coating 21 gas. 201133729 = also = the use of photoresist formation technology. A reticle (not shown) is placed in the light according to the conventional technique, so that the light selectively passes through the reticle, so that the affected portion becomes insoluble, and then the unreceiving portion is removed by the developer: the dissolved photoresist portion The photoresist layer is patterned, that is, the patterned resist layer 16 is formed. Thus, the photoresist layer (i.e., the patterned resist layer 16) has a pattern of selectively exposed surface 12, while the photoresist layer (i.e., the fully covered resist layer 18) is unpatterned and covers the surface 14. Fig. 1C is a cross-sectional view showing that the metal plate 1 is formed with a recess 20 into which the metal plate 10 is dug. The recess 20 is formed in a manner that the metal plate 10 is formed such that the metal plate 10 forms a pattern defined by the patterned etched layer 16. The name of the surname is engraved on the front side of the wet chemical money engraving. For example, 'the structure is reversed so that the patterned etch stop layer 16 faces downward and the full-scale etched layer 18 faces upward, and then the bottom nozzle of the α-layer 16 facing upwards and facing the pattern (Fig. The chemical etching solution is sprayed onto the metal plate 10 and the patterned etch stop layer 16. At the same time, a top nozzle (not shown) facing the fully-covered surname resist layer 18 is not activated, so By gravity, the by-products of the money can be removed. Alternatively, the backing protection may be provided by a fully-covered surname resist layer 18, or the structure may be immersed in a chemical engraving to form the recess 20. The chemical etchant is highly targeted to copper and can be engraved into the metal plate 10 up to 200 microns. Therefore, the groove 2〇 extends from the surface ^ but does not penetrate the metal plate 1〇, is 3 μm from the surface 14 and has a depth of 200 μm. The chemical etchant also causes lateral etch in the metal plate 10 below the patterned etch stop layer. A suitable chemical etching solution may be a solution containing an alkali ammonia or a diluted mixture of nitric acid and hydrochloric acid. In other words, the etchant can be acidic or basic. . Sufficient to form the groove 2 过度 excessive exposure to the ideal etching time of the chemical surname 20 without causing the metal plate to be determined by trial and error

圖，其中該等光阻層已經溶劑處理去除之剖視圖、俯視圖里去除。例如，所用溶劑可為PH為14之強鹼性氫氧化鉀溶液。蝕刻後之金屬板ίο因此包含凸柱22及基座24。凸柱22為金屬板1〇上一受圖案化之蝕刻阻層16保護而未被蝕刻之部分。凸柱22係鄰接基座24，與基座24形成一體，且突伸於基座24上方，在侧向則由凹槽2〇所包圍。凸柱22高200微米（等於凹槽2〇之深度），其頂面（表面12(如圖1A)之圓形部分）之直徑為1〇〇〇微米，而底部（鄰接基座24之圓形部分）之直徑則為11〇〇微米。因此凸柱 22呈平頂錐柱形（類似一平截頭體），其側壁漸縮直徑則自基座24處朝其平坦圓形頂面向上遞減。該漸縮側壁係因化學蝕刻液側向蝕入圖案化之蝕刻阻層16下方而形成。該頂面與該底部之圓周同心（如第1E圖所示）。基座24為金屬板1〇在凸柱22下方之一未受蝕刻部分，自凸柱22沿一側向平面（如左、右等側面方向）側向延伸 ’厚度為300微米（即500-200)。凸柱22與基座24可經處理以加強與環氧樹脂及焊料之結合度。例如’凸柱22與基座24可經化學氧化或微蝕刻以產生較粗糙之表面。 23 201133729 凸柱22與基座24在圖式中為透過削減法形成之單一金屬(銅)體。此外，亦可利用-具有凹槽或孔洞以定義凸柱 22部位之接觸件沖壓金屬板1Q，使凸柱22與基座Μ成為沖壓成型之單一金屬體。或者，可利用增添法形成凸柱22 ，其作法係透過電鍍、化學氣相沉積（cvd)、物理氣相沉積（PVD)等技術，將凸柱22沉積於基座24上。例如，可於銅質基座24上電鑛焊料凸柱22 ;在此情況下，凸柱22與基座24係以冶金介面相接，彼此鄰接但並非—體成形。或者，可利用半增添法形成凸柱22，例如可於凸柱22其钱刻形成之下部上方沉積凸柱22之上部。此外，凸柱22與基座24亦可同時以半增添法形成，例如可在凸柱22與基^ 24其蝕刻形成之下部上方沉積凸柱22與基座24之同形上部。凸柱22亦可燒結於基座24。第2A及2B圖為剖視圖，說明本發明之一實施例中一種製作黏著層之方法。帛2(：及2D圖分別為根據第2b圖所繪製之俯視圖及仰視圖。第2A圖為黏著層26之剖視圖，其中黏著層％為乙階 (B-stage)未固化環氧樹脂之膠片，其為一未經固化且無圖案之片體，厚125微米。黏著層26可為多種有機或無機電性絕緣體製成之各種介電膜或膠片。例如，黏著層26起初可為一膠片，其中樹脂型態之熱固性環氧樹脂浸入一加強材料後部分固化至中期。所述環氧樹脂可為FR-4，但亦可使用諸如多官能與雙馬來醯亞胺·三氮雜苯（BT)樹脂等其他環氧樹脂。在特定應 24 201133729 用中，氰酸酯、聚醯凸肚^ 严窗鮮亞胺及聚四氣乙烯(pTFE)亦為衣氧祕知。所述加強材料可為電子級玻璃，亦:之強材料，如向強度破璃、低誘電率玻璃、石克加維（kevlar aramicn月试哲、兄維拉纖專。所述加強材料也可為織物、不織布或”、、方向性微纖維。可將諸如石夕（研粉溶融物加入膠片中以楛弁邋、）寺填充物 …* 、…衝擊阻抗力與熱膨脹匹配性 …用市售預浸潰體’如美國威斯康辛州奥克萊ΜThe figure in which the photoresist layers have been removed by solvent treatment and removed in a plan view and a top view. For example, the solvent used may be a strong alkaline potassium hydroxide solution having a pH of 14. The etched metal plate ίο thus includes a stud 22 and a pedestal 24. The studs 22 are portions of the metal plate 1 that are protected by the patterned etch stop layer 16 and are not etched. The studs 22 are adjacent to the base 24 and are integrally formed with the base 24 and project above the base 24 and are laterally surrounded by the recesses 2''. The stud 22 is 200 microns high (equal to the depth of the groove 2〇), the top surface (the circular portion of the surface 12 (Fig. 1A) has a diameter of 1 μm, and the bottom (the circle adjacent to the pedestal 24) The shape of the shape is 11 μm. Thus the stud 22 is in the form of a flat-topped conical cylinder (like a frustum) with a tapered diameter of the side wall that tapers from the base 24 toward its flat circular top. The tapered sidewalls are formed by lateral etching of the chemical etchant into the patterned etch stop layer 16. The top surface is concentric with the circumference of the bottom (as shown in Figure 1E). The susceptor 24 is an unetched portion of the metal plate 1 below the stud 22, and extends laterally from the stud 22 to a plane (such as the left and right side directions) to a thickness of 300 microns (ie, 500- 200). The posts 22 and pedestal 24 can be treated to enhance bonding to epoxy and solder. For example, the studs 22 and the susceptor 24 may be chemically oxidized or microetched to create a rougher surface. 23 201133729 The stud 22 and the pedestal 24 are a single metal (copper) body formed by a reduction method in the drawings. Alternatively, the contact metal stamping metal plate 1Q may be formed by a contact having a groove or a hole to define the portion of the stud 22, so that the stud 22 and the pedestal Μ are formed into a single metal body by press forming. Alternatively, the studs 22 may be formed by an additive method by depositing the studs 22 on the susceptor 24 by techniques such as electroplating, chemical vapor deposition (cvd), and physical vapor deposition (PVD). For example, the solder bumps 22 can be electroformed on the copper pedestal 24; in this case, the posts 22 and the pedestal 24 are joined by a metallurgical interface, adjacent to each other but not formed. Alternatively, the studs 22 may be formed by a semi-addition method, for example, the upper portion of the studs 22 may be deposited above the lower portion of the studs 22. In addition, the stud 22 and the base 24 can also be formed by a semi-additive method. For example, the upper portion of the stud 22 and the pedestal 24 can be deposited above the etched portion of the stud 22 and the base. The studs 22 can also be sintered to the pedestal 24. 2A and 2B are cross-sectional views showing a method of making an adhesive layer in an embodiment of the present invention.帛2 (: and 2D are respectively a top view and a bottom view drawn according to Fig. 2b. Fig. 2A is a cross-sectional view of the adhesive layer 26, wherein the adhesive layer % is a B-stage uncured epoxy film. It is an uncured and unpatterned sheet having a thickness of 125 microns. The adhesive layer 26 can be a variety of dielectric films or films made of various organic or inorganic electrical insulators. For example, the adhesive layer 26 can initially be a film. The resin-type thermosetting epoxy resin is partially cured to a medium stage after being immersed in a reinforcing material. The epoxy resin may be FR-4, but may also be used, for example, a polyfunctional and bismaleimide triazine. (BT) Resin and other epoxy resins. In the specific application of 24 201133729, cyanate esters, polyfluorenes, succinimide, and polytetraethylene (pTFE) are also known as clothing oxygen. The material can be electronic grade glass, also: strong material, such as the strength of the broken glass, low-inducing rate glass, Shi Kejiawei (kevlar aramicn monthly test philosopher, brother Vera fiber. The reinforcing material can also be fabric, Non-woven or ",, directional microfiber. Can be such as Shi Xi (grinding powder The melt is added to the film to 楛弁邋,) the temple filler...*,... the impact resistance and the thermal expansion match...using a commercially available pre-impregnated body' such as Oakley, Wisconsin, USA

Gore & Assoclates 之 speedb〇ard c 膠片即為—例。第2C及2D圖分別為具有開口 28之黏著層26的剖視=、俯視圖及仰視圖。開口 28為一穿透黏著層％之中央61 口。開α 28係以機械方式鑽透該膠片而形成，其直徑為115G微米。開口 28亦可利用其他技術製作，製沖壓等。第3Α至3D圖為剖視圖，說明本發明之—實施例中一種製作導電層之方法，而第3£及3F圖則分別為根據第圖繪製之俯視圖及仰視圖。第3A圖係導電層30之剖視圖。導電層3〇為電性導體。例如，導電層30係一無圖案且厚度為125微米之銅板。第3B圖為一剖視圖，顯示導電層3〇之頂面及底面上分別形成有圖案化之蝕刻阻層32與34。圖示之圖案化之蝕刻阻層32與34係類似於圖案化之蝕刻阻層16之光阻層，其中光阻層（即圖案化之钱刻阻層32)設有可選擇性曝露導電層30頂面之圖案，而光阻層（即圖案化之蝕刻阻層34)亦設有相同圖案’藉以選擇性曝露導電層30之底面。Gore & Assoclates speedb〇ard c film is an example. The 2C and 2D views are respectively a cross-sectional view, a plan view, and a bottom view of the adhesive layer 26 having the opening 28. The opening 28 is a central opening 61 of a penetration adhesive layer. The open α 28 system was formed by mechanically drilling through the film and had a diameter of 115 Gm. The opening 28 can also be made by other techniques, stamping, and the like. 3D to 3D are cross-sectional views showing a method of fabricating a conductive layer in the embodiment of the present invention, and FIGS. 3 and 3F are respectively a plan view and a bottom view according to the first drawing. 3A is a cross-sectional view of the conductive layer 30. The conductive layer 3 is an electrical conductor. For example, the conductive layer 30 is a copper plate having no pattern and having a thickness of 125 μm. Fig. 3B is a cross-sectional view showing patterned etching resist layers 32 and 34 formed on the top and bottom surfaces of the conductive layer 3, respectively. The patterned etch stop layers 32 and 34 are similar to the photoresist layer of the patterned etch stop layer 16, wherein the photoresist layer (ie, the patterned etch resist layer 32) is provided with a selectively exposed conductive layer. The top surface pattern is 30, and the photoresist layer (ie, the patterned etch stop layer 34) is also provided with the same pattern 'to selectively expose the bottom surface of the conductive layer 30.

S 25 201133729 第3C圖顯示具有通孔36之導電層30，其中通孔36之形成方式係依圖案化之蝕刻阻層32與34所定義之圖案蝕刻導電層30。圖示之蝕刻方式為雙面濕式化學蝕刻。例如，可利用一面向圖案化之蝕刻阻層32之頂部噴嘴（圖未示）將化學蝕刻液向下喷灑於導電層3〇及圖案化之蝕刻阻層U ，同時利用一面向圖案化之蝕刻阻層34之底部喷嘴（圖未示 )將化學蝕刻液向上喷灑於導電層3〇及圖案化之蝕刻阻層 34。或者，亦可將結構體浸入化學蝕刻液中。所述化學^ 刻液對鋼具有高度針對性，且可蝕透導電層3〇。因此，通孔36係延伸貫穿導電層3〇。適用之化學姓刻液可為含驗氨之溶液或硝酸與鹽酸之稀釋混合物。換言之，所述化學蝕刻液可為酸性或鹼性。足以形成通孔36而不致使導電層3〇過度曝露於化學蝕刻液之理想蝕刻時間可由試誤法決定。第3D、3E及3F圖分別為具有通孔36之導電層3〇於去除圖案化之㈣阻層32與34後之剖面圖、俯視圖與仰視圖。剝除光阻層（即圖案化之蝕刻阻層32與34)之方式可與剝除光阻層（圖案化之蝕刻阻層16與18)之方式相同。通孔36為一延伸貫穿導電層3〇之中央窗口，直徑為 1150微米。通孔36亦可以機械鑽孔法、沖製法及沖壓法等其他技術形成。較佳者，開口 28(如圖2B)與通孔36具有相同直徑。第4A至4L圖為剖視圖，說明本發明之一實施例中一種製作導熱板之方法，該導熱板包含凸柱22、基座24、黏著層26及導電層30。第4M&4N圖分別為第礼圖之俯視 26 201133729 圖及仰視圖。第4A圖為黏著層26設置於基座24上之剖視圖。黏著層26係下降至基座24上，使凸柱22向上***並貫穿開口 28，而黏著層26則接觸並定位於基座24。較佳者，凸柱 22在***及貫穿開口 28後係對準開口 28且位於開口 μ内之中央位置而不接觸黏著層26。在第4Β圖所示結構中，導電層3〇係設置於黏著層％上。導電層30係下降至黏著層26上，使凸柱22向上*** 通孔36,而導電層30則接觸並定位於黏著層％。較佳者，凸柱22在***（但並未貫穿）通孔36後係對準通孔且位於通孔36内之中央位置而不接觸導電層3〇。是以，缺口 38係位於通孔36内且介於凸柱22與導電層3〇之間。缺口 38側向環繞凸柱22，同時被導電層3〇側向包圍。此外，開口 28與通孔36係相互對齊且具有相同直徑。此時，導電層30係安置於黏著層26上並與之接觸，且延伸於黏著層26上方。凸柱22則延伸通過開口 28，並進入通孔36。凸柱22較導電層30之頂面低50微米，並經由通孔36朝一向上方向外露。黏著層26接觸基座24與導電層30且介於該兩者之間。在此階段，黏著層26仍為乙階（B-stage)未固化環氧樹脂之膠片，而缺口 38中則為空氣〇第4C圖繪示黏著層26經加熱加壓後流入缺口 38中。在此圖中，迫使黏著層26流入缺口 38之方法係對導電層 30施以向下壓力及/或對基座24施以向上壓力，亦即將某 27 S. 201133729 座24與導電層30相對壓合，藉以對黏著層％施壓；在此同時亦對黏著層26加熱。受熱後之黏著層26可在壓力下㈣成形。因此，位於基座24與導電層3〇間之黏著層％欠到擠壓後，改變其原始形狀並向上流入缺口 38。基座24 與導電層30持續朝彼此壓合，直到黏著層％填滿缺口％為止。此外，在基座24與導電層3〇間之間隙縮小後，黏著層26仍舊填滿此一縮小之間隙内。例如，可將基座24及導電層30設置於一壓合機之上、下壓台（圖未示）之間。此外，可將一上擋板及上緩衝紙（圖未示）夾置於導電層3〇與上壓台之間，並將—下播板及下緩衝紙（圖未示）夾置於基座24與下麼台之間。以此構成之疊合體由上到下依次為上壓台、上擋板、上緩衝紙、導電層30、黏著層26、基座24、下緩衝紙、下擋板及下壓台 °此外’可利用m台向上延伸並穿過基座24對位孔（圖未不）之工具接腳（圖未示）將此疊合體定位於下壓台上。而後將上、下壓台加熱並相互推進，藉此對黏著層26 加熱並施壓。擋板可將壓台之熱分散’使熱均勻施加於基座24與導電層30乃至於黏著層％。緩衝紙則將壓台之壓力分散，使壓力均勻施加於基座24與導電層3〇乃至於黏著層26。起初，導電層3〇接觸並壓合於黏著層％。隨著壓台持續動作與持續加熱，基座24與導電層3〇間之黏著層26受到擠壓並開始熔化，因而向上流入缺口％,通過導電層30。例如，未固化環氧樹脂遇熱熔化後，被壓力擠入缺口 38中，但加強材料及填充物仍留在基座24與導電層 28 201133729 3〇之間。黏著層26在通孔36内上升之速度大於凸柱22，真滿缺口 38。黏著層26亦上升至稍高於缺口 38之位置並在壓D停止動作前，溢流至凸柱22頂面以及導電層 &之頂面姊接缺口 38處。若膠片厚度略大於實際所需便可能發生此一情形。如此-來，黏著層26便在凸柱22頂面形成-覆蓋薄層。壓台在觸及凸柱22後停止動作但仍持續對黏著層2 6加熱。 a黏著層26於缺d 38中向上流動之方向如圖中向上粗箭號所示’凸柱22與基座24相對於導電層3Q之向上移動如向上細箭號所示，而導電層30相對於凸柱22與基座24 之向下移動則如向下細箭號所示。第4D圖中之黏著層26已經固化。例如，壓台停止移動後仍持續夾合凸柱22與基座Μ 並供熱，#此將已炫化之乙階（B_stage)環氧樹脂轉換為丙階 (C-stage)固化或硬化之環氧樹月旨。因&，環氧樹脂係以類似習知多層壓合之方式固化。環氧樹脂固化後，壓台分離，以便將結構體從壓台機中取出。固化之黏著層26在凸柱22與導電層30之間以及基座 24與導電層30之間提供牢固之機械性連結。黏著層％可承爻一般操作壓力而不致變形損毀，遇過大壓力時則僅暫時扭曲。再者，黏著層26可吸收凸柱22與導電層30之間以及基座24與導電層3〇之間的熱膨脹不匹配。在此階段，凸柱22與導電層30大致共平面，而黏著層26與導電層30則延伸至一面朝該向上方向之頂面。例S 25 201133729 Figure 3C shows a conductive layer 30 having vias 36 formed in such a manner that the conductive layer 30 is etched in accordance with the pattern defined by the patterned etch stop layers 32 and 34. The illustrated etching method is a two-sided wet chemical etching. For example, a top nozzle (not shown) facing the patterned etch stop layer 32 can be used to spray the chemical etchant down onto the conductive layer 3 and the patterned etch stop layer U while using a pattern-oriented pattern. A bottom nozzle (not shown) of the etch stop layer 34 sprays the chemical etchant up onto the conductive layer 3 and the patterned etch stop layer 34. Alternatively, the structure may be immersed in a chemical etching solution. The chemical etching solution is highly targeted to steel and can etch the conductive layer 3〇. Therefore, the through holes 36 extend through the conductive layer 3A. The applicable chemical surrogate may be a solution containing ammonia or a diluted mixture of nitric acid and hydrochloric acid. In other words, the chemical etchant can be acidic or basic. The ideal etching time sufficient to form the vias 36 without causing the conductive layer 3A to be excessively exposed to the chemical etchant can be determined by trial and error. The 3D, 3E, and 3F are respectively a cross-sectional view, a top view, and a bottom view of the conductive layer 3 having the via holes 36 after the patterned (four) resist layers 32 and 34 are removed. The photoresist layer (i.e., patterned etch stop layers 32 and 34) may be stripped in the same manner as the photoresist layer (patterned etch stop layers 16 and 18). The through hole 36 is a central window extending through the conductive layer 3, and has a diameter of 1,150 μm. The through hole 36 can also be formed by other techniques such as mechanical drilling, punching, and stamping. Preferably, the opening 28 (Fig. 2B) has the same diameter as the through hole 36. 4A through 4L are cross-sectional views illustrating a method of fabricating a thermally conductive plate in accordance with one embodiment of the present invention, the thermally conductive plate including studs 22, a susceptor 24, an adhesive layer 26, and a conductive layer 30. The 4th & 4th views are the top view of the ceremony map 26 201133729 and the bottom view. 4A is a cross-sectional view showing the adhesive layer 26 disposed on the susceptor 24. Adhesive layer 26 is lowered onto susceptor 24 such that stud 22 is inserted upwardly through opening 28 and adhesive layer 26 contacts and is positioned at pedestal 24. Preferably, the stud 22 is aligned with the opening 28 after insertion and penetration through the opening 28 and is located centrally within the opening μ without contacting the adhesive layer 26. In the structure shown in Fig. 4, the conductive layer 3 is provided on the adhesive layer %. The conductive layer 30 is lowered onto the adhesive layer 26 such that the studs 22 are inserted upward into the through holes 36, and the conductive layer 30 contacts and is positioned at the adhesive layer %. Preferably, the stud 22 is aligned with the through hole after being inserted (but not penetrating) through the through hole 36 and located at a central position within the through hole 36 without contacting the conductive layer 3A. Therefore, the notch 38 is located in the through hole 36 and between the stud 22 and the conductive layer 3A. The notch 38 laterally surrounds the stud 22 while being laterally surrounded by the conductive layer 3〇. Further, the opening 28 and the through hole 36 are aligned with each other and have the same diameter. At this time, the conductive layer 30 is disposed on and in contact with the adhesive layer 26 and extends over the adhesive layer 26. The stud 22 extends through the opening 28 and into the through opening 36. The stud 22 is 50 microns lower than the top surface of the conductive layer 30 and is exposed in an upward direction by the through hole 36. Adhesive layer 26 contacts pedestal 24 and conductive layer 30 and is interposed therebetween. At this stage, the adhesive layer 26 is still a film of B-stage uncured epoxy resin, and the air in the notch 38 is 〇. FIG. 4C shows that the adhesive layer 26 is heated and pressurized and flows into the notch 38. In this figure, the method of forcing the adhesive layer 26 to flow into the indentation 38 applies downward pressure to the conductive layer 30 and/or applies upward pressure to the susceptor 24, i.e., a 27 S. 201133729 block 24 is opposite the conductive layer 30. Pressing is used to apply pressure to the adhesive layer; at this time, the adhesive layer 26 is also heated. The heated adhesive layer 26 can be formed under pressure (d). Therefore, the adhesive layer % between the susceptor 24 and the conductive layer 3 欠 is pressed, changes its original shape and flows upward into the notch 38. The susceptor 24 and the conductive layer 30 are continuously pressed toward each other until the adhesive layer % fills the notch %. In addition, after the gap between the susceptor 24 and the conductive layer 3 is reduced, the adhesive layer 26 still fills the reduced gap. For example, the susceptor 24 and the conductive layer 30 can be disposed between a press machine and a lower pressing table (not shown). In addition, an upper baffle plate and an upper buffer paper (not shown) may be interposed between the conductive layer 3 and the upper pressing table, and the lower and lower cushioning sheets (not shown) may be placed on the base. Between seat 24 and the next. The laminated body thus constructed is, in order from top to bottom, an upper pressing table, an upper baffle plate, an upper baffle paper, a conductive layer 30, an adhesive layer 26, a susceptor 24, a lower cushioning paper, a lower baffle plate, and a lower pressing table. The stack can be positioned on the lower press table by means of tool pins (not shown) extending upwardly through the alignment holes of the base 24 (not shown). The upper and lower press tables are then heated and pushed into each other, whereby the adhesive layer 26 is heated and pressed. The baffle can disperse the heat of the press table to uniformly apply heat to the base 24 and the conductive layer 30 or even the adhesive layer. The cushioning paper disperses the pressure of the pressing table so that the pressure is uniformly applied to the susceptor 24 and the conductive layer 3 or even the adhesive layer 26. Initially, the conductive layer 3 is in contact with and is pressed against the adhesive layer %. As the platen continues to operate and continues to heat, the adhesive layer 26 between the susceptor 24 and the conductive layer 3 is squeezed and begins to melt, thereby flowing upward into the notch % through the conductive layer 30. For example, the uncured epoxy resin is melted into the gap 38 after being melted by heat, but the reinforcing material and the filler remain between the susceptor 24 and the conductive layer 28 201133729 3〇. The adhesive layer 26 rises faster in the through hole 36 than the stud 22, and the full gap 38. The adhesive layer 26 also rises slightly above the notch 38 and overflows to the top surface of the stud 22 and the top surface of the conductive layer < This can happen if the film thickness is slightly larger than actually needed. Thus, the adhesive layer 26 is formed on the top surface of the stud 22 to cover the thin layer. The platen stops after touching the stud 22 but continues to heat the adhesive layer 26. a direction in which the adhesive layer 26 flows upward in the absence of d 38 as shown by the upward bold arrow in the figure. The upward movement of the stud 22 and the susceptor 24 with respect to the conductive layer 3Q is as indicated by the upward fine arrow, and the conductive layer 30 The downward movement relative to the stud 22 and the base 24 is as indicated by the downwardly fine arrow. The adhesive layer 26 in Figure 4D has cured. For example, after the platen stops moving, the post 22 and the base cymbal are continuously clamped and heated, # this converts the B-stage epoxy resin to C-stage curing or hardening. Epoxy tree month. Due to & epoxy resins are cured in a similar manner to conventional lamination. After the epoxy resin is cured, the platen is separated to remove the structure from the press. The cured adhesive layer 26 provides a strong mechanical bond between the stud 22 and the conductive layer 30 and between the pedestal 24 and the conductive layer 30. The adhesive layer can be subjected to normal operating pressure without deformation and damage. In case of excessive pressure, it is only temporarily distorted. Furthermore, the adhesive layer 26 can absorb thermal expansion mismatch between the stud 22 and the conductive layer 30 and between the pedestal 24 and the conductive layer 3A. At this stage, the studs 22 are substantially coplanar with the conductive layer 30, and the adhesive layer 26 and the conductive layer 30 extend to a top surface facing the upward direction. example

29 S 201133729 如’基座24與導電層30間之黏著層26厚75微米，較其初始厚度125微米減少50微米；亦即凸柱22在通孔36中升咼50微米，而導電層30則相對於凸柱22下降50微米。凸柱22高度200微米基本上等同於導電層30(125微米）與下方黏者層26(75微米）之結合尚度。此外，凸柱22仍位於開口 28與通孔36内之中央位置並與導電層3〇保持距離，黏著層26則填滿基座24與導電層3〇間之空間並填滿缺口 38。例如，缺口 38(以及凸柱22與導電層3〇間之黏著層 26)在凸柱22頂面處寬75微米（（115〇一1〇〇〇)/2)。黏著層％在缺口 38中延伸跨越導電層3〇。換言之，缺口 38中之黏者層26係沿該向上方向及一向下方向延伸並跨越缺口％外側壁之導電層3G厚度。黏著層26亦包含缺口％上方之薄頂部分’其接觸凸柱22之頂面與導電層3()之頂面並在凸柱22上方延伸微米。在第4E圖所示結射，凸柱22、黏著層％及導電声 30之頂部皆已去除。 θ 凸柱22、黏著層26及導電層％之頂部細研磨方式 :除例如以奴轉鑽石砂輪及蒸餾水處理結構體之頂部。 =磨^砂輪僅磨絲著層26。持續研磨，職著層％層州不必然同時)，因而開始研磨凸：：續研磨後:凸柱〜…導電層3。= =移而變薄。研磨持續至去除所需厚度為止餾水沖洗結構體去除污物。之後以蒸 30 201133729 上述研磨步驟將黏著層26之頂部磨去25微米，將凸柱22之頂部磨去15微米’並將導電層％之頂部磨去μ 微米。厚度減少對凸柱22、黏著層2“戈導電層3〇均益明顯影響。 ‘' 至此，凸柱22、黏著層26及導電層3〇係共同位於基座24上方一面朝該向上方向之平滑拼接側頂面上。第4F圖所示之結構體具有導電層4〇，其係沉積於凸柱 22、黏著層26及導電層30上。導電層40接觸凸柱22、黏著層26及導電層30,並從上方覆蓋此三者。例如，可將結構體浸入一活化劑溶液中因而使黏著層26可與無電鍍銅產生觸媒反應，接著將一第銅層以無電鑛被覆之方式設於凸柱22、黏著層26及導電層30上，然後將一第二銅層以電鍍方式設於該第一銅層上。第一鋼層厚約2微米，第二銅層厚約13微米，故導電層40之總厚度約為15微米。如此一來，導電層之厚度便增為約125微米（110+15)。導電層40係作為凸柱22之一覆蓋層及導電層3〇之一加厚層。為便於說明，凸柱22與導電層40以及導電層30與40均以單層顯示。由於鋼為同質被覆’凸柱22與導電層40間之界線以及導電層30與40 間之界線（均以虛線繪示）可能不易察覺甚至無法察覺。然而 ’黏著層26與導電層40間之界線則清楚可見。第4G圖所示結構體之上、下表面分別設有圖案化之蚀刻阻層42與全面覆蓋之蝕刻阻層44。圖示之圖案化之蝕刻阻層42與全面覆蓋之蝕刻阻層44係分別類似於光阻層（即29 S 201133729 If the adhesive layer 26 between the pedestal 24 and the conductive layer 30 is 75 microns thick, it is reduced by 50 microns from its initial thickness of 125 microns; that is, the stud 22 is raised by 50 microns in the through hole 36, and the conductive layer 30 Then it is lowered by 50 micrometers with respect to the stud 22 . The height of the studs 22 of 200 microns is substantially equivalent to the combination of the conductive layer 30 (125 microns) and the underlying adhesive layer 26 (75 microns). In addition, the stud 22 is still located at the center of the opening 28 and the through hole 36 and is spaced apart from the conductive layer 3, and the adhesive layer 26 fills the space between the pedestal 24 and the conductive layer 3 and fills the gap 38. For example, the notch 38 (and the adhesive layer 26 between the stud 22 and the conductive layer 3) is 75 microns ((115 〇 -1 〇〇〇)/2) wide at the top surface of the stud 22 . The adhesive layer % extends across the conductive layer 3 in the notch 38. In other words, the adhesive layer 26 in the notch 38 extends in the upward direction and in a downward direction and spans the thickness of the conductive layer 3G of the outer sidewall of the notch. The adhesive layer 26 also includes a thin top portion ' above the notch % which contacts the top surface of the stud 22 and the top surface of the conductive layer 3 () and extends a micron over the stud 22 . In the projection shown in Fig. 4E, the top of the stud 22, the adhesive layer %, and the conductive sound 30 are removed. The top of the θ stud 22, the adhesive layer 26, and the conductive layer % is finely ground: except for, for example, the top of the structure is treated with a slave diamond wheel and distilled water. = Grinding the grinding wheel only grinds the layer 26. Continuous grinding, the occupation layer % layer does not necessarily have to be at the same time), and thus begins to grind the convex :: after the grinding: the studs ~ ... the conductive layer 3. = = Move and thin. The grinding is continued until the desired thickness is removed. The distilled water rinses the structure to remove dirt. Thereafter, the top of the adhesive layer 26 was ground to 25 μm by steaming, and the top of the conductive layer 22 was ground to 15 μm. The thickness reduction has a significant effect on the pillars 22 and the adhesive layer 2 "the conductive layer 3". At this point, the pillars 22, the adhesive layer 26 and the conductive layer 3 are co-located above the susceptor 24 toward the upward direction. The structure shown in FIG. 4F has a conductive layer 4 〇 deposited on the stud 22, the adhesive layer 26 and the conductive layer 30. The conductive layer 40 contacts the stud 22 and the adhesive layer 26 And the conductive layer 30, and covering the three from above. For example, the structure can be immersed in an activator solution so that the adhesive layer 26 can react with the electroless copper to generate a catalyst, and then a second copper layer is coated with an electroless ore. The method is disposed on the stud 22, the adhesive layer 26 and the conductive layer 30, and then a second copper layer is electroplated on the first copper layer. The first steel layer is about 2 microns thick and the second copper layer is thick. Approximately 13 microns, so the total thickness of the conductive layer 40 is about 15 microns. As a result, the thickness of the conductive layer is increased to about 125 microns (110 + 15). The conductive layer 40 is used as a cover layer and conductive One of the layers 3 加厚 a thickened layer. For convenience of explanation, the stud 22 and the conductive layer 40 and the conductive layers 30 and 40 are The layer is displayed. Since the steel is a homogeneous coating, the boundary between the pillars 22 and the conductive layer 40 and the boundary between the conductive layers 30 and 40 (both shown by dashed lines) may be difficult to detect or even undetectable. However, the adhesive layer 26 and the conductive layer The boundaries between the 40 lines are clearly visible. The upper and lower surfaces of the structure shown in Fig. 4G are respectively provided with a patterned etching resist layer 42 and a comprehensively covered etching resist layer 44. The patterned etching resist layer 42 is shown and The fully covered etch stop layer 44 is similar to the photoresist layer (ie,

S 31 201133729 圖案化之蝕刻阻層16與18)之光阻層。光阻層（即圖案化之蝕刻阻層42)設有可選擇性曝露導電層4〇之圖案，而光阻層（即全面覆蓋之蝕刻阻層44)則無圖案且覆蓋基座以。在第4Η圖所示之結構體中，導電層3〇與4〇已經由蝕刻去除其選定部分以形成圖案化之蝕刻阻層42所定義之圖案。所述蝕刻與施用於金屬板1〇之正面濕式化學蝕刻相仿。化學蝕刻液蝕刻穿透導電層3〇及4〇以曝露黏著層％，因而將原本無圖案之導電層30及4〇轉換為圖案層，至於基座24則未形成圖案。在第41圖中，結構體上之圖案化之蝕刻阻層42與全面覆蓋之#刻阻層44均已去除。去除光阻層（即圖案化之钱刻阻層42及全面覆蓋之敍刻阻層44)之方式可與去除光阻層（即圖案化之❹]阻層16及全面覆蓋之㈣阻層18)之方式相同。钱刻後之導電層30及40包含焊墊46、路由線48與端子50,而餘刻後之導電層4〇則包含蓋體^焊塾牝、路由線料與端子50係導電層30與4〇受圖案化之㈣阻層 42(如圖4G)保護而未被㈣之部分，蓋體52則為導電層仙受圖案化之#刻阻層42(如圖4G)保護而未被钱刻之部分。如此一來’導電層30與40便成為圖案層，其包含焊塾Μ 、路由線48與端子50但不包含蓋體52。此外路由線μ 為-銅導線，其接觸黏著層26並延伸於其上方，同時鄰接且電性連結焊墊46與端子50。焊墊46、路由線48及端子％共同形成導線54。路由 32 201133729 線48係焊塾46與端子5〇間之-導電路徑。導線54提供從焊塾46 $砂2 味千50之水平（側向）路由。導線54並不限於構里舉例而言，上述導電路徑尚可包含被動元件，例如δ又置於其他焊塾上之電阻與電容。政熱座56包含凸柱22、基座24及蓋體52。凸柱22 與基座24係—體成形。蓋體52位於凸柱22之頂部上方，鄰接凸柱22之頂部’同時從上方覆蓋凸柱22之頂部，並由^柱22之頂部往側向延伸。設置蓋體52後，凸柱22係坐落於蓋體52圓周内之中央區域。蓋體52亦從上方接觸 ^蓋其下方黏著層26之—部分黏著層％之該部分係與凸,22共平面’鄰接凸柱22,同時側向包圍凸柱22。柱2 '座56實質上為—倒Τ形之散熱塊，其包含柱部（凸 )翼。卩（基座24自柱部侧向延伸之部分）以及一導埶墊 (蓋體52)。 … 第4J圖之結構體在黏著層％ '導電層4〇及蓋體％上設有防焊綠漆58。防焊綠漆58為—電性絕緣層，其可依吾人之選擇形成圖案以曝露料46、端子5〇與蓋體52，並從上方覆蓋黏 L曰6之外路部分及路由線48。防焊綠漆58在焊墊46與端子〇上方之厚度為25微米，且防焊綠漆Μ於黏著層％上方延伸150微米（125+25)。防焊綠漆58起初為塗佈於結構體上之-光顯像型液態 Η曰。之後再於防焊綠漆58上形成圖案其作法係令光線選擇性透過光罩(圖未示)’使受光之部分防坪綠漆％變為 33 201133729 不可溶解，然後利用__顯影溶部分可溶解之。^漆58,最後再進行硬烤，以上步驟乃f知技藝體52上=所示結構體之基^24、焊塾46、端子50與蓋體52上5又有被覆接點60。破覆接點60為-多層金屬鍍層，其從下方接觸及覆蓋 :座24,並從上方接觸焊塾46、端子5q與蓋體u同時覆盖其外露之部分。例如鎳層係以無電链被覆之方式气於基座24、焊塾46、端子50與蓋體52上，而後再將一金層以無電錢被覆之方式設於該錦層上’其中内部錄層厚約3 微米，表面金層厚約0.5微米，故被覆接點⑹之厚度 3 · 5微米。 ' 以被覆接點60作為基座24、焊墊46、端子5〇與蓋體 52之表面處理具有幾項優點。内部錄層提供主要之機械性與電性連結及/或熱連結’而表面金層則提供—可濕性表面以利焊料迴焊《被覆接點60亦保護基座24、焊塾46、子50與蓋體52不受腐#。被覆接點6〇可包含各種金屬Z 符合外部連結媒介之需要。例如，一被覆在鎳層上之銀層可搭配焊錫或打線。 3 為便於說明，設有被覆接點60之基座24、焊塾、端子50與蓋體52均以單-層體方式顯示。被覆接點6〇與基座24、焊墊46、端子50及蓋體52間之界線（圖未示）為銅/錄介面。至此完成導熱板62(如圖4L)之製作。 34 201133729 第4L、4M及4N圖分別為導熱板62之剖視圖、俯視圖及仰視圖，圖中導熱板62之邊緣已沿切割線而與支撐架及/或同批生產之相鄰導熱板分離。導熱板62包含黏著層26、導線54、散熱座％及防焊綠漆58。導線54包含焊墊46、路由線48及端子50。散熱座56包含凸柱22、基座24及蓋體52。凸柱22延伸貫穿開口 28(如圖4B)後，仍位於開口 28 内之中央位置，並與黏著層26位於焊墊40底面上方之一相鄰部分共平面。凸柱22保持平頂錐柱形，其漸縮側壁使其直徑自基座24朝鄰接蓋體52之平坦圓頂向上遞減。基座24從下方覆蓋凸柱22、黏著層26、蓋體52、導線54及防焊綠漆58，並延伸至導熱板62之外圍邊緣。蓋體52位於凸柱22上方，與之鄰接並為熱連結，蓋體52同時從上方覆蓋凸柱22之頂部，並自凸柱22頂部沿側向延伸。蓋體52亦從上方接觸並覆蓋黏著層26之一部分，黏著層26 之該部分係鄰接凸柱22，與凸柱22共平面，且側向環繞凸柱22。蓋體52亦與焊墊46及端子50於黏著層26上方共平面。黏著層26係設置於基座24上並於其上方延伸。黏著層26在缺口 38内係延伸於凸柱22與焊墊46之間；在缺口 38外則接觸且介於基座24與導線54之間，並填滿基座 24與導線54間之空間。黏著層26係從凸柱22側向延伸並越過知子50’且被端子5〇重疊。此外，黏著層26從上方覆蓋基座24位於凸柱22周緣外之一部分，並從下方覆蓋 35 201133729 導線54，同時沿側面方向接觸、覆蓋且環繞凸柱22。黏著層26被限制在導線54與散熱座56間之空間内，並填滿此空間之絕大部分。此時黏著層26已固化。導線54(以及焊墊46、路由線48與端子50)係設置於黏著層26上，接觸並重疊於黏著層％，且延伸於黏著層％上方。凸柱22基座24及蓋體52均與導線54保持距離。因此，導線54與散熱座56係機械性連接且彼此電性隔離。同批製作之導熱板62經裁切後，其基座24、黏著層 26及防焊綠漆58均延伸至裁切而成之垂直邊緣。焊墊46係一專為LED封裝體或半導體晶片等半導體元件！^身訂做之電性介面，該半導體元件將於後續製程中設 ;蓋體52上。端子5〇係一專為下一層組體（例如來自一印刷電路板之可焊接線）量身訂做之電性介面。蓋體52係-專為該半導體元件量身訂做之熱介面。基座24係-專為下一層組體（例如1子設備之散熱裝置）量身訂做之熱介面。此外^蓋體52係經由凸柱22而熱連結至基座％。焊墊46與端子5G在側向上彼此錯位且均外露於導熱板62之頂面’藉此提供該半導體元件與下—層組體間之水平輸入/輸出路由。 θ 6端子50與蓋體52三者之頂面於黏著層26上方共平面。為便於說明’導線54於剖視圖中係繪示為—連續電路跡線。然而，導線54通㈣時提供χ#γ方向之水平訊號 36 201133729 =焊墊46與端子5〇彼此在χ#γ方向形成側向錯位，而路由線48則構成乂與丫方向之路徑。散熱座56可將隨後設置於蓋冑52上之半導體元件所產生之熱能擴散至散熱座56所連接之下—層組體。該半導體元件產生之熱能流人蓋體52,自蓋體52進入凸柱22, 並經由凸柱22進人基座24。熱能從基座24沿該向下方向散出，例如擴散至一下方散熱裝置。導熱板62之凸柱22與路由線48均未外露其中凸柱 22被蓋體52覆蓋，路由線48係由防焊綠漆％覆蓋，至於黏著層26之頂面則同時由蓋體52及防焊綠漆兄覆篕。為便於說明，第4Μ圖以虛線緣示凸柱22、黏著層％與路由線48。導熱板62亦包含其他導線54,該些導線54基本上係由焊墊46、路由線48與端子5〇所構成。為便於說明，在此僅說明並繪示單一導線Μ。於導線54中，焊墊46及端子50通常具有相同之形狀及尺寸，而路由線48則通常採用不同之路由構型。例如，部分導線54設有間距’彼此分離，且為電性隔離，而部分導線54則彼此交錯或導向同一焊塾46、路由線48或端子50且彼此電性連結。同樣地，部分焊塾46可用以接收獨立訊號，而部分焊墊46則共用一 sfL號、電源或接地端。導熱板62可適用於具有藍、綠及紅色LED晶片之 LED封裝體’其中各LED晶片包含一陽極與一陰極，且各 LED封裝體包含對應之陽極端子與陰極端子。在此例中， 37 201133729 _ 62可包含六個焊墊46與四個端子％，以便將每一陽極從-獨立料46導向—獨立料％，並將每一陰極從一獨立焊墊46導向一共同之接地端子5〇。衣在各製造階段均可利用-簡易清潔步驟去除外露金屬 ^之氧化物與殘留物，例如可對本案結構體施行一短暫之氧電漿清潔步驟。或者’可利用-祕酸鉀溶液對本案結構體進行-短暫之濕式化學清潔步驟。同樣地亦可利用蒸餾水淋洗本案結構體以去除污物。此清潔步驟可清潔所需表面而不對結構體造成明顯之影響或破壞。本案之優點在於導線54形成後不需從中分離或分割出匯流點或相關電路系統。匯流點可於形成焊墊46、路由線 48、端子5〇與蓋體52之濕式化學蝕刻步驟中分離。導熱板62可包含鑽透或切通基座24、黏著層26與防焊綠漆58而形成之對位孔（圖未示）。如此一來，當導熱板 62需於後續製程中設置於一下方載體時，便可將工具接腳 ***對位孔中，藉以將導熱板62置於定位。導熱板62可略去蓋體52。欲達此一目的，可調整圖案化之姓刻阻層42(如圖4H)，使整個通孔36上方之導電声 4〇均曝露於用以形成焊墊46、路由線48與端子50之化學银刻液中。略去蓋體52之另一作法係不設導電層4〇(如圖 4J)。導熱板62可容納多個半導體元件而非僅容納單一半導體元件。欲達此一目的’可調整圖案化之蝕刻阻層16(如圖 1C)以定義更多凸柱22，調整黏著層26以包含更多開口 28 38 201133729 ，調整導電層30以包含更多通孔36(如圖4B)，調整圖案化之蝕刻阻層42(如圖4H)以定義更多焊墊私、路由線心、端子M)與蓋體52,並調整防焊綠漆58以包含更多開口。端子50以外之元件可改變側向位置以便為四個半導體元件提供-加陣列。此外’部分但非所有元件之剖面形狀及高低（即側面形狀）亦可有所調整。例如，焊墊46、端子5〇與蓋體52可保持相同之侧面形狀，而路由線48則具有不同之路由構型。第5A、5B及5C圖分別為本發明一實施例中一半導體晶片組體之剖視圖、俯視圖及仰視圖，該半導體晶片組體包含一導熱板及一具有背面接點之LED封裝體。半導體晶片組體1 〇〇包含導熱板62、LED封裝體i 〇2 及第一、第二焊錫104與1〇6。LED封裝體1〇2包含LED 晶片108、基座11〇、打線112、電接點114、熱接點116 與透明封裝材料118。LED晶片1〇8之一電極（圖未示）係經由打線112電性連結至基座11〇中之一導電孔（圖未示），藉以將LED晶片108電性連結至電接點U4。lEd晶片1〇8 係透過一固晶材料（圖未示）設置於基座110上，使LED晶片108熱連結且機械性黏附於基座11〇，藉此將LED晶片 108熱連結至熱接點116。基座11〇為一具有低導電性及高導熱性之陶瓷塊，接點114及116係被覆於基座11〇背部並自基座110背部向下突伸。S 31 201133729 Patterned etch stop layers 16 and 18) photoresist layer. The photoresist layer (i.e., the patterned etch stop layer 42) is provided with a pattern that selectively exposes the conductive layer 4'', and the photoresist layer (i.e., the etch stop layer 44 that is entirely covered) is unpatterned and covers the pedestal. In the structure shown in Fig. 4, the conductive layers 3 and 4 have been etched away from their selected portions to form a pattern defined by the patterned etch stop layer 42. The etching is similar to the front wet chemical etching applied to the metal plate. The chemical etching solution etches through the conductive layers 3 and 4 to expose the adhesive layer %, thereby converting the originally unpatterned conductive layers 30 and 4 to the pattern layer, and the susceptor 24 is not patterned. In Fig. 41, the patterned etch stop layer 42 on the structure and the fully covered #etch resist layer 44 have been removed. The photoresist layer (ie, the patterned etched layer 42 and the overlying resist layer 44) may be removed by removing the photoresist layer (ie, the patterned germanium) resist layer 16 and the fully covered (four) resist layer 18. The way is the same. After the etching, the conductive layers 30 and 40 include the bonding pad 46, the routing line 48 and the terminal 50, and the remaining conductive layer 4〇 includes the cover body, the routing wire and the terminal 50-based conductive layer 30 and 4〇 The patterned (4) resistive layer 42 (as shown in Fig. 4G) is protected from the part (4), and the cover 52 is protected by the patterned resistive layer 42 (Fig. 4G). Engraved part. As a result, the conductive layers 30 and 40 become patterned layers comprising solder bumps, routing lines 48 and terminals 50 but no cover 52. In addition, the routing line μ is a copper wire that contacts and extends over the adhesive layer 26 while abutting and electrically bonding the pad 46 to the terminal 50. The pad 46, routing line 48, and terminal % together form a wire 54. Routing 32 201133729 Line 48 is the conductive path between the pad 46 and the terminal 5〇. Wire 54 provides a horizontal (lateral) route from weld 46 $ sand 2 to a thousand. The wire 54 is not limited to the structure. For example, the conductive path may further include passive components such as δ and resistors and capacitors placed on other pads. The hot seat 56 includes a stud 22, a base 24, and a cover 52. The stud 22 is integrally formed with the base 24. The cover 52 is located above the top of the stud 22 adjacent the top of the stud 22 while covering the top of the stud 22 from above and extending laterally from the top of the post 22. After the cover 52 is provided, the stud 22 is seated in a central region within the circumference of the cover 52. The cover 52 also contacts the portion of the adhesive layer 26 from above which is attached to the adhesive layer 26, and the portion of the adhesive layer is coplanar with the projections 22, adjacent to the projections 22, while laterally surrounding the projections 22. The post 2 'seat 56 is essentially an inverted heat sink block that includes a post (convex) wing.卩 (the portion of the pedestal 24 extending laterally from the column portion) and a guide pad (cover 52). The structure of Fig. 4J is provided with a solder resist green paint 58 on the adhesive layer % 'conductive layer 4' and the cover %. The solder resist green paint 58 is an electrically insulating layer which can be patterned to expose the material 46, the terminal 5 turns and the cover 52, and covers the outer portion of the adhesive L6 and the routing line 48 from above. The solder resist green paint 58 has a thickness of 25 microns above the pad 46 and the terminal turns, and the solder resist green paint extends 150 microns (125 + 25) above the adhesive layer %. The solder resist green paint 58 is initially a light-developing liquid helium that is applied to the structure. Then, a pattern is formed on the solder resist green paint 58. The method is to selectively pass the light through the mask (not shown) to make the portion of the light-receiving portion of the green paint lacquered to be 33 201133729 insoluble, and then use the __ developing solution portion. Soluble. The lacquer 58 is finally hard baked. The above steps are the base 24 of the structure shown in Fig. 52, the solder bump 46, and the terminal 50 and the cover 52 have covered contacts 60. The broken contact 60 is a multi-layer metal plating which contacts and covers the seat 24 from below and contacts the solder tab 46, the terminal 5q and the cover u from above to cover the exposed portion thereof. For example, the nickel layer is gas-freely coated on the susceptor 24, the solder bumps 46, the terminals 50 and the cover 52, and then a gold layer is placed on the brocade in a manner free of electricity. The layer thickness is about 3 microns and the surface gold layer is about 0.5 microns thick, so the thickness of the covered joint (6) is 3 · 5 microns. The surface treatment with the covered contacts 60 as the susceptor 24, the pads 46, the terminals 5, and the cover 52 has several advantages. The inner recording layer provides the main mechanical and electrical connection and/or thermal connection ' while the surface gold layer provides the wettable surface for solder reflow. The covered contact 60 also protects the pedestal 24, the solder 塾 46, and the sub-layer. 50 and the cover 52 are not rotted #. The covered joints 6〇 can contain various metals Z in accordance with the needs of externally connected media. For example, a silver layer coated on a nickel layer can be soldered or wired. 3 For convenience of explanation, the susceptor 24 provided with the covered contacts 60, the solder bumps, the terminals 50 and the cover 52 are all displayed in a single-layer manner. The boundary between the covered contact 6 〇 and the susceptor 24, the pad 46, the terminal 50 and the cover 52 (not shown) is a copper/recording interface. The fabrication of the heat conducting plate 62 (Fig. 4L) is thus completed. 34 201133729 The 4L, 4M and 4N drawings are respectively a cross-sectional view, a top view and a bottom view of the heat conducting plate 62, in which the edge of the heat conducting plate 62 has been separated along the cutting line from the support frame and/or the adjacent heat conducting plate produced in the same batch. The heat conducting plate 62 includes an adhesive layer 26, a wire 54, a heat sink %, and a solder resist green paint 58. Wire 54 includes pad 46, routing line 48, and terminal 50. The heat sink 56 includes a stud 22, a base 24, and a cover 52. The post 22 extends through the opening 28 (Fig. 4B) and remains centrally within the opening 28 and is coplanar with an adjacent portion of the adhesive layer 26 above the bottom surface of the pad 40. The stud 22 maintains a flat-topped tapered cylindrical shape with tapered side walls that decrease in diameter from the base 24 toward the flattened dome adjacent the cover 52. The base 24 covers the stud 22, the adhesive layer 26, the cover 52, the wire 54 and the solder resist green paint 58 from below and extends to the peripheral edge of the heat conducting plate 62. The cover 52 is located above the stud 22 and is adjacent to and thermally coupled. The cover 52 simultaneously covers the top of the stud 22 from above and extends laterally from the top of the stud 22 . The cover 52 also contacts and covers a portion of the adhesive layer 26 from above, the portion of the adhesive layer 26 abutting the stud 22, coplanar with the stud 22, and laterally surrounding the post 22. The cover 52 is also coplanar with the pads 46 and the terminals 50 above the adhesive layer 26. The adhesive layer 26 is disposed on the base 24 and extends above it. The adhesive layer 26 extends between the studs 22 and the pads 46 in the notches 38; it contacts between the pedestals 24 and the wires 54 outside the notches 38, and fills the space between the pedestals 24 and the wires 54. . The adhesive layer 26 extends laterally from the stud 22 and over the zither 50' and is overlapped by the terminal 5'. Further, the adhesive layer 26 covers the base 24 from above with a portion outside the periphery of the stud 22 and covers the 35 201133729 wire 54 from below while contacting, covering and surrounding the stud 22 in the lateral direction. Adhesive layer 26 is confined within the space between conductor 54 and heat sink 56 and fills most of this space. At this time, the adhesive layer 26 has solidified. Lead 54 (and pad 46, routing line 48 and terminal 50) are disposed on adhesive layer 26, contact and overlap the adhesive layer %, and extend over the adhesive layer %. Both the base 24 and the cover 52 of the stud 22 are spaced from the wire 54. Therefore, the wires 54 are mechanically coupled to the heat sink 56 and electrically isolated from each other. After the same batch of thermally conductive plates 62 have been cut, the base 24, the adhesive layer 26 and the solder resist green paint 58 extend to the cut vertical edges. The pad 46 is a semiconductor element such as an LED package or a semiconductor chip! ^ The customized electrical interface, the semiconductor component will be set in the subsequent process; the cover 52. Terminal 5 is a tailor-made electrical interface for the next layer of components (e.g., solderable wires from a printed circuit board). The cover 52 is a thermal interface tailored specifically for the semiconductor component. The pedestal 24 is a hot interface tailored to the next set of components (such as the heat sink of a sub-device). In addition, the cover body 52 is thermally coupled to the susceptor % via the studs 22 . The pad 46 and the terminal 5G are laterally offset from each other and are exposed on the top surface of the heat conducting plate 62, thereby providing a horizontal input/output routing between the semiconductor component and the lower-layer assembly. The top surface of the θ 6 terminal 50 and the lid body 52 are coplanar above the adhesive layer 26. For ease of illustration, the conductor 54 is shown in cross-section as a continuous circuit trace. However, when the wire 54 is turned on (4), the horizontal signal of the γ#γ direction is provided. 36 201133729 = The pad 46 and the terminal 5 形成 form a lateral misalignment in the χ #γ direction, and the routing line 48 constitutes a path in the 乂 and 丫 directions. The heat sink 56 diffuses the thermal energy generated by the semiconductor component subsequently disposed on the cover 52 to the submount of the heat sink 56. The heat energy generated by the semiconductor component flows into the body 22 from the cover 52 and enters the base 24 via the boss 22. Thermal energy is dissipated from the susceptor 24 in the downward direction, for example, to a lower heat sink. The pillars 22 and the routing wires 48 of the heat conducting plate 62 are not exposed. The pillars 22 are covered by the cover 52, and the routing line 48 is covered by the solder resist green paint. The top surface of the adhesive layer 26 is simultaneously covered by the cover 52 and Anti-weld green paint brothers cover. For convenience of explanation, the fourth figure shows the stud 22, the adhesive layer %, and the routing line 48 with a dotted line. Thermally conductive plate 62 also includes other conductors 54, which are substantially comprised of pads 46, routing wires 48 and terminals 5A. For ease of explanation, only a single wire turns are illustrated and illustrated herein. In wire 54, pad 46 and terminal 50 are generally of the same shape and size, while routing line 48 is typically of a different routing configuration. For example, a portion of the conductors 54 are spaced apart from each other and electrically isolated, and a portion of the conductors 54 are staggered or directed to the same pad 46, routing line 48 or terminal 50 and electrically coupled to one another. Similarly, a portion of the pad 46 can be used to receive an independent signal, while a portion of the pad 46 shares a sfL number, power supply or ground. The heat conducting plate 62 can be applied to an LED package having blue, green and red LED chips, wherein each LED chip comprises an anode and a cathode, and each LED package comprises a corresponding anode terminal and cathode terminal. In this example, 37 201133729 _ 62 may include six pads 46 and four terminal % to direct each anode from the individual material 46 - separate % and direct each cathode from a separate pad 46 A common ground terminal 5〇. The fabric can be removed at various stages of manufacture - a simple cleaning step to remove oxides and residues from the exposed metal. For example, a short oxygen plasma cleaning step can be applied to the structure. Alternatively, the structure of the present invention may be subjected to a short wet chemical cleaning step. Similarly, the structure can be rinsed with distilled water to remove dirt. This cleaning step cleans the surface as needed without causing significant damage or damage to the structure. The advantage of this case is that there is no need to separate or separate the confluence points or associated circuitry from the wires 54 after they are formed. The confluence point can be separated during the wet chemical etching step of forming the pad 46, the routing line 48, the terminal 5, and the cover 52. The heat conducting plate 62 may include alignment holes (not shown) formed by drilling or cutting through the base 24, the adhesive layer 26 and the solder resist green paint 58. In this way, when the heat conducting plate 62 needs to be disposed on a lower carrier in a subsequent process, the tool pin can be inserted into the alignment hole to position the heat conducting plate 62. The cover 52 can be omitted from the heat conducting plate 62. To achieve this purpose, the patterned surname resist layer 42 (as shown in FIG. 4H) can be adjusted to expose the conductive traces 4 above the entire via 36 to the pads 46, the routing lines 48 and the terminals 50. In chemical silver engraving. Another method of omitting the cover 52 is to provide no conductive layer 4 (Fig. 4J). The heat conducting plate 62 can accommodate a plurality of semiconductor elements instead of only a single half of the conductor elements. To achieve this goal, the patterned etch stop layer 16 (as shown in FIG. 1C) can be modified to define more bumps 22, the adhesive layer 26 can be adjusted to include more openings 28 38 201133729, and the conductive layer 30 can be adjusted to include more passes. Hole 36 (Fig. 4B), the patterned etch stop layer 42 (Fig. 4H) is adjusted to define more pad private, routing core, terminal M) and cover 52, and adjust the solder resist green paint 58 to include More openings. Elements other than terminal 50 can change the lateral position to provide an array of four semiconductor components. In addition, the cross-sectional shape and height (ie, side shape) of some but not all components may be adjusted. For example, pad 46, terminal 5〇 and cover 52 can maintain the same side shape, while routing line 48 has a different routing configuration. 5A, 5B, and 5C are respectively a cross-sectional view, a top view, and a bottom view of a semiconductor wafer package in accordance with an embodiment of the present invention, the semiconductor wafer package including a heat conductive plate and an LED package having a back contact. The semiconductor wafer package 1 includes a heat conductive plate 62, an LED package i 〇 2, and first and second solders 104 and 1 〇6. The LED package 1〇2 includes an LED wafer 108, a pedestal 11 〇, a wire 112, an electrical contact 114, a thermal contact 116, and a transparent encapsulation material 118. One of the LED chips 1 〇 8 (not shown) is electrically connected to one of the pedestals 11 导电 via a wire 112 (not shown) to electrically connect the LED chip 108 to the electrical contact U4. The LED chip 108 is disposed on the susceptor 110 through a die bonding material (not shown), and the LED chip 108 is thermally bonded and mechanically adhered to the pedestal 11 〇, thereby thermally bonding the LED chip 108 to the thermal connection. Point 116. The susceptor 11 is a ceramic block having low conductivity and high thermal conductivity, and the contacts 114 and 116 are covered on the back of the pedestal 11 and protrude downward from the back of the pedestal 110.

LED封裝體1〇2係設置於導線54與散熱座56上，電性連結至導線54，並熱連結至散熱座56。詳而言之，LED 201133729 封裝體102係設置於焊墊46與蓋體52上，重疊於凸柱22 ’且經由第一焊錫104電性連結至導線54，並經由第二焊錫106熱連結至散熱座56。例如’第一焊錫1〇4接觸且係位於焊墊46與電接點114之間，同時電性連結且機械性黏合焊墊46與電接點114,藉此將LED晶片1〇8電性連結至端子50。同樣地，第二焊錫106接觸且係位於蓋體52與熱接點116之間，同時熱連結且機械性黏合蓋體52與熱接點 116 ’藉此將LED晶片108熱連結至基座24。焊墊46上設有錄/金之被覆金屬接塾以利與第一焊錫1 〇4穩固結合，且焊墊46之形狀及尺寸均配合電接點114，藉此改善自導線 54至LED封裝體1〇2之訊號傳導。同樣地，蓋體52上設有鎳/金之被覆金屬接墊以利與第二焊錫1〇6穩固結合，且蓋體52之形狀及尺寸均配合熱接點116，藉此改善自封裝體102至散熱座56之熱傳遞。至於凸柱22之形狀及尺寸則並未且亦不需配合熱接點丨丨6而設計。透明封裝材料118為一固態電性絕緣保護性塑膠包覆體其可為晶片108及打線112提供諸如抗潮溼及防微粒等環境保護°晶片1()8與打線112係、埋設於透明封裝材料118 中。 ^欲製造半導體晶片組體100,可將一焊料沉積於焊墊及蓋體52上，然後將接點114與116分別放置於焊墊％及盍體52上方之焊料上，繼而使該焊料迴焊以形成接著之第第一焊錫104及106。例如，先以網版印刷之方式將錫膏選擇性印刷於焊墊 40 201133729 46及蓋體52上，而後利用—抓取頭與—自動化圖案辨識系統以步進重複之方式將LED封裝體1〇2放置於導熱板以上 *广焊機之抓取頭將接點114及116分別放置於焊墊及蓋體52上方之錫膏上。接著加熱錫膏’使其以相對較低之溫度(如190。〇迴焊’然後移除熱源，#待錫膏冷卻並固化以形成硬化的第一、第二焊錫刚及雇。或者，可於焊墊 46與蓋體52上放置錫多求，然後將接點ιΐ4及μ分別放置於焊塾46與蓋體52上方之錫球上，接著加熱錫球使其迴焊以形成接著之第一、第二焊錫1〇4及1〇6。焊料起初可經由被覆或印刷或佈置技術沉積於導熱板 62或LED封裝體1〇2上，使其位於導熱板62與led封裝體102之間，並使其迴焊。焊料亦可置於端子％上以供下 1組體使用。此外’尚可利用-導電黏著劑（例如填充銀之環氧樹脂）或其他連結媒介取代焊料，且焊墊46、端子與蓋體52上之連接媒介不必相同。 »亥半導體晶片組體1 〇〇為—第二級單晶模組。第6A、6B與6C圖分別為本發明一實施例中一半導體晶片組體之剖視圖、俯視圖及仰視圖，其中該半導體晶片組體包含一導熱板及一具有側引腳之LED封裴體。於此實施例中，！亥LED封裝體具有側引腳而不具有背面接點。為求簡明，凡組體100之相關說明適用於此實施例者均併人此處，㈣之說明不予重覆。同樣地本實施例組體之S件與組冑_之元件相仿者，均採對應之參考標號，但其編碼之基數由100改為2〇〇。例如，led晶片The LED package 1〇2 is disposed on the wire 54 and the heat sink 56, electrically connected to the wire 54 and thermally coupled to the heat sink 56. In detail, the LED 201133729 package 102 is disposed on the pad 46 and the cover 52 , overlaps the stud 22 ′ and is electrically connected to the wire 54 via the first solder 104 , and is thermally coupled to the second solder 106 via the second solder 106 . Heat sink 56. For example, the first solder 1〇4 contacts and is located between the bonding pad 46 and the electrical contact 114, and electrically and mechanically bonds the bonding pad 46 and the electrical contact 114, thereby electrically connecting the LED chip 1〇8. Connected to terminal 50. Similarly, the second solder 106 contacts and is located between the cover 52 and the thermal contact 116 while thermally bonding and mechanically bonding the cover 52 and the thermal contact 116 ' thereby thermally bonding the LED wafer 108 to the pedestal 24 . The pad 46 is provided with a gold-plated metal bond to facilitate solid bonding with the first solder 1 〇 4, and the shape and size of the pad 46 are matched with the electrical contacts 114, thereby improving the self-conducting wire 54 to the LED package. The signal transmission of the body 1〇2. Similarly, the cover body 52 is provided with a nickel/gold coated metal pad for stable bonding with the second solder 1〇6, and the shape and size of the cover 52 are matched with the thermal contact 116, thereby improving the self-package body. The heat transfer from 102 to the heat sink 56. As for the shape and size of the stud 22, it is not and does not need to be designed with the hot joint 丨丨6. The transparent encapsulating material 118 is a solid electrically insulating protective plastic covering body, which can provide environmental protection such as moisture resistance and anti-particles for the wafer 108 and the wire 112. The wafer 1 (8) and the wire 112 are embedded in the transparent packaging material. 118 in. To fabricate the semiconductor wafer package 100, a solder can be deposited on the pad and the cover 52, and the contacts 114 and 116 are placed on the solder on the pad % and the body 52, respectively, and then the solder is returned. Welding is performed to form the first first solders 104 and 106. For example, the solder paste is selectively printed on the pad 40 201133729 46 and the cover 52 by screen printing, and then the LED package 1 is stepped and repeated by using the grab head and the automated pattern recognition system. 〇2 is placed above the heat conducting plate. * The picking head of the wide welding machine places the contacts 114 and 116 on the solder paste above the soldering pad and the cover 52, respectively. Then heat the solder paste 'to make it at a relatively low temperature (such as 190. 〇 reflow) and then remove the heat source, #wait the solder paste to cool and solidify to form the hardened first and second solder just hired. Place tin on the pad 46 and the cover 52, and then place the contacts ι 4 and μ on the solder balls above the solder 46 and the cover 52, and then heat the solder balls to reflow to form the next First, the second solder 1〇4 and 1〇6. The solder may initially be deposited on the heat conducting plate 62 or the LED package 1〇2 via coating or printing or placement techniques, between the heat conducting plate 62 and the LED package 102. And solder reflow. Solder can also be placed on the terminal % for use in the next group. In addition, solder can be replaced with a conductive adhesive (such as silver-filled epoxy) or other bonding medium, and soldered. The connection medium on the pad 46 and the terminal and the cover 52 need not be the same. The semiconductor semiconductor package 1 is a second-order single crystal module. The sixth embodiment, the sixth embodiment, the sixth embodiment, the sixth embodiment, the sixth embodiment, the sixth embodiment, the sixth embodiment, the sixth embodiment, the sixth embodiment a cross-sectional view, a top view, and a bottom view of a semiconductor wafer package, wherein the semiconductor wafer The assembly includes a heat conducting plate and an LED package having side pins. In this embodiment, the LED package has side pins and no back contacts. For simplicity, the group 100 is related. The description applies to this embodiment, and the description of (4) is not repeated. Similarly, the S piece of the embodiment is similar to the component of the group _, and the corresponding reference number is used, but the code is encoded. The base number is changed from 100 to 2. For example, led chip

41 S 201133729 208對應於LED晶片108，而基座210則對應於基座11〇，以此類推。41 S 201133729 208 corresponds to LED chip 108, while pedestal 210 corresponds to pedestal 11 〇 , and so on.

半導體晶片組體200包含導熱板62、LED封裂體202 與第一、第一焊錫204及206。LED封裝體202包含LED 晶片208、基座210、打線212、引腳214與透明封裝材料 218。LED晶片208係經由打線212電性連結至引腳214。基座210背面包含熱接觸表面216，此外，基座21〇係窄於基座110且與熱接觸表面216具有相同之側向尺寸及形狀。 LED晶片208係經由一固晶材料（圓未示）設置於於基座21〇上，使LED晶片208熱連結且機械性黏附於基座21〇，藉此將LED晶片208熱連結至熱接觸表面216。引腳214自基座210侧向延伸，且熱接觸表面216係面朝下。 LED封裝體202係設置於導線54與散熱座％上，電性連結至導線54，且熱連結至散熱座56。詳而言之，led 封裝體202係設置於焊墊46與蓋體52上，重疊於凸柱22 ，且經由第一焊錫204電性連結至導線54,並經由第二焊錫206熱連結至散熱座56。例如’第一焊錫2〇4接觸且係位於焊塾46與引腳214之間，同時電性連結且機械性黏合焊墊46與引腳214，藉此將LED晶片208電性連結至端子 50。同樣地，第二焊錫206接觸且位於蓋體52與熱接觸表面216之間，同時熱連結且機械性黏合蓋體52與熱接觸表面216 ’藉此將LED晶片208熱連結至基座24。若欲製造半導體晶片組體200，可將一焊料置於焊塾 46與蓋體52上，然後分別在焊墊46與蓋體52上方之焊料 42 201133729 上放置引腳214與熱接觸表面216，繼而使該焊料迴焊以形成接著之第一、第二焊錫2〇4及2〇6。該半導體晶片組體200為一第二級單晶模組。第7A、7B及7C ®分別為本發明一實施例中一半導體曰曰片..且體之J視圖、俯視圖及仰視圖，其中該半導體晶片組體包含一導熱板及一半導體晶片β 於此實施例中，該半導體元件為一晶片而非一封裝體 ’且該晶片係設置於前述散熱座而非前述導線上。此外，該晶片係重疊於前述凸柱而非前述導線，且該晶片係經由一打線電性連結至前述焊塾，並利用—固晶材料熱連結至前述蓋體。半導體晶片組體300包含導熱板62、晶片3〇2、打線綱、固晶材料306及封裝材料3〇8。晶片3〇2包含頂面則、底Φ 312與打線接墊314。頂面31〇為活性表面且包含打線接墊314，而底面312則為熱接觸表面。晶片302係設置於散熱座56上，電性連結至導線Μ，且熱連結至散熱座56。詳而言之，晶片搬係設置於蓋體 52上，位於蓋體52之周緣内，重疊於凸柱22但未重疊於導線54。此外’晶片3〇2係經由打線遍電性連結至導線 54,同時經由固晶材料3〇6熱連結且機械性黏附於散熱座 56例如’打線3〇4係連接於並電性連結焊墊及打線接墊314,藉此將晶片3〇2電性連結至端子5〇。同樣地固晶材料306接觸並位於蓋體μ與底面312(即熱接觸表面）之間，同時熱連結且機械性黏合蓋體52與底面312，藉此將 S- 43 201133729 晶片302熱連結至基座24。焊墊46上設有鎳/銀之被覆金屬接墊以利與打線3〇4穩固接合，藉此改善自導線54 了—曰曰片302之訊號傳送。此外，蓋體52之形狀及尺寸係與底面 312配適，藉此改善自晶片3〇2至散熱座％之熱傳送。至於凸柱22之形狀及尺寸則並未且亦不需配合底面312而設計。封裝材料308為一固態電性絕緣保護性塑膠包覆體，其可為晶片302及打線304提供抗潮溼及防微粒等環境保護。晶片302與打線304係埋設於封裝材料3〇8中。此外，若晶片302係一諸如LED之光學晶片，則封裝材料3〇8 可為透明狀《封裝材料308在第7B圖中呈透明狀係為方便圖不說明。若欲製造半導體晶片組體300，可利用固晶材料3〇6將晶片302設置於蓋體52上，接著將烊墊46及打線接墊314 以打線接合，而後形成封裝材料308。例如，固晶材料306原為一具有高導熱性之含銀環氧樹脂膏，並以網版印刷之方式選擇性印刷於蓋體52上。然後利用一抓取頭及一自動化圖案辨識系統以步進重複之方式將晶片302放置於該環氧樹脂銀膏上。繼而加熱該環氧樹脂銀膏，使其於相對低溫（如190〇C)下硬化以完成固晶。打線304為金線，其隨即以熱超音波連接焊墊46及打線接墊314。最後再將封裝材料308轉移模製於結構體上。晶片302可透過多種連結媒介電性連結至焊墊46，利用多種熱黏著劑熱連結或機械性黏附於散熱座56,並以多 44 201133729 種封裝材料封裝。該半導體晶片組體300為一第一級單晶封裝體。第8A、8B及8C圖分別為本發明一實施例中一光源次體之。彳視圖、俯視圖及仰視圖，其中該光源次組體包含一半導體晶片組體與一散熱裝置。光源次組體400包含半導體晶片組體1〇〇與散熱裝置 402。散熱裝置402包含熱接觸表面404、鰭片406與風扇 408。半導體晶片组體1〇〇係設置於散熱裝置術上且機械性結合於散熱裝置402，例如以螺絲（圖未示）結合。因此，基座24係j緊於熱接觸表自4〇4且與之熱連結，藉此將散熱座56熱連結至散熱裝置4〇2。散熱座％可擴散l U 1 曰曰 08所產生之熱能，並將此擴散之熱能傳遞至散熱裝置 4〇2’散熱裝置402隨即利用韓片4〇6與風扇4〇8將2熱能散發至外圍環境。 -光源次組體400係為一可換裝標準白熾燈泡之燈座（圖未不）而設計。該燈座包含次組體4〇〇、一玻璃蓋、一螺紋基座、一控制板、線路及一外殼。次組體4〇〇、該控制板及該線路係包覆於料㈣。該料係延伸自賴制板並與端子焊合。該玻璃蓋及該螺紋基座分別突岐該外殼兩端。該玻璃蓋使LED晶片1〇8顯露於外’該螺紋基座可螺鎖入-光源插座，而該控制板料過該線路電性連結至端子50。該外殼為一兩件式塑膠殼，分下兩部分。該玻璃蓋係黏附並突出於該外殼上半部公之上方，該螺紋基座係黏附並突出於該外殼下半部分之下士 r石。光源次組體400 45 201133729 與該控制板係設置於該外殼之下半部分並伸入該外殼之上半部分。操作時，該螺紋基座將來自該光源插座之交流電傳遞至該控制板，該控制板則將此交流電轉換為整流後之直流電。該線路一方面將整流後之直流電傳送至端子5〇，一方面將另一端子50接地。因此，LED晶片1〇8可透過該玻璃蓋發光照明。& LED晶片1G8產生之強大局部熱能係流入散熱座56,並由散熱座56擴散至散熱裴置4〇2。散熱裝置 402中之鰭片406將熱能傳至空氣，再由風扇4〇8將熱空氣透過該外殼上之長孔以放射狀吹出至外圍環境中。上述之半導體晶片組體與導熱板僅為說明範例，本發明尚可透過其他多種實施例實現。此外，上述實施例可依。又。十及可罪度之考里，彼此混合搭配使用或與其他實施例混合搭配使用。例如’該半導體元件可為-LED封裝體，並打線接合至該導線；該半導體元件亦可為-半導體晶片 ’且重疊於該導線。該導熱板可包含多個凸柱，且該些凸柱係排成-陣列以供多個半導體元件使用，此外，該導執板為配合額外之半導體元件’可包含更多導線。同樣地，The semiconductor wafer package 200 includes a heat conductive plate 62, an LED sealing body 202, and first and first solders 204 and 206. The LED package 202 includes an LED wafer 208, a pedestal 210, a wire 212, a pin 214, and a transparent encapsulant 218. The LED chip 208 is electrically coupled to the pin 214 via the wire 212. The back side of the susceptor 210 includes a thermal contact surface 216. Further, the pedestal 21 is narrower than the pedestal 110 and has the same lateral dimensions and shape as the thermal contact surface 216. The LED chip 208 is disposed on the susceptor 21 via a die bond material (circular not shown) to thermally bond the LED die 208 and mechanically adhere to the pedestal 21 〇, thereby thermally bonding the LED chip 208 to the thermal contact. Surface 216. Pin 214 extends laterally from pedestal 210 with thermal contact surface 216 facing downward. The LED package 202 is disposed on the wire 54 and the heat sink, electrically connected to the wire 54, and thermally coupled to the heat sink 56. In detail, the LED package 202 is disposed on the pad 46 and the cover 52 , overlaps the stud 22 , is electrically connected to the wire 54 via the first solder 204 , and is thermally coupled to the heat through the second solder 206 . Block 56. For example, the first solder 2 〇 4 contacts and is located between the solder bumps 46 and the leads 214 , and electrically and mechanically bonds the solder pads 46 and the leads 214 , thereby electrically connecting the LED chips 208 to the terminals 50 . . Similarly, the second solder 206 contacts and is positioned between the cover 52 and the thermal contact surface 216 while thermally bonding and mechanically bonding the cover 52 to the thermal contact surface 216' thereby thermally bonding the LED wafer 208 to the pedestal 24. If the semiconductor wafer package 200 is to be fabricated, a solder may be placed on the solder bumps 46 and the cover 52, and then the pins 214 and the thermal contact surfaces 216 are placed on the solder pads 42 201133729 above the pads 46 and the cover 52, respectively. The solder is then reflowed to form the first and second solders 2〇4 and 2〇6. The semiconductor wafer package 200 is a second-level single crystal module. 7A, 7B, and 7C are respectively a semiconductor wafer according to an embodiment of the present invention: and a J-view, a top view, and a bottom view of the body, wherein the semiconductor wafer package includes a heat conductive plate and a semiconductor wafer β. In an embodiment, the semiconductor component is a wafer rather than a package ' and the wafer is disposed on the heat sink instead of the wire. Further, the wafer is overlapped with the studs instead of the wires, and the wafer is electrically connected to the solder fillet via a wire and thermally bonded to the cover by a die bonding material. The semiconductor wafer package 300 includes a heat conductive plate 62, a wafer 3, a wire bond, a die bonding material 306, and a package material 3〇8. The wafer 3〇2 includes a top surface, a bottom Φ 312, and a wire bonding pad 314. The top surface 31 is an active surface and includes a wire bond pad 314, while the bottom surface 312 is a thermal contact surface. The chip 302 is disposed on the heat sink 56, electrically connected to the wire Μ, and thermally coupled to the heat sink 56. In detail, the wafer transfer system is disposed on the lid body 52, is located in the periphery of the lid body 52, and overlaps the stud 22 but does not overlap the lead wire 54. In addition, the 'wafer 3〇2 is electrically connected to the wire 54 via a wire, and is thermally coupled via the die bonding material 3〇6 and mechanically adhered to the heat sink 56. For example, the wire is connected to the wire and is electrically connected to the pad. And bonding the wire pad 314, thereby electrically connecting the wafer 3〇2 to the terminal 5〇. Similarly, the die bonding material 306 is in contact with and located between the cover body μ and the bottom surface 312 (ie, the thermal contact surface) while thermally bonding and mechanically bonding the cover 52 to the bottom surface 312, thereby thermally bonding the S-43 201133729 wafer 302 to Base 24. The pad 46 is provided with a nickel/silver coated metal pad to securely engage the wire 3〇4, thereby improving the signal transmission from the wire 54 to the chip 302. In addition, the shape and size of the cover 52 is adapted to the bottom surface 312, thereby improving heat transfer from the wafer 3〇2 to the heat sink. The shape and size of the studs 22 are not designed and do not need to be matched to the bottom surface 312. The encapsulating material 308 is a solid electrically insulating protective plastic covering that provides environmental protection for the wafer 302 and the wire 304 against moisture and particulates. The wafer 302 and the wire 304 are embedded in the packaging material 3〇8. In addition, if the wafer 302 is an optical wafer such as an LED, the encapsulating material 3〇8 may be transparent. The encapsulating material 308 is transparent in FIG. 7B for convenience. If the semiconductor wafer assembly 300 is to be fabricated, the wafer 302 may be placed on the cover 52 by means of a die bonding material 3? 6, and then the pad 46 and the bonding pad 314 may be wire bonded to form a package material 308. For example, the die bond material 306 is originally a silver-containing epoxy resin paste having high thermal conductivity and is selectively printed on the cover 52 by screen printing. The wafer 302 is then placed on the epoxy silver paste in a step-and-repeat manner using a gripping head and an automated pattern recognition system. The epoxy silver paste is then heated and hardened at a relatively low temperature (e.g., 190 ° C) to complete the solid crystal. The wire 304 is a gold wire which is then connected to the bonding pad 46 and the wire bonding pad 314 by thermal ultrasonic waves. Finally, the encapsulation material 308 is transferred onto the structure. The wafer 302 can be electrically connected to the bonding pad 46 through a plurality of bonding media, thermally bonded or mechanically adhered to the heat sink 56 by a plurality of thermal adhesives, and packaged in a package material of 201133729. The semiconductor wafer package 300 is a first-level single crystal package. 8A, 8B and 8C are respectively a light source sub-body in an embodiment of the invention. The top view, the top view and the bottom view, wherein the subgroup of the light source comprises a semiconductor wafer package and a heat sink. The light source sub-assembly 400 includes a semiconductor wafer package 1 and a heat sink 402. The heat sink 402 includes a thermal contact surface 404, fins 406, and a fan 408. The semiconductor wafer package 1 is disposed on the heat sink and mechanically coupled to the heat sink 402, for example, by screws (not shown). Therefore, the susceptor 24 is fastened to and thermally coupled to the thermal contact table, thereby thermally connecting the heat sink 56 to the heat sink 4〇2. The heat sink % can diffuse the heat energy generated by l U 1 曰曰08, and transfer the heat energy of the diffusion to the heat sink 4〇2' heat sink 402, then use the Korean film 4〇6 and the fan 4〇8 to dissipate 2 heat energy to Peripheral environment. - The light source sub-assembly 400 is designed as a lamp holder that can be replaced with a standard incandescent light bulb. The lamp holder comprises a sub-assembly 4〇〇, a glass cover, a threaded base, a control board, a line and a casing. The sub-group 4〇〇, the control board and the line are coated on the material (4). The material extends from the laminate and is soldered to the terminals. The glass cover and the threaded base respectively protrude at both ends of the outer casing. The glass cover exposes the LED chip 1 8 to the outer end. The threaded base can be screwed into the light source socket, and the control board is electrically connected to the terminal 50 through the line. The outer casing is a two-piece plastic case divided into two parts. The glass cover is adhered and protrudes above the upper half of the outer casing, and the threaded base is adhered to and protrudes from the lower portion of the outer casing. The light source sub-assembly 400 45 201133729 and the control plate are disposed in the lower half of the outer casing and extend into the upper half of the outer casing. In operation, the threaded base transfers AC power from the light source socket to the control panel, which converts the alternating current to a rectified direct current. On the one hand, the line transmits the rectified direct current to the terminal 5, and the other terminal 50 is grounded on the other side. Therefore, the LED chip 1 8 can be illuminated by the glass cover. & The powerful local thermal energy generated by the LED chip 1G8 flows into the heat sink 56 and is diffused by the heat sink 56 to the heat sink 4〇2. The fins 406 in the heat sink 402 transfer heat energy to the air, and the hot air is blown through the long holes in the casing by the fan 4 to radially radiate into the peripheral environment. The semiconductor wafer package and the heat conducting plate described above are merely illustrative examples, and the present invention can be implemented by other various embodiments. Furthermore, the above embodiments may be relied upon. also. The ten and the guilty exams are used in combination with each other or in combination with other embodiments. For example, the semiconductor component can be an -LED package and wire bonded to the wire; the semiconductor component can also be a - semiconductor wafer and overlap the wire. The thermally conductive plate may comprise a plurality of studs, and the studs are arranged in an array for use with a plurality of semiconductor components. Further, the guide plate may include more wires for mating additional semiconductor components. Similarly,

該半導體元件可為一具有多牧IF 负夕校LED晶片之LED封裝體，而該導熱板料包含更多導線㈣合額外之LED晶片。該半導體元件可獨自使用該散熱座或與其他半導體元件共用該散熱座。例如，可將垔^ J將单一半導體元件設置於該散熱座上，或將多個半裝种；# 牛導體70件設置於該散熱座上。舉例而言，可將四枚排列成2χ2陣』义小型晶片黏附於該凸柱， 46 201133729 而該導熱板則可包含額外之導線以配合該些晶片之電性連接。此-作法遠較為每-晶片設置一微小凸柱更具經濟效益。該半導體晶片可為光學性或非光學性。例如，該晶片可為一 LED ' —太陽能電池、一微處理器、一控制器或一射頻_功率放大器。同樣地，該半導體封裝體^為一 led封裝體或—射簡纟a。目此，該半導^件可為一經封裝或未經封裝之光學或非光學晶片。此外，吾人可利用多種連結媒介將該半導體元件機械性連結、電性連結及熱連結至該導熱板，包括利用焊接及使用導電及/或導熱黏著劑等方式達成。忒散熱座可將該半導體元件所產生之熱能迅速、有效且均勻散發至下一層組體而不需使熱流通過該黏著層、該導線或該導熱板之他處。如此一來便可使用導熱性較低之黏著層，因而大幅降低成本。該散熱座可包含一體成形之凸柱與基座，以及與該凸柱為冶金連結及熱連結之一蓋體，藉此提咼可靠度並降低成本。該蓋體可與該焊墊共平面，以便與該半導體元件形成電性、熱能及機械性連結。此外，该蓋體可依該半導體元件量身訂做，而該基座則可依下一層組體量身訂做’藉此加強自該半導體元件至下一層組體之熱連結。例如，該凸柱在一側向平面上可呈圓形，該蓋體在一側向平面上可呈正方形或矩形，且該蓋體之侧面形狀與該半導體元件熱接點之侧面形狀相同或相似。該散熱座可與該半導體元件及該導線為電性連結或電 47 201133729 2隔離。例如，位於研磨後之表面上之該第二導電層可包 3 —路由線，該路由線係於該導線與該蓋體之間延伸通過該黏著I ’藉以將該半導體元件電性連結至該散熱座。之後，該散熱座可電性接地，藉以將該半導體元件電性接地 Ο 該散熱座可為銅質、鋁質、鋼/鎳/鋁合金或其他導熱金屬結構。 — 該凸柱可沉積於該基座上或與該基座一體成形。該凸柱可與該基座-體絲，因而成為單—金屬體（如銅或銘）。该凸柱亦可與該基座一體成形，使該兩者之介面包含單一金屬體（例如銅）’至於他處則包含其他金屬（例如凸柱之上部為焊料，凸柱之下部及基座則為銅質該凸柱亦可與該基座一體成形，使該兩者之介面包含多層單一金屬體（例如在一鋁核心外設有一鎳緩衝層，而該鎳緩衝層上則設有一銅層）。該凸柱可包含一平坦之頂面，且該頂面係與該黏著層共平面。例如，該凸柱可與該黏著層共平面，或者該凸柱可在該黏著層固化後接受蝕刻，因而在該凸柱上方之黏著層形成一凹穴。吾人亦可選擇性蝕刻該凸柱，藉以在該凸柱中形成一延伸至其頂面下方之凹穴。在上述任一情況下，該半導體元件均可設置於該凸柱上並位於該凹穴中，而該打線則可從該凹穴内之該半導體元件延伸至該凹穴外之該焊墊。在此情況下，該半導體元件可為一 LED晶片，並由該凹穴將LED光線朝該向上方向聚焦。 48 201133729 該基座可為該導線提供機械性支撐。例如，該基座可止該導電層在金屬研磨過程中f曲變形，並防止該在晶片設置、打線接合及模製料材料之過程中.f曲變來。該基座亦可從下方覆蓋該組體。此外，該基座之背料包含沿該向下方向突伸之妹Η。甲之，片例如’可利用-鑽板機切削該基座之底面以形成侧向溝槽，而此等側向溝槽即為轉片。在此例中’該基座之厚度可& 微米，該等溝槽之深度可為500微米’亦即該等轉片之高度可為·微米。該等縛片可增加該基座之表面積，若該等韓片係曝露於空氣中而非設置於-散熱裝置上，則可提升該基座經由孰對流之導熱性。該蓋體可於該黏著層固化後，該焊塾及/或該端子形成之前、中或後，以多種沉積技術製成，包括以電鍍、無電鑛被覆、蒸發及噴濺等技術形成單層或多層結構。該蓋體可採用與該凸柱相同之金屬材質，或採用與鄰接該蓋體之凸柱頂部相同之金屬材質。在上述任一情況下，該蓋體均係從該凸柱之頂部沿側面方向側向延伸而出。該黏著層可在該散熱座與該導線之間提供堅固之機械性連結。例如，該黏著層可自該凸柱側向延伸並越過該導線到達該組體之外圍邊緣，該黏著層可填滿該基座與該導線間之空間，該黏著層可位於該散熱座與該導線間之空間内，且該黏著層可為一具有均勻分佈之結合線之無孔洞結構。該黏著層亦可吸收該散熱座與該導線間因熱膨脹所產生之不匹配現象。此外，該黏著層可為一低成本電介質， 49 201133729 且不需具備高導熱性。再者，該黏著層不易脫層。吾人可調整該黏著層之厚度，使該黏著層實二口，並使幾乎所有黏著劑在固化及/或研磨後均位於結;秦體内。例如，理想之W厚度可由試誤法決定。同樣地，吾人亦可調整該導電層之厚度以達此一效果。該導電層可單獨設置於該黏著層上。例如，可先在該導電層切成該通孔，’然後將該導電層（不含其他層體）設置於該黏著層上’使該導電層接觸該黏著層，並朝該向上方向外露’在此同時，該凸柱則延伸進入該通孔，並透過該通孔朝該向上方向外露。在此情況下，該導電層之厚度可為100至200微米，例如125微米，此厚度一方面夠厚，故搬運時不致彎曲晃動，且可承受高驅動電流一方面則夠薄，故不需過度餘刻即可形成圖案。亦可將該導電層與一載體同時設置於該黏著層上。例如，可先利用一薄膜將該導電層黏附於一諸如雙定向聚對笨二甲酸乙二酯膠膜（Mylar)之載體，然後僅在該導電層而非該載體上形成該通孔，接著將該導電層及該載體設置於該黏著層上，使該載體覆蓋該導電層，且朝該向上方向外露’並使該薄膜接觸且介於該載體與該導電層之間，至於該導電層則接觸且介於該薄膜與該黏著層之間，在此同時 ’該凸柱係對準該通孔，並由該載體從上方覆蓋。該黏著層固化後’可到用紫外光分解該薄膜，以便將該載體從該導電層上剝除’從而使該導電層朝該向上方向外露，之後便可研磨及圖案化該導電層以形成該導線。在此情況下， 50 201133729 該導電層之厚度可為10至50微米，例如3〇微米，此厚度一方面夠厚，可提供可靠之訊號傳導，一方面則夠薄，可降低重量及成本；至於該載體之厚度可為3〇〇至5〇〇微米，此厚度一方面夠厚丨故搬運時不致彎曲晃動，一方面又夠嫜，有助於減少重量及成本。該載體僅為一暫時固定物 ’並非永久屬於該導熱板之一部分。 °玄知塾與該端子可視该半導體元件與下一層組體之需要而採用多種封裝形式。該焊墊與該蓋體之頂面可為共平面，如此一來便可藉由控制錫叙㈣㈣，強化該何體元件與該導熱板間之焊接。該焊墊、該端子與該路由線可在該導電層或該導線尚未或已然設置於該黏著層上時，以多種沉積技術製成，包括以電鍍、無f鑛被覆、蒸發及噴濺等技術形成單層或多層結構。例如，可先於一載體上形成該導電層之圖案，再將該導電層設置於該黏著層上。或者，可先利用該黏著層再將該導電層圖案化將該導電層黏附於該凸柱與該基座以所述被覆接點進行表面處理之工序可於該焊塾及該端子形成之前或之後為之。例如，該被覆層可沉積於該第 -導電層上’然後利用圖案化之蝕刻阻層定義該焊墊、該端子與該路由線錢行_，以使該縣層具有圖案。該導線可包含額外之谭塾、端子與路由線以及被動元件，且可為不㈣型。料線可料-㈣層、-功率層 51 £ 201133729 或一接地層’端視其相應半導體元件焊墊之目的而定。該導線亦可包含各種導電金屬，例如銅、金、錄、銀、鈀、錫、其混合物及其合金。理想之組成既取決於外部連結媒介之性質，亦取決於設計及可靠度方面之考量。此外，精於此技藝之人士應可瞭解’在該半導體晶片組體中所用之銅可為純銅’但通常係以銅為主之合金，如銅-錯（99.9%銅）、銅-銀-填-鎮（99.7%銅）及銅-錫-鐵-磷（μ.?%銅），藉以提高如抗張強度與延展性等機械性能。在一般情況下，最好在前述研磨後之表面上設有該蓋體、防知綠漆、被覆接點及第二導電層，但於某也實施例中則可省略之。例如’若該開口及該通孔係以衝孔而非鑽孔之方式產生’因而使該凸柱頂部之形狀及尺寸均與該半導體元件之熱接觸表面相配適，則可省略該蓋體與該第二導電層以降低成本。該導熱板可包含一導熱孔’該導熱孔係與該凸柱保持距離，並於該開口外延伸穿過該黏著層，同時鄰接且熱連結該基座與該蓋體’藉此提升自該蓋體至該基座之散熱效果，並促進熱能在該基座内擴散。該導熱板之作業格式可為單一或多個導熱板，視製造設計而定。例如，可單獨製作單一導熱板。或者，可利用單一金屬板、單一黏著層、單一導電層及單一防烊綠漆同時批次製造多個導熱板’而後再行分離。同樣地，針對同一批次中之各導熱板，吾人亦可利用單一金屬板、單一黏著層、單一導電層與單一防焊綠漆同時批次製造多組分別 52 201133729 供單一半導體元件使用之散熱座與導線。例如，可在一金屬板上姓刻出多條凹槽以形成該基座及多個凸柱；而後將一具有對應該等凸柱之開口的未固化黏著層設置於該基座上，俾使每—凸柱均延伸貫穿一對應開口：然後將-具有對應該等凸柱之通孔的導電層設置於該黏著層上，俾使每均㈣貫對應一並進入 -對應通孔·，而後利用壓台將該基座與該導電層彼此靠合，迫使該黏著層進入該等通孔内介於該等凸柱與該導電層間之缺口；然後固化該黏著層，繼而研磨該等凸柱、該黏著層及該導電層以形成一頂面；然後將第二導電層被覆設置於該等凸柱、該黏著層及該導電層上；接著蝕刻該等導電層以形成多組分別對應該等凸柱之焊墊、端子及路由線，並蝕刻该第二導電層以形成多個分別對應該等凸柱之蓋體；而後將防焊綠漆置於結構體上，使該防焊綠漆產生圖案，藉以曝露該等焊墊、該等端子及該等蓋體；而後以被覆接點對該基座、該等焊墊、該等端子及該等蓋體進行表面處理，隶後於该4導熱板外圍邊緣之適當位置切割或劈裂該基座、該黏著層及該防焊綠漆，俾使個別之導熱板彼此分離。該半導體晶片組體之作業格式可為單一組體或多個組體’取決於製造設計。例如，可單獨製造單一組體。或者 ’可同時批次製造多個組體’之後再將各導熱板一一分離。同樣地’亦可將多個半導體元件電性連結、熱連結及機械性連結至批次量產中之每一導熱板。 53 S. 201133729 例如’可將多個錫膏部分分別沉積於多個焊墊及蓋體上’而後將多個LED封裝體分別置於該等錫膏部分上接著同時加熱該等錫膏部分以使其迴焊、硬化並形成多個焊接點，之後再將各導熱板--分離。在另一範例中係將多個固晶材料分別沉積於多個蓋體上’而後將多牧晶片分別放置於該等固晶材料上，之後再同時加熱該等固晶材料以使其硬化並形成多個固晶而後將該等晶片打線接合至對應之焊墊，接著在該等晶片與打線上形成對應之封裝材料，最後再將各導熱板一一分離。吾人可透過單一步驟或多道步驟使各導熱板彼此分離。例如，可將多個導熱板批次製成一平板，接著將多個半導體元件设置於該平板上，然後再將該平板所構成之多個半導體晶片組體一一分離。或者，可將多個導熱板批次製成一平板，而後將該平板所構成之多個導熱板分切為多個導熱板條，接著將多個半導體元件分別設置於該等導熱板條上，最後再將各導熱板條所構成之多個半導體晶片組體分離為個體。此外，在分割導熱板時可利用機械切割、雷射切割、分劈或其他適用技術。在本文中’「鄰接」一語意指元件係一體成形（形成單一個體）或相互接觸（彼此無間隔或未隔開）。例如，該凸柱係鄰接該基座，此與形成該凸柱時採用增添法或削減法無關〇「重疊」一語意指位於上方並延伸於一下方元件之周緣内。「重疊」包含延伸於該周緣之内、外或坐落於該周緣 54 201133729 内。例如，該半導體元件係重里且於该凸柱，乃因—假想垂 ° 5時貫穿該半導體元件與該凸柱，不論該半導體元件與該凸柱間是否存在有另—同為該假想垂直線貫穿之元 ^如該蓋體）’且亦不論是否有另—假想垂直線僅貫穿該半導體讀而未貫穿該凸柱（亦即位於該凸柱之周緣外）。同樣該黏著層係重疊於該基座並被該焊塾重疊而該基座則被該凸柱重疊。因揭从 ^ 里1 η樣地，该凸柱係重疊於該基座且位於其周緣内。此外，「重疊」與「位於上方」同義，「被重疊」則與「位於下方」同義。接觸」一語意指直接接觸。例如，該導線接觸該黏著層但並未接觸該凸柱或該基座。「覆盍」一語意指從上方、從下方及/或從側面完全覆蓋。例如，該基座從下方覆蓋該凸柱，㈣凸柱並未從上方覆蓋該基座。層」子包含设有圖案或未設圖案之層體。例如，當該導電層設置於尚未固化之黏著層上時，該導電層可為一空白無圖案之平板·’而當該半導體元件設置於該散熱座上之後，該導電層可為已固化之黏著層上一具有間隔導線之電路圖案。此外，「層」可包含複數疊合層。「焊墊」一語與該導線搭配使用時係指一用於連接及/ 或接合外部連接媒介（如焊料或打線）之連結區域，而該外部連接媒介則可將該導線電性連結至該半導體元件。「端子」一語與該導線搭配使用時係指一連結區域，其可接觸及/或接合外部連結媒介（如焊料或打線），而該外The semiconductor component can be an LED package having a multi-grazing IF negative LED chip, and the thermally conductive sheet contains more wires (4) and additional LED chips. The semiconductor component can use the heat sink alone or share the heat sink with other semiconductor components. For example, a single semiconductor component may be disposed on the heat sink, or a plurality of semiconductors may be mounted on the heat sink. For example, four small arrays of thin wafers can be attached to the studs, 46 201133729, and the thermally conductive plates can include additional wires to accommodate the electrical connections of the wafers. This practice is far more economical than placing a tiny stud on each wafer. The semiconductor wafer can be optical or non-optical. For example, the wafer can be an LED' - a solar cell, a microprocessor, a controller or a radio frequency power amplifier. Similarly, the semiconductor package is a led package or a thin package a. Thus, the semiconductor component can be an encapsulated or unpackaged optical or non-optical wafer. In addition, the semiconductor element can be mechanically bonded, electrically connected, and thermally bonded to the thermally conductive plate by a variety of bonding media, including by soldering and using conductive and/or thermally conductive adhesives. The heat sink can quickly, efficiently and evenly dissipate the heat generated by the semiconductor component to the next layer without passing heat through the adhesive layer, the wire or other portion of the heat conducting plate. As a result, an adhesive layer having a lower thermal conductivity can be used, thereby greatly reducing the cost. The heat sink can include an integrally formed stud and a base, and a cover body that is metallurgically coupled and thermally coupled to the stud, thereby improving reliability and reducing cost. The cover may be coplanar with the pad to form electrical, thermal and mechanical bonds with the semiconductor component. In addition, the cover can be tailored to the semiconductor component, and the pedestal can be tailored to the next layer of components to thereby enhance thermal bonding from the semiconductor component to the next layer. For example, the stud may be circular in a lateral plane, the cover may be square or rectangular in a lateral plane, and the side shape of the cover is the same as the side shape of the thermal junction of the semiconductor element or similar. The heat sink can be electrically connected to the semiconductor component and the wire or electrically isolated. For example, the second conductive layer on the polished surface can include a routing line extending between the wire and the cover through the adhesive I' to electrically connect the semiconductor component to the Heat sink. Thereafter, the heat sink can be electrically grounded to electrically ground the semiconductor component. The heat sink can be copper, aluminum, steel/nickel/aluminum alloy or other thermally conductive metal structure. - The stud can be deposited on the base or integrally formed with the base. The studs can be associated with the base-body filaments and thus become a single-metal body (e.g., copper or inscription). The stud can also be integrally formed with the base such that the interface between the two comprises a single metal body (for example, copper)', and other portions include other metals (for example, the upper portion of the stud is solder, the lower portion of the stud and the base) The copper pillar may also be integrally formed with the base such that the interface between the two comprises a plurality of single metal bodies (for example, a nickel buffer layer is disposed on an aluminum core peripheral portion, and a copper buffer layer is disposed on the nickel buffer layer). The protrusion may include a flat top surface, and the top surface is coplanar with the adhesive layer. For example, the protrusion may be coplanar with the adhesive layer, or the protrusion may be cured after the adhesive layer is cured Receiving an etch, thereby forming a recess in the adhesive layer above the stud. We can also selectively etch the stud to form a recess in the stud that extends below its top surface. The semiconductor component can be disposed on the stud and located in the recess, and the wire can extend from the semiconductor component in the cavity to the pad outside the cavity. In this case, the The semiconductor component can be an LED wafer, and The recess focuses the LED light toward the upward direction. 48 201133729 The pedestal provides mechanical support for the wire. For example, the pedestal stops the conductive layer from deforming during the metal grinding process and prevents the wafer from being deformed. During the process of setting, wire bonding and molding the material, the base can also be covered by the base. The base can also cover the group from below. In addition, the backing of the base includes the sisters protruding in the downward direction. The sheet, for example, can be cut by a rig to cut the bottom surface of the pedestal to form a lateral groove, and the lateral grooves are the rotators. In this case, the thickness of the pedestal can be & The depth of the grooves may be 500 micrometers, that is, the height of the rotors may be micrometers. The spacers may increase the surface area of the base, if the Korean films are exposed to the air instead of being disposed. In the heat sink, the thermal conductivity of the susceptor via convection can be improved. The cover can be formed by various deposition techniques before, during or after the solder bump and/or the terminal is formed. Formation, including electroplating, electroless ore coating, evaporation and splashing Forming a single layer or a multi-layer structure. The cover body may be made of the same metal material as the protrusion or the same metal material as the top of the protrusion adjacent to the cover body. In either case, the cover body is The top of the stud extends laterally in a lateral direction. The adhesive layer provides a strong mechanical connection between the heat sink and the wire. For example, the adhesive layer can extend laterally from the stud and over the The wire reaches the peripheral edge of the group, the adhesive layer can fill the space between the base and the wire, the adhesive layer can be located in the space between the heat sink and the wire, and the adhesive layer can be uniform The non-porous structure of the bonding wire of the distribution. The adhesive layer can also absorb the mismatch between the heat sink and the wire due to thermal expansion. In addition, the adhesive layer can be a low-cost dielectric, 49 201133729 and does not need to be high Thermal conductivity. Furthermore, the adhesive layer is not easily delaminated. We can adjust the thickness of the adhesive layer so that the adhesive layer is two, and almost all the adhesives are located in the knot after curing and/or grinding. For example, the ideal thickness of W can be determined by trial and error. Similarly, we can also adjust the thickness of the conductive layer to achieve this effect. The conductive layer can be separately disposed on the adhesive layer. For example, the conductive layer may be first cut into the through hole, and then the conductive layer (excluding other layer) is disposed on the adhesive layer, so that the conductive layer contacts the adhesive layer and is exposed toward the upward direction. At the same time, the stud extends into the through hole and is exposed through the through hole in the upward direction. In this case, the conductive layer may have a thickness of 100 to 200 micrometers, for example, 125 micrometers, and the thickness is thick enough on the one hand, so that it does not cause bending and shaking during transportation, and can withstand high driving current on the one hand, and is thin enough, so that it is not required Excessive moments can form a pattern. The conductive layer may also be disposed on the adhesive layer simultaneously with a carrier. For example, the conductive layer may be adhered to a carrier such as a double-oriented polyethylene terephthalate film (Mylar) by using a film, and then the via hole is formed only on the conductive layer instead of the carrier, and then The conductive layer and the carrier are disposed on the adhesive layer, the carrier covers the conductive layer, and is exposed toward the upward direction and the film is contacted and interposed between the carrier and the conductive layer, as for the conductive layer Then contacting and interposed between the film and the adhesive layer, at the same time 'the pillar is aligned with the through hole and covered by the carrier from above. After the adhesive layer is cured, the film can be decomposed by ultraviolet light to strip the carrier from the conductive layer to expose the conductive layer in the upward direction, and then the conductive layer can be ground and patterned to form The wire. In this case, 50 201133729 the conductive layer may have a thickness of 10 to 50 micrometers, for example 3 micrometers, which is thick enough to provide reliable signal transmission and thin on the one hand to reduce weight and cost; As for the thickness of the carrier, it can be 3 〇〇 to 5 〇〇 micrometers, and the thickness is thick enough on the one hand, so that it does not bend and shake when transported, and is sturdy on the other hand, which helps to reduce weight and cost. The carrier is only a temporary fixture ‘not permanently part of the heat conducting plate. ° Xuanzhi and the terminal can be used in a variety of package forms depending on the needs of the semiconductor component and the next layer. The pad and the top surface of the cover may be coplanar, so that the welding between the body element and the heat conducting plate can be strengthened by controlling the tin (4) and (4). The solder pad, the terminal and the routing line can be formed by various deposition techniques, including plating, no f mine coating, evaporation, splashing, etc., when the conductive layer or the wire is not yet or already disposed on the adhesive layer. The technology forms a single layer or a multilayer structure. For example, the pattern of the conductive layer may be formed prior to a carrier, and the conductive layer may be disposed on the adhesive layer. Alternatively, the conductive layer may be patterned by using the adhesive layer, and the step of surface-treating the conductive layer to the pillar and the substrate may be performed before the solder bump and the terminal are formed or After that. For example, the capping layer can be deposited on the first conductive layer. The pad, the terminal and the routing line are then defined by a patterned etch stop layer to impart a pattern to the county layer. The wire can contain additional tantalum, terminal and routing wires, and passive components, and can be of the (four) type. The feed line can be - (four) layer, - power layer 51 £ 201133729 or a ground plane ' depending on the purpose of its corresponding semiconductor component pad. The wire may also comprise various conductive metals such as copper, gold, ruthenium, silver, palladium, tin, mixtures thereof, and alloys thereof. The ideal composition depends on both the nature of the external media and the design and reliability considerations. In addition, those skilled in the art should be able to understand that 'the copper used in the semiconductor wafer package can be pure copper' but is usually a copper-based alloy such as copper-wrong (99.9% copper), copper-silver- Fill- town (99.7% copper) and copper-tin-iron-phosphorus (μ.?% copper) to improve mechanical properties such as tensile strength and ductility. In general, it is preferable to provide the cover, the anti-knowledge green paint, the coated contact, and the second conductive layer on the surface after the polishing, but it may be omitted in some embodiments. For example, if the opening and the through hole are formed by punching instead of drilling, and thus the shape and size of the top of the stud are matched with the thermal contact surface of the semiconductor element, the cover and the cover may be omitted. The second conductive layer reduces cost. The heat conducting plate may include a heat conducting hole that is spaced from the stud and extends outside the opening through the adhesive layer while abutting and thermally joining the base and the cover body The heat dissipation effect of the cover to the base and the promotion of thermal energy diffusion in the base. The heat shield can be operated in a single or multiple heat shield depending on the manufacturing design. For example, a single heat conducting plate can be fabricated separately. Alternatively, a plurality of thermally conductive plates can be fabricated from a single metal sheet, a single adhesive layer, a single conductive layer, and a single tamper-proof green paint simultaneously and then separated. Similarly, for each of the heat-conducting plates in the same batch, we can also use a single metal plate, a single adhesive layer, a single conductive layer and a single solder-proof green paint to simultaneously manufacture multiple sets of separate 52 201133729 for the heat dissipation of a single semiconductor component. Seat and wire. For example, a plurality of grooves may be formed on a metal plate to form the base and the plurality of protrusions; and then an uncured adhesive layer having openings corresponding to the protrusions is disposed on the base, Extending each of the studs through a corresponding opening: then, a conductive layer having a through hole corresponding to the stud is disposed on the adhesive layer, so that each (four) corresponds to and enters the corresponding through hole. Then, the susceptor and the conductive layer are pressed against each other by the pressing table, forcing the adhesive layer to enter a gap between the protruding pillars and the conductive layer in the through holes; then curing the adhesive layer, and then grinding the convexities a pillar, the adhesive layer and the conductive layer to form a top surface; then, a second conductive layer is coated on the pillars, the adhesive layer and the conductive layer; and then the conductive layers are etched to form a plurality of groups respectively The pad, the terminal and the routing line of the stud should be equal, and the second conductive layer is etched to form a plurality of caps respectively corresponding to the studs; then the solder resist green paint is placed on the structure to make the solder resist Green paint produces a pattern to expose the pads, etc. And the cover body; and then the base, the pads, the terminals and the cover are surface-treated by the covered contacts, and then cut or split at appropriate positions on the peripheral edge of the 4 heat-conducting plates The susceptor, the adhesive layer and the solder resist green lacquer separate individual heat conducting plates from each other. The operational format of the semiconductor wafer package can be a single assembly or multiple assemblies' depending on the manufacturing design. For example, a single set can be manufactured separately. Alternatively, each of the heat conducting plates may be separated one by one after the plurality of groups can be manufactured at the same time. Similarly, a plurality of semiconductor elements can be electrically connected, thermally coupled, and mechanically coupled to each of the heat conducting plates in mass production. 53 S. 201133729 For example, 'a plurality of solder paste portions may be deposited on a plurality of solder pads and a cover respectively' and then a plurality of LED packages are respectively placed on the solder paste portions and then the solder paste portions are heated simultaneously It is re-welded, hardened and formed into a plurality of solder joints, after which the heat conducting plates are separated. In another example, a plurality of die-bonding materials are separately deposited on the plurality of caps' and then the multi-grain wafers are separately placed on the die-bonding materials, and then the die-bonding materials are simultaneously heated to harden them. A plurality of solid crystals are formed, and then the wafers are wire bonded to the corresponding pads, and then corresponding packaging materials are formed on the wafers and the wires, and finally the heat conducting plates are separated one by one. We can separate the heat conducting plates from each other in a single step or in multiple steps. For example, a plurality of heat conducting plates can be batched into a flat plate, and then a plurality of semiconductor elements can be placed on the flat plate, and then the plurality of semiconductor wafer assemblies formed by the flat plates can be separated one by one. Alternatively, a plurality of heat conducting plates can be batched into a flat plate, and then the plurality of heat conducting plates formed by the flat plate are slit into a plurality of heat conducting strips, and then a plurality of semiconductor elements are respectively disposed on the heat conducting strips. Finally, the plurality of semiconductor wafer assemblies formed by the heat conducting strips are separated into individual parts. In addition, mechanical cutting, laser cutting, bifurcation or other suitable techniques can be utilized when splitting the heat conducting plates. The term "adjacent" as used herein means that the elements are integrally formed (forming a single entity) or in contact with one another (with or without separation from one another). For example, the stud is adjacent to the pedestal, which is independent of the addition or reduction method when forming the stud. 「 The term "overlapping" means located above and extending within the periphery of a lower element. "Overlap" includes extending within, outside of, or within the perimeter of the perimeter 54 201133729. For example, the semiconductor element is heavy and is in the stud, because the semiconductor element and the stud are penetrated through the imaginary yoke 5, regardless of whether there is another imaginary vertical line between the semiconductor element and the stud. Throughout the element ^ as the cover) 'and whether or not there is another imaginary vertical line only through the semiconductor read without penetrating the stud (ie, outside the periphery of the stud). Similarly, the adhesive layer overlaps the pedestal and is overlapped by the solder fillet and the pedestal is overlapped by the stud. Due to the fact that the pillars are overlapped with the pedestal and are located in the periphery thereof. In addition, "overlap" is synonymous with "above" and "overlapping" is synonymous with "below". The term "contact" means direct contact. For example, the wire contacts the adhesive layer but does not contact the stud or the pedestal. The term "overlapping" means completely covering from above, from below and/or from the side. For example, the pedestal covers the stud from below, and (iv) the stud does not cover the pedestal from above. The layer includes a layer with or without a pattern. For example, when the conductive layer is disposed on the adhesive layer that has not been cured, the conductive layer may be a blank unpatterned flat panel. 'When the semiconductor component is disposed on the heat sink, the conductive layer may be cured. A circuit pattern having spaced wires on the adhesive layer. In addition, a "layer" may comprise a plurality of superposed layers. The term "pad" as used in connection with the conductor means a connection area for connecting and/or engaging an external connection medium (such as solder or wire), and the external connection medium electrically connects the wire to the Semiconductor component. The term "terminal" when used in conjunction with the conductor means a connection area that contacts and/or engages an externally bonded medium (such as solder or wire), and

S 55 201133729 部連結媒介則可將該導線電性遠έ士你平冰电丨王埂結至與下一層組體相關之一外部設備（例如一印刷電路板或與其連接之一導線）。「蓋體」一語與該散熱座搭配使用時係指一用於連接及/或接合外部連接媒介（如焊料或導熱黏著劑）之接觸區域，而該外部連接媒介則可將該散熱座熱連結至該半導體元件。「開口」與「通孔」等語同指貫穿孔洞。例如，當該凸柱***該黏著層之該開口時，該凸柱係沿向上方向曝露於該黏著層。同樣地，當該凸柱***該導電層之該通孔時，該凸柱係沿向上方向曝露於該導電層。「***」一語意指元件間之相對移動。例如，「將該凸柱***該通孔中」包含：該凸柱固定不動而由該導電層向 §亥基座移動，該導電層固定不動而由該凸柱向該導電層移動；以及該凸柱與該導電層兩者彼此靠合。又例如，「將該凸柱***（或延伸至）該通孔内」包含：該凸柱貫穿（穿入並穿出）该通孔，以及該凸柱***但未貫穿.（穿入但未穿出）該通孔。「彼此靠合」一語亦指元件間之相對移動。例如，「琴基座與該導電層彼此靠合」包含：該基座固定不動而由該導電層移往該基座；該導電層固定不動而由該基座向該導電層移動；以及該基座與該導電層相互靠近。「對準」一語意指元件間之相對位置。例如，當該毒占著層已設置於該基座上、該導電層已設置於該黏著層上、該凸柱已***並對準該開口，且該通孔已對準該開口時， 56 201133729 無論該凸柱係***該通孔或位於該通孔下方且與其保持距離，該凸柱均已對準該通孔。置於」5吾包含與單一或多個支撐元件間之接觸與非接觸0例如，兮车道^^ - μ J如料導體疋件係設置於該散熱座上，不論該半導體7〇件係眚F 4* a® 干伸貫際接觸該散熱座或係、與該散熱座以一固晶材料相隔。同樣地，嗜本 4牛導體7C件係設置於該散熱座上’不論該半導體元件係僅 1重》又置於δ亥散熱座上或係同時設置於該散熱座與該導線上。 #著層…於„亥缺口之中」一語意指位於該缺口中之該黏著層。例如，「黏著層在該缺口中延伸跨越該導電層」意指該缺口内之該黏著層延伸跨越該導電層。同樣地，「黏著層於该缺口之中接觸且介於該、茨凸柱與該導電層之間」意指該缺口中之該黏著層接觸且介名買讶啁I"於该缺口内侧壁之該凸柱盥該缺口外側壁之該導電層之間。 ^ 上方」—語意指向上延伸’且包含鄰接與非鄰接元件以及重疊與非重疊元件。例如，該凸柱係延伸於該基座上方’同時鄰接、重疊於該基座並自該基座突伸而出。同樣地，該導線係延伸於該基座上方，即便該導線並未鄰接該基座。下方」一5吾意指向下延伸，且包含鄰接與非鄰接元件以及重疊與非重疊元件。例知， U如該基座係延伸於該凸柱下方’鄰接該凸柱，被該Α知舌蟲傲通凸桎重疊，並自該凸柱突伸而出。同樣地’該凸柱係延伸於該導線下方，即便該凸柱並未鄰接該導線或被該導線重疊。 57 201133729 所兩向上」及「向下」之垂直方向並非取決於該半導體晶片組體（或該導熱板）之定向，凡熟悉此項技藝之人士可輕易瞭解其實際所指之方向。例如，該凸柱係沿向上方向垂直延伸於該基座上方，而該黏著層則沿向下方向垂直延伸於該焊墊下方，此與該組體是否倒置及/或是否係設置於-散熱裝置上無關。同樣地，該基座係沿—側向平面自該凸柱「側向」延伸而出，此與該組體是否倒置、旋轉或傾斜無關。因此，該向上及向下方向係彼此相對且垂直於側面方向，此外，側向對齊之元件係在一垂直於該向上與向下方向之侧向平面上彼此共平面。本發明之半導體晶片組體具有多項優點。該組體之可 #度间^格平實且極適合量產。該組體尤其適用於易產生南熱且需優異散熱效果方可有效及可靠運作之高功率半導體元件’例# LED封裝體、大型半導體晶片以及多個同時使用之小型半導體元件（例如以陣列方式排狀多牧小形半導體晶片）。本案之製k工序具有雨度適用性，且係以獨特、進步S 55 201133729 The connecting medium can electrically connect the wire to your external device (such as a printed circuit board or a wire connected to it) connected to the next layer. The term "cover" when used in conjunction with the heat sink refers to a contact area for connecting and/or bonding an external connection medium (such as solder or a thermally conductive adhesive), and the external connection medium can heat the heat sink. Connected to the semiconductor component. The words "opening" and "through hole" refer to the through hole. For example, when the stud is inserted into the opening of the adhesive layer, the stud is exposed to the adhesive layer in an upward direction. Similarly, when the stud is inserted into the through hole of the conductive layer, the stud is exposed to the conductive layer in an upward direction. The term "insertion" means the relative movement between components. For example, "inserting the stud into the through hole" includes: the stud is fixed and moved by the conductive layer to the base, the conductive layer is fixed and moved by the stud to the conductive layer; Both the stud and the conductive layer abut each other. For another example, "inserting (or extending into) the through hole" includes: the through hole penetrates (passes through) the through hole, and the protrusion is inserted but not penetrated. Wear out) the through hole. The phrase "together with each other" also refers to the relative movement between components. For example, "the piano base and the conductive layer abut each other" includes: the base is fixed and moved by the conductive layer to the base; the conductive layer is fixed and moved by the base to the conductive layer; The pedestal and the conductive layer are close to each other. The term "aligned" means the relative position between components. For example, when the poison occupying layer is disposed on the pedestal, the conductive layer is disposed on the adhesive layer, the stud has been inserted and aligned with the opening, and the through hole has been aligned with the opening, 56 201133729 Whether the stud is inserted into the through hole or under the through hole and kept away from the through hole, the stud is aligned with the through hole. Placed in the "5" including contact and non-contact between the single or multiple support members. For example, the 兮 lane ^^ - μ J such as the conductor member is disposed on the heat sink, regardless of the semiconductor 7-piece system The F 4* a® is continuously extended to contact the heat sink or system, and is spaced apart from the heat sink by a solid crystal material. Similarly, the 7C conductor 7C is disposed on the heat sink, regardless of whether the semiconductor component is only one heavy, and is placed on the heat sink or on the heat sink. #层层... The term "in the middle of the gap" means the adhesive layer located in the gap. For example, "the adhesive layer extends across the conductive layer in the gap" means that the adhesive layer within the gap extends across the conductive layer. Similarly, "the adhesive layer is in contact between the gap and between the tab and the conductive layer" means that the adhesive layer in the gap contacts and refers to the inside wall of the notch. The stud is between the conductive layers of the outer sidewall of the notch. ^ Above" - semantically extends upwards and includes contiguous and non-contiguous elements and overlapping and non-overlapping elements. For example, the studs extend above the pedestal while adjoining, overlapping the pedestal and projecting therefrom. Similarly, the wire extends over the base even if the wire does not abut the base. The lower one is a downward extension and contains adjacent and non-contiguous elements as well as overlapping and non-overlapping elements. For example, if the pedestal extends below the stud and abuts the stud, it is overlapped by the protuberance of the larvae and protrudes from the stud. Similarly, the stud extends below the wire even if the stud is not adjacent to or overlapped by the wire. 57 201133729 The vertical direction of the two upwards and the downward direction is not dependent on the orientation of the semiconductor wafer package (or the heat conduction plate), and those skilled in the art can easily understand the direction in which they actually refer. For example, the stud column extends vertically above the pedestal in an upward direction, and the adhesive layer extends vertically below the pad in a downward direction, and whether the set is inverted and/or is disposed at - heat dissipation Not relevant on the device. Similarly, the pedestal extends laterally from the stud along the lateral plane regardless of whether the set is inverted, rotated or tilted. Thus, the upward and downward directions are opposite each other and perpendicular to the side direction, and further, the laterally aligned elements are coplanar with each other in a lateral plane perpendicular to the upward and downward directions. The semiconductor wafer package of the present invention has a number of advantages. The group can be leveled and very suitable for mass production. This group is especially suitable for high-power semiconductor components that are easy to generate south heat and require excellent heat dissipation to operate efficiently and reliably. 'Example #LED package, large semiconductor wafer, and multiple small semiconductor components used simultaneously (for example, in an array) Row-shaped multi-grazing small semiconductor wafer). The process of this case has a rain applicability and is unique and progressive.

之方式結合運用各種成熟之雷；鱼々士 -fe / I 取氕I電連結、熱連結及機械性連結技術。此外’本案之製造卫序不需昂貴工具即可實施。因此，此製造工序可大幅提升傳統封裝技術之產量、良率、效能與成本效益。再者，太査+ 4 本案之組體極適合於鋼晶片及盔鉛之環保要求。，其中所涉及之本技略以免模糊本發明之在此所述之實施例係為例示之用藝習知元件或步驟或經簡化或有所省 58 201133729 特點。同樣地’為使圖式清晰，圖式中重覆或非必要之元件及參考標號或有所省略。精於此項技藝之人士針對本文所述之實施例當可輕易思及各種變化及修改。例如，前述之原料、尺寸、形狀、大小、步狀内容與步驟之順序皆僅為範例。上述人士可於不脫離本發明之精神與範圍之條件下從事此等改變、調整與均等技藝’其中本發明之範圍係由後附之巾請專圍加以界定。【圖式簡單說明】第1A至1D圖為剖視圖，說明本發明一實施例中用以製作一凸柱及一基座之方法；第1E及1F圖刀別為第1D圖之俯視圖及仰視圖；第2A及2B圖為剖視圖，說明本發明一實施例製作一黏著層之方法；第2C及2D圖刀別為第2B圖之俯視圖及仰視圖；第3A至3D圖為剖視圖，說明本發明一實施例中用以製作一導電層之方法；刀別為第3D圖之俯視圖及仰視圖；第4A S 4L圖為剖視圖，說明本發明一實施例令用以製作一導熱板之方法；第4M及4N圖分別為帛4L目之俯視圖及仰視圖半導體片組體第5A、5B及5C ®分別為本發明一實施例中一晶片組體之剖視圖、俯視圖及仰視圖，該半導體晶包含該導熱板及一具有背面接點之LED封裝體； 59 S： 201133729 曰第6A、6B&6C圖分別為本發明一實施例中一半導體曰曰^，、且體之剖視圖、俯視圖及仰視圖，該半導體晶片組體匕3該導熱板及一具有側引腳之封裝體；第7A、7B & 7C圖分別為本發明一實施例中_半導體晶片組體之剖視圖 '俯視圖及仰視圖，該半導體晶片組體包含該導熱板及一半導體晶片；及第8A、8B及8C圖分別為本發明一實施例中一光源次組體之别視圖、俯視圖及仰視圖，該光源次組體包含第5A 至5C圖所示之半導體晶片組體及一散熱裝置。 60 201133729 【主要元件符號說明】 ίο.........金屬板 12、14 · ·表面 16、32···圖案化之蝕刻阻層 34、42··圖案化之蝕刻阻層 18、44 ··全面覆蓋之蝕刻阻層 20.........凹槽 22.........凸柱 24.........基座 26.........黏著層 28.........開口 30、40 ··導電層 36.........通孔 38.........缺口 46.........焊墊 48.........路由線 50.........端子 52.........蓋體 54.........導線 56.........散熱座 58.........防焊綠漆 60.........被覆接點 62.........導熱板 100、200··半導體晶片組體 300 . •半導體晶片組 102、 202· LED 封裝體 104- ••第一焊錫 106- 第二焊錫 204··· "第一焊錫 206- "第二焊錫 108、 208-LED 晶片 110、 210 .·基座 112、 212 ••打線 114 · •電接點 116 •熱接點 118、 218 ••透明封裝材料 214 .引腳 216、 404 .·熱接觸表面 302 _ •曰曰片 306 •固日日材料 308 •封裝材料 310 •頂面 312 •底面 314 •打線接墊 400 •光源次組體 402 •散熱裝置 406 •鰭片 61 201133729 風扇 408 62The combination of various mature mines; fish gentleman -fe / I take 氕I electrical connection, thermal connection and mechanical connection technology. In addition, the manufacturing process of this case can be implemented without expensive tools. As a result, this manufacturing process significantly increases the yield, yield, performance and cost effectiveness of traditional packaging technologies. Furthermore, Taicha + 4 is a group suitable for environmental protection requirements for steel wafers and helmets. The present invention is not intended to be inconsistent with the invention. The embodiments described herein are exemplified by the teachings of the elements or the. Similarly, in order to clarify the drawings, the repeated or non-essential elements and reference numerals in the drawings may be omitted. Those skilled in the art will be able to readily appreciate various changes and modifications in the embodiments described herein. For example, the foregoing materials, dimensions, shapes, sizes, step contents, and order of steps are merely examples. The above-mentioned persons can make such changes, adjustments and equalizations without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1D are cross-sectional views illustrating a method for fabricating a stud and a pedestal in an embodiment of the present invention; and FIGS. 1E and 1F are top and bottom views of the first DD; 2A and 2B are cross-sectional views illustrating a method of fabricating an adhesive layer in accordance with an embodiment of the present invention; 2C and 2D views are a plan view and a bottom view of FIG. 2B; and FIGS. 3A to 3D are cross-sectional views illustrating the present invention. A method for fabricating a conductive layer in an embodiment; a top view and a bottom view of the 3D view; and a cross-sectional view of the fourth embodiment of the present invention, illustrating a method for fabricating a heat conductive plate according to an embodiment of the present invention; 4M and 4N are respectively a top view of the L4L mesh and a bottom view of the semiconductor chip group 5A, 5B, and 5C ® respectively, which are a cross-sectional view, a top view, and a bottom view of a wafer package in an embodiment of the present invention, the semiconductor crystal including the A heat conducting plate and an LED package having a back contact; 59 S: 201133729 曰 6A, 6B & 6C are respectively a cross-sectional view, a top view and a bottom view of a semiconductor device according to an embodiment of the present invention, Semiconductor wafer package 3, the heat conducting plate and a package having a side pin; 7A, 7B & 7C are respectively a cross-sectional view of a semiconductor wafer package in a top view and a bottom view of the semiconductor wafer package, The heat conducting plate and a semiconductor wafer; and FIGS. 8A, 8B, and 8C are respectively a different view, a top view, and a bottom view of a light source sub-group according to an embodiment of the present invention, the light source sub-group including the 5A to 5C The semiconductor chip assembly and a heat sink. 60 201133729 [Description of main component symbols] ίο.........metal plates 12, 14 · Surfaces 16, 32 · Patterned etching resist layers 34, 42 · Patterned etching resist layer 18 , 44 · · comprehensively covered etching resist layer 20 ... ... groove 22 ... ... ... ... ... ... ... ... ... ... ... ... ... 26 ... ...adhesive layer 28...the opening 30,40 ·the conductive layer 36...the through hole 38...the gap 46 .........pad 48.........route line 50.........terminal 52......cover 54... ... wire 56.........heatsink 58.........anti-weld green paint 60.........covered contact 62... ... heat conducting plate 100, 200 · semiconductor wafer package 300. • semiconductor wafer set 102, 202 · LED package 104 - • • first solder 106 - second solder 204 · · · " first Solder 206- "Second Solder 108, 208-LED Wafer 110, 210. · Dock 112, 212 •• Wire 114 · • Electrical Contact 116 • Hot Junction 118, 218 • Transparent Packaging Material 214. Pin 216, 404 .. Thermal contact surface 302 _ • 曰曰 306 • Solid day material 308 • Package material 310 • Top surface 312 • Bottom surface 314 • Wire bond pad 400 • Light source sub-assembly 402 • Heat sink 406 • Fin 61 201133729 Fan 408 62

Claims

201133729 七、申請專利範圍： 1 _ 一種半導體晶片組體，至少包含：一半導體元件；一黏著層，其至少具有一開口；一散熱座’其至少包含一凸柱及一基座，其中該凸柱係鄰接該基座並沿一向上方向延伸於該基座上方，且該基座係沿一與該向上方向相反之向下方向延伸於該凸柱下方’並沿垂直於該向上及向下方向之側面方向從該凸柱側向延伸；及一導線，其至少包含一焊墊及一端子；其中該半導體元件係位於該凸柱上方並重疊於該凸柱，該半導體元件係電性連結至該焊墊，從而電性連結至该端子，且該半導體元件係熱連結至該凸柱，從而熱連結至該基座； ^ 其中該黏著層係設置於該基座上，延伸於該基座上方，延伸進入一位於該凸柱與該焊墊間之缺口，並自該凸柱側向延伸至該端子或越過該端子，且該黏著層係介於該基座與該焊塾之間；其中該焊墊係設置於該黏著層上，並延伸於該基座上方；以及其中該凸柱延伸進入該開口’該基座則延伸於該半導體元件、該黏著層及該焊墊下方。 2.根據申請專利範圍第丨項所述之半導體晶片組體，其中 ’該半導體元件為一包含LED晶片之LED封裝體。 63 201133729 3. 根據中請專利範圍第2項所述之半導體晶片組體，其中 ’該LED封裝㈣利用一第—焊錫電性連結至該焊塾，並利用一第二焊錫熱連結至該散熱座。 4. 根據中請專利範圍第丨項所述之半導體晶片組體其中 ’該半導體元件為一半導體晶片。 5. 根據申請專利範圍第4項所述之半導體晶片組體其中，該晶片係利用一打線電性連結至該焊墊，並利用一固晶材料熱連結至該散熱座。 6. 根據申請專利範圍第丨項所述之半導體晶片組體，其中，該黏著層在該缺口内接觸該凸柱，並在該缺口之外接觸該基座、該焊墊與該端子。 7 ·根據申請專利範圍第丨項所述之半導體晶片組體，其中 ’該黏著層於該等側面方向覆蓋且環繞該凸柱。 8. 根據申請專利範圍第1項所述之半導體晶片組體，其中 ’該黏著層同形被覆於該凸柱之側壁以及該基座位於該凸柱外之一頂面。 9. 根據申請專利範圍第1項所述之半導體晶片組體，其中 ’該黏著層填滿該基座與該導線間之一空間。 1〇·根據申請專利範圍第1項所述之半導體晶片組體，其中 ’該黏著層自該凸柱側向延伸，越過該端子，且被該端子重疊。 11.根據申請專利範圍第1項所述之半導體晶片組體，其中 ’該黏著層延伸至該組體之外圍邊緣。 12·根據申請專利範圍第1項所述之半導體晶片組體，其中 64 201133729 該凸柱與該基座一體成形。201133729 VII. Patent application scope: 1 _ A semiconductor wafer assembly comprising at least: a semiconductor component; an adhesive layer having at least one opening; a heat sink having at least one post and a base, wherein the bump a column system abuts the base and extends above the base in an upward direction, and the base extends below the protrusion 'in a downward direction opposite to the upward direction' and is perpendicular to the upward and downward directions a lateral direction of the direction extending laterally from the stud; and a wire comprising at least one pad and a terminal; wherein the semiconductor component is located above the stud and overlaps the stud, the semiconductor component is electrically connected To the solder pad, electrically connected to the terminal, and the semiconductor component is thermally coupled to the stud to be thermally coupled to the pedestal; ^ wherein the adhesive layer is disposed on the pedestal and extends to the base Above the seat, extending into a gap between the stud and the pad, and extending laterally from the stud to the terminal or over the terminal, and the adhesive layer is interposed between the base and the solder The solder pad is disposed on the adhesive layer and extends over the base; and wherein the protrusion extends into the opening, the base extends to the semiconductor component, the adhesive layer, and the bonding pad Below. 2. The semiconductor wafer package of claim 3, wherein the semiconductor component is an LED package comprising an LED chip. The semiconductor chip package according to the second aspect of the patent application, wherein the LED package (4) is electrically connected to the soldering pad by a first solder, and is thermally coupled to the heat sink by a second solder. seat. 4. The semiconductor wafer package according to the above-mentioned patent scope, wherein the semiconductor component is a semiconductor wafer. 5. The semiconductor wafer package of claim 4, wherein the wafer is electrically connected to the pad by a wire and thermally bonded to the heat sink by a solid material. 6. The semiconductor wafer package of claim 3, wherein the adhesive layer contacts the stud within the notch and contacts the pedestal, the pad and the terminal outside the notch. The semiconductor wafer package according to the above application, wherein the adhesive layer covers and surrounds the convex column in the lateral direction. 8. The semiconductor wafer package of claim 1, wherein the adhesive layer is isomorphically coated on a sidewall of the stud and the pedestal is located on a top surface of the stud. 9. The semiconductor wafer package of claim 1, wherein the adhesive layer fills a space between the pedestal and the wire. The semiconductor wafer package according to claim 1, wherein the adhesive layer extends laterally from the stud, passes over the terminal, and is overlapped by the terminal. 11. The semiconductor wafer package of claim 1, wherein the adhesive layer extends to a peripheral edge of the set. 12. The semiconductor wafer package of claim 1, wherein 64 201133729 the stud is integrally formed with the base.

μ凸柱為平頂錐柱形，其直徑自該基座至該凸柱之一平坦頂部係呈向上遞減。根據巾請專利範圍帛丨項所述之半導體晶片組體，其中，該基座從下方覆蓋該半導體元件、該凸柱、該黏著層與该導線’並延伸至該組體之外園邊緣。 μ.根據中請專利範圍第丨項所述之半導體晶片組體，其中，該導線係與該凸柱及該基座保持距離，該焊墊與該端子則接觸且重疊於該黏著層。 π.根據申請專利範圍第丨項所述之半導體晶片組體，其中，該散熱座至少包含一蓋體，該蓋體位於該凸柱之一頂部上方，鄰接該凸柱之該頂部，並從上方覆蓋該凸柱之該頂部，伸。同時沿該等側面方向自該凸柱之該頂部侧向根據申請專利範圍第17項所述之半導體晶片組體，其中 ’ β亥蓋體與該焊墊以及該端子於該黏著層上方為丘平面〇體，其中一熱接觸根據申請專利範圍第17項所述之半導體晶片組體，其中 ’該蓋體為矩形或正方形，且該凸柱之該頂部為圓形。 20.根據申請專利範圍第17項所述之半導體晶片組 ’該蓋體之尺寸及形狀係配合該半導體元件之 65 201133729 表面而設計，該凸柱之該頂部之尺寸及形狀則並非配合該半導體元件之該熱接觸表面而設計。 21. —種半導體晶片組體，至少包含：一半導體元件；一黏著層，其至少具有一開口；一散熱座，其至少包含一凸柱與一基座，其中該凸柱鄰接該基座並與該基座一體成形，且該凸柱沿一向上方向延伸於該基座上方，該基座則沿一與該向上方向相反之向下方向延伸於該凸柱下方，並沿垂直於該向上及向下方向之側面方向自該凸柱側向延伸；及一導線，其至少包含一焊墊、一端子與一路由線，其中該焊墊與該端子間之一導電路徑包含該路由線；其中該半導體元件係設置於該散熱座上，重疊於該凸柱，並電性連結至該焊墊，從而電性連結至該端子，且該半導體元件係熱連結至該凸柱，從而熱連結至該基座；其中該黏著層係設置於該基座i，延仲於該基座上方，延伸進入一位於該凸柱與該焊塾間之缺口且該黏著層在該缺π之外係介於該基座與該導線之間該黏著層並於該等側面方向環繞該凸柱，同時延伸至該組體之外圍邊緣；其中該導線係5又置於該黏著層上並延伸於該基座上方’且該焊墊、該端子與該路由線接觸並重疊於該黏著層；以及 66 201133729 其中該凸柱延伸進入該開口，該基座延伸於該半導體元件、該黏著層及該導線下方，且從下方覆蓋該凸柱、該黏著層及該導線’同時延伸至該組體之外圍邊緣。 22.根據申請專利範圍第21項所述之半導體晶片組體，其中 ’該半導體元件為一包含LED晶片之LED封裝體，且係利用一第一焊錫設置於該焊墊上，並利用一第二焊錫设置於該散熱座上’該半導體元件利用該第一焊錫電性連結至該焊墊，並利用該第二焊錫熱連結至該散熱座。 23_根據申請專利範圍第21項所述之半導體晶片組體，其中，該黏著層在該缺口内接觸該凸柱，並在該缺口之外接觸該基座、該焊墊、該端子與該路由線，該黏著層於該等側面方向覆蓋且環繞該凸柱，從下方覆蓋該導線，並從上方覆蓋該基座位於該凸柱外之一部分，同時填滿該基座與該導線間之一空間。 24. 根據申請專利範圍第21項所述之半導體晶片組體，其中，該凸柱為平頂錐柱形，其直徑自該基座至該凸柱之一平坦頂部係呈向上遞減，該凸柱之該頂部為圓形，一蓋體係設置於該凸柱之該頂部上，位於該凸柱之該頂部上方，鄰接該凸柱之該頂部’並從上方覆蓋該凸柱之該頂。(^同時沿該等侧面方向自該凸柱之該頂部侧向延伸， s亥盏體為矩形或正方形。 25. 根據申請專㈣圍第21項所述之半導體晶片組體，其中 ’該凸柱與該黏著層於該導線之—底部上方為共平面，且該焊墊與該端子於該黏著層上方為共平面。 67The μ-bump is a flat-topped tapered column whose diameter decreases upward from the pedestal to the flat top of one of the studs. The semiconductor wafer package according to the scope of the invention, wherein the pedestal covers the semiconductor element, the stud, the adhesive layer and the wire ′ from below and extends to the outer edge of the group. The semiconductor wafer package of claim 3, wherein the wire is spaced from the stud and the pedestal, the pad being in contact with the terminal and overlapping the adhesive layer. The semiconductor wafer package according to the invention of claim 2, wherein the heat sink comprises at least a cover, the cover is located above a top of one of the protrusions, abutting the top of the protrusion, and The top of the stud is covered above and extends. And the semiconductor wafer assembly according to claim 17 of the invention, wherein the β-cap and the pad and the terminal are above the adhesive layer A planar wafer body, wherein the thermal contact is in accordance with the semiconductor wafer assembly of claim 17, wherein the cover is rectangular or square, and the top of the stud is circular. 20. The semiconductor wafer set according to claim 17, wherein the size and shape of the cover are designed to match the surface of the semiconductor component 65 201133729, and the size and shape of the top of the stud is not compatible with the semiconductor The thermal contact surface of the component is designed. 21. A semiconductor wafer package comprising: at least: a semiconductor component; an adhesive layer having at least one opening; a heat sink having at least a stud and a pedestal, wherein the stud is adjacent to the pedestal Forming integrally with the base, and the stud extends above the base in an upward direction, the base extending below the stud in a downward direction opposite to the upward direction, and perpendicular to the upward direction And a side direction extending downward from the protruding column; and a wire comprising at least one pad, a terminal and a routing line, wherein a conductive path between the pad and the terminal comprises the routing line; The semiconductor component is disposed on the heat sink, overlaps the bump, and is electrically connected to the solder pad to be electrically connected to the terminal, and the semiconductor component is thermally coupled to the bump to thermally connect The susceptor is disposed on the susceptor i, extends over the pedestal, extends into a gap between the stud and the squeegee, and the adhesive layer is outside the π Between The adhesive layer between the base and the wire surrounds the protrusion in the lateral direction and extends to the peripheral edge of the group; wherein the wire 5 is placed on the adhesive layer and extends above the base And the pad, the terminal is in contact with the routing line and overlying the adhesive layer; and 66 201133729 wherein the stud extends into the opening, the pedestal extending over the semiconductor component, the adhesive layer and the wire, and The stud is covered from below, the adhesive layer and the wire 'extend to the peripheral edge of the set. The semiconductor wafer package according to claim 21, wherein the semiconductor component is an LED package including an LED chip, and the first solder is disposed on the bonding pad, and a second is utilized. Solder is disposed on the heat sink. The semiconductor device is electrically connected to the pad by the first solder, and is thermally coupled to the heat sink by the second solder. The semiconductor wafer package according to claim 21, wherein the adhesive layer contacts the stud in the notch, and contacts the pedestal, the pad, the terminal and the outside of the notch a routing line, the adhesive layer covering and surrounding the protruding column, covering the wire from below, and covering the base from a part of the protruding column from above, while filling the space between the base and the wire A space. 24. The semiconductor wafer package according to claim 21, wherein the stud is a flat-topped tapered column having a diameter that decreases upward from the pedestal to a flat top of the stud. The top of the column is circular, and a cover system is disposed on the top of the stud, above the top of the stud, adjoining the top of the stud and covering the top of the stud from above. (^ at the same time extending from the top side of the stud in the lateral direction, the sigma body is rectangular or square. 25. According to the semiconductor wafer assembly according to Item 21 of the application (4), wherein the convex The pillar and the adhesive layer are coplanar above the bottom of the wire, and the pad and the terminal are coplanar above the adhesive layer.