TWI416682B - 封裝結構 - Google Patents

封裝結構 Download PDF

Info

Publication number
TWI416682B
TWI416682B TW099129380A TW99129380A TWI416682B TW I416682 B TWI416682 B TW I416682B TW 099129380 A TW099129380 A TW 099129380A TW 99129380 A TW99129380 A TW 99129380A TW I416682 B TWI416682 B TW I416682B
Authority
TW
Taiwan
Prior art keywords
layer
package structure
disposed
wire
semiconductor wafer
Prior art date
Application number
TW099129380A
Other languages
English (en)
Other versions
TW201212186A (en
Inventor
Kun Chen Tsai
Original Assignee
Unimicron Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unimicron Technology Corp filed Critical Unimicron Technology Corp
Priority to TW099129380A priority Critical patent/TWI416682B/zh
Priority to US13/161,685 priority patent/US8786108B2/en
Publication of TW201212186A publication Critical patent/TW201212186A/zh
Application granted granted Critical
Publication of TWI416682B publication Critical patent/TWI416682B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85401—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/85411—Tin (Sn) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85455—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/85464—Palladium (Pd) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

封裝結構
　　本發明係有關一種封裝結構，尤指一種使半導體晶片保持平穩且位置不偏移之封裝結構。
　　隨著半導體封裝技術的演進，除傳統打線式(Wire bonding)及覆晶(Flip chip)之半導體封裝技術外，目前半導體裝置(Semiconductor device)已開發出不同的封裝型態，例如直接在一封裝基板(package substrate) 中嵌埋一晶片，此種封裝件能縮減整體封裝結構之體積並提昇電性功能，且可配合各種封裝形式作變化。
　　請參閱第1A至1D圖，係為習知封裝結構1之製法示意圖。如第1A圖所示，提供一銅基板10，而銅基板10具有相對之第一表面10a與第二表面10b，於該第一表面10a與第二表面10b上分別形成圖案化光阻層110與阻層111，再對該銅基板10進行蝕刻製程，以形成ㄧ容置槽12a與複數凹槽12b。如第1B圖所示，於該容置槽12a之壁面上鍍上第一金屬層120a，且於該凹槽12b之壁面上鍍上第二金屬層120b，再移除該圖案化光阻層110與阻層111。如第1C圖所示，於該容置槽12a底部之第一金屬層120a上塗佈黏膠層15以黏置半導體晶片13，該半導體晶片13具有複數電極墊130，以藉由導線14電性連接該第二金屬層120b。接著，於該銅基板10上形成封裝膠體17，以包覆該半導體晶片13與導線14。如第1D圖所示，移除該銅基板10，以外露該第一金屬層120a及第二金屬層120b，且該第二金屬層120b係作為凸接點16。該半導體晶片13上之電極墊130可經由導線14與凸接點16而外接至印刷電路板。
　　然，習知技術中，因該容置槽12a與凹槽12b係經蝕刻製程所形成之，導致於槽底必定產生不平整之現象，以致於當該半導體晶片13置放於該容置槽12a中時，會造成不平穩且偏移的問題；且該封裝體無強化結構，遇外力易彎曲變形。
　　再者，當蝕刻去除該銅基板10，因該容置槽12a與凸接點16間的厚度差異，需較多蝕刻時間，容易造成該第一金屬層120a及第二金屬層120b受損。
　　因此，如何避免習知封裝結構之種種缺失，實已成為目前亟欲解決的課題。
　　鑑於上述習知技術之種種缺失，本發明之一目的係在提供一種封裝結構，能使其半導體晶片保持平穩且位置不偏移，並使封裝結構具一定強度不易彎曲變形。
　　本發明之另一目的在於提供一種封裝結構，能使其打線墊於封裝時不會受損。
　　為達上述及其他目的，本發明揭露一種封裝結構，係包括：介電層，係具有相對之第一表面及第二表面，且具有複數貫穿該第一及第二表面之穿孔；強化層，係設於該介電層之第一表面上；線路層，係設於該介電層之第二表面上，且該線路層具有複數外露於各該穿孔之打線墊及電性連接該打線墊之植球墊；第一防焊層，係設於該介電層之第一表面及強化層上，且該第一防焊層形成複數第一開孔，以令各該打線墊外露於各該第一開孔；第二防焊層，係設於該介電層之第二表面及線路層上，而該第二防焊層形成複數第二開孔，以令各該植球墊外露於各該第二開孔；以及半導體晶片，係設於該第一防焊層上，且該半導體晶片藉由導線電性連接外露於各該穿孔之打線墊。
　　前述之封裝結構中，該半導體晶片具有相對之作用面及非作用面，該作用面具有複數電性連接各該導線之電極墊，該非作用面結合至該第一防焊層上。
　　前述之封裝結構復包括表面處理層，係設於該打線墊及植球墊上，且形成該表面處理層之材料係選自由電鍍鎳/金、化學鍍鎳/金、化鎳浸金（ENIG）、化鎳鈀浸金（ENEPIG）、化學鍍錫（Immersion Tin）及有機保焊劑 (OSP)所組成之群組中之其中一者。
　　前述之封裝結構復包括焊球，係設於該第二開孔中之植球墊上。
　　前述之封裝結構復包括封裝膠體，係設於該第一防焊層上、第一開孔及穿孔中，以覆蓋半導體晶片、導線及各該打線墊。
　　由上可知，本發明封裝結構因該強化層之表面未受破壞，故形成於其上之第一防焊層係保持平整；相較於習知技術，當該半導體晶片置放於該第一防焊層上時，該半導體晶片可保持平穩且位置不偏移。再者，因貫穿之穿孔不須經長時間蝕刻而得，以令形成開孔後不會傷及打線墊及植球墊，因而提升電性連接之品質。
　　以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
　　請參閱第2A至2E圖，係為本發明所提供之封裝結構2之其中ㄧ種製法的剖視示意圖。
　　如第2A圖所示，提供一介電層20，係具有相對之第一表面20a及第二表面20b，且於該介電層20之第一及第二表面20a,20b上分別具有強化層21a及金屬層200。其中，形成該強化層21a之材質係金屬材質，例如：銅。
　　如第2B圖所示，進行圖案化製程，以令該金屬層200形成線路層21b，且該線路層21b具有複數打線墊210及電性連接該打線墊210之植球墊211，而於該強化層21a上形成複數對應該打線墊210之開口210a，以外露出該介電層20之部分第一表面20a。
　　如第2C圖所示，於該介電層20之第一表面20a及強化層21a上形成第一防焊層22a，而於該介電層20之第二表面20b及線路層21b上形成第二防焊層22b；且於該第一防焊層22a上形成複數對應該開口210a且尺寸小於該開口210a之第一開孔220a，以外露出該介電層20之部分第一表面20a。又於該第二防焊層22b上形成複數外露該植球墊211之第二開孔220b。
　　如第2D圖所示，於該第一開孔220a中形成貫穿該介電層20之穿孔201，以外露出各該打線墊210。
　　如第2E圖所示，於該第一防焊層22a上結合半導體晶片23，且該半導體晶片23藉由導線24經該穿孔201以電性連接各該打線墊210，又於該第一防焊層22a上、第一開孔220a及穿孔201中形成封裝膠體27，以覆蓋半導體晶片23、導線24及各該打線墊210；最後，可於該第二開孔220b中之植球墊211上結合焊球26，以供電性連接至印刷電路板。
　　然，於形成該導線24與焊球26之前，可先於該打線墊210及植球墊211上形成表面處理層25，且形成該表面處理層25之材料係選自由電鍍鎳/金、化學鍍鎳/金、化鎳浸金（ENIG）、化鎳鈀浸金（ENEPIG）、化學鍍錫（Immersion Tin）及有機保焊劑 (OSP)所組成之群組中之其中一者。
　　本發明之封裝結構2中，因該強化層21a除開口210a外之表面並未受破壞，故形成於該強化層21a上之第一防焊層22a係保持平整；因此，當該半導體晶片23置放於該第一防焊層22a上時，可避免習知技術中之不平穩與偏移的問題。
　　再者，因該穿孔201係僅貫穿該介電層20而未破壞該打線墊210表面，故該打線墊210表面係保持平整；且該穿孔201因介電層20厚度一致，並不需要長時間蝕刻，可避免習知技術中之外接凸點之金屬層受損之問題。
　　由上可知，本發明之封裝結構2係包括：具有相對之第一及第二表面20a,20b之介電層20、設於該介電層20之第一表面20a上之強化層21a、設於該介電層20之第二表面20b上之線路層21b、設於該介電層20之第一表面20a及強化層21a上之第一防焊層22a、設於該介電層20之第二表面20b及線路層21b上之第二防焊層22b、以及設於該第一防焊層22a上之半導體晶片23。
　　所述之介電層20具有複數貫穿該第一及第二表面20a,20b之穿孔201。
　　所述之強化層21a係用以支撐及加強結構。
　　所述之線路層21b具有複數外露於各該穿孔201之打線墊210及電性連接該打線墊210之植球墊211。
　　所述之第一防焊層22a形成複數對應該穿孔201之第一開孔220a，以令各該打線墊211外露於各該第一開孔220a。
　　所述之第二防焊層22b形成複數第二開孔220b，以令各該植球墊211外露於各該第二開孔220b。
　　所述之半導體晶片23具有相對之作用面23a及非作用面23b，該作用面23a具有複數電極墊230以藉由導線24電性連接外露於各該穿孔之打線墊，該非作用面23b結合至該第一防焊層22a上。
　　所述之封裝結構2復包括表面處理層25，係設於該打線墊210及植球墊211上，且形成該表面處理層25之材料係選自由電鍍鎳/金、化學鍍鎳/金、化鎳浸金（ENIG）、化鎳鈀浸金（ENEPIG）、化學鍍錫（Immersion Tin）及有機保焊劑 (OSP)所組成之群組中之其中一者。
　　所述之封裝結構2復包括焊球26，係設於該第二開孔220b中之植球墊211上。
　　所述之封裝結構2復包括封裝膠體27，係設於該第一防焊層22a上、第一開孔220a及穿孔201中，以覆蓋半導體晶片23、導線24及各該打線墊210。
　　綜上所述，本發明封裝結構因該強化層之表面未受破壞，故形成於其上之第一防焊層係保持平整；因此，當該半導體晶片置放於該第一防焊層上時，該半導體晶片可保持平穩且位置不偏移，以利於導線之接置而提升電性連接之品質。
　　再者，因貫穿之穿孔未破壞該打線墊表面，故該打線墊表面係保持平整；且該穿孔因介電層厚度一致，並不需要長時間蝕刻，而造成該打線墊受損，以利於電性導通而提升電性連接之品質。
　　上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
1,2‧‧‧封裝結構
10‧‧‧銅基板
10a,20a‧‧‧第一表面
10b,20b‧‧‧第二表面
110‧‧‧圖案化光阻層
111‧‧‧阻層
12a‧‧‧容置槽
12b‧‧‧凹槽
120a‧‧‧第一金屬層
120b‧‧‧第二金屬層
13,23‧‧‧半導體晶片
130,230‧‧‧電極墊
14,24‧‧‧導線
15‧‧‧黏膠層
16‧‧‧凸接點
17,27‧‧‧封裝膠體
20‧‧‧介電層
200‧‧‧金屬層
201‧‧‧穿孔
21a‧‧‧強化層
210a‧‧‧開口
21b‧‧‧線路層
210‧‧‧打線墊
211‧‧‧植球墊
22a‧‧‧第一防焊層
22b‧‧‧第二防焊層
220a‧‧‧第一開孔
220b‧‧‧第二開孔
23a‧‧‧作用面
23b‧‧‧非作用面
25‧‧‧表面處理層
26‧‧‧焊球
　　第1A至1D圖係為習知封裝結構之製法的剖視示意圖；
　　第2A至2E圖係為本發明封裝結構之製法的剖視示意圖；
　　第3A圖係為本發明封裝結構未形成封裝膠體的上視示意圖；以及
　　第3B圖係為本發明封裝結構未形成封裝膠體的下視示意圖。
2‧‧‧封裝結構
20‧‧‧介電層
20a‧‧‧第一表面
20b‧‧‧第二表面
201‧‧‧穿孔
21a‧‧‧強化層
21b‧‧‧線路層
210‧‧‧打線墊
211‧‧‧植球墊
22a‧‧‧第一防焊層
22b‧‧‧第二防焊層
220a‧‧‧第一開孔
220b‧‧‧第二開孔
23‧‧‧半導體晶片
23a‧‧‧作用面
23b‧‧‧非作用面
230‧‧‧電極墊
24‧‧‧導線
25‧‧‧表面處理層
26‧‧‧焊球
27‧‧‧封裝膠體

Claims (6)

  1. 一種封裝結構，係包括：
    　　介電層，係具有相對之第一表面及第二表面，且具有複數貫穿該第一及第二表面之穿孔；
    　　強化層，係設於該介電層之第一表面上；
    　　線路層，係設於該介電層之第二表面上，且該線路層具有複數外露於各該穿孔之打線墊及電性連接該打線墊之植球墊；
    　　第一防焊層，係設於該介電層之第一表面及強化層上，且該第一防焊層形成複數第一開孔，以令各該打線墊外露於各該第一開孔；
    　　第二防焊層，係設於該介電層之第二表面及線路層上，而該第二防焊層形成複數第二開孔，以令各該植球墊外露於各該第二開孔；以及
    　　半導體晶片，係設於該第一防焊層上，且該半導體晶片藉由導線電性連接外露於各該穿孔之打線墊。
  2. 如申請專利範圍第1項所述之封裝結構，其中，該半導體晶片具有相對之作用面及非作用面，該作用面具有複數電性連接各該導線之電極墊，該非作用面結合至該第一防焊層上。
  3. 如申請專利範圍第1項所述之封裝結構，復包括表面處理層，係設於該打線墊及植球墊上。
  4. 如申請專利範圍第3項所述之封裝結構，其中，形成該表面處理層之材料係選自由電鍍鎳/金、化學鍍鎳/金、化鎳浸金（ENIG）、化鎳鈀浸金（ENEPIG）、化學鍍錫（Immersion Tin）及有機保焊劑 (OSP)所組成之群組中之其中一者。
  5. 如申請專利範圍第1或3項所述之封裝結構，復包括焊球，係設於該第二開孔中之植球墊上。
  6. 如申請專利範圍第1、3或5項所述之封裝結構，復包括封裝膠體，係設於該第一防焊層上、第一開孔及穿孔中，以覆蓋半導體晶片、導線及各該打線墊。
TW099129380A 2010-09-01 2010-09-01 封裝結構 TWI416682B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW099129380A TWI416682B (zh) 2010-09-01 2010-09-01 封裝結構
US13/161,685 US8786108B2 (en) 2010-09-01 2011-06-16 Package structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW099129380A TWI416682B (zh) 2010-09-01 2010-09-01 封裝結構

Publications (2)

Publication Number Publication Date
TW201212186A TW201212186A (en) 2012-03-16
TWI416682B true TWI416682B (zh) 2013-11-21

Family

ID=45696040

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099129380A TWI416682B (zh) 2010-09-01 2010-09-01 封裝結構

Country Status (2)

Country Link
US (1) US8786108B2 (zh)
TW (1) TWI416682B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI480989B (zh) * 2012-10-02 2015-04-11 矽品精密工業股份有限公司 半導體封裝件及其製法
JP6125332B2 (ja) * 2013-05-31 2017-05-10 ルネサスエレクトロニクス株式会社 半導体装置
CN106847713B (zh) * 2016-12-29 2019-03-01 清华大学 卷对卷制作扇出型封装结构的方法和扇出型封装结构

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201003866A (en) * 2008-07-04 2010-01-16 Phoenix Prec Technology Corp Package substrate
TW201026189A (en) * 2008-12-24 2010-07-01 Via Tech Inc Circuit board and fabrication method thereof and chip package structure

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003007918A (ja) 2001-06-19 2003-01-10 Sanyo Electric Co Ltd 回路装置の製造方法
US20050253245A1 (en) * 2004-05-12 2005-11-17 Mark Lynch Package design and method for electrically connecting die to package
US7985980B2 (en) 2007-10-31 2011-07-26 Sharp Kabushiki Kaisha Chip-type LED and method for manufacturing the same
JP2009194079A (ja) * 2008-02-13 2009-08-27 Panasonic Corp 半導体装置用配線基板とその製造方法及びそれを用いた半導体装置
CN101515574B (zh) 2008-02-18 2011-06-22 旭德科技股份有限公司 芯片封装载板、芯片封装体及其制造方法
TW201041105A (en) 2009-05-13 2010-11-16 Advanced Semiconductor Eng Substrate having single patterned metal layer, and package applied with the same, and methods of manufacturing the substrate and package

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201003866A (en) * 2008-07-04 2010-01-16 Phoenix Prec Technology Corp Package substrate
TW201026189A (en) * 2008-12-24 2010-07-01 Via Tech Inc Circuit board and fabrication method thereof and chip package structure

Also Published As

Publication number Publication date
US20120049363A1 (en) 2012-03-01
TW201212186A (en) 2012-03-16
US8786108B2 (en) 2014-07-22

Similar Documents

Publication Publication Date Title
TWI420634B (zh) 封裝結構及其製法
TWI418003B (zh) 嵌埋電子元件之封裝結構及其製法
US7105918B2 (en) Interposer with flexible solder pad elements and methods of manufacturing the same
TWI395274B (zh) 製造電路基材的方法及製造電子部件封裝結構的方法
US8859912B2 (en) Coreless package substrate and fabrication method thereof
TWI446508B (zh) 無核心式封裝基板及其製法
US20130249083A1 (en) Packaging substrate
TWI496258B (zh) 封裝基板之製法
TW201106453A (en) Package substrate having embedded semiconductor chip
JP2017163027A (ja) 配線基板、半導体装置及び配線基板の製造方法
JP5117270B2 (ja) 配線基板、半導体装置、ならびに半導体装置の製造方法
KR20110064471A (ko) 패키지 기판 및 그의 제조방법
TWI416682B (zh) 封裝結構
JP2009528707A (ja) 多層パッケージ構造物及びその製造方法
TWI419630B (zh) 嵌入式印刷電路板及其製造方法
TW201622025A (zh) 單層線路式封裝基板及其製法、單層線路式封裝結構及其製法
TWI419278B (zh) 封裝基板及其製法
TWI520278B (zh) 嵌埋有晶片之封裝結構的製法
TWI394250B (zh) 封裝結構及其製法
TWI508197B (zh) 半導體封裝件及其製法
US20110061907A1 (en) Printed circuit board and method of manufacturing the same
TWI407542B (zh) 嵌埋半導體元件之電路板及其製法
TWI418006B (zh) 單層線路之封裝基板及其製法暨封裝結構
TWI541952B (zh) 半導體封裝件及其製法
TW201324715A (zh) 封裝基板及其製法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees