TWI416625B - Plasma-etching apparatus and method for doping or contact region definition on surface layer of semiconductor by using the same - Google Patents
Plasma-etching apparatus and method for doping or contact region definition on surface layer of semiconductor by using the same Download PDFInfo
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Abstract
Description
本發明係關於一種電漿蝕刻裝置及以該裝置選擇摻雜區的半導體製程方法，特別是針對太陽能電池選擇性射極(selective emitter)及背電極(back contact)結構的製備方法。The present invention relates to a plasma etching apparatus and a semiconductor processing method for selecting a doping region by the apparatus, particularly for a solar cell selective emitter and a back contact structure.
近年來，由於環保意識的抬頭和其他能源逐漸的枯竭，使得世界各國開始重視再生能源的利用。由於太陽光是取之不盡，用之不竭的天然能源，除了沒有能源耗盡的問題之外，也可以避免能源被壟斷的問題。In recent years, due to the rise of environmental awareness and the gradual depletion of other energy sources, countries around the world have begun to pay attention to the use of renewable energy. Because the sun is inexhaustible, inexhaustible natural energy, in addition to the problem of no energy exhaustion, can also avoid the problem of energy monopoly.
然而，目前太陽能電池的光電轉換效率以及其製造成本，還未滿足取代目前石化能源的條件，因此，如何增加太陽能源的收集與利用，以降低對石化能源的依賴，是目前最熱門的研究課題之一。However, the photoelectric conversion efficiency and manufacturing cost of solar cells have not yet met the conditions for replacing the current petrochemical energy. Therefore, how to increase the collection and utilization of solar energy sources to reduce dependence on petrochemical energy is currently the most popular research topic. one.
請參考圖1A~1G，為習知的太陽能電池製程的剖面示意圖。首先提供一半導體基材1，經過清洗後，將晶圓表面的雜質及污染物去除，如圖1A。接著，以酸液將基材1表面蝕刻成粗糙面，降低入射光之反射率，使入射光能得以充分利用，如圖1B。Please refer to FIGS. 1A-1G for a schematic cross-sectional view of a conventional solar cell process. First, a semiconductor substrate 1 is provided. After cleaning, impurities and contaminants on the surface of the wafer are removed, as shown in FIG. 1A. Next, the surface of the substrate 1 is etched into a rough surface with an acid solution to reduce the reflectance of the incident light, so that the incident light energy can be fully utilized, as shown in FIG. 1B.
接著請參照圖1C，一P型半導體基材1，在一含氧氣氛導入含N型導電性雜質的氣體，例如：P2 O5 、PH3 或PF3 之退火爐管進行雜質擴散製程，以形成一摻雜層10於P型半導體基材1上，產生光電轉換效應所需的P-N介面。與此同時，在N型區域10表層也會同時形成一磷的氧化層11(P2 O5 )，因此，在下一步驟中，需再以蝕刻移除。否則以後續製程形成電極後，會增加電極與摻雜層10的串聯電阻，如圖1D所示。Next, referring to FIG. 1C, a P-type semiconductor substrate 1 is introduced into an annealing furnace tube containing an N-type conductive impurity, such as P 2 O 5 , PH 3 or PF 3 , in an oxygen-containing atmosphere to carry out an impurity diffusion process. To form a doped layer 10 on the P-type semiconductor substrate 1, a PN interface required for the photoelectric conversion effect is produced. At the same time, a phosphorous oxide layer 11 (P 2 O 5 ) is also formed in the surface layer of the N-type region 10, and therefore, in the next step, it is removed by etching. Otherwise, after forming the electrode in a subsequent process, the series resistance of the electrode and the doped layer 10 is increased, as shown in FIG. 1D.
接著，請參照圖1E，為了提高光的轉換效率，一層抗反射層13被形成於摻雜層10上，緊接著在圖1F中顯示利用一刮棒16以網印方式將金屬漿料14印製於預定位置。最後，以燒結方式，使金屬漿料14穿透正面抗反射層13並滲入半導體基材1表層的摻雜層10緊密結合，以形成電極來使電流導出，如圖1G所示。Next, referring to FIG. 1E, in order to improve the light conversion efficiency, an anti-reflection layer 13 is formed on the doped layer 10, and then, in FIG. 1F, the metal paste 14 is printed by screen printing using a bar 16 Made at a predetermined location. Finally, in a sintering manner, the doping layer 10 of the metal paste 14 penetrating the front anti-reflective layer 13 and penetrating into the surface layer of the semiconductor substrate 1 is tightly bonded to form an electrode to conduct current, as shown in FIG. 1G.
一般說來，太陽能電池電極14下方的摻雜層10內導電性雜質摻雜濃度愈高，愈能形成良好的歐姆接觸，將電流導出。然而，重摻雜雖然可以降低電極14與摻雜層10的串聯電阻，卻會提高電子和電洞(hole)再復合(recombination)的機率而降低光電轉換效率。In general, the higher the doping concentration of the conductive impurities in the doped layer 10 under the solar cell electrode 14, the better the formation of a good ohmic contact, and the current is derived. However, although heavy doping can reduce the series resistance of the electrode 14 and the doped layer 10, it increases the probability of electron and hole recombination and reduces the photoelectric conversion efficiency.
為了提高太陽能電池的光電轉換效率，目前又發展了具有選擇性射極(selective emitter)及背電極(back contact)結構的太陽能電池。上述兩種太陽能電池在進行擴散摻雜的製程時，都需要先定義摻雜的區域。In order to improve the photoelectric conversion efficiency of a solar cell, a solar cell having a selective emitter and a back contact structure has been developed. In the above two types of solar cells, in the process of performing diffusion doping, it is necessary to define a doped region first.
比如，具有選擇性射極(selective emitter)結構的太陽能電池中，只加重在金屬電極下方的摻雜濃度，電極導線外的吸光面則是輕摻雜的，以減少電子-電洞對再復合的機會。For example, in a solar cell with a selective emitter structure, only the doping concentration under the metal electrode is emphasized, and the light absorbing surface outside the electrode wire is lightly doped to reduce the electron-hole pair recombination. chance.
而具有背電極(back contact)結構的太陽能電池是直接將P-N電極製備於太陽能電池基板背面，所以，在製備過程中，要在太陽能電池基板背面分別定義出P或N型導電性雜質的摻雜區。此種太陽能電池的優點是吸光面沒有金屬遮蔽效應的問題，也不用擔心摻雜層內電子-電洞對再復合機率過高，而造成光電轉換效率降低。The solar cell with a back contact structure directly prepares the PN electrode on the back surface of the solar cell substrate. Therefore, in the preparation process, the doping of P or N type conductive impurities is respectively defined on the back surface of the solar cell substrate. Area. The advantage of such a solar cell is that the light absorbing surface has no metal shadowing effect, and there is no need to worry that the electron-hole pairing ratio in the doped layer is too high, resulting in a decrease in photoelectric conversion efficiency.
習知的技術是採用雷射來輔助形成重摻雜區，或是在網印金屬漿料時，添加欲摻雜的雜質，如：磷的化合物於金屬漿料中。使金屬漿料被燒結，穿透抗反射層與半導體基材結合時，同時將磷摻入半導體基材中。Conventional techniques use lasers to assist in forming heavily doped regions, or to add impurities to be doped, such as phosphorus compounds, to the metal paste during screen printing of the metal paste. The metal paste is sintered, and when the antireflection layer is bonded to the semiconductor substrate, phosphorus is simultaneously incorporated into the semiconductor substrate.
然而，雷射輔助摻雜成本高，且製程時間長；而在網印及燒結形成電極的製程同時做摻雜的動作，其製程參數不易控制，難以兼顧歐姆接觸的效果及摻雜的濃度。However, the laser-assisted doping cost is high, and the processing time is long. However, in the process of screen printing and sintering forming electrodes, the process parameters are difficult to control, and it is difficult to balance the effect of ohmic contact and the concentration of doping.
有鑒於此，開發新的設備及製程方法，應用於需要選區摻雜技術的太陽能電池製程，為當前重要的研發課題之一。In view of this, the development of new equipment and process methods for solar cell processes requiring selective doping technology is one of the current important research and development topics.
有鑒於上述課題，本發明之目的係提供一種電漿蝕刻裝置，可針對一鍍有抗反射層或隔絕層的半導體基材預設的區域進行選擇性蝕刻，以定義出後續進行摻雜的區域或接觸區，其特徵在於，電漿蝕刻裝置包括一選擇性蝕刻遮板，當進行蝕刻製程時，以選擇性蝕刻遮板為罩冪，對半導體基材進行非等向性蝕刻，產生一開放迴路圖案。In view of the above problems, an object of the present invention is to provide a plasma etching apparatus capable of selectively etching a predetermined region of a semiconductor substrate plated with an anti-reflection layer or an isolation layer to define a region to be subsequently doped. Or a contact region, characterized in that the plasma etching device comprises a selective etching mask, and when the etching process is performed, the semiconductor substrate is anisotropically etched by using a selective etching mask to generate an open Loop pattern.
本發明之另一目的是提供一種以選擇性蝕刻遮板選擇摻雜區的半導體製程方法，包括：提供一摻雜第一型導電性雜質的半導體基材；形成一抗反射層或隔絕層於半導體基材表面；對半導體基材施以一非等向性蝕刻，以一選擇性蝕刻遮板為罩冪，以產生一蝕刻圖案；及施以一擴散製程，以第二型導電性雜質為擴散雜質，用以在半導體基材表層蝕刻圖案開口形成摻雜區。Another object of the present invention is to provide a semiconductor process for selectively etching a mask to select a doped region, comprising: providing a semiconductor substrate doped with a first type of conductive impurity; forming an anti-reflective layer or an insulating layer a surface of the semiconductor substrate; applying an anisotropic etch to the semiconductor substrate, using a selective etch mask as a mask to generate an etch pattern; and applying a diffusion process to the second type of conductive impurities Diffusion impurities are used to etch pattern openings in the surface of the semiconductor substrate to form doped regions.
如果要形成太陽能電池背電極，則半導體基材需要先完成清潔、粗糙化處理(surface texturing)，並且，半導體基材正面形成第一型導電性雜質重摻雜層。而對半導體基材進行非等向性蝕刻時，是針對在半導體基材背面進行此一蝕刻製程，並且，形成摻雜區之後，網印金屬漿料於摻雜區，施以一燒結處理，以使金屬漿料形成電極。If a solar cell back electrode is to be formed, the semiconductor substrate needs to be cleaned and surface texturing first, and a first type of conductive impurity heavily doped layer is formed on the front surface of the semiconductor substrate. When the semiconductor substrate is anisotropically etched, the etching process is performed on the back surface of the semiconductor substrate, and after the doping region is formed, the screen printing metal paste is subjected to a sintering treatment in the doping region. The metal paste is formed into an electrode.
若要形成太陽能電池選擇性射極結構，則將抗反射層形成於半導體基材正面，且抗反射層厚度大約30 nm至50 nm，以在施以該擴散製程之後，於抗反射層下方形成一輕摻雜區，在蝕刻圖案開口形成一重摻雜區。最後，網印金屬漿料於蝕刻圖案開口，施以一燒結處理，使金屬漿料形成電極。To form a solar cell selective emitter structure, an anti-reflective layer is formed on the front surface of the semiconductor substrate, and the anti-reflection layer has a thickness of about 30 nm to 50 nm to form under the anti-reflection layer after the diffusion process is applied. A lightly doped region forms a heavily doped region in the etched pattern opening. Finally, the screen printing metal paste is etched into the pattern opening, and a sintering treatment is applied to form the metal paste to form an electrode.
另一種方式，是在半導體基材鍍抗反射層之前，對半導體基材正面進行第一次擴散製程，以第二型導電性雜質為擴散雜質，在半導體基材表層形成一輕摻雜層，使得施以擴散製程之後，於蝕刻圖案開口的半導體基材表層形成重摻雜區，之後同樣以網印金屬漿料的方式在重摻雜區形成電極。其中，蝕刻圖案開口係為在半導體基材上預定形成匯流排(bus bar)及柵線(grid line)的位置。In another method, before the anti-reflection layer is coated on the semiconductor substrate, the first diffusion process is performed on the front surface of the semiconductor substrate, and the second type conductivity impurity is used as a diffusion impurity to form a lightly doped layer on the surface of the semiconductor substrate. After the diffusion process is applied, a heavily doped region is formed on the surface of the semiconductor substrate in which the pattern is opened, and then the electrode is formed in the heavily doped region in the same manner as the screen printed metal paste. The etched pattern opening is a position on the semiconductor substrate where a bus bar and a grid line are predetermined to be formed.
第三種形成太陽能電池選擇性射極結構的方式，係針對半導體基材正面形成抗反射層及進行非等向性蝕刻，並且，對半導體基材進行擴散製程時，係網印一含有第二型導電性雜質化合物的金屬漿料於蝕刻圖案開口，並施以一燒結處理，使金屬漿料中所含的第二型導電性雜質擴散進入半導體表層的輕摻雜層，在形成重摻雜區的同時形成電極。The third way to form the selective emitter structure of the solar cell is to form an anti-reflective layer on the front surface of the semiconductor substrate and perform anisotropic etching, and when the semiconductor substrate is subjected to a diffusion process, the screen printing has a second The metal paste of the type of conductive impurity compound is opened in the etching pattern, and a sintering treatment is applied to diffuse the second type conductivity impurities contained in the metal paste into the lightly doped layer of the semiconductor surface layer to form a heavily doped layer. The electrodes are formed simultaneously at the regions.
本發明所提供的電漿蝕刻裝置不但方法簡便，成本低廉，並且，容易和現有太陽能製程整合在一起，產生多種應用方式。關於本發明的優點與精神可以藉由以下的發明詳述及所附圖式得到進一步的瞭解。The plasma etching device provided by the invention is not only simple in method, low in cost, but also easy to integrate with existing solar energy processes, and produces various application modes. The advantages and spirit of the present invention will be further understood from the following detailed description of the invention.
為使本發明之上述目的、特徵和優點能更明顯易懂，下文依本發明電漿蝕刻裝置及其應用於選擇摻雜區或接觸區的半導體製程的方法，特舉較佳實施例，並配合所附相關圖式，作詳細說明如下，其中相同的元件將以相同的元件符號加以說明。要說明的是，圖中各區域尺寸比例僅為方便指明相對位置，而非實際結構之放大。In order to make the above objects, features and advantages of the present invention more comprehensible, the following is a preferred embodiment of the plasma etching apparatus and its method for selecting a semiconductor process for selecting a doping region or a contact region, and The detailed description is as follows with reference to the accompanying drawings, wherein the same elements will be described with the same element symbols. It should be noted that the size ratio of each area in the figure is only for convenience to indicate the relative position, rather than the enlargement of the actual structure.
請參照圖2A，本發明的電漿蝕刻裝置2，可針對一鍍有抗反射層或隔絕層的半導體基材預設的區域進行選擇性蝕刻以定義出摻雜區或接觸區。本發明電漿蝕刻裝置2的特徵在於使用一選擇性蝕刻遮板21。當進行蝕刻製程時，以選擇性蝕刻遮板21為罩冪，對半導體基材23進行非等向性蝕刻，產生一開放圖案開口。Referring to FIG. 2A, the plasma etching apparatus 2 of the present invention can selectively etch a predetermined region of a semiconductor substrate plated with an anti-reflection layer or an isolation layer to define a doped region or a contact region. The plasma etching apparatus 2 of the present invention is characterized in that a selective etching shutter 21 is used. When the etching process is performed, the semiconductor substrate 23 is anisotropically etched by selectively etching the shutter 21 to generate an open pattern opening.
選擇性蝕刻遮板21表面需選擇抗蝕刻的材料，在本發明實施例中，選擇性蝕刻遮板21的材質選自單晶矽、鐵氟龍鍍膜、氧化鋁鍍膜其中之一種。選擇性蝕刻遮板21所定義的圖案可以依照製程的需求來設計。In the embodiment of the present invention, the material of the selective etching mask 21 is selected from one of a single crystal germanium, a Teflon coating, and an aluminum oxide coating. The pattern defined by the selective etch mask 21 can be designed according to the needs of the process.
本發明的電漿蝕刻裝置2包括一反應室20，反應室內包括一載台22、一冷卻裝置24、一極板25及一端點偵測器26。極板25與一射頻電源相連接，在氣體通入時，由射頻電源對極板25加偏壓以產生電漿。載台22用來承載半導體基材23，且在載台22中並設置冷卻裝置24。端點偵測器26設置於反應室20側壁，係用來回饋製程的時間。而選擇性蝕刻遮板21與半導體基材23之間距可依實際蝕刻結果做調整。The plasma etching apparatus 2 of the present invention includes a reaction chamber 20 including a stage 22, a cooling unit 24, a plate 25 and an end point detector 26. The plate 25 is connected to a radio frequency power source that is biased by the RF power source to generate plasma as the gas is introduced. The stage 22 is used to carry the semiconductor substrate 23, and a cooling device 24 is disposed in the stage 22. The endpoint detector 26 is disposed on the side wall of the reaction chamber 20 and is used to feed back the process time. The distance between the selective etch mask 21 and the semiconductor substrate 23 can be adjusted according to the actual etching result.
電漿蝕刻裝置2也可以同時針對複數片半導體基材23做處理。只要改變載台22的尺寸，使之能夠承載多片基材，並於選擇性蝕刻遮板21定義多個重複的蝕刻圖案，一一對準不同的半導體基材，就可以讓多個半導體基材23同步進行蝕刻。The plasma etching apparatus 2 can also simultaneously process a plurality of semiconductor substrates 23. As long as the size of the stage 22 is changed to carry a plurality of substrates, and a plurality of repeated etching patterns are defined in the selective etching mask 21, and the semiconductor substrates are aligned one by one, a plurality of semiconductor bases can be made. The material 23 is etched simultaneously.
請參照圖2B，為本發明一實施例選擇性蝕刻遮板21的俯視示意圖。在本實施例中，係配合太陽能電池背電極的製程，將選擇性蝕刻遮板21的圖案定義成具有複數根梳齒的梳狀圖案開口210，梳齒之間具有一預定距離，使後續要進行擴散製程時，擴散的區域不至於相互重疊。Please refer to FIG. 2B , which is a top plan view of a selective etching mask 21 according to an embodiment of the invention. In this embodiment, the pattern of the selective etching shutter 21 is defined as a comb-like pattern opening 210 having a plurality of comb teeth in combination with the process of the solar cell back electrode, and the comb teeth have a predetermined distance therebetween, so that the subsequent When the diffusion process is performed, the diffused regions do not overlap each other.
若要在半導體基材23表面形成封閉迴路圖案，可將蝕刻製程分為兩個階段，並在兩次蝕刻製程中使用兩個不同的選擇性蝕刻遮板做為罩冪。To form a closed loop pattern on the surface of the semiconductor substrate 23, the etching process can be divided into two stages, and two different selective etching masks are used as a mask power in the two etching processes.
圖3A及圖3B中分別為第一選擇性蝕刻遮板21a及第二選擇性蝕刻遮板21b的俯視示意圖。本實施例中，是配合太陽能電池選擇性射極(selective emitter)結構的製程，將第一及第二選擇性蝕刻遮板21a、21b的圖案分別定義為匯流排(bus bar)及柵線(grid line)圖案212、214，即代表在後續製程中將要形成匯流排及柵線的位置。應用選擇性蝕刻遮板於製程的方法將於後文詳細描述。3A and 3B are top plan views of the first selective etch mask 21a and the second selective etch shutter 21b, respectively. In this embodiment, the pattern of the selective emitter structure of the solar cell is defined, and the patterns of the first and second selective etching shutters 21a and 21b are respectively defined as a bus bar and a gate line ( The grid lines) 212, 214 represent the locations where the busbars and grid lines are to be formed in subsequent processes. The method of applying the selective etching mask to the process will be described in detail later.
當然，匯流排及柵線的位置會依據美觀需求做不同的調整，所以，選擇性蝕刻遮板所定義的圖案也可以因應匯流排及柵線的位置做不同的變化，並不限於本實施例中所採用的圖案。Certainly, the positions of the bus bar and the grid line are adjusted differently according to the aesthetic requirements. Therefore, the pattern defined by the selective etching mask can also be changed according to the position of the bus bar and the grid line, and is not limited to the embodiment. The pattern used in the film.
兩階段的製程可以在同一個反應室中，以更換選擇性蝕刻遮板的方式完成。在另一較佳實施例中，如圖3C所示，電漿蝕刻裝置2可以包括一第一反應室20a、一第二反應室20b及一傳輸裝置27。第一及第二選擇性蝕刻遮板21a、21b分別設置於第一反應室20a及第二反應室20b內。半導體基材23在第一反應室20a完成第一階段蝕刻製程之後，再由傳輸裝置27傳送至第二反應室20b來完成第二階段蝕刻製程。The two-stage process can be done in the same reaction chamber by replacing the selective etch mask. In another preferred embodiment, as shown in FIG. 3C, the plasma etching apparatus 2 may include a first reaction chamber 20a, a second reaction chamber 20b, and a transfer device 27. The first and second selective etching shutters 21a, 21b are disposed in the first reaction chamber 20a and the second reaction chamber 20b, respectively. After the first reaction chamber 20a completes the first-stage etching process, the semiconductor substrate 23 is transferred from the transfer device 27 to the second reaction chamber 20b to complete the second-stage etching process.
本發明並提供以選擇性蝕刻遮板選擇摻雜區的半導體製程方法，包括下列步驟。首先，提供一摻雜第一型導電性雜質的半導體基材。形成一抗反射層或隔絕層於半導體基材表面之後，對半導體基材施以一非等向性蝕刻，以前述的選擇性蝕刻遮板為罩冪，產生一蝕刻圖案開口。最後，施以一擴散製程，以第二型導電性雜質為擴散雜質，用以在半導體基材表層蝕刻圖案開口形成摻雜區。The present invention also provides a semiconductor process method for selectively etching a mask to select a doped region, including the following steps. First, a semiconductor substrate doped with a first type of conductive impurity is provided. After forming an anti-reflective layer or insulating layer on the surface of the semiconductor substrate, an anisotropic etching is applied to the semiconductor substrate, and the selective etching mask is used as a mask to generate an etching pattern opening. Finally, a diffusion process is applied, and the second type of conductive impurities are used as diffusion impurities for etching the pattern openings on the surface of the semiconductor substrate to form doped regions.
此處以形成太陽能電池背電極及選擇性射極結構的製程為實施例。請參照圖4A至圖4F，為太陽能電池背電極的製備流程圖。Here, a process for forming a solar cell back electrode and a selective emitter structure is taken as an example. Please refer to FIG. 4A to FIG. 4F , which are flowcharts for preparing a solar cell back electrode.
請參照圖4A，首先，提供一N型或P型導電性雜質的半導體基材，在本實施例中，半導體基材摻雜N型導電性雜質，並已完成清潔、粗糙化處理(surface texturing)。Referring to FIG. 4A, first, a semiconductor substrate having an N-type or P-type conductive impurity is provided. In the embodiment, the semiconductor substrate is doped with N-type conductive impurities, and the surface texturing is completed. ).
半導體基材40正面形成N型導電性雜質重摻雜層41，以提升光電轉換效應。為了增加太陽能電池的光使用效率，半導體基材40的正面鍍有抗反射層42，抗反射層的材料可選自二氧化矽(SiO2 )、二氧化鈦(TiO2 )、氮化矽(Si3 N4 )及其組成的群組其中之一種。通常在正面形成抗反射層時，也同時會在半導體基材40背面形成。The N-type conductive impurity heavily doped layer 41 is formed on the front surface of the semiconductor substrate 40 to enhance the photoelectric conversion effect. In order to increase the light use efficiency of the solar cell, the front surface of the semiconductor substrate 40 is plated with an anti-reflection layer 42 which may be selected from the group consisting of cerium oxide (SiO 2 ), titanium dioxide (TiO 2 ), and tantalum nitride (Si 3 ). N 4 ) and a group of its constituents. Usually, when the antireflection layer is formed on the front surface, it is also formed on the back surface of the semiconductor substrate 40 at the same time.
圖4B顯示對半導體基材40背面施行一非等向性蝕刻。本發明實施例中，以圖2B之選擇性蝕刻遮板為罩冪，於基材背面產生一蝕刻圖案420。4B shows an anisotropic etch of the back side of semiconductor substrate 40. In the embodiment of the present invention, the selective etching mask of FIG. 2B is used as a cover power to generate an etching pattern 420 on the back surface of the substrate.
接著，請參照圖4C，對半導體基材40背面進行P型導電性雜質擴散製程，使位於蝕刻圖案開口420的半導體基材表層形成P型導電性雜質摻雜區43。Next, referring to FIG. 4C, a P-type conductive impurity diffusion process is performed on the back surface of the semiconductor substrate 40, and a P-type conductive impurity doping region 43 is formed on the surface of the semiconductor substrate located in the etching pattern opening 420.
請參照圖4D及圖4E，網印金屬漿料44、45於半導體基材40背面的摻雜區43及蝕刻圖案開口420以外的區域。Referring to FIGS. 4D and 4E, the screen printed metal pastes 44, 45 are in regions other than the doped regions 43 on the back surface of the semiconductor substrate 40 and the etch pattern openings 420.
最後，施以一燒結處理，如圖4F，金屬漿料44、45，滲入半導體基材40表層，分別形成連接P及N型導電性雜質半導體基材的電極，產生太陽能電池的背電極結構。Finally, a sintering treatment is applied. As shown in FIG. 4F, the metal pastes 44 and 45 are infiltrated into the surface layer of the semiconductor substrate 40 to form electrodes for connecting the P and N-type conductive impurity semiconductor substrates, respectively, to produce a back electrode structure of the solar cell.
另一實施例是製備太陽能電池選擇性射極結構的流程圖，請參照圖5A至圖5I。Another embodiment is a flow chart for preparing a solar cell selective emitter structure, please refer to FIGS. 5A-5I.
如5A所示，同樣先提供一摻雜P或N型導電性雜質的半導體基材，本發明實施例中，係提供一P型半導體基材50。半導體基材50經過清洗(wafer cleaning)，去除附著於晶片表面的微粒及髒污。在太陽能電池的製程中，常使用的溶液是氫氧化鈉(sodium hydroxide；NaOH)或氫氧化鉀(potassium hydroxide；KOH)。且P型半導體基材50經過粗糙化處理(surface texturing)，使其表面產生大小不一的散亂分布金字塔結構粗糙面。As shown in FIG. 5A, a semiconductor substrate doped with P or N type conductive impurities is also provided first. In the embodiment of the present invention, a P-type semiconductor substrate 50 is provided. The semiconductor substrate 50 is subjected to wafer cleaning to remove particles and dirt adhering to the surface of the wafer. In the process of solar cells, the commonly used solution is sodium hydroxide (NaOH) or potassium hydroxide (KOH). Moreover, the P-type semiconductor substrate 50 is subjected to surface texturing to produce a rough surface of a scattered pyramid structure having a size of different sizes.
請參照圖5B，對半導體基材50進行N型導電性雜質擴散製程，以在半導體基材50表層形成一輕摻雜層51。此擴散製程是在退火爐管中，導入含N型導電性雜質的氣體，例如：P2 O5 、PH3 或PF3 來進行雜質擴散製程。Referring to FIG. 5B, the semiconductor substrate 50 is subjected to an N-type conductive impurity diffusion process to form a lightly doped layer 51 on the surface of the semiconductor substrate 50. In the diffusion process, a gas containing an N-type conductive impurity such as P 2 O 5 , PH 3 or PF 3 is introduced into the annealing furnace tube to carry out an impurity diffusion process.
而在此一製程中，也同時會形成一磷氧化層(P2 O5 )於P型半導體基材50的表面上，但緊接著即以濕式蝕刻的方式將殘餘在半導體基材50表面的磷氧化層501移除，以減少電子-電洞的再復合(recombination)效應，如圖5C。In this process, a phosphorous oxide layer (P 2 O 5 ) is also formed on the surface of the P-type semiconductor substrate 50, but is then wet-etched to remain on the surface of the semiconductor substrate 50. The phosphorous oxide layer 501 is removed to reduce the electron-hole recombination effect, as shown in Figure 5C.
為了增加太陽能電池的光使用效率，形成一抗反射層52於半導體基材50表面，如圖5D。In order to increase the light use efficiency of the solar cell, an anti-reflection layer 52 is formed on the surface of the semiconductor substrate 50 as shown in FIG. 5D.
請參照圖5E，對半導體基材50施行一非等向性蝕刻，以一選擇性蝕刻遮板為罩冪，以產生一蝕刻圖案開口520。與前一製程實施例不同的是，本實施例中的非等向性蝕刻分為兩階段進行，使用如圖3C中多反應室的電漿蝕刻裝置。本實施例中，在經過兩階段非等向性蝕刻製程之後，蝕刻圖案開口520為一封閉迴路圖案開口，即為前述圖3A及圖3B的蝕刻圖案開口以一預設角度疊合而成。其中，封閉迴路圖案開口係為在半導體基材上預定形成匯流排(bus bar)及柵線(grid line)的位置。Referring to FIG. 5E, an anisotropic etch is performed on the semiconductor substrate 50, and a selective etch mask is used as a mask to generate an etch pattern opening 520. Unlike the previous process embodiment, the anisotropic etch in this embodiment is performed in two stages, using a plasma etching apparatus as shown in Fig. 3C. In this embodiment, after the two-stage anisotropic etching process, the etch pattern opening 520 is a closed loop pattern opening, that is, the etch pattern openings of the foregoing FIGS. 3A and 3B are stacked at a predetermined angle. The closed loop pattern opening is a position on the semiconductor substrate where a bus bar and a grid line are predetermined to be formed.
接著，進行一擴散製程，以在蝕刻圖案開口520行成重摻雜區。本實施例中的擴散製程可以採用兩種方式。第一種如圖5F至圖5G所示，直接將含N型導電性雜質化合物，比如：高摻雜磷之矽微粒(P doped Si nano particle)的金屬漿料54網印至圖案開口520。並施以一燒結處理，使金屬漿料中的N型導電性雜質擴散至半導體基材50內部，在蝕刻圖案開口520形成重摻雜區53，並同時形成電極。Next, a diffusion process is performed to form a heavily doped region in the etch pattern opening 520. The diffusion process in this embodiment can be performed in two ways. The first type, as shown in FIGS. 5F to 5G, directly screens a metal paste 54 containing an N-type conductive impurity compound such as a highly doped P doped Si nano particle to the pattern opening 520. A sintering treatment is applied to diffuse the N-type conductive impurities in the metal paste to the inside of the semiconductor substrate 50, and the heavily doped regions 53 are formed in the etching pattern opening 520, and the electrodes are simultaneously formed.
當然，若半導體基材50是摻雜N型導電性雜質，則只要改用含P型導電性雜質的化合物的金屬漿料即可，如：鋁、高摻雜硼之矽微粒。Of course, if the semiconductor substrate 50 is doped with an N-type conductive impurity, it is only necessary to use a metal paste of a compound containing a P-type conductive impurity, such as aluminum or highly doped boron particles.
金屬漿料在燒結時，既形成電極54，又形成重摻雜區53，相較於習知技術而言，本發明實施例中金屬漿料不需要穿透抗反射層才能接觸到半導體基材50，減少了變因，降低了製程控制的複雜程度。When the metal paste is sintered, the electrode 54 is formed, and the heavily doped region 53 is formed. Compared with the prior art, the metal paste in the embodiment of the invention does not need to penetrate the anti-reflection layer to contact the semiconductor substrate. 50, reducing the cause of the problem and reducing the complexity of the process control.
儘管如此，重摻雜區中的雜質濃度仍然較不易控制，有可能影響太陽能電池的光轉換效率。所以在另一較佳實施例中，是在進行非等向性蝕刻製程之後，於退火爐管中，再施以一第二次擴散製程，用以在蝕刻圖案開口520形成重摻雜區53，如圖5H。Nevertheless, the impurity concentration in the heavily doped region is still less controllable, which may affect the light conversion efficiency of the solar cell. Therefore, in another preferred embodiment, after the anisotropic etching process, a second diffusion process is applied to the annealing furnace tube to form a heavily doped region 53 in the etch pattern opening 520. , as shown in Figure 5H.
最後，再網印金屬漿料54於重摻雜區53，並施以燒結處理，形成太陽能電池選擇性射極(selective emitter)結構，如圖5I。Finally, the metal paste 54 is re-printed in the heavily doped region 53 and subjected to a sintering treatment to form a solar cell selective emitter structure, as shown in FIG. 5I.
但是，進行兩次擴散製程畢竟增加了製程的複雜程度，所以本發明更提供另一實施例，使太陽能電池選擇性射極的製備流程中，不需透過含有雜質化合物的金屬漿料來進行重摻雜，但是僅需要做一次擴散製程或離子植入，就能解決摻雜濃度不易控制的問題，同時也降低製程的複雜程度。However, performing the diffusion process twice increases the complexity of the process. Therefore, the present invention further provides another embodiment for making the process of preparing the selective emitter of the solar cell without passing through the metal paste containing the impurity compound. Doping, but only need to do a diffusion process or ion implantation, can solve the problem that the doping concentration is difficult to control, and also reduce the complexity of the process.
請參照圖6A至6F。本實施例和前一實施例不同之處在於，在摻雜N型導電性雜質於半導體基材60之前，先形成一抗反射層62於半導體基材60表面，如圖6B，並進行非等向性蝕刻製程，以形成蝕刻圖案開口620，如圖6C。接著，才對半導體基材進行N型導電性雜質擴散製程，如圖6D。Please refer to FIGS. 6A to 6F. This embodiment differs from the previous embodiment in that an anti-reflective layer 62 is formed on the surface of the semiconductor substrate 60 before being doped with the N-type conductive impurities on the semiconductor substrate 60, as shown in FIG. 6B. The etch process is performed to form an etch pattern opening 620, as shown in FIG. 6C. Next, the N-type conductive impurity diffusion process is performed on the semiconductor substrate, as shown in FIG. 6D.
要特別注意的是，在習知的太陽能電池製程中，抗反射層的厚度大約80 nm至100nm，但在本發明實施例中，抗反射層的厚度大約30 nm至50 nm。It is particularly noted that in conventional solar cell processes, the thickness of the antireflective layer is about 80 nm to 100 nm, but in embodiments of the invention, the thickness of the antireflective layer is about 30 nm to 50 nm.
這是為了在後續進行擴散製程時或另外施以一離子植入製程時，使N型導電性雜質仍然能夠穿過抗反射層62，擴散或植入至抗反射層62下方的半導體基材60，形成輕摻雜層61。而位於蝕刻圖案開口620的區域，雜質原子擴散沒有任何阻障層，因此，會形成一重摻雜區63，如圖6E。This is to enable N-type conductive impurities to pass through the anti-reflective layer 62, diffuse or implant into the semiconductor substrate 60 under the anti-reflective layer 62 during subsequent diffusion processes or when an ion implantation process is additionally applied. A lightly doped layer 61 is formed. While in the region where the pattern opening 620 is etched, impurity atoms are diffused without any barrier layer, and thus, a heavily doped region 63 is formed, as shown in FIG. 6E.
最後同樣網印金屬漿料64於蝕刻圖案開口620，並施以一燒結處理，以使金屬漿料64在重摻雜區形成電極。Finally, the metal paste 64 is also screen printed on the etch pattern opening 620 and subjected to a sintering process to cause the metal paste 64 to form electrodes in the heavily doped regions.
綜上所述，本發明所提供的電漿蝕刻裝置及其應用於形成太陽能電池選擇性射極(selective emitter)及背電極(back contact)結構的方法，相較於習知技術而言具有下列優點：In summary, the plasma etching apparatus provided by the present invention and the method thereof for forming a solar cell selective emitter and back contact structure have the following characteristics compared with the prior art. advantage:
(1)方法簡便，成本低廉，容易和現有製程整合。本發明中只要在電漿蝕刻裝置中，增設一選擇性蝕刻遮板，就能夠只針對預設的位置進行蝕刻。應用在定義太陽能電池選擇性射極(selective emitter)及背電極(back contact)結構時，不但製程方法簡單，且成本低，也容易和現有太陽能電池製程整合在一起，產生不同的應用。(1) The method is simple, the cost is low, and it is easy to integrate with the existing process. In the present invention, as long as a selective etching mask is added to the plasma etching apparatus, etching can be performed only for a predetermined position. When defining the solar cell selective emitter and back contact structure, the process method is simple, low cost, and easy to integrate with the existing solar cell process to produce different applications.
(2)選擇型電漿蝕刻裝置可使多片半導體基材同步進行蝕刻製程，有利於大量生產。(2) The selective plasma etching device can simultaneously perform etching processes on a plurality of semiconductor substrates, which is advantageous for mass production.
(3)由於選擇性蝕刻遮板的圖案會對應到太陽能電池基板表面將要形成電極的位置。所以，為了使建築物美觀，而在太陽能電池基板表面做出不同的花紋設計時，選擇性蝕刻遮板的圖案在製備時也需配合作變更。但本發明中的選擇性蝕刻遮板圖案製備十分容易，所以即使要因應太陽能電池基板表面電極的分布做變更時，不需要耗費太多成本，即可達到上述需求。(3) Since the pattern of the selective etching mask corresponds to the position at which the surface of the solar cell substrate is to be formed. Therefore, in order to make the building beautiful, and to make a different pattern design on the surface of the solar cell substrate, the pattern of the selective etching mask needs to be cooperatively changed during preparation. However, the selective etching mask pattern in the present invention is very easy to prepare, so even if it is necessary to change the distribution of the surface electrodes of the solar cell substrate, it is possible to achieve the above demand without consuming too much cost.
本發明雖以較佳實例闡明如上，然其並非用以限定本發明精神與發明實體僅止於上述實施例。凡熟悉此項技術者，當可輕易了解並利用其它元件或方式來產生相同的功效。是以，在不脫離本發明之精神與範疇內所作之修改，均應包含在下述之申請專利範圍內。The present invention has been described above by way of a preferred example, but it is not intended to limit the spirit of the invention and the inventive subject matter. Those who are familiar with the technology can easily understand and utilize other components or methods to produce the same effect. Modifications made without departing from the spirit and scope of the invention are intended to be included within the scope of the appended claims.
1、23、40、50、60．．．半導體基材1, 23, 40, 50, 60. . . Semiconductor substrate
10、41、51、61．．．輕摻雜層10, 41, 51, 61. . . Lightly doped layer
11、510．．．雜質氧化層11, 510. . . Impurity oxide layer
13、42、52、62．．．抗反射層13, 42, 52, 62. . . Antireflection layer
420、520、602．．．蝕刻圖案開口420, 520, 602. . . Etching pattern opening
12、43、53、63．．．重摻雜區12, 43, 53, 63. . . Heavily doped region
14、44、45、54、64．．．金屬漿料14, 44, 45, 54, 64. . . Metal paste
16．．．刮棒16. . . Scraper
2．．．電漿蝕刻裝置2. . . Plasma etching device
20．．．反應室20. . . Reaction chamber
21．．．選擇性蝕刻遮板twenty one. . . Selective etching shutter
210．．．梳狀圖案開口210. . . Comb pattern opening
22．．．載台twenty two. . . Loading platform
24．．．冷卻裝置twenty four. . . Cooling device
25．．．極板25. . . Plate
26．．．端點偵測器26. . . Endpoint detector
27．．．傳輸裝置27. . . Transmission device
20a．．．第一反應室20a. . . First reaction chamber
20b．．．第二反應室20b. . . Second reaction chamber
21a．．．第一選擇性蝕刻遮板21a. . . First selective etching shutter
21b．．．第二選擇性蝕刻遮板21b. . . Second selective etching shutter
212．．．匯流排圖案開口212. . . Bus pattern opening
214．．．柵線圖案開口214. . . Grid line pattern opening
圖1A至1G顯示習知的太陽能電池製程的示意圖；1A to 1G are schematic views showing a conventional solar cell process;
圖2A顯示本發明實施例電漿蝕刻裝置之剖面示意圖；2A is a schematic cross-sectional view showing a plasma etching apparatus according to an embodiment of the present invention;
圖2B顯示本發明實施例選擇性蝕刻遮板俯視示意圖；2B is a top plan view showing a selective etching mask according to an embodiment of the present invention;
圖3A及圖3B顯示本發明另一實施例選擇性遮板俯視示意圖；3A and 3B are schematic views showing a top view of a selective shutter according to another embodiment of the present invention;
圖3C顯示本發明另一實施例電漿蝕刻裝置之示意圖；3C is a schematic view showing a plasma etching apparatus according to another embodiment of the present invention;
圖4A至圖4F顯示本發明電漿蝕刻裝置應用於半導體製程之流程示意圖；4A to 4F are schematic views showing the flow of a plasma etching apparatus of the present invention applied to a semiconductor process;
圖5A至圖5I顯示本發明電漿蝕刻裝置應用於半導體製程之流程示意圖；及5A to 5I are views showing a flow of a plasma etching apparatus of the present invention applied to a semiconductor process; and
圖6A至圖6E顯示本發明電漿蝕刻裝置應用於半導體製程之流程示意圖。6A to 6E are schematic views showing the flow of the plasma etching apparatus of the present invention applied to a semiconductor process.
2．．．電漿蝕刻裝置2. . . Plasma etching device
20．．．反應室20. . . Reaction chamber
21．．．選擇性蝕刻遮板twenty one. . . Selective etching shutter
22．．．載台twenty two. . . Loading platform
24．．．冷卻裝置twenty four. . . Cooling device
25．．．極板25. . . Plate
26．．．端點偵測器26. . . Endpoint detector
Claims (12)
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| Application Number | Priority Date | Filing Date | Title |
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| TW099120833A TWI416625B (en) | 2010-06-25 | 2010-06-25 | Plasma-etching apparatus and method for doping or contact region definition on surface layer of semiconductor by using the same |
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| Application Number | Priority Date | Filing Date | Title |
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| TW099120833A TWI416625B (en) | 2010-06-25 | 2010-06-25 | Plasma-etching apparatus and method for doping or contact region definition on surface layer of semiconductor by using the same |
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| TWI416625B true TWI416625B (en) | 2013-11-21 |
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| US7339110B1 (en) * | 2003-04-10 | 2008-03-04 | Sunpower Corporation | Solar cell and method of manufacture |
| TW200939510A (en) * | 2007-11-19 | 2009-09-16 | Applied Materials Inc | Solar cell contact formation process using a patterned etchant material |
| TW200940736A (en) * | 2007-11-07 | 2009-10-01 | Mattson Tech Inc | Workpiece support with fluid zones for temperature control |
| TW200952185A (en) * | 2008-06-10 | 2009-12-16 | Mosel Vitelic Inc | Solar cell and method for manufacturing the same |
| TW201007968A (en) * | 2008-07-16 | 2010-02-16 | Applied Materials Inc | Hybrid heterojunction solar cell fabrication using a doping layer mask |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7339110B1 (en) * | 2003-04-10 | 2008-03-04 | Sunpower Corporation | Solar cell and method of manufacture |
| TW200940736A (en) * | 2007-11-07 | 2009-10-01 | Mattson Tech Inc | Workpiece support with fluid zones for temperature control |
| TW200939510A (en) * | 2007-11-19 | 2009-09-16 | Applied Materials Inc | Solar cell contact formation process using a patterned etchant material |
| TW200952185A (en) * | 2008-06-10 | 2009-12-16 | Mosel Vitelic Inc | Solar cell and method for manufacturing the same |
| TW201007968A (en) * | 2008-07-16 | 2010-02-16 | Applied Materials Inc | Hybrid heterojunction solar cell fabrication using a doping layer mask |
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