TWI451527B - Method of forming a solar cell having depletion region increment and the structure of the same - Google Patents
Method of forming a solar cell having depletion region increment and the structure of the same Download PDFInfo
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Description
本發明關於太陽能電池，特別是指一種使pn接面空乏區加大的一種太陽能電池結構及其製程方法，以提高電流收集的製程方法及結構。The invention relates to a solar cell, in particular to a solar cell structure and a manufacturing method thereof for increasing a pn junction depletion region, so as to improve a current collecting process and structure.
近年來，由於環保意識的抬頭和其他能源逐漸的枯竭，使得世界各國開始重視再生能源的利用。由於太陽光是取之不盡，用之不竭的天然能源，除了沒有能源耗盡的問題之外，也可以避免能源被壟斷的問題。In recent years, due to the rise of environmental awareness and the gradual depletion of other energy sources, countries around the world have begun to pay attention to the use of renewable energy. Because the sun is inexhaustible, inexhaustible natural energy, in addition to the problem of no energy exhaustion, can also avoid the problem of energy monopoly.
請參考圖1A~1G，為習知的太陽能電池吸光面製程的剖面示意圖。p型半導體基板1經過清洗，將晶圓表面的雜質及污染物去除，並以酸液將基板1表面蝕刻成粗糙面後，在一含氧氣氛導入含n型導電性雜質的氣體，例如POCL3 、P2 O5 、PH3 或PF3 之退火爐管進行雜質擴散製程，以形成一摻雜層10於p型半導體基板1上，產生光電轉換效應所需的pn介面。Please refer to FIGS. 1A-1G for a schematic cross-sectional view of a conventional solar cell light absorption surface process. The p-type semiconductor substrate 1 is cleaned to remove impurities and contaminants on the surface of the wafer, and the surface of the substrate 1 is etched into a rough surface with an acid solution, and then a gas containing an n-type conductive impurity such as POCL is introduced in an oxygen-containing atmosphere. 3. An annealing furnace tube of P 2 O 5 , PH 3 or PF 3 is subjected to an impurity diffusion process to form a doped layer 10 on the p-type semiconductor substrate 1 to generate a pn interface required for photoelectric conversion effect.
由於在n型區域10表層也會同時形成一磷的氧化層11(P2 O5 )，因此，在後續步驟中，需以蝕刻移除，再依序於p型半導體基板表面，形成抗反射層13及金屬電極14。Since the oxide layer 10 will form a surface layer of phosphorus 11 (P 2 O 5), and therefore, in a subsequent step, the need to remove the etching, and then sequentially the p-type semiconductor substrate surface while the n-type region forming an antireflective Layer 13 and metal electrode 14.
請參照圖2A虛線B為半導體基板1本身p型雜質濃度曲線，曲線A為經過擴散方式摻雜後，在半導體基板內部n型導電性雜質的濃度分布。由圖中可以看出在距表面一距離處n型雜質和p型雜質互為補償(compensate)而低於一水準時就形成空乏區。Referring to FIG. 2A, a broken line B is a p-type impurity concentration curve of the semiconductor substrate 1 itself, and a curve A is a concentration distribution of n-type conductive impurities inside the semiconductor substrate after being doped by diffusion. It can be seen from the figure that the n-type impurity and the p-type impurity are mutually compensated at a distance from the surface, and a depletion region is formed when the level is lower than a level.
請再參照圖2B，為光載子產生機率及收集機率在太陽能電池內部不同的位置的關係圖。其中，曲線C為載子被收集的機率，曲線D為載子產生的機率。由曲線C可以看出，在空乏區因pn介面之電場作用，載子被收集機率最大，儘管，載子產生的機率不是最大的。而在靠近表面處載子產生的機率最高，但光照所產生的部分載子，會被表面的雜質所復合，因此，表面被收集的機率反而不如空乏區。Please refer to FIG. 2B again, which is a relationship diagram of the photon generation probability and the collection probability at different positions inside the solar cell. Among them, the curve C is the probability that the carrier is collected, and the curve D is the probability of the carrier being generated. It can be seen from curve C that in the depletion region, the carrier is most likely to be collected due to the electric field of the pn interface, although the probability of carrier generation is not the greatest. The carrier is most likely to be generated near the surface, but some of the carriers generated by the illumination are compounded by the impurities on the surface. Therefore, the probability of the surface being collected is not as good as that of the depletion zone.
光電流的大小與載子產生的機率以及被收集的機率成正向關係，所以，使載子在太陽能電池內部產生的機率增加，或是提高載子被收集的機率，都能增加光電流，提高太陽能電池的光電轉換效率。The magnitude of the photocurrent is positively related to the probability of the carrier and the probability of being collected. Therefore, increasing the probability of the carrier inside the solar cell or increasing the probability of the carrier being collected increases the photocurrent and improves the photocurrent. Photoelectric conversion efficiency of solar cells.
就目前的太陽能電池相關製程產業而言，改變太陽能電池的製備方式，提高載子被收集的機率，降低電子和電洞再復合的機率，使太陽能電池光電轉換效率提高，仍是目前在這一領域中最熱門的研究課題之一。In the current solar cell-related process industry, changing the way solar cells are prepared, increasing the probability of carriers being collected, reducing the probability of recombination of electrons and holes, and improving the photoelectric conversion efficiency of solar cells is still present in this One of the most popular research topics in the field.
有鑒於上述課題，本發明之目的之一在於提供一種增加太陽能電池pn接面空乏區大小的方法，至少包含以下步驟：提供一表面已粗糙化且為p型輕摻雜的矽基板；施以第一次毯覆式且較低能量n型離子佈植，以形成n型雜質第一摻雜區，因此，第一摻雜區與p型矽基板接面形成第一道pn接面空乏區；及施以第二次較高能量n型離子佈植，以一具有複數個開口圖案罩幕為離子佈值罩幕，以形成複數個n型雜質第二摻雜區，第二摻雜區連接自第一摻雜區且如彈頭形向下延伸，第二摻雜區與p型矽基板接面形成彈頭形的第二道pn接面空乏區，第一道pn接面空乏區與第二道pn接面空乏區相連接，以擴大pn接面面積。In view of the above problems, one of the objects of the present invention is to provide a method for increasing the size of a pn junction depletion region of a solar cell, comprising at least the steps of: providing a germanium substrate having a surface roughened and being p-type lightly doped; The first blanket-type and lower-energy n-type ion implantation is performed to form a first doped region of the n-type impurity, and therefore, the first doped region and the p-type germanium substrate junction form a first pn junction depletion region And applying a second higher energy n-type ion implantation, using a plurality of open pattern masks as ion cloth value masks to form a plurality of n-type impurity second doping regions, the second doping region Connected from the first doped region and extending downwardly as a bullet shape, the second doped region and the p-type germanium substrate junction form a second pn junction depletion region of the warhead shape, and the first pn junction gap region and the first The two pn junctions are connected to each other to expand the pn junction area.
本發明之另一目的在於提供一種增加太陽能電池pn接面空乏區大小的方法，與前一實施例不同的是在進行離子佈植時，第一次是施以毯覆式，且較低能量高劑量的n型離子佈植，第二次是以較高能量低劑量的n型離子佈植，以形成一n型雜質第二摻雜區。Another object of the present invention is to provide a method for increasing the size of a pn junction depletion region of a solar cell. The difference from the previous embodiment is that when ion implantation is performed, the blanket is applied for the first time, and the energy is lower. The high dose of n-type ion implantation, the second time is a higher energy and low dose of n-type ion implantation to form an n-type impurity second doped region.
其中，第二摻雜區連接第一摻雜區，且向第一摻雜區下方延伸，與p型半導體基板接面形成一第二道pn接面空乏區，其中，佈植劑量的選擇以約略大於或能補償p型半導體基板的原始摻雜濃度為原則，以增加pn接面空乏區的寬度。The second doped region is connected to the first doped region and extends below the first doped region to form a second pn junction depletion region with the p-type semiconductor substrate junction, wherein the implant dose is selected The principle is slightly larger or can compensate for the original doping concentration of the p-type semiconductor substrate to increase the width of the pn junction depletion region.
在本發明中，空乏區的寬度及面積增加，也表示在太陽能電池內部，具有高載子收集機率的區域變大。使太陽能電池內部產生的光載子能更有效的被收集，用來產生更多光電流，進一步提升太陽能電池的光電轉換效率。In the present invention, the increase in the width and area of the depletion region also indicates that the area having a high carrier collection probability becomes large inside the solar cell. The photocarriers generated inside the solar cell can be collected more efficiently to generate more photocurrent, further improving the photoelectric conversion efficiency of the solar cell.
為使本發明之上述目的、特徵和優點能更明顯易懂，下文依本發明太陽能電池的製程方法及結構，特舉較佳實施例，並配合所附相關圖式，作詳細說明如下，其中相同的元件將以相同的元件符號加以說明。要說明的是，圖中各區域尺寸比例僅為方便指明相對位置，而非實際結構之放大。In order to make the above-mentioned objects, features and advantages of the present invention more comprehensible, the following is a detailed description of the method and structure of the solar cell according to the present invention. The same elements will be described with the same element symbols. It should be noted that the size ratio of each area in the figure is only for convenience to indicate the relative position, rather than the enlargement of the actual structure.
本發明所提供之太陽能電池的製程，是以增加pn接面空乏區(junction depletion region)寬度或面積為手段，而因此提高獲得載子收集的機率為主要目的。當太陽能電池吸收太陽光而於空乏區所產生電子-電洞對會分別被空乏區內的電場所加速，而向相反方向移動至太陽能電池兩個表面的電極線而被收集。因此，在空乏區中幾乎不會有電子-電洞對再復合的情況發生。The process of the solar cell provided by the present invention is to increase the width or area of the junction depletion region of the pn junction, thereby improving the probability of obtaining carrier collection. When the solar cell absorbs sunlight, the electron-hole pairs generated in the depletion zone are respectively accelerated by the electric field in the depletion zone, and are moved to the electrode lines on both surfaces of the solar cell in the opposite direction to be collected. Therefore, there is almost no electron-hole pair recombination in the depletion zone.
換言之，若能使空乏區在太陽能電池內部的寬度或面積增加，將可預期光載子被收集的機率大增，進一步提升太陽能電池的光電轉換效率。本發明之精神可參照圖3，係藉由進行兩次離子佈值，調整雜質分佈而達到增加空乏區寬度或面積，並使其位置向半導體基板表面移動的目的。In other words, if the width or area of the solar cell inside the solar cell is increased, it is expected that the probability of photocarriers being collected is greatly increased, further improving the photoelectric conversion efficiency of the solar cell. The spirit of the present invention can be achieved by referring to FIG. 3 by adjusting the impurity distribution by performing two ion cloth values to increase the width or area of the depletion region and to move its position toward the surface of the semiconductor substrate.
請參照圖4A至4G，顯示本發明所提供太陽能電池的方法之較佳實施例。首先，請參照圖4A，提供一硼輕摻雜的p型半導體基板2，經過清洗以去除附著於晶片表面的微粒及髒污。在太陽能電池的製程中，常使用的溶液是氫氧化鈉(sodium hydroxide；NaOH)或氫氧化鉀(potassium hydroxide；KOH)。Referring to Figures 4A through 4G, a preferred embodiment of the method of the solar cell of the present invention is shown. First, referring to FIG. 4A, a boron-doped p-type semiconductor substrate 2 is provided, which is cleaned to remove particles and dirt adhering to the surface of the wafer. In the process of solar cells, the commonly used solution is sodium hydroxide (NaOH) or potassium hydroxide (KOH).
接著，對半導體基板2施以粗糙化處理(surface texturing)，如圖4B所示以減少太陽光反射。粗糙化處理是以鹼性或酸性溶液以對半導體基板2表面產生非等向性蝕刻(anisotropic etching)。比如，針對表面為(110)平面的矽晶片而言，是利用氫氧化鈉(NaOH)加異丙醇(isopropyl alcohol；IPA)溶液來使其表面產生大小不一的散亂分布金字塔結構粗糙面。Next, the semiconductor substrate 2 is subjected to surface texturing as shown in FIG. 4B to reduce solar reflection. The roughening treatment is an anisotropic etching on the surface of the semiconductor substrate 2 with an alkaline or acidic solution. For example, for a tantalum wafer with a (110) plane on the surface, sodium hydroxide (NaOH) plus isopropyl alcohol (IPA) solution is used to produce a scattered pyramidal structure with different sizes on the surface. .
請參照圖4C及4D，圖示為藉著增加空乏區22的面積，來達到增加光電流的目的的示意圖。在本發明實施例中，對半導體基板2進行摻雜，形成pn接面時，係至少對半導體基板2進行兩次n型導電性雜質的離子佈值，例如，磷離子或砷離子。但這僅是本發明其中一實施例，實際上採用n型半導體基板，摻雜p型導電性雜質也是可以的。Referring to Figures 4C and 4D, there is shown a schematic diagram for the purpose of increasing the photocurrent by increasing the area of the depletion region 22. In the embodiment of the present invention, when the semiconductor substrate 2 is doped to form a pn junction, at least the ion implantation value of the n-type conductivity impurities, for example, phosphorus ions or arsenic ions, is performed on the semiconductor substrate 2. However, this is only one embodiment of the present invention. Actually, an n-type semiconductor substrate is used, and it is also possible to dope p-type conductive impurities.
如圖4C所示，先進行第一次毯覆式低能量離子佈植，用以在半導體基板2表層下方形成第一摻雜區20，以和p型半導體基板2形成第一道pn接面空乏區22a，離子佈植的能量大約5至20 keV為佳。隨後，施以第二次離子佈植，佈植能量高於第一次離子佈值，較佳為50至數百keV，並且僅在選定區域進行佈植，用以在第一摻雜區20下方形成複數個第二摻雜區21。然而，這僅是本發明其中一實施例，若是掉換兩次離子佈植的順序，還是可以達到相同效果。As shown in FIG. 4C, a first blanket low energy ion implantation is performed to form a first doping region 20 under the surface layer of the semiconductor substrate 2 to form a first pn junction with the p-type semiconductor substrate 2. In the depletion zone 22a, the ion implantation energy is preferably about 5 to 20 keV. Subsequently, a second ion implantation is applied, the implantation energy is higher than the first ion cloth value, preferably 50 to several hundred keV, and implantation is performed only in selected regions for use in the first doping region 20 A plurality of second doping regions 21 are formed below. However, this is only one embodiment of the present invention, and if the order of ion implantation is changed twice, the same effect can be achieved.
如圖4D所示，第二摻雜區21連接自第一摻雜區20且如彈頭形向下延伸，第二摻雜區21與p型半導體基板2接面形成彈頭形的第二道pn接面空乏區22b，第一道pn接面空乏區22a與第二道pn接面空乏區22b相連接，形成一三維立體結構，以擴大pn接面空乏區面積。As shown in FIG. 4D, the second doping region 21 is connected from the first doping region 20 and extends downward like a bullet. The second doping region 21 and the p-type semiconductor substrate 2 are joined to form a second pn of the bullet shape. In the junction depletion zone 22b, the first pn junction depletion zone 22a is connected to the second pn junction depletion zone 22b to form a three-dimensional structure to expand the pn junction depletion zone area.
本實施例中，第二次離子佈植的佈植劑量和第一離子佈植相當，約為1014 至1016 /cm2 。並且，選擇要進行第二離子佈植的區域時，以一具有複數個開口圖案罩幕27為離子佈值罩幕，可利用光罩或光阻圖案來定義。In this embodiment, the implantation dose of the second ion implantation is equivalent to the first ion implantation, and is about 10 14 to 10 16 /cm 2 . Moreover, when the region where the second ion implantation is to be performed is selected, a mask having a plurality of opening patterns 27 as an ion cloth value mask can be defined by a mask or a photoresist pattern.
隨後，對半導體基板2施以退火製程以活化離子之外，並回復佈植所導致之半導體基板損傷。退火溫度大約700至1000℃，依離子佈植之種類，調整退火溫度與時間之最適條件，必要時可選擇快速升溫退火裝置以達到最佳效果。圖4D顯示退火後的導電性雜質分佈示意圖，選定的第二摻雜區41的雜質分佈有如數個分立的子彈殼體。Subsequently, the semiconductor substrate 2 is subjected to an annealing process to activate ions, and the semiconductor substrate damage caused by the implantation is restored. The annealing temperature is about 700 to 1000 ° C. Depending on the type of ion implantation, the optimum conditions for annealing temperature and time can be adjusted. If necessary, a rapid temperature annealing device can be selected to achieve the best effect. 4D shows a schematic diagram of the distribution of conductive impurities after annealing. The impurity of the selected second doped region 41 is distributed as a plurality of discrete bullet casings.
接著，形成一抗反射層23於半導體基板2表面，如圖4E。抗反射層23的材料可選自二氧化矽(SiO2 )、二氧化鈦(TiO2 )或氮化矽(Si3 N4 )其中之一種或組合，並可採用濺鍍、蒸鍍或電漿輔助化學氣相沉積等方式來製備。Next, an anti-reflection layer 23 is formed on the surface of the semiconductor substrate 2 as shown in FIG. 4E. The material of the anti-reflection layer 23 may be selected from one or a combination of cerium oxide (SiO 2 ), titanium oxide (TiO 2 ) or cerium nitride (Si 3 N 4 ), and may be sprayed, vapor-deposited or plasma-assisted. Prepared by chemical vapor deposition or the like.
最後，請參照圖4F，利用刮棒26將金屬漿料24以網印方式印製於半導體基板2表面。施以一燒結處理後，金屬漿料24穿透正面抗反射層22，並滲入半導體基板2表層，與第一摻雜區20緊密結合以形成電極24，如圖4G所示。Finally, referring to FIG. 4F, the metal paste 24 is printed on the surface of the semiconductor substrate 2 by screen printing using a bar 26. After a sintering treatment, the metal paste 24 penetrates the front anti-reflective layer 22 and penetrates into the surface layer of the semiconductor substrate 2, and is tightly bonded to the first doping region 20 to form the electrode 24, as shown in FIG. 4G.
本發明的第二較佳實施例，如圖5A至5G所示，是藉著增加空乏區的寬度，以提高光電子被收集的機率。圖5A至圖5B之離子佈植的前處理流程步驟與第一實施例同。A second preferred embodiment of the present invention, as shown in Figures 5A through 5G, is to increase the probability of photoelectrons being collected by increasing the width of the depletion region. The pretreatment process steps of the ion implantation of Figs. 5A to 5B are the same as those of the first embodiment.
接著，請參照圖5C及5D，先進行低能量及高劑量的第一次離子佈值以形成第一摻雜區30，使摻雜層和金屬射極形成良好的歐姆接觸。隨後，施以較高能量但較低劑量的第二次離子佈值，用以在距表層較深處產生第二摻雜區31。Next, referring to FIGS. 5C and 5D, the first ion cloth values of low energy and high dose are first performed to form the first doping region 30, so that the doped layer and the metal emitter form a good ohmic contact. Subsequently, a higher energy but lower dose second ion cloth value is applied to create a second doped region 31 deeper from the surface layer.
第二摻雜區31連接第一摻雜區30，且向第一摻雜區30下方延伸，並覆蓋過該第一道pn接面空乏區32a，與p型半導體基板接面形成一第二道pn接面空乏區32b。The second doping region 31 is connected to the first doping region 30 and extends below the first doping region 30 and covers the first pn junction depletion region 32a to form a second surface with the p-type semiconductor substrate junction. The channel pn junction is depleted region 32b.
在較佳實施例中，第一次離子佈值所使用的能量及劑量分別為5至20 keV和1014 至1016 /cm2 。第二次離子佈值的能量較佳為50至數百keV，佈植劑量的選擇則以約略大於或能補償(compensate)p型半導體基板2的原始摻雜濃度為原則，較佳為1013 至5×1013 /cm2 。隨後的退火、鍍抗反射層、網印金屬電極及燒結等後續製程與第一實施例同。故不再贅述。In a preferred embodiment, the first dose and ion energy distribution values are used 5 to 20 keV and 1014 to 10 16 / cm 2. The energy of the second ion cloth value is preferably 50 to several hundred keV, and the implantation dose is selected to be approximately larger than or capable of compensating the original doping concentration of the p-type semiconductor substrate 2, preferably 10 13 Up to 5 × 10 13 /cm 2 . Subsequent annealing, plating antireflection layer, screen printed metal electrode, and sintering, and the like are the same as in the first embodiment. Therefore, it will not be repeated.
由於第二摻雜區31的濃度較低，在p型半導體基板內部形成pn接面時，空乏區32b的寬度會增加，使光載子被收集到的機率提升。Since the concentration of the second doping region 31 is low, when the pn junction is formed inside the p-type semiconductor substrate, the width of the depletion region 32b is increased, and the probability that the photocarriers are collected is increased.
本發明的再一實施例，如圖6A至6H所示，是將前兩個實施例的優點結合，亦即，在進行圖6D的第二次離子佈植步驟之後，於選定區域，再進行第三次離子佈植，佈植的能量更大於第二次離子佈植，如圖6E所示，以在第二摻雜區41下方形成複數個第三摻雜區45。According to still another embodiment of the present invention, as shown in FIGS. 6A to 6H, the advantages of the first two embodiments are combined, that is, after performing the second ion implantation step of FIG. 6D, in the selected region, For the third ion implantation, the energy of implantation is greater than that of the second ion implantation, as shown in FIG. 6E, to form a plurality of third doping regions 45 under the second doping region 41.
第三次離子佈植的能量大約100至數百keV，並且，第三次離子佈植的劑量與第二次離子佈植的劑量約略相同。以此製備方式，在靠近半導體基板表層具有濃度較高的摻雜區40，和金屬電極44可以形成良好的歐姆接觸，而在pn接面處，空乏區42b、42c的面積及寬度都會增加。The energy of the third ion implantation is about 100 to several hundred keV, and the dose of the third ion implantation is about the same as the dose of the second ion implantation. In this manner, the doped region 40 having a higher concentration near the surface of the semiconductor substrate can form a good ohmic contact with the metal electrode 44, and at the pn junction, the area and width of the depleted regions 42b, 42c increase.
綜上所述，本發明所提供的太陽能電池的製程方法，藉由控制二次離子佈植的能量及劑量，來調整空乏區的結構，具有下列優點：In summary, the method for manufacturing a solar cell provided by the present invention adjusts the structure of the depletion region by controlling the energy and dose of the secondary ion implantation, and has the following advantages:
(1)在空乏區可以收集更多載子。當空乏區的寬度及面積增加，位置也更靠近太陽能電池照射面時，能夠在空乏區收集的載子數量也會增加。(2)載子損失的機率降低。由於不需要考慮空乏區中載子再復合的情況，再加上載子移動到太陽能電池表面金屬電極的距離縮短，可以減少電子-電洞再復合的機率。前述兩個優點都可以增加光電流，使太陽能電池的光電轉換效率大幅提升。(1) More carriers can be collected in the depletion zone. As the width and area of the depletion zone increase and the location is closer to the solar cell illumination surface, the number of carriers that can be collected in the depletion zone will also increase. (2) The probability of carrier loss is reduced. Since it is not necessary to consider the case where the carriers are recombined in the depletion zone, and the distance that the uploader moves to the metal electrode on the surface of the solar cell is shortened, the probability of recombination of the electron-hole can be reduced. Both of the above advantages can increase the photocurrent, so that the photoelectric conversion efficiency of the solar cell is greatly improved.
本發明雖以較佳實例闡明如上，然其並非用以限定本發明精神與發明實體僅止於上述實施例。凡熟悉此項技術者，當可輕易了解並利用其它元件或方式來產生相同的功效。是以，在不脫離本發明之精神與範疇內所作之修改，均應包含在下述之申請專利範圍內。The present invention has been described above by way of a preferred example, but it is not intended to limit the spirit of the invention and the inventive subject matter. Those who are familiar with the technology can easily understand and utilize other components or methods to produce the same effect. Modifications made without departing from the spirit and scope of the invention are intended to be included within the scope of the appended claims.
1、2、3、4．．．半導體基板1, 2, 3, 4. . . Semiconductor substrate
11．．．雜質氧化層11. . . Impurity oxide layer
10．．．輕摻雜層10. . . Lightly doped layer
12．．．重摻雜區12. . . Heavily doped region
20、30、40．．．第一摻雜區20, 30, 40. . . First doped region
21、31、41．．．第二摻雜區21, 31, 41. . . Second doped region
22a、32a、42a．．．第一道pn接面空乏區22a, 32a, 42a. . . First pn junction
22b、32b、42b．．．第二道pn接面空乏區22b, 32b, 42b. . . Second pn junction
42c．．．第三道pn接面空乏區42c. . . Third pn junction
13、23、33、43．．．抗反射層13, 23, 33, 43. . . Antireflection layer
14、24、34、44．．．金屬14, 24, 34, 44. . . metal
45．．．第三摻雜區45. . . Third doped region
16、26、36、46．．．刮棒16, 26, 36, 46. . . Scraper
27、47．．．離子佈植罩冪27, 47. . . Ion cloth cover power
圖1A至1G顯示習知的太陽能電池製程的示意圖；1A to 1G are schematic views showing a conventional solar cell process;
圖2A顯示以擴散方式摻雜後，雜質的濃度在半導體內部的分布曲線；2A shows a distribution curve of the concentration of impurities inside the semiconductor after doping in a diffusion manner;
圖2B顯示光載子產生及收集機率在太陽能電池內部不同的位置的關係圖；Figure 2B shows a relationship between photon generation and collection probability at different locations inside the solar cell;
圖3 顯示進行兩次不同能量及劑量的離子佈值後，空乏區寬度增加；Figure 3 shows that the width of the depletion zone increases after two different energy and dose ion cloth values are performed;
圖4A至4G顯示本發明的太陽能電池製程的示意圖；4A to 4G are schematic views showing the process of the solar cell of the present invention;
圖5A至5G顯示本發明之太陽能電池製程另一實施例的示意圖；及5A to 5G are views showing another embodiment of the solar cell process of the present invention; and
圖6A至6H顯示本發明之太陽能電池製程又一實施例的示意圖。6A to 6H are schematic views showing still another embodiment of the solar cell process of the present invention.
2．．．半導體基板2. . . Semiconductor substrate
20．．．第一摻雜區20. . . First doped region
21．．．第二摻雜區twenty one. . . Second doped region
22a．．．第一道pn接面空乏區22a. . . First pn junction
22b．．．第二道pn接面空乏區22b. . . Second pn junction
23．．．抗反射層twenty three. . . Antireflection layer
24．．．金屬twenty four. . . metal
26．．．刮棒26. . . Scraper
27．．．離子佈植罩冪27. . . Ion cloth cover power
Claims (10)
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| CN201110231923.4A CN102623312B (en) | 2011-01-31 | 2011-08-15 | Method and structure for increasing size of pn junction depletion region of solar cell |
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| TWI323009B (en) * | 2005-05-09 | 2010-04-01 | Tokyo Electron Ltd | Heating device, coating and developing apparatus, and heating method |
| TW201034235A (en) * | 2009-03-10 | 2010-09-16 | Neo Solar Power Corp | Processing method of semiconductor element |
| TW201036179A (en) * | 2009-03-19 | 2010-10-01 | Gintech Energy Corp | Non-linear design of sunnyside contact solar cells |
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| TWI323009B (en) * | 2005-05-09 | 2010-04-01 | Tokyo Electron Ltd | Heating device, coating and developing apparatus, and heating method |
| TW201034235A (en) * | 2009-03-10 | 2010-09-16 | Neo Solar Power Corp | Processing method of semiconductor element |
| TW201036179A (en) * | 2009-03-19 | 2010-10-01 | Gintech Energy Corp | Non-linear design of sunnyside contact solar cells |
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