TWI407542B - Substrate having semiconductor chip embedded therein and fabrication method thereof - Google Patents
Substrate having semiconductor chip embedded therein and fabrication method thereof Download PDFInfo
- Publication number
- TWI407542B TWI407542B TW097122816A TW97122816A TWI407542B TW I407542 B TWI407542 B TW I407542B TW 097122816 A TW097122816 A TW 097122816A TW 97122816 A TW97122816 A TW 97122816A TW I407542 B TWI407542 B TW I407542B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- dielectric layer
- opening
- circuit board
- semiconductor wafer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
本發明係有關於一種電路板及其製法,尤指一種嵌埋半導體元件之電路板及其製法。The present invention relates to a circuit board and a method of fabricating the same, and more particularly to a circuit board embedding a semiconductor component and a method of fabricating the same.
隨著電子產業的蓬勃發展,電子產品亦朝輕、薄、短、小、高集積度、多功能化方向發展。為滿足半導體封裝件高積集度(Integration)以及微型化(Miniaturization)的封裝需求,半導體晶片之封裝形逐漸由單一晶片之球柵陣列(BGA)封裝或覆晶式(Flip Chip,FC)封裝演進到模組化封裝形態,使得封裝結構有SIP(System Integrated Package)及SiB(System in Board)等多種形式。With the vigorous development of the electronics industry, electronic products are also developing in the direction of light, thin, short, small, high accumulation and multi-functionality. In order to meet the packaging requirements of semiconductor package high integration and miniaturization, the package shape of semiconductor wafers is gradually encapsulated by single-chip ball grid array (BGA) or flip chip (FC) package. It has evolved into a modular package form, and the package structure has various forms such as SIP (System Integrated Package) and SiB (System in Board).
惟,該些模組化封裝形態係為覆晶技術(flip chip)或打線技術(wire bonding),而將單一半導體晶片電性連接至封裝基板上,抑或使用表面黏貼技術(SMT)黏貼於基板表面;惟該半導體晶片係設置於基板上,因而不利於模組化結構尺寸之縮小及性能的提高。However, the modular package forms are flip chip or wire bonding, and a single semiconductor chip is electrically connected to the package substrate, or is adhered to the substrate by surface mount technology (SMT). The surface of the semiconductor wafer is disposed on the substrate, which is disadvantageous for the size reduction of the modular structure and the improvement of performance.
為此,遂有業界提出將半導體元件埋入基板之製法;請參閱第1A至1D圖所示之習知嵌埋半導體元件之基板之製法示意圖。For this reason, the industry has proposed a method of embedding a semiconductor element in a substrate; please refer to the schematic diagram of a conventional substrate for embedding a semiconductor element as shown in FIGS. 1A to 1D.
如第1A圖所示,提供一第一承載板11,於該第一承載板11上接置有一第二承載板12,且該第二承載板12具有相對之第一表面12a及第二表面12b,並於該第二承載板12中形成至少一貫穿該第一表面12a及第二表面 12b之開口120,使該第二承載板12之第二表面12b接合於該第一承載板11上,並封住該第二承載板12之開口120的一端。As shown in FIG. 1A, a first carrier 11 is disposed, and a second carrier 12 is disposed on the first carrier 11, and the second carrier 12 has an opposite first surface 12a and a second surface. 12b, and forming at least one through the first surface 12a and the second surface in the second carrier 12 The opening 120 of the second carrier 12 is joined to the first carrier 11 and encloses one end of the opening 120 of the second carrier 12 .
如第1B圖所示,提供一半導體晶片13,該半導體晶片13具有相對之作用面13a及非作用面13b,於該作用面13a上具有複數電極墊131,且藉由一黏著層14將該半導體晶片13之非作用面13b接置於該第二承載板12之開口120中的第一承載板11上。As shown in FIG. 1B, a semiconductor wafer 13 is provided. The semiconductor wafer 13 has an opposite active surface 13a and a non-active surface 13b. The active surface 13a has a plurality of electrode pads 131, and is adhered by an adhesive layer 14. The non-active surface 13b of the semiconductor wafer 13 is placed on the first carrier 11 in the opening 120 of the second carrier 12.
如第1C圖所示,於該第二承載板12及半導體晶片13之作用面13a上形成有介電層15,且該介電層15並填入該第二承載板12之開口120與半導體晶片13之間的間隙中,以將該半導體晶片13固定於該開口120中;惟該介電層15進行熱壓時,因為壓力不均,易造成該半導體晶片13於該開口120中產生偏移差e。As shown in FIG. 1C, a dielectric layer 15 is formed on the active surface 13a of the second carrier 12 and the semiconductor wafer 13, and the dielectric layer 15 is filled in the opening 120 of the second carrier 12 and the semiconductor. In the gap between the wafers 13 , the semiconductor wafer 13 is fixed in the opening 120; however, when the dielectric layer 15 is hot pressed, the semiconductor wafer 13 is liable to be biased in the opening 120 due to uneven pressure. Shift e.
如第1D圖所示,於該介電層15上形成有線路層16,且於該介電層15中形成有複數導電盲孔161,以電性連接該半導體晶片13之電極墊131;但由於熱壓形成該介電層15時該半導體晶片13發生偏移差e,造成該導電盲孔161連接該電極墊131之對位偏差,甚至因偏差過大而無法電性連接該電極墊131。As shown in FIG. 1D, a wiring layer 16 is formed on the dielectric layer 15, and a plurality of conductive vias 161 are formed in the dielectric layer 15 to electrically connect the electrode pads 131 of the semiconductor wafer 13; When the dielectric layer 15 is formed by hot pressing, the semiconductor wafer 13 is offset by e, which causes the conductive blind via 161 to be connected to the electrode pad 131, and the electrode pad 131 cannot be electrically connected even if the deviation is too large.
由上述可知,該半導體晶片13雖以該黏著層14接置於該第二承載板12之開口120中的第一承載板11上,於形成該介電層15並填入該半導體晶片13及第二承載板12之開口120之間的間隙時,仍然會造成容置於該開口 120中的半導體晶片13產生偏移;因此,該半導體晶片13在該開口120中產生偏移,導致該導電盲孔161連接該電極墊131之對位偏差,甚至因偏差過大而無法電性連接該電極墊131,進而影響電性連接之可靠度。As can be seen from the above, the semiconductor wafer 13 is placed on the first carrier 11 in the opening 120 of the second carrier 12 by the adhesive layer 14 to form the dielectric layer 15 and fill the semiconductor wafer 13 and When the gap between the openings 120 of the second carrier 12 is still placed in the opening The semiconductor wafer 13 in 120 is offset; therefore, the semiconductor wafer 13 is offset in the opening 120, causing the conductive blind via 161 to be connected to the alignment offset of the electrode pad 131, and even being electrically disconnected due to excessive deviation The electrode pad 131, in turn, affects the reliability of the electrical connection.
因此,如何提出一種嵌埋半導體元件之電路板,以避免習知之電路板嵌埋製程中,容置於核心板開口中的半導體元件產生偏移,實以成為目前業界亟待克服之課題。Therefore, how to propose a circuit board embedded with a semiconductor component to avoid the offset of the semiconductor component housed in the opening of the core board in the conventional circuit board embedding process has become an urgent problem to be overcome in the industry.
鑒於上述習知技術之種種缺失,本發明之主要目的在於提供一種嵌埋半導體元件之電路板及其製法,能將半導體晶片有效地固定於核心板開口中,以避免產生偏移。In view of the above-mentioned various deficiencies of the prior art, it is a primary object of the present invention to provide a circuit board in which a semiconductor element is embedded and a method of fabricating the same, which can effectively fix a semiconductor wafer in an opening of a core board to avoid offset.
為達上揭目的,本發明提供一種嵌埋半導體元件之電路板,係包括:核心板,係具有第一表面及相對應之第二表面,且具有至少一貫穿該第一表面及該第二表面之核心板開口;第一介電層,係形成於該核心板之第二表面,該第一介電層具有相對應該核心板開口之介電層開口;金屬層,係壓合於該第一介電層未接置該第二表面之表面上,該金屬層具有粗化面及非粗化面,並以該粗化面壓合於該第一介電層上,使該金屬層之粗化面顯露於該核心板開口及介電層開口中;黏著層,係覆設於該核心板開口及介電層開口中之粗化面上;以及半導體晶片,係接置於該黏著層上。In order to achieve the above, the present invention provides a circuit board embedded with a semiconductor component, comprising: a core plate having a first surface and a corresponding second surface, and having at least one through the first surface and the second a core plate opening of the surface; a first dielectric layer is formed on the second surface of the core plate, the first dielectric layer has a dielectric layer opening corresponding to the opening of the core plate; and the metal layer is pressed against the first layer a dielectric layer is not attached to the surface of the second surface, the metal layer has a roughened surface and a non-roughened surface, and the roughened surface is pressed onto the first dielectric layer to make the metal layer The roughened surface is exposed in the opening of the core plate and the opening of the dielectric layer; the adhesive layer is disposed on the roughened surface of the opening of the core plate and the opening of the dielectric layer; and the semiconductor wafer is attached to the adhesive layer on.
依上述之嵌埋半導體元件之電路板,該核心板係為絕緣板或具有線路之線路板;該金屬層係為銅箔;該半導 體晶片具有相對之作用面及非作用面,於該作用面具有電極墊,且該非作用面以黏著層接置於該核心板開口及介電層開口中之粗化面上。According to the above circuit board embedding a semiconductor component, the core board is an insulating board or a circuit board having a line; the metal layer is a copper foil; the semiconductor The body wafer has an opposite active surface and an inactive surface, and the active surface has an electrode pad, and the non-active surface is adhered to the roughened surface of the core plate opening and the dielectric layer opening by an adhesive layer.
依上述之結構,復包括於該核心板之第一表面及半導體晶片之作用面形成有增層結構,該增層結構係包括至少一第二介電層、設於該第二介電層上之線路層、及設於該第二介電層中之導電盲孔,該導電盲孔並電性連接該線路層與半導體晶片之電極墊,又於該增層結構之最外層線路層具有電性接觸墊,且於該增層結構之最外層覆設有防焊層,該防焊層並具有複數開孔,以對應露出各該電性接觸墊。According to the above structure, the first surface of the core board and the active surface of the semiconductor wafer are formed with a build-up structure, and the build-up structure includes at least one second dielectric layer disposed on the second dielectric layer. a circuit layer, and a conductive via hole disposed in the second dielectric layer, the conductive via hole is electrically connected to the circuit layer and the electrode pad of the semiconductor chip, and has electricity in the outermost circuit layer of the layered structure The contact pad is covered with a solder resist layer on the outermost layer of the build-up structure, and the solder resist layer has a plurality of openings to correspondingly expose the respective electrical contact pads.
依上所述,該第二介電層並填入該半導體晶片與核心板開口之間的間隙、以及該半導體晶片與介電層開口之間的間隙中。According to the above, the second dielectric layer fills the gap between the semiconductor wafer and the core plate opening, and the gap between the semiconductor wafer and the dielectric layer opening.
本發明復提供一種嵌埋半導體元件之電路板製法,係包括:提供一核心板,該核心板係具有第一表面及相對應之第二表面,且具有至少一貫穿該第一表面及該第二表面之核心板開口;於該第二表面形成有第一介電層,且該第一介電層具有介電層開口,以對應該核心板開口;於該第一介電層未接置該第二表面之表面上壓合一金屬層,該金屬層具有粗化面及非粗化面,並以該粗化面壓合於該第一介電層上,使該金屬層之粗化面顯露於該核心板開口及介電層開口中;於該核心板開口及介電層開口中之粗化面上形成有黏著層;以及於該黏著層上結合半導體晶片。The present invention provides a circuit board manufacturing method for embedding a semiconductor device, comprising: providing a core board having a first surface and a corresponding second surface, and having at least one through the first surface and the first a core plate opening of the two surfaces; a first dielectric layer is formed on the second surface, and the first dielectric layer has a dielectric layer opening to correspond to the core plate opening; and the first dielectric layer is not connected Pressing a metal layer on the surface of the second surface, the metal layer having a roughened surface and a non-roughened surface, and pressing the roughened surface on the first dielectric layer to roughen the metal layer The surface is exposed in the opening of the core plate and the opening of the dielectric layer; an adhesive layer is formed on the roughened surface of the opening of the core plate and the opening of the dielectric layer; and the semiconductor wafer is bonded to the adhesive layer.
依上述之嵌埋半導體元件之電路板製法,該核心板係為絕緣板或具有線路之線路板;該金屬層係為銅箔;該半導體晶片具有相對之作用面及非作用面,於該作用面具有電極墊,且以非作用面接置於該黏著層上。According to the circuit board manufacturing method for embedding a semiconductor device, the core board is an insulating board or a circuit board having a line; the metal layer is a copper foil; the semiconductor wafer has a relative active surface and a non-active surface. The surface has an electrode pad and is placed on the adhesive layer with an inactive surface.
依上述之製法,復包括於該核心板之第一表面及半導體晶片之作用面形成有增層結構,該增層結構係包括至少一第二介電層、形成於該第二介電層上之線路層、及形成於該第二介電層中之導電盲孔,該導電盲孔並電性連接該線路層與半導體晶片之電極墊,又於該增層結構之最外層線路層形成有複數電性接觸墊,且於該增層結構之最外層形成有防焊層,於該防焊層中形成有複數開孔,以對應露出各該電性接觸墊。According to the above method, the first surface of the core board and the active surface of the semiconductor wafer are formed with a build-up structure, and the build-up structure includes at least one second dielectric layer formed on the second dielectric layer. a circuit layer, and a conductive via hole formed in the second dielectric layer, the conductive via hole is electrically connected to the circuit layer and the electrode pad of the semiconductor wafer, and the outermost circuit layer of the buildup structure is formed A plurality of electrical contact pads are formed, and a solder resist layer is formed on an outermost layer of the build-up structure, and a plurality of openings are formed in the solder resist layer to correspondingly expose the respective electrical contact pads.
依上所述,該第二介電層並填入該半導體晶片與核心板開口之間的間隙、以及該半導體晶片與介電層開口之間的間隙中。According to the above, the second dielectric layer fills the gap between the semiconductor wafer and the core plate opening, and the gap between the semiconductor wafer and the dielectric layer opening.
本發明嵌埋半導體元件之電路板及其製法,係於具有核心板開口之核心板的第二表面形成具有介電層開口之第一介電層及金屬層,其中,該金屬層係以粗化面壓合於該第一介電層上,再將該半導體晶片之非作用面以黏著層結合於該粗化面上,俾藉由該粗化面以提高該半導體晶片與金屬層之間的結合性,以避免該半導體晶片於後續形成增層結構產生偏移的問題,進而使該增層結構之線路層中的導電盲孔能準確電性連接該半導體晶片之電極墊,以避免產生電性連接不良的情況,而能提高電性連接的可靠 度。A circuit board embedding a semiconductor device according to the present invention, and a method for manufacturing a first dielectric layer and a metal layer having a dielectric layer opening on a second surface of a core plate having a core plate opening, wherein the metal layer is thick The surface of the semiconductor wafer is bonded to the first dielectric layer, and the non-active surface of the semiconductor wafer is bonded to the roughened surface by an adhesive layer, and the roughened surface is used to improve the between the semiconductor wafer and the metal layer. The bonding is avoided to avoid the problem that the semiconductor wafer is offset in the subsequent formation of the build-up structure, so that the conductive blind holes in the wiring layer of the build-up structure can be electrically connected to the electrode pads of the semiconductor wafer to avoid generation. Poor electrical connection, and can improve the reliability of electrical connection degree.
以下係藉由特定的具體實例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點與功效。The embodiments of the present invention are described below by way of specific examples, and those skilled in the art can readily appreciate other advantages and functions of the present invention from the disclosure herein.
請參閱第2A至2F圖,係為本發明之嵌埋半導體元件之電路板及其製法實施例之剖面示意圖。2A to 2F are cross-sectional views showing a circuit board in which a semiconductor element is embedded in the present invention and a method of manufacturing the same.
如第2A圖所示,首先,提供一具有相對應之第一表面20a及第二表面20b之核心板20,該核心板20係為絕緣板或具有線路之線路板,並具有至少一貫穿該第一表面20a及第二表面20b之核心板開口200。As shown in FIG. 2A, firstly, a core board 20 having a corresponding first surface 20a and a second surface 20b is provided, and the core board 20 is an insulating board or a circuit board having a line, and has at least one through The core plate opening 200 of the first surface 20a and the second surface 20b.
如第2B圖所示,於該核心板20之第二表面20b形成有第一介電層21,且該第一介電層21具有相對應該核心板開口200之介電層開口210。As shown in FIG. 2B, a first dielectric layer 21 is formed on the second surface 20b of the core board 20, and the first dielectric layer 21 has a dielectric layer opening 210 corresponding to the core board opening 200.
如第2C圖所示,於該第一介電層21未接置該第二表面20b之表面上壓合一金屬層22,且該金屬層22具有粗化面22a及非粗化面22b,並以該粗化面22a壓合於該第一介電層21上,使該金屬層22之粗化面22a顯露於該核心板開口200及介電層開口210中;其中,該金屬層22係為銅箔(Copper foil)。As shown in FIG. 2C, a metal layer 22 is press-bonded on the surface of the first dielectric layer 21 where the second surface 20b is not connected, and the metal layer 22 has a roughened surface 22a and a non-roughened surface 22b. And the roughened surface 22a is pressed onto the first dielectric layer 21, and the roughened surface 22a of the metal layer 22 is exposed in the core plate opening 200 and the dielectric layer opening 210; wherein the metal layer 22 It is made of copper foil.
如第2D圖所示,於該核心板開口200及介電層開口210中之金屬層22的粗化面22a上以黏著層23結合一半導體晶片24,該半導體晶片24具有一作用面24a及與其相對應之非作用面24b,於該作用面24a具有複數電極墊 241。As shown in FIG. 2D, a semiconductor wafer 24 is bonded to the roughened surface 22a of the metal layer 22 in the core plate opening 200 and the dielectric layer opening 210. The semiconductor wafer 24 has an active surface 24a and The non-acting surface 24b corresponding thereto has a plurality of electrode pads on the active surface 24a 241.
如第2E圖所示,於該核心板20之第一表面20a及該半導體晶片24之作用面24a形成有增層結構25,該增層結構25係包括至少一第二介電層251、形成於該第二介電層251上之線路層252、及形成於該第二介電層251中之導電盲孔253,該導電盲孔253並電性連接該線路層252與半導體晶片24之電極墊241,又於該增層結構25之最外層線路層252形成有電性接觸墊254,且於該增層結構25之最外層覆設有防焊層26,該防焊層26並形成有複數開孔260,以對應露出各該電性接觸墊254;該第二介電層251並填入該半導體晶片24與核心板開口200、及半導體晶片24與介電層開口210之間的間隙中,以將該半導體晶片24固定於該核心板開口200及介電層開口210中。As shown in FIG. 2E, a first layer 20a of the core board 20 and an active surface 24a of the semiconductor wafer 24 are formed with a build-up structure 25, and the build-up structure 25 includes at least one second dielectric layer 251. a circuit layer 252 on the second dielectric layer 251, and a conductive via 253 formed in the second dielectric layer 251. The conductive via 253 is electrically connected to the circuit layer 252 and the electrode of the semiconductor wafer 24. The pad 241 is further formed with an electrical contact pad 254 on the outermost circuit layer 252 of the build-up structure 25, and a solder resist layer 26 is formed on the outermost layer of the build-up structure 25, and the solder resist layer 26 is formed with A plurality of openings 260 are formed to correspondingly expose the respective electrical contact pads 254; the second dielectric layer 251 is filled in the gap between the semiconductor wafer 24 and the core plate opening 200, and between the semiconductor wafer 24 and the dielectric layer opening 210. The semiconductor wafer 24 is fixed in the core plate opening 200 and the dielectric layer opening 210.
本發明復提供一種嵌埋半導體元件之電路板,係包括:核心板20,係具有第一表面20a及相對應之第二表面20b,且具有至少一貫穿該第一表面20a及該第二表面20b之核心板開口200;第一介電層21,係形成於該核心板20之第二表面20b,該第一介電層21具有相對應該核心板開口200之介電層開口210;金屬層22,係壓合於該第一介電層21未接置該第二表面20b之表面上,該金屬層22具有粗化面22a及非粗化面22b,並以該粗化面22a壓合於該第一介電層21上,使該金屬層22之粗化面22a顯露於該核心板開口200及介電層開口210中;黏著層 23,係覆設於該核心板開口200及介電層開口210中之粗化面22a上;以及半導體晶片24,係接置於該黏著層23上。The present invention provides a circuit board embedded with a semiconductor component, comprising: a core plate 20 having a first surface 20a and a corresponding second surface 20b, and having at least one through the first surface 20a and the second surface a core plate opening 200 of 20b; a first dielectric layer 21 is formed on the second surface 20b of the core plate 20, the first dielectric layer 21 has a dielectric layer opening 210 corresponding to the core plate opening 200; a metal layer 22, press-bonded to the surface of the first dielectric layer 21 not connected to the second surface 20b, the metal layer 22 having a roughened surface 22a and a non-roughened surface 22b, and pressed by the roughened surface 22a On the first dielectric layer 21, the roughened surface 22a of the metal layer 22 is exposed in the core plate opening 200 and the dielectric layer opening 210; the adhesive layer 23, which is disposed on the roughened surface 22a of the core plate opening 200 and the dielectric layer opening 210; and the semiconductor wafer 24 is attached to the adhesive layer 23.
依上述嵌埋半導體元件之電路板,該核心板20係為絕緣板或具有線路之線路板;該金屬層22係為銅箔;該半導體晶片24具有相對之作用面24a及非作用面24b,於該作用面24a具有電極墊241,且以非作用面24b接置於該粗化面22a上。According to the circuit board embedded with the semiconductor component, the core board 20 is an insulating board or a circuit board having a line; the metal layer 22 is a copper foil; the semiconductor wafer 24 has an opposite active surface 24a and an inactive surface 24b. The active surface 24a has an electrode pad 241, and is attached to the roughened surface 22a by an inactive surface 24b.
又依上述之結構,復包括黏著層23,係形成於該半導體晶片24之非作用面24b與粗化面22a之間。Further, according to the above configuration, the adhesive layer 23 is formed to be formed between the non-active surface 24b of the semiconductor wafer 24 and the roughened surface 22a.
再依上述之結構,復包括於該核心板20之第一表面20a及半導體晶片24之作用面24a形成有增層結構25,該增層結構25係包括至少一第二介電層251、設於該第二介電層251上之線路層252、及設於該第二介電層251中之導電盲孔253,該導電盲孔253並電性連接該線路層252與半導體晶片24之電極墊241,又於該增層結構25之最外層線路層252具有電性接觸墊254,且於該增層結構25之最外層覆設有防焊層26,該防焊層26並具有複數開孔260,以對應露出各該電性接觸墊254;該第二介電層251並填入該半導體晶片24與核心板開口200之間的間隙、該半導體晶片24與介電層開口210之間的間隙中。According to the above structure, the first surface 20a of the core board 20 and the active surface 24a of the semiconductor wafer 24 are formed with a build-up structure 25, and the build-up structure 25 includes at least one second dielectric layer 251. a circuit layer 252 on the second dielectric layer 251, and a conductive via 253 disposed in the second dielectric layer 251. The conductive via 253 is electrically connected to the circuit layer 252 and the electrode of the semiconductor wafer 24. The pad 241 has an electrical contact pad 254 on the outermost circuit layer 252 of the build-up structure 25, and a solder resist layer 26 is disposed on the outermost layer of the build-up structure 25, and the solder resist layer 26 has a plurality of openings. a hole 260 correspondingly exposing each of the electrical contact pads 254; the second dielectric layer 251 is filled between the semiconductor wafer 24 and the core plate opening 200, and between the semiconductor wafer 24 and the dielectric layer opening 210 In the gap.
綜上所述,本發明嵌埋半導體元件之電路板及其製法,係於具有核心板開口之核心板的第二表面形成具有介 電層開口之第一介電層及金屬層,其中,該金屬層係以粗化面壓合於該第一介電層上,再將該半導體晶片之非作用面以黏著層結合於該粗化面上,俾藉由該粗化面以提高該半導體晶片與金屬層之間的結合性,以避免該半導體晶片於後續形成增層結構產生偏移的問題,進而使該增層結構之線路層中的導電盲孔能準確電性連接該半導體晶片之電極墊,以避免產生電性連接不良的情況,而能提高電性連接的可靠度。In summary, the circuit board with embedded semiconductor components of the present invention and the method for fabricating the same are formed on the second surface of the core plate having the opening of the core plate. a first dielectric layer and a metal layer of the electrical layer, wherein the metal layer is pressed onto the first dielectric layer with a roughened surface, and the non-active surface of the semiconductor wafer is bonded to the thick layer by an adhesive layer The roughening surface is used to improve the bonding between the semiconductor wafer and the metal layer to avoid the problem that the semiconductor wafer is offset in the subsequent formation of the build-up structure, thereby making the line of the build-up structure The conductive blind holes in the layer can accurately electrically connect the electrode pads of the semiconductor wafer to avoid the occurrence of electrical connection failure, and can improve the reliability of the electrical connection.
上述實施例僅例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修飾與改變。因此,本發明之權利保護範圍,應如後述之申請專利範圍所列。The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Modifications and variations of the above-described embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the scope of the claims described below.
11‧‧‧第一承載板11‧‧‧First carrier board
12‧‧‧第二承載板12‧‧‧Second carrier board
120‧‧‧開口120‧‧‧ openings
12a、20a‧‧‧第一表面12a, 20a‧‧‧ first surface
12b、20b‧‧‧第二表面12b, 20b‧‧‧ second surface
13、24‧‧‧半導體晶片13, 24‧‧‧ semiconductor wafer
13a、24a‧‧‧作用面13a, 24a‧‧‧ action surface
13b、24b‧‧‧非作用面13b, 24b‧‧‧ non-active surface
131、241‧‧‧電極墊131, 241‧‧ ‧ electrode pads
14、23‧‧‧黏著層14, 23‧‧‧ adhesive layer
15‧‧‧介電層15‧‧‧Dielectric layer
16、252‧‧‧線路層16, 252‧‧‧ circuit layer
161、253‧‧‧導電盲孔161, 253‧‧ ‧ conductive blind holes
20‧‧‧核心板20‧‧‧ core board
200‧‧‧核心板開口200‧‧‧ core plate opening
21‧‧‧第一介電層21‧‧‧First dielectric layer
210‧‧‧介電層開口210‧‧‧Dielectric layer opening
22‧‧‧金屬層22‧‧‧metal layer
22a‧‧‧粗化面22a‧‧‧ roughened surface
22b‧‧‧非粗化面22b‧‧‧non-roughened surface
25‧‧‧增層結構25‧‧‧Additional structure
251‧‧‧第二介電層251‧‧‧Second dielectric layer
254‧‧‧電性接觸墊254‧‧‧Electrical contact pads
26‧‧‧防焊層26‧‧‧ solder mask
260‧‧‧開孔260‧‧‧ openings
e‧‧‧偏移差e‧‧‧Offset difference
第1A至1D圖係為習知核心電路板之製法之剖面示意圖;以及第2A至2E圖係為本發明嵌埋半導體元件之電路板及其製法之剖面示意圖。1A to 1D are schematic cross-sectional views showing a method of manufacturing a conventional core circuit board; and Figs. 2A to 2E are schematic cross-sectional views showing a circuit board in which a semiconductor element is embedded and a method of manufacturing the same.
20‧‧‧核心板20‧‧‧ core board
20a‧‧‧第一表面20a‧‧‧ first surface
20b‧‧‧第二表面20b‧‧‧second surface
200‧‧‧核心板開口200‧‧‧ core plate opening
24‧‧‧半導體晶片24‧‧‧Semiconductor wafer
24a‧‧‧作用面24a‧‧‧Action surface
24b‧‧‧非作用面24b‧‧‧Non-active surface
241‧‧‧電極墊241‧‧‧electrode pads
21‧‧‧第一介電層21‧‧‧First dielectric layer
210‧‧‧介電層開口210‧‧‧Dielectric layer opening
22‧‧‧金屬層22‧‧‧metal layer
22a‧‧‧粗化面22a‧‧‧ roughened surface
23‧‧‧黏著層23‧‧‧Adhesive layer
Claims (14)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW097122816A TWI407542B (en) | 2008-06-19 | 2008-06-19 | Substrate having semiconductor chip embedded therein and fabrication method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW097122816A TWI407542B (en) | 2008-06-19 | 2008-06-19 | Substrate having semiconductor chip embedded therein and fabrication method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201001662A TW201001662A (en) | 2010-01-01 |
TWI407542B true TWI407542B (en) | 2013-09-01 |
Family
ID=44824931
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW097122816A TWI407542B (en) | 2008-06-19 | 2008-06-19 | Substrate having semiconductor chip embedded therein and fabrication method thereof |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI407542B (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI418003B (en) | 2011-04-28 | 2013-12-01 | Unimicron Technology Corp | Package structure having embedded electronic component and fabrication method thereof |
TWI503902B (en) * | 2013-11-29 | 2015-10-11 | 矽品精密工業股份有限公司 | Semiconductor package and manufacturing method thereof |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20020043672A (en) * | 2000-12-02 | 2002-06-12 | 마이클 디. 오브라이언 | Substrate for manufacturing semiconductor package and method for manufacturing the same |
US6455408B1 (en) * | 1999-09-30 | 2002-09-24 | Samsung Electronics Co., Ltd. | Method for manufacturing semiconductor devices having redistribution patterns with a concave pattern in a bump pad area |
JP2004063742A (en) * | 2002-07-29 | 2004-02-26 | Hitachi Chem Co Ltd | Wiring board, semiconductor package and method for manufacturing them |
US20040232534A1 (en) * | 2003-05-22 | 2004-11-25 | Shinko Electric Industries, Co., Ltd. | Packaging component and semiconductor package |
JP2005353821A (en) * | 2004-06-10 | 2005-12-22 | Yamaha Corp | Semiconductor element, its manufacturing method, and wafer-level chip-size package provided therewith |
JP2006080576A (en) * | 2005-12-05 | 2006-03-23 | Shinko Electric Ind Co Ltd | Package component and its manufacturing method, and semiconductor package |
TWI275149B (en) * | 2005-05-09 | 2007-03-01 | Phoenix Prec Technology Corp | Surface roughing method for embedded semiconductor chip structure |
-
2008
- 2008-06-19 TW TW097122816A patent/TWI407542B/en active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6455408B1 (en) * | 1999-09-30 | 2002-09-24 | Samsung Electronics Co., Ltd. | Method for manufacturing semiconductor devices having redistribution patterns with a concave pattern in a bump pad area |
KR20020043672A (en) * | 2000-12-02 | 2002-06-12 | 마이클 디. 오브라이언 | Substrate for manufacturing semiconductor package and method for manufacturing the same |
JP2004063742A (en) * | 2002-07-29 | 2004-02-26 | Hitachi Chem Co Ltd | Wiring board, semiconductor package and method for manufacturing them |
US20040232534A1 (en) * | 2003-05-22 | 2004-11-25 | Shinko Electric Industries, Co., Ltd. | Packaging component and semiconductor package |
JP2005353821A (en) * | 2004-06-10 | 2005-12-22 | Yamaha Corp | Semiconductor element, its manufacturing method, and wafer-level chip-size package provided therewith |
TWI275149B (en) * | 2005-05-09 | 2007-03-01 | Phoenix Prec Technology Corp | Surface roughing method for embedded semiconductor chip structure |
JP2006080576A (en) * | 2005-12-05 | 2006-03-23 | Shinko Electric Ind Co Ltd | Package component and its manufacturing method, and semiconductor package |
Also Published As
Publication number | Publication date |
---|---|
TW201001662A (en) | 2010-01-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI418003B (en) | Package structure having embedded electronic component and fabrication method thereof | |
JP4361826B2 (en) | Semiconductor device | |
US8669653B2 (en) | Semiconductor device having electronic component in through part, electronic device, and manufacturing method of semiconductor | |
TWI496254B (en) | Package structure of embedded semiconductor component and manufacturing method thereof | |
TW200908268A (en) | Packaging substrate structure with capacitor embedded therein and method for fabricating the same | |
TW201410089A (en) | Package on package structure and method for manufacturing same | |
TWI384602B (en) | Package substrate having embedded photosensitive semiconductor chip and fabrication method thereof | |
TWI511250B (en) | Ic substrate,semiconductor device with ic substrate and manufucturing thereof | |
TWI498056B (en) | Printed circuit board with burried element and method for manufacture same and package structure | |
TWI380419B (en) | Integrated circuit package and the method for fabricating thereof | |
TWI550744B (en) | Single-layered circuit-type package substrate and the manufacture thereof, single-layered circuit-type package structure and the manufacture thereof | |
TWI407542B (en) | Substrate having semiconductor chip embedded therein and fabrication method thereof | |
TWI438880B (en) | Package structure having (tsv) through-silicon-vias chip embedded therein and fabrication method thereof | |
TWI392073B (en) | Fabrication method of package substrate having semiconductor component embedded therein | |
TWI546931B (en) | Method for manufacturing semiconductor device | |
TWI483321B (en) | Package on package structure and method for manufacturing same | |
TWI416682B (en) | Package structure | |
TW201110250A (en) | Package substrate structure and method of forming same | |
TWI394250B (en) | Package structure and fabrication method thereof | |
TWI658557B (en) | Load circuit board and methord for manufacturing the same | |
KR20100002870A (en) | Method for fabricating semiconductor package | |
KR20080048846A (en) | Stack structure of carrier board embedded with semiconductor components and method for fabricating the same | |
TWI758756B (en) | Package carrier and manufacturing method thereof | |
TWI541952B (en) | Semiconductor package and manufacturing method thereof | |
TW201446086A (en) | Package structure and method for manufacturing same |