TWI541952B - Semiconductor package and manufacturing method thereof - Google Patents

Semiconductor package and manufacturing method thereof Download PDF

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Publication number
TWI541952B
TWI541952B TW102146553A TW102146553A TWI541952B TW I541952 B TWI541952 B TW I541952B TW 102146553 A TW102146553 A TW 102146553A TW 102146553 A TW102146553 A TW 102146553A TW I541952 B TWI541952 B TW I541952B
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Taiwan
Prior art keywords
encapsulant
semiconductor package
electrical connection
connection pad
adhesive layer
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TW102146553A
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Chinese (zh)
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TW201526174A (en
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陳彥亨
林畯棠
紀傑元
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矽品精密工業股份有限公司
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Priority to TW102146553A priority Critical patent/TWI541952B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

半導體封裝件及其製法 Semiconductor package and its manufacturing method

本發明提供一種封裝件及其製法，尤指一種半導體封裝件及其製法。 The invention provides a package and a manufacturing method thereof, in particular to a semiconductor package and a manufacturing method thereof.

隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。為了滿足半導體封裝件微型化(miniaturization)的封裝需求，遂發展出許多封裝技術。 With the rapid development of the electronics industry, electronic products are gradually moving towards multi-functional and high-performance trends. In order to meet the packaging requirements of semiconductor package miniaturization, many packaging technologies have been developed.

請參照第1A至1H圖，係為習知技術中形成半導體封裝件之各步驟製程的剖視圖。 Please refer to FIGS. 1A to 1H for a cross-sectional view showing the steps of forming a semiconductor package in the prior art.

如第1A圖所示，首先提供一其上形成有第一黏著層122a的第一承載板12a，第一承載板12a之材質可為玻璃、金屬及陶瓷等等。 As shown in FIG. 1A, a first carrier 12a having a first adhesive layer 122a formed thereon may be provided. The material of the first carrier 12a may be glass, metal, ceramics or the like.

之後，如第1B圖所示地將具有作用面132及形成在作用面132處之銲墊134的晶片13接置於第一黏著層122a上。 Thereafter, the wafer 13 having the active surface 132 and the pads 134 formed at the active surface 132 is placed on the first adhesive layer 122a as shown in FIG. 1B.

而後，如第1C圖所示地於第一黏著層122a上形成封裝膠體11以包覆晶片13，並在之後於封裝膠體11上接置第二承載板12b，其中，第二承載板12b係可選擇性地在其表面上形成有第二黏著層122b，以藉由第二黏著層122b接置封裝膠體11。 Then, the encapsulant 11 is formed on the first adhesive layer 122a to cover the wafer 13 as shown in FIG. 1C, and then the second carrier 12b is attached to the encapsulant 11, wherein the second carrier 12b is A second adhesive layer 122b may be selectively formed on the surface thereof to attach the encapsulant 11 by the second adhesive layer 122b.

之後，如第1D圖所示地將第一黏著層122a及第一承載板12a從作用面132及封裝膠體11的表面上移除。 Thereafter, the first adhesive layer 122a and the first carrier 12a are removed from the surface of the active surface 132 and the encapsulant 11 as shown in FIG. 1D.

接著如第1E圖所示地將線路重佈層15形成在作用面132及封裝膠體11的外露表面上，並使線路重佈層15電性連接晶片13。更具體而言，線路重佈層15係具有介電層150、線路(未標元件符號)、第一電性連接墊152、導電盲孔154及第二電性連接墊156，其中，介電層150係形成在作用面132及封裝膠體11的外露表面上，而介電層150內係在與該外露表面相接的一側形成有電性連接於銲墊134的第一電性連接墊152，此外第一電性連接墊152與封裝膠體11連接側之另一側上係形成有與其電性連接之導電盲孔154，而導電盲孔154與第一電性連接墊152電性連接側的另一側上則形成有第二電性連接墊156。 Next, as shown in FIG. 1E, the circuit redistribution layer 15 is formed on the exposed surface of the active surface 132 and the encapsulant 11, and the circuit redistribution layer 15 is electrically connected to the wafer 13. More specifically, the circuit redistribution layer 15 has a dielectric layer 150, a line (unmarked component symbol), a first electrical connection pad 152, a conductive blind via 154, and a second electrical connection pad 156, wherein the dielectric layer The layer 150 is formed on the exposed surface of the active surface 132 and the encapsulant 11 , and the first electrical connection pad electrically connected to the bonding pad 134 is formed on the side of the dielectric layer 150 on the side contacting the exposed surface. 152. Further, on the other side of the connection side of the first electrical connection pad 152 and the encapsulant 11, a conductive via 154 electrically connected thereto is formed, and the conductive via 154 is electrically connected to the first electrical connection pad 152. A second electrical connection pad 156 is formed on the other side of the side.

隨後，如第1F圖所示地將形成於第三承載板12c上的第三黏著層122c接置於線路重佈層15上。 Subsequently, the third adhesive layer 122c formed on the third carrier 12c is placed on the line redistribution layer 15 as shown in Fig. 1F.

接著，如第1G圖所示地將第二承載板12b及第二黏著層122b一併移除。 Next, the second carrier 12b and the second adhesive layer 122b are collectively removed as shown in FIG. 1G.

最後，如第1H圖所示地在封裝膠體11中以雷射鑽孔的方式形成封裝膠體開孔112，以外露第一電性連接墊152。後續將於該封裝膠體開孔112中形成導電材料(未圖示)，並藉由該導電材料電性連接另一封裝結構，而形成半導體封裝件(省略後續步驟之圖式)。 Finally, as shown in FIG. 1H, the encapsulation opening 112 is formed by laser drilling in the encapsulant 11 to expose the first electrical connection pad 152. A conductive material (not shown) is formed in the encapsulation opening 112, and the other package structure is electrically connected to the semiconductor package to form a semiconductor package (the following steps are omitted).

然而，於第1H圖之步驟中，由於習知技術之雷射能量不易控制或其功率不穩定，故容易使線路重佈層中之第一電性連接墊152因雷射燒蝕而造成斷路等狀況，進而造成良率過低及產品可 靠度不佳等問題。 However, in the step of FIG. 1H, since the laser energy of the prior art is difficult to control or its power is unstable, it is easy to cause the first electrical connection pad 152 in the circuit redistribution layer to be broken due to laser ablation. And other conditions, resulting in low yield and product availability Problems such as poor reliability.

因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。 Therefore, how to overcome the various problems of the above-mentioned prior art has become a problem that is currently being solved.

有鑒於上述習知技術之缺失，本發明提供一種半導體封裝件之製法，係包括：於一其上形成有第一黏著層的第一承載板上接置具有作用面之晶片，令該晶片藉其作用面接置於該第一承載板之第一黏著層上；於該第一黏著層上形成包覆該晶片的封裝膠體，該封裝膠體具有結合至該第一黏著層的第一表面及與其相對之第二表面；形成複數外露該第一黏著層的封裝膠體開孔；於各該封裝膠體開孔中的第一黏著層上形成電性連接墊；於各該電性連接墊上接置第一導電元件；藉由第二黏著層於該封裝膠體之第二表面上接置第二承載板；移除該第一承載板與第一黏著層；於該封裝膠體之第一表面上形成電性連接該作用面與電性連接墊的線路重佈層；以及移除該第二承載板與第二黏著層。 In view of the above-mentioned deficiencies of the prior art, the present invention provides a method for fabricating a semiconductor package, comprising: attaching a wafer having an active surface to a first carrier plate on which a first adhesive layer is formed, and borrowing the wafer The active surface is disposed on the first adhesive layer of the first carrier; the encapsulant covering the wafer is formed on the first adhesive layer, and the encapsulant has a first surface bonded to the first adhesive layer and a second surface; a plurality of encapsulation openings exposing the first adhesive layer; forming an electrical connection pad on the first adhesive layer in each of the encapsulation openings; and connecting the electrical connection pads a conductive member; the second carrier is attached to the second surface of the encapsulant by the second adhesive layer; the first carrier and the first adhesive layer are removed; and the first surface of the encapsulant is electrically formed And connecting the active surface to the circuit redistribution layer of the electrical connection pad; and removing the second carrier plate and the second adhesive layer.

於本發明之製法中，於形成該線路重佈層之後，復包括於該線路重佈層上接置複數第二導電元件，且於移除該第二承載板與第二黏著層之後，復包括於該封裝膠體之第二表面上方接置一電子元件，該電子元件係經由該第一導電元件電性連接該線路重佈層。 In the method of the present invention, after the circuit redistribution layer is formed, the plurality of second conductive elements are connected to the circuit redistribution layer, and after the second carrier and the second adhesive layer are removed, An electronic component is disposed above the second surface of the encapsulant, and the electronic component is electrically connected to the circuit redistribution layer via the first conductive component.

依前述之半導體封裝件之製法，該電子元件復包括用以電性連接該第一導電元件的第三導電元件，且該電子元件係為半導體晶片或封裝結構。 According to the foregoing method of fabricating a semiconductor package, the electronic component includes a third conductive component for electrically connecting the first conductive component, and the electronic component is a semiconductor wafer or a package structure.

於本發明之製法中，該封裝膠體開孔係藉由雷射來形成，形 成該電性連接墊之材料係為銅，且形成該電性連接墊之方式係為濺鍍。 In the manufacturing method of the present invention, the encapsulation colloid is formed by laser, and the shape is formed. The material of the electrical connection pad is copper, and the manner of forming the electrical connection pad is sputtering.

本發明復提供一種半導體封裝件，係包括：封裝膠體，係具有相對之第一表面與第二表面及複數貫穿該第一表面與第二表面之封裝膠體開孔；晶片，係嵌埋於該封裝膠體中，且具有外露於該封裝膠體之第一表面的作用面；線路重佈層，係形成於該封裝膠體之第一表面上；電性連接墊，係形成於外露於該封裝膠體開孔的線路重佈層上，且電性連接該線路重佈層；以及第一導電元件，係接置於該電性連接墊上。 The present invention further provides a semiconductor package comprising: an encapsulant having opposite first and second surfaces and a plurality of encapsulation openings extending through the first surface and the second surface; the wafer is embedded in the The encapsulant has an active surface exposed on the first surface of the encapsulant; the circuit redistribution layer is formed on the first surface of the encapsulant; and the electrical connection pad is formed on the exposed encapsulant The circuit is re-distributed on the circuit and electrically connected to the circuit redistribution layer; and the first conductive component is electrically connected to the electrical connection pad.

於前述之半導體封裝件中，復包括複數第二導電元件，係接置於該線路重佈層上，並復包括電子元件，係接置於該封裝膠體之第二表面上方，且經由該第一導電元件電性連接該線路重佈層，該電子元件復包括用以電性連接該第一導電元件的第三導電元件。 In the foregoing semiconductor package, the plurality of second conductive elements are further disposed on the circuit redistribution layer, and further comprise electronic components connected to the second surface of the encapsulant, and A conductive element is electrically connected to the circuit redistribution layer, and the electronic component further comprises a third conductive component for electrically connecting the first conductive component.

於前所述之半導體封裝件，該電子元件係為半導體晶片或封裝結構，且形成該電性連接墊之材料係銅，該封裝膠體開孔係呈該第一表面端窄且第二表面端寬的錐形，且該電性連接墊係填滿該封裝膠體開孔之第一表面端而呈錐形。 In the semiconductor package described above, the electronic component is a semiconductor wafer or a package structure, and the material forming the electrical connection pad is copper. The encapsulation colloid has a narrow first surface end and a second surface end. The utility model has a wide taper shape, and the electrical connection pad fills the first surface end of the encapsulation opening and is tapered.

本發明係於形成封裝膠體開孔後才形成線路重佈層，所以能克服習知之形成封裝膠體開孔時容易損傷線路重佈層，進而造成線路斷路之缺點，以提高線路重佈層的良率與產品可靠度。 The invention forms the circuit redistribution layer after forming the opening of the encapsulant, so that it can overcome the shortcomings of the prior art to form the re-distribution layer of the encapsulation colloid, thereby causing the circuit to be broken, thereby improving the line redistribution layer. Rate and product reliability.

11、23‧‧‧封裝膠體 11, 23‧‧‧Package colloid

112、230‧‧‧封裝膠體開孔 112, 230‧‧‧Package colloid opening

12a、20‧‧‧第一承載板 12a, 20‧‧‧ first carrier board

12b、27‧‧‧第二承載板 12b, 27‧‧‧second carrier board

12c‧‧‧第三承載板 12c‧‧‧ third carrier board

122a、21‧‧‧第一黏著層 122a, 21‧‧‧ first adhesive layer

122b、26‧‧‧第二黏著層 122b, 26‧‧‧ second adhesive layer

122c‧‧‧第三黏著層 122c‧‧‧ third adhesive layer

13、22‧‧‧晶片 13, 22‧‧‧ wafer

132、221‧‧‧作用面 132, 221‧‧‧ action surface

134‧‧‧銲墊 134‧‧‧ solder pads

15、28‧‧‧線路重佈層 15, 28‧‧‧Line redistribution

150‧‧‧介電層 150‧‧‧ dielectric layer

152‧‧‧第一電性連接墊 152‧‧‧First electrical connection pad

154‧‧‧導電盲孔 154‧‧‧ Conductive blind holes

156‧‧‧第二電性連接墊 156‧‧‧Second electrical connection pad

23a‧‧‧第一表面 23a‧‧‧ first surface

23b‧‧‧第二表面 23b‧‧‧ second surface

24‧‧‧電性連接墊 24‧‧‧Electrical connection pads

25‧‧‧第一導電元件 25‧‧‧First conductive element

29‧‧‧第二導電元件 29‧‧‧Second conductive element

30‧‧‧電子元件 30‧‧‧Electronic components

31‧‧‧第三導電元件 31‧‧‧ Third conductive element

第1A至1H圖係說明習知技術中形成半導體封裝件之各步驟的剖視圖；以及 第2A至2K圖係本發明之半導體封裝件之製法的剖視。 1A to 1H are cross-sectional views illustrating respective steps of forming a semiconductor package in the prior art; 2A to 2K are cross-sectional views showing a method of manufacturing the semiconductor package of the present invention.

以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。本發明亦可藉由其它不同的具體實施例加以施行或應用，本說明書中的各項細節亦可基於不同觀點與應用，在不悖離本發明之精神下進行各種修飾與變更。 The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes can be made without departing from the spirit and scope of the invention.

請參閱第2A至2K圖，其係本發明之半導體封裝件之製法的剖視圖。 Please refer to FIGS. 2A to 2K, which are cross-sectional views showing the method of fabricating the semiconductor package of the present invention.

首先，請參照第2A圖，提供一其上形成有第一黏著層21的第一承載板20，該第一承載板20之材質可為玻璃、金屬及陶瓷等等。 First, referring to FIG. 2A, a first carrier 20 on which the first adhesive layer 21 is formed may be provided. The material of the first carrier 20 may be glass, metal, ceramic or the like.

接著，請參照第2B圖，於該第一黏著層21上接置晶片22，而該晶片22係具有接置於第一黏著層21上的作用面221。 Next, referring to FIG. 2B, the wafer 22 is attached to the first adhesive layer 21, and the wafer 22 has an active surface 221 attached to the first adhesive layer 21.

請參照第2C圖，於該第一黏著層21上形成包覆該晶片22的封裝膠體23，令該封裝膠體23具有接觸該第一黏著層21的第一表面23a與其相對之第二表面23b。 Referring to FIG. 2C, an encapsulant 23 covering the wafer 22 is formed on the first adhesive layer 21, so that the encapsulant 23 has a first surface 23a contacting the first adhesive layer 21 and a second surface 23b opposite thereto. .

請參照第2D圖，藉由雷射形成外露該第一黏著層21的封裝膠體開孔230，該封裝膠體開孔230係可呈該第一表面23a端窄且第二表面23b端寬的錐形。 Referring to FIG. 2D, the encapsulation opening 230 exposing the first adhesive layer 21 is formed by laser. The encapsulation opening 230 is a cone having a narrow end of the first surface 23a and a width of the second surface 23b. shape.

請參照第2E圖，於該封裝膠體開孔230中的第一黏著層21上形成電性連接墊24，形成該電性連接墊24之材料可為銅，且形成該電性連接墊24之方式可為濺鍍，且該電性連接墊24可填滿該封裝膠體開孔230之第一表面23a端而呈錐形。 Referring to FIG. 2E, an electrical connection pad 24 is formed on the first adhesive layer 21 of the encapsulation opening 230. The material forming the electrical connection pad 24 may be copper, and the electrical connection pad 24 is formed. The method can be sputtering, and the electrical connection pad 24 can fill the first surface 23a end of the encapsulation opening 230 to be tapered.

請參照第2F圖，於該電性連接墊24上接置例如銲球的第一導電元件25。 Referring to FIG. 2F, a first conductive element 25 such as a solder ball is attached to the electrical connection pad 24.

請參照第2G圖，藉由第二黏著層26於該封裝膠體23之第二表面23b上接置第二承載板27。 Referring to FIG. 2G, the second carrier layer 27 is attached to the second surface 23b of the encapsulant 23 by the second adhesive layer 26.

請參照第2H圖，移除該第一承載板20與第一黏著層21。 Referring to FIG. 2H, the first carrier 20 and the first adhesive layer 21 are removed.

請參照第2I圖，於該封裝膠體23之第一表面23a上形成電性連接該作用面221與電性連接墊24的線路重佈層28，並於該線路重佈層28上接置複數第二導電元件29。 Referring to FIG. 2I, a circuit redistribution layer 28 electrically connecting the active surface 221 and the electrical connection pad 24 is formed on the first surface 23a of the encapsulant 23, and a plurality of circuit redistribution layers 28 are connected to the circuit redistribution layer 28. Second conductive element 29.

請參照第2J圖，移除該第二承載板27與第二黏著層26。 Referring to FIG. 2J, the second carrier plate 27 and the second adhesive layer 26 are removed.

請參照第2K圖，於該封裝膠體23之第二表面23b上方接置一電子元件30，該電子元件30係經由該第一導電元件25電性連接該線路重佈層28，該電子元件30復包括用以電性連接該第一導電元件25的第三導電元件31，於本實施例中，該電子元件30係為一封裝結構，而最終構成一層疊式封裝件(package on package，簡稱POP)，但本發明之電子元件30亦可為半導體晶片。 An electronic component 30 is connected to the second surface 23b of the encapsulant 23, and the electronic component 30 is electrically connected to the circuit redistribution layer 28 via the first conductive component 25, the electronic component 30. The third conductive element 31 is electrically connected to the first conductive element 25. In the embodiment, the electronic component 30 is a package structure, and finally constitutes a package on package. POP), but the electronic component 30 of the present invention may also be a semiconductor wafer.

本發明復提供一種半導體封裝件，係包括：封裝膠體23，係具有相對之第一表面23a與第二表面23b及複數貫穿該第一表面23a與第二表面23b之封裝膠體開孔230；晶片22，係嵌埋於該封裝膠體23中，且具有外露於該封裝膠體23之第一表面23a的作用面221；線路重佈層28，係形成於該封裝膠體23之第一表面23a上；電性連接墊24，係形成於外露於該封裝膠體開孔230的線路重佈層28上，且電性連接該線路重佈層28；以及第一導電元件25，係接置於該電性連接墊24上。 The present invention further provides a semiconductor package comprising: an encapsulant 23 having opposite first and second surfaces 23a and 23b, and a plurality of encapsulating openings 230 extending through the first surface 23a and the second surface 23b; 22, embedded in the encapsulant 23, and having an active surface 221 exposed on the first surface 23a of the encapsulant 23; a circuit redistribution layer 28 is formed on the first surface 23a of the encapsulant 23; The electrical connection pad 24 is formed on the circuit redistribution layer 28 exposed on the encapsulation opening 230, and electrically connected to the circuit redistribution layer 28; and the first conductive component 25 is connected to the electrical property. Connected to the pad 24.

於本實施例之半導體封裝件中，復包括複數第二導電元件 29，係接置於該線路重佈層28上，且復包括電子元件30，係接置於該封裝膠體23之第二表面23b上方，且經由該第一導電元件25電性連接該線路重佈層28。 In the semiconductor package of the embodiment, the plurality of second conductive elements are further included 29, is connected to the circuit redistribution layer 28, and further includes an electronic component 30, which is connected to the second surface 23b of the encapsulant 23, and is electrically connected to the line via the first conductive component 25 Cloth layer 28.

依前所述之半導體封裝件，該電子元件30復包括用以電性連接該第一導電元件25的第三導電元件31，該電子元件30係為半導體晶片或封裝結構，且形成該電性連接墊24之材料係銅，該封裝膠體開孔230係呈該第一表面23a端窄且第二表面23b端寬的錐形，且該電性連接墊24係填滿該封裝膠體開孔230之第一表面23a端而呈錐形。 According to the semiconductor package described above, the electronic component 30 includes a third conductive component 31 for electrically connecting the first conductive component 25, and the electronic component 30 is a semiconductor wafer or package structure, and the electrical property is formed. The material of the connection pad 24 is copper. The encapsulation opening 230 is tapered with the end of the first surface 23a and the end of the second surface 23b, and the electrical connection pad 24 fills the encapsulation opening 230. The first surface 23a end is tapered.

綜上所述，相較於習知技術，由於本發明係於形成封裝膠體開孔後才形成線路重佈層，所以能克服習知之形成封裝膠體開孔時容易損傷線路重佈層，進而造成線路斷路之缺點，以提高線路重佈層的良率與產品可靠度。 In summary, compared with the prior art, since the present invention forms the circuit redistribution layer after forming the encapsulation opening of the encapsulant, it can overcome the conventional formation of the encapsulation colloid opening, which is easy to damage the re-layer of the circuit, thereby causing The shortcomings of line breaking are to improve the yield of the line redistribution layer and product reliability.

上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。 The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

22‧‧‧晶片 22‧‧‧ wafer

221‧‧‧作用面 221‧‧‧Action surface

23‧‧‧封裝膠體 23‧‧‧Package colloid

230‧‧‧封裝膠體開孔 230‧‧‧Package colloid opening

23a‧‧‧第一表面 23a‧‧‧ first surface

23b‧‧‧第二表面 23b‧‧‧ second surface

24‧‧‧電性連接墊 24‧‧‧Electrical connection pads

25‧‧‧第一導電元件 25‧‧‧First conductive element

28‧‧‧線路重佈層 28‧‧‧Line redistribution

29‧‧‧第二導電元件 29‧‧‧Second conductive element

Claims (15)

一種半導體封裝件之製法，係包括：於一其上形成有第一黏著層的第一承載板上接置具有作用面之晶片，令該晶片藉其作用面接置於該第一承載板之第一黏著層上；於該第一黏著層上形成包覆該晶片的封裝膠體，該封裝膠體具有結合至該第一黏著層的第一表面及與其相對之第二表面；形成複數外露該第一黏著層的封裝膠體開孔；於各該封裝膠體開孔中的第一黏著層上形成電性連接墊；於各該電性連接墊上接置第一導電元件；藉由第二黏著層於該封裝膠體之第二表面上接置第二承載板；移除該第一承載板與第一黏著層；於該封裝膠體之第一表面上形成電性連接該作用面與電性連接墊的線路重佈層；以及移除該第二承載板與第二黏著層。 A method of fabricating a semiconductor package, comprising: mounting a wafer having an active surface on a first carrier plate on which a first adhesive layer is formed, and placing the wafer on the first carrier by its active surface Forming an encapsulant covering the wafer on the first adhesive layer, the encapsulant having a first surface bonded to the first adhesive layer and a second surface opposite thereto; forming a plurality of exposed first Forming a colloidal opening of the adhesive layer; forming an electrical connection pad on the first adhesive layer in each of the encapsulation colloids; and attaching the first conductive element to each of the electrical connection pads; Attaching a second carrier to the second surface of the encapsulant; removing the first carrier and the first adhesive layer; forming a circuit electrically connecting the active surface and the electrical connection pad on the first surface of the encapsulant Re-layering; and removing the second carrier and the second adhesive layer. 如申請專利範圍第1項所述之半導體封裝件之製法，於形成該線路重佈層之後，復包括於該線路重佈層上接置複數第二導電元件。 The method for manufacturing a semiconductor package according to claim 1, wherein after forming the circuit redistribution layer, the plurality of second conductive elements are connected to the circuit redistribution layer. 如申請專利範圍第1項所述之半導體封裝件之製法，於移除該第二承載板與第二黏著層之後，復包括於該封裝膠體之第二表面上方接置一電子元件，該電子元件係經由該第一導電元件電 性連接該線路重佈層。 The method of manufacturing the semiconductor package of claim 1, after removing the second carrier and the second adhesive layer, the electronic component is mounted on the second surface of the encapsulant. The component is electrically connected via the first conductive component Sexually connect the line redistribution layer. 如申請專利範圍第3項所述之半導體封裝件之製法，其中，該電子元件復包括用以電性連接該第一導電元件的第三導電元件。 The method of fabricating a semiconductor package according to claim 3, wherein the electronic component further comprises a third conductive component for electrically connecting the first conductive component. 如申請專利範圍第3項所述之半導體封裝件之製法，其中，該電子元件係為半導體晶片或封裝結構。 The method of fabricating a semiconductor package according to claim 3, wherein the electronic component is a semiconductor wafer or a package structure. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，該封裝膠體開孔係藉由雷射來形成。 The method of fabricating a semiconductor package according to claim 1, wherein the encapsulation opening is formed by laser. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，形成該電性連接墊之材料係為銅。 The method of fabricating a semiconductor package according to claim 1, wherein the material forming the electrical connection pad is copper. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，形成該電性連接墊之方式係為濺鍍。 The method of fabricating a semiconductor package according to claim 1, wherein the method of forming the electrical connection pad is sputtering. 一種半導體封裝件，係包括：封裝膠體，係具有相對之第一表面與第二表面及複數貫穿該第一表面與第二表面之封裝膠體開孔；晶片，係嵌埋於該封裝膠體中，且具有外露於該封裝膠體之第一表面的作用面；電性連接墊，係嵌埋於該封裝膠體中，且外露於該封裝膠體之第一表面；線路重佈層，係形成於該封裝膠體之第一表面及該電性連接墊上，且電性連接該電性連接墊；以及第一導電元件，係設於該封裝膠體開孔內且接置於該電性連接墊上。 A semiconductor package comprising: an encapsulant having opposite first and second surfaces and a plurality of encapsulation openings extending through the first surface and the second surface; and a wafer embedded in the encapsulant And having an active surface exposed on the first surface of the encapsulant; the electrical connection pad is embedded in the encapsulant and exposed on the first surface of the encapsulant; the circuit redistribution layer is formed in the package The first surface of the colloid and the electrical connection pad are electrically connected to the electrical connection pad; and the first conductive component is disposed in the opening of the encapsulant and is disposed on the electrical connection pad. 如申請專利範圍第9項所述之半導體封裝件，復包括複數第二導電元件，係接置於該線路重佈層上。 The semiconductor package of claim 9, comprising a plurality of second conductive elements attached to the circuit redistribution layer. 如申請專利範圍第9項所述之半導體封裝件，復包括電子元件，係接置於該封裝膠體之第二表面上方，且經由該第一導電元件電性連接該線路重佈層。 The semiconductor package of claim 9, wherein the electronic component is electrically connected to the second surface of the encapsulant and electrically connected to the circuit redistribution layer via the first conductive component. 如申請專利範圍第11項所述之半導體封裝件，其中，該電子元件復包括用以電性連接該第一導電元件的第三導電元件。 The semiconductor package of claim 11, wherein the electronic component comprises a third conductive component for electrically connecting the first conductive component. 如申請專利範圍第11項所述之半導體封裝件，其中，該電子元件係為半導體晶片或封裝結構。 The semiconductor package of claim 11, wherein the electronic component is a semiconductor wafer or a package structure. 如申請專利範圍第9項所述之半導體封裝件，其中，形成該電性連接墊之材料係銅。 The semiconductor package of claim 9, wherein the material forming the electrical connection pad is copper. 如申請專利範圍第9項所述之半導體封裝件，其中，該封裝膠體開孔係呈該第一表面端窄且第二表面端寬的錐形，且該電性連接墊係填滿該封裝膠體開孔之第一表面端而呈錐形。 The semiconductor package of claim 9, wherein the encapsulation colloid has a tapered shape with the first surface end being narrow and the second surface end being wide, and the electrical connection pad fills the package The first surface end of the colloidal opening is tapered.
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