TWI406375B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

Info

Publication number
TWI406375B
TWI406375B TW099116106A TW99116106A TWI406375B TW I406375 B TWI406375 B TW I406375B TW 099116106 A TW099116106 A TW 099116106A TW 99116106 A TW99116106 A TW 99116106A TW I406375 B TWI406375 B TW I406375B
Authority
TW
Taiwan
Prior art keywords
layer
conductive
pillar
semiconductor device
solder
Prior art date
Application number
TW099116106A
Other languages
English (en)
Other versions
TW201128749A (en
Inventor
Tin Hao Kuo
Chen Shien Chen
Ching Wen Hsiao
Original Assignee
Taiwan Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg filed Critical Taiwan Semiconductor Mfg
Publication of TW201128749A publication Critical patent/TW201128749A/zh
Application granted granted Critical
Publication of TWI406375B publication Critical patent/TWI406375B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/03452—Chemical vapour deposition [CVD], e.g. laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05681—Tantalum [Ta] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/13076—Plural core members being mutually engaged together, e.g. through inserts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13084—Four-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13169—Platinum [Pt] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/165—Material
    • H01L2224/16505—Material outside the bonding interface, e.g. in the bulk of the bump connector
    • H01L2224/16507—Material outside the bonding interface, e.g. in the bulk of the bump connector comprising an intermetallic compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01072—Hafnium [Hf]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

半導體裝置及其製造方法
本發明係有關於半導體裝置，且特別是有關於一種具有非平坦表面之柱體結構(pillar structures)之半導體裝置。
近年來電子裝置及半導體封裝的技術變遷衝擊了整個半導體產業。表面黏著技術(surface mount technology；SMT)及球柵陣列(ball grid array；BGA)封裝技術的導入，成為各種積體電路(IC)裝置高產能組裝的關鍵步驟，並同時縮小了印刷電路板上各接墊間的間距。傳統上，封裝積體電路的結構中係透過位於晶片上金屬接墊與延伸至模製樹脂封裝體外側的電極之間的細金線作為基本的內連接。雙列式封裝(Dual Inline Package；DIP)或四方扁平式封裝(Quad Flat Package)為現今積體電路封裝之基本架構。然而，隨著封裝體周圍引腳總數於設計及排列上的增加，造成引腳導線的間距過短，而限制了封裝晶片的裝配。
晶片級封裝(CSP)及球柵陣列(BGA)封裝為上述問題的解決方案其中之一，其能使電極排列更為緊密而不大幅增加封裝體體積。某些晶片級封裝技術可提供額外的優點，例如使晶圓在晶片級尺寸下作封裝。使用晶片級封裝(CSP)的封裝體尺寸常在晶片尺寸的1.2倍內，其大幅減少了由晶片級封裝(CSP)材料所製程之裝置體積。
某些晶片級封裝(CSP)或球柵陣列(BGA)封裝是以焊料凸塊作為晶片上的接點與基材(例如封裝基板、印刷電路板，其他晶片/晶圓或其類似物)上的接點的電性連接。其他晶片級封裝(CSP)或球柵陣列(BGA)封裝則是將焊球或焊料凸塊置於凸塊電極或柱體(pillar)上，藉由銲點(soldered joint)接合以維持結構完整性。由於組成的內連線的不同膜層通常具有不同的熱膨脹係數。如此，因柱體(post)與凸塊電極間的接點處會產生相對較大的應力，經常會在凸塊電極/柱體與焊球/焊料凸塊之間的接合區域中產生裂縫。
本發明係提供一種半導體裝置，包括：一基材，包含一第一導電層；一柱體，具有一非平坦表面，電性連接至此第一導電層；以及一焊料，位於此柱體上並電性接觸此第一導電層。
本發明亦提供一種半導體裝置之製造方法，包含：提供一基材，其具有一接點；形成一鈍化層於此基材上，且暴露至少一部分的接點；以及形成一導電柱體電性接觸此接點，此導電柱體具有一非平坦上表面。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
本發明接下來將會提供許多不同的實施例以說明本發明中不同的特徵。然而，值得注意的是，各特定實施例中的構成及配置將會在以下作詳細說明以闡述本發明之精神，但這些實施例並非用於限定本發明。
在此所揭示的實施例係關於半導體裝置中導電柱體(conductive pillar)的使用。如以下所述，在此揭示之實施例使用一導電柱體以連結一基材至另一基材，其中各基材可為晶片、晶圓、印刷電路板、封裝基材或其類似物，因而上述連結可為晶片對晶片、晶片對晶圓、晶圓對晶圓、晶片或晶圓對印刷電路板或封裝基板等。雖然這些實施例可使用任何柱體尺寸，然可發現的是，這些實施例特別適用於較小之柱體尺寸，例如小於約80μm。在以下各個圖示及實施例中，相同參考標號表示為類似元件。
第1-7圖顯示為依照本發明一實施例製造具有非平坦柱體之半導體裝置之各種中間階段。首先參見第1圖，其顯示為依照本發明實施例之一部分的基板102，具有電路104形成於其上。基材102可包含，例如摻雜或未摻雜的塊狀矽，或絕緣層上覆半導體(SOI)基材之主動層。通常，絕緣層上覆半導體(SOI)基材包含一半導體材料層(例如矽)形成於絕緣層上，其中絕緣層可包含，例如，深埋氧化層(buried-oxide layer；BOX)或氧化矽層。此絕緣層通常形成在基材上，一般為矽基材或玻璃基材，或也可使用其他基材，例如多層(multi-layered)基材或梯度(gradient)基材。
形成於半導體基材102上的電路104可為適用於特定應用之任何類型的電路。在一實施例中，此電路104包含形成於基材上之電子元件，且此電子元件上覆蓋一或多層介電層。可於介電層之間形成金屬層，藉以傳遞電子元件間的電子訊號。電子元件也可形成在一或多層介電層中。
例如，電路104可包含各種N型金氧半導體(NMOS)及/或P型金氧半導體(PMOS)元件，例如電晶體、電容、電阻、二極體、光電二極體、熔絲及其類似物，上述元件相互連接以進行一或多種功能。此功能可包含記憶體結構、處理器結構(processing structures)、感測器、放大器、配電系統(power distribution)、輸入/輸出電路或其類似物。本發明所屬技術領域中具有通常知識者應可了解，上述實施例僅為進一步解釋所揭露之發明，並非用以限定本發明。也可使用其他合適的電路以作指定的應用。
第1圖也顯示層間介電層(inter-layer dielectric；ILD)108。層間介電層(ILD)108可由低介電常數材料形成，例如磷矽玻璃(phosphosilicate glass；PSG)、硼磷矽玻璃(borophosphosilicate glass；BPSG)、氟矽玻璃(fluorinated silicate glass；FSG)、碳氧化矽(SiOx Cy )、旋塗式玻璃(Spin-On-Glass)、旋塗式高分子(Spin-On-Polymers)、碳化矽材料、前述之化合物、前述之複合材料或前述之組合。此層間介電層108可由此技術領域中任何習知的合適方法形成，例如旋轉塗佈(spinning)、化學氣相沉積(chemical vapor deposition；CVD)及電漿增強型化學氣相沉積(plasma-enhanced CVD；PECVD)。值得注意的是，層間介電層108可包含複數層介電層。
接點(例如接點110)形成於層間介電層108中並貫穿之，以提供電性接觸至電路104。可使用光學微影技術形成接點110，於層間介電層108上沉積光阻材料並將其圖案化，以暴露一部分的層間介電層108成為接點110。可使用蝕刻製程(例如非等向性乾蝕刻製程)在層間介電層108中形成開口。此開口可使用擴散阻障層及/或黏著層(未顯示)作為內襯，並填滿導電材料。在一實施例中，擴散阻障層包含一或多層由氮化鉭、鉭、氮化鈦、鈦、鎢化鈷或其類似物所組成之膜層，且導電材料包含銅、鎢、鋁、銀、前述之組合或其類似物，因而形成如第1圖所示之接點110。
一或多層金屬間介電(inter-metal dielectric；IMD)層112及其相關之金屬化層(未顯示)形成於層間介電層108上。一般而言，係利用此一或多層之金屬間介電層(IMD)112及其相關的金屬層使電路104彼此互相連接，並藉以提供外部電性連接(external electrical connection)。金屬間介電(IMD)層112可由低介電常數材料形成，例如由電漿增強型化學氣相沉積(PECVD)技術或高密度電漿化學氣相沉積(HDPCVD)所形成之氟矽玻璃(FSG)，或其類似物，且此金屬間介電(IMD)層120可包含中間蝕刻停止層(intermediate etch stop layer)。接點114形成於最上層之金屬間介電層中，以提供外部電性連接。
值得注意的是，可設置一或多層蝕刻停止層(未顯示)於相鄰的一或多層介電層之間(例如層間介電層108及金屬間介電層112)。通常，當形成通孔及/或接點時，蝕刻停止層提供停止蝕刻製程的機制。蝕刻停止層可由蝕刻選擇性不同於鄰近膜層(例如下方之半導體基材102、上方之層間介電層108，及上方之金屬間介電層112)之介電材料所組成。在一實施例中，蝕刻停止層可由化學氣相沉積(CVD)或電漿增強型化學氣相沉積(PECVD)技術所形成之氮化矽、氮碳化矽、碳氧化矽、氮化碳、前述之組合、或其類似物所形成。
可於最上層之金屬間介電層112表面上形成保護層116(例如介電材料)並將其圖案化，以形成開口於接墊點114上及保護底下的膜層不受環境污染物污染。隨後，於保護層116上形成導電層118並將其圖案化。導電層118可提供電性連接至形成於導電層118上之接觸凸塊，以作外部連接。導電層118也可扮演重分佈層(redistribution laye；RDL)，以提供所需之引腳或銲球之佈局。導電層118由任何合適導電材料形成，例如銅、鎢、鋁、銀及前述之組合或其類似物。
於如第1圖所示之導電層118上形成鈍化層120(例如介電層)並將其圖案化。鈍化層120可由任何合適方法形成，例如化學氣相沉積、物理氣相沉積或其他類似方法。在一實施例中，鈍化層120之厚度約1.5至1.9μm。
上述結構可使用任何合適的製程來形成，故在此不再贅述。如本技術領域中具有通常知識者所知，上述說明概述了本發明實施例之元件，或也可為其他元件。例如，其他的電路、襯層、阻障層、凸塊底層金屬(under-bump metallization)結構及其類似物。上述說明僅提供用以描述本發明之實施例，但非用以將本發明或申請專利範圍限制於這些特定實施例。
第2圖顯示一阻障層210沉積於鈍化層120之表面上。阻障層210係為由導電材料所組成之一薄層，其可於隨後製程步驟中幫助形成較厚的膜層。在一實施例中，阻障層210可由沉積一或多層薄的導電層形成，例如一或多層由銅、鈦、鉭、氮化鈦、氮化鉭、前述之組合或其類似物組成之薄層，可使用化學氣相沉積或物理氣相沉積技術形成。例如在一實施例中，由進行物理氣相沉積製程沉積一鈦層以形成擴散阻障薄膜，及由物理氣相沉積製程沉積一銅層以形成銅晶種層。值得注意的是，可視需要形成一聚亞醯胺層(polyimide layer)於鈍化層120及阻障層210之間。
隨後如第3圖所示，依照本發明一實施例形成圖案化罩幕310於晶種層210上。圖案化罩幕層310定義(defines)導電柱體之橫向邊界，導電柱體會於隨後會有更詳盡的說明。圖案化罩幕310可為圖案化的光阻罩幕、硬罩幕、前述之組合或其類似物。
第4圖顯示為依照本發明一實施例形成之導電柱體410。導電柱體410可由任何合適導電材料形成，包含由銅、鎳、鉑、鋁、前述之組合或其類似物形成，且可由任何合適技術形成，包含物理氣相沉積、化學氣相沉積、電化學沉積(electrochemical deposition；ECD)、分子束磊晶(molecular beam epitaxy；MBE)、原子層沉積(ALD)、電鍍及其類似方法。在一實施例中，導電柱體410之厚度為約30至60μm。
導電柱體係由可導致非平坦表面之製程形成，例如形成如第4圖所示之凹面。在一實施例中，導電柱體410由電鍍製程形成，其中晶圓為浸沒(submerged or immersed)於電鍍溶液中。晶圓表面電性連接至外部直流電源供應器(external DC power supply)之負極，以使晶圓在電鍍過程中作為陰極。另外浸入固體導電陽極(例如銅)至溶液中，並連接至電源供應器之正極。陽極解離之原子溶解至溶液中，陰極(例如晶圓)自溶液中獲得原子，因此電鍍在晶圓的導電區域，例如在圖案化罩幕310中開口中之晶種層210的暴露部分。在電鍍製程中，可調整電鍍溶液中的添加物以形成非平坦表面。例如，為了形成如第4圖所示之凹面，可減少平整劑(leveler)之濃度，此平整劑為添加劑中之其中一種。添加劑之配方可隨著不同的溶劑供應商而有所變化。然而，也可使用其他製程。
第5圖顯示為視需要形成一導電蓋層510於導電柱體410上。如以下更詳細的描述，銲料將形成在導電柱體410上。在銲合製程(soldering process)中，金屬間化合物(inter-metallic compound；IMC)層自然形成在銲料與及其底下膜層表面之間的接點處。可發現的是，某些材料可創造出較強及較耐久的金屬間化合物層。因此，較佳形成蓋層(例如導電蓋層510)，以提供具有所需性質之金屬間化合物(IMC)層。例如，在一實施例中，導電柱體410係由銅形成，則導電蓋層510較佳可由鎳形成，或者也可使用其他材料，例如鉑、金、銀、前述之組合或其類似物。導電蓋層510可由任何合適技術形成，包含物理氣相沉積、化學氣相沉積、電化學沉積、分子束磊晶、原子層沉積、電鍍及其類似方法。
第6圖顯示為形成銲料610及金屬間化合物(IMC)層612。在一實施例中，焊料610包含錫鉛合金(SnPb)、高含鉛材料、錫基焊料(Sn-based solder)、無鉛焊料(lead-free solder)或其他合適導電材料。
本技術領域中具有通常知識者可瞭解的是，導電柱體410具有粗糙、非平坦之表面。例如，如第4圖所示，導電柱體410是以使其具有凹面之方式形成。在一實施例中，導電柱體之表面粗糙程度大於金屬間化合物(IMC)層612之厚度。上述的結構經發現可減少裂縫產生及/或減少裂縫沿著金屬間化合物層612擴展。裂縫擴展的減少相信是由於底下的導電柱體410的非平坦表面。金屬間化合物層612本身為非平坦的，且厚度小於柱體之粗糙程度，相信更阻礙了破裂的擴展。例如，可觀察到在某些實施例中，金屬間化合物層612之厚度小於6μm，因此在第6圖中，高度Hd 大於6μm。如此的粗糙程度可減少裂縫以線性或近線性擴展的機會。在另一實施例中，高度Hd 除以寬度D大於約6%。
此外，在某些實施例中，如第4-6圖所示之凹面導電柱體，可使導電凸塊更佳的固定或限制銲料於導電柱體之末端，以減少焊料沿著導電柱體410側壁潤濕的量，以避免導致較弱的金屬間化合物(IMC)界面。
隨後，如第7圖所示，可移除圖案化罩幕310。在某些實施例中，圖案化罩幕310係由光阻材料形成，此光阻可由含有下列混合液之化學溶液剝除，例如乳酸乙酯(ethyl lactate)、苯甲醚(anisole)、乙酸異戊酯(methyl butyl acetate)、乙酸戊酯(amyl acetate)、甲酚樹脂(cresol novolak resin)及疊氮光敏化合物(diazo photoactive compound)(亦稱SPR9)剝除，或由其他剝除製程剝除。可使用清潔製程移除晶種層210之暴露部分及任何在鈍化層210表面的污染物，例如濕式浸泡在磷酸及過氧化氫所組成之化學溶液(亦稱為DPP)及1%氫氟酸(HF)進行濕式浸泡，或其他清潔製程。
隨後，進行焊料迴流製程及可進行適合於特定應用的其他後段(BEOL)製程技術。例如，可形成封膠、進行切割製程以分開個別的晶片、進行晶圓級或晶片級堆疊製程等。值得注意的是，上述實施例可使用於不同的型態。例如，上述實施例可使用於晶片對晶片接合、晶片對晶圓接合、晶圓對晶圓接合、晶片級封裝、晶圓級封裝等。
值得注意的是，在其他實施例中，在基板102連結至另一基板(未顯示)之前，不會將焊料置於導電柱體410上。在上述實施例中，焊料係置於另一基板上，然後以基板102上之導電柱體410直接碰觸另一基板上之焊料，並進行焊料迴流製程，以將兩基板銲合在一起。
第8a及8b圖顯示為導電柱體其他種類的表面。首先參見第8a圖，此表面乃是一凸面，而非如第4-7圖所示之凹面。在此實施例中，此導電柱體可由增加平整劑(leveler)的濃度來形成，其中平整劑係為電鍍溶液添加劑之其中一種。添加劑之配方可隨溶劑供應商不同而有所變化。然而，也可使用其他製程。
第8b圖顯示為形成具有波浪狀表面之導電柱體410之。在此實施例中，可在電鍍時增加電流密度以形成此導電柱體。然而，也可使用其他製程。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。再者，本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此，本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。另外，每一申請專利範圍構成個別的實施例，且本發明之保護範圍也包括各個申請專利範圍及實施例的組合。
102．．．基材
104．．．電路
108．．．層間介電層
110．．．接點
112．．．金屬間介電層
114．．．接墊點
116．．．保護層
118．．．導電層
120．．．鈍化層
210．．．阻障層
310．．．圖案化罩幕層
410．．．導電柱體
510．．．導電蓋層
610．．．焊料
612．．．金屬間化合物層
第1~7圖顯示為依照本發明一實施例製造具有非平坦柱體之半導體裝置之各種中間階段。
第8a及8b圖顯示依照本發明其他實施例之具有其他形狀之柱體。
102．．．基材
104．．．電路
108．．．層間介電層
110．．．接點
112．．．金屬間介電層
114．．．接墊點
116．．．保護層
118．．．導電層
120．．．鈍化層
210．．．阻障層
410．．．導電柱體
510．．．導電蓋層
610．．．焊料
612．．．金屬間化合物層

Claims (8)

  1. 一種半導體裝置，包括：一基材，包含一第一導電層；一柱體電性連接至該第一導電層，且該柱體具有一非平坦表面；一焊料，位於該柱體上並電性接觸該第一導電層；以及一金屬間化合物層介於該柱體及該焊料之間，其中該金屬間化合物層之厚度小於該非平坦表面之最高點至最低點之距離。
  2. 如申請專利範圍第1項所述之半導體裝置，其中該非平坦表面至少包含有一凸面、一凹面或一波浪狀。
  3. 如申請專利範圍第1項所述之半導體裝置，更包含一蓋層介於該柱體及該焊料之間，其中該蓋層係由鎳、鉑、金或銀所組成。
  4. 如申請專利範圍第1項所述之半導體裝置，其中該非平坦表面最高點至最低點之距離為該柱體寬度的約6%。
  5. 一種半導體裝置之製造方法，包含：提供一基材，其具有一接點；形成一鈍化層於該基材上，且暴露至少一部分的接點；形成一導電柱體與該接點電性接觸，該導電柱體具有一非平坦上表面；以及形成一金屬間化合物層位於該導電柱體上，其中該金屬間化合物層之厚度小於該非平坦上表面之最高點至 最低點之距離。
  6. 如申請專利範圍第5項所述之半導體裝置之製造方法，其中該非平坦上表面之最高點至最低點之距離為該導電柱體寬度的約6%。
  7. 如申請專利範圍第5項所述之半導體裝置之製造方法，更包含形成一蓋層於該導電柱體上，其中該蓋層係由鎳、鉑、金或銀所組成。
  8. 如申請專利範圍第7項所述之半導體裝置之製造方法，更包含形成一焊料於該蓋層上。
TW099116106A 2010-02-11 2010-05-20 半導體裝置及其製造方法 TWI406375B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/704,183 US8318596B2 (en) 2010-02-11 2010-02-11 Pillar structure having a non-planar surface for semiconductor devices

Publications (2)

Publication Number Publication Date
TW201128749A TW201128749A (en) 2011-08-16
TWI406375B true TWI406375B (zh) 2013-08-21

Family

ID=44353046

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099116106A TWI406375B (zh) 2010-02-11 2010-05-20 半導體裝置及其製造方法

Country Status (3)

Country Link
US (2) US8318596B2 (zh)
CN (1) CN102157473B (zh)
TW (1) TWI406375B (zh)

Families Citing this family (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8492263B2 (en) * 2007-11-16 2013-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Protected solder ball joints in wafer level chip-scale packaging
US8299616B2 (en) * 2010-01-29 2012-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. T-shaped post for semiconductor devices
US8803319B2 (en) 2010-02-11 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar structure having a non-planar surface for semiconductor devices
US8318596B2 (en) 2010-02-11 2012-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar structure having a non-planar surface for semiconductor devices
US9142533B2 (en) 2010-05-20 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate interconnections having different sizes
US8241963B2 (en) 2010-07-13 2012-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Recessed pillar structure
KR101695353B1 (ko) * 2010-10-06 2017-01-11 삼성전자 주식회사 반도체 패키지 및 반도체 패키지 모듈
JP2012129369A (ja) * 2010-12-15 2012-07-05 Ngk Spark Plug Co Ltd 配線基板
JP5559023B2 (ja) * 2010-12-15 2014-07-23 日本特殊陶業株式会社 配線基板及びその製造方法
CN102693962A (zh) * 2011-03-22 2012-09-26 精材科技股份有限公司 具有电磁屏蔽作用的集成电路晶圆及其制造方法
TW201250959A (en) * 2011-05-05 2012-12-16 Siliconware Precision Industries Co Ltd Semiconductor structure and fabrication method thereof
KR101782503B1 (ko) * 2011-05-18 2017-09-28 삼성전자 주식회사 솔더 범프 붕괴를 억제하는 반도체 소자의 범프 형성방법
US8431478B2 (en) * 2011-09-16 2013-04-30 Chipmos Technologies, Inc. Solder cap bump in semiconductor package and method of manufacturing the same
US9230932B2 (en) 2012-02-09 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect crack arrestor structure and methods
US9263412B2 (en) 2012-03-09 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and packaged semiconductor devices
US20130234317A1 (en) * 2012-03-09 2013-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging Methods and Packaged Semiconductor Devices
WO2013136896A1 (ja) * 2012-03-15 2013-09-19 富士電機株式会社 半導体装置およびその製造方法
JP2013214557A (ja) * 2012-03-30 2013-10-17 Olympus Corp 電極形成体、配線基板、および半導体装置
KR20130110959A (ko) * 2012-03-30 2013-10-10 삼성전자주식회사 반도체 패키지
US9425136B2 (en) 2012-04-17 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Conical-shaped or tier-shaped pillar connections
US9646923B2 (en) 2012-04-17 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices
US9299674B2 (en) 2012-04-18 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Bump-on-trace interconnect
US9515036B2 (en) 2012-04-20 2016-12-06 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for solder connections
US9230896B2 (en) 2012-06-05 2016-01-05 Stats Chippac, Ltd. Semiconductor device and method of reflow soldering for conductive column structure in flip chip package
CN103515341B (zh) * 2012-06-20 2016-12-21 讯忆科技股份有限公司 晶圆焊垫的化镀镍凸块结构及其制造方法
CN103531571B (zh) * 2012-07-05 2016-09-28 讯忆科技股份有限公司 晶圆焊垫的化镀镍凸块结构及其制造方法
US9548283B2 (en) * 2012-07-05 2017-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package redistribution layer structure and method of forming same
TW201409636A (zh) * 2012-08-31 2014-03-01 Chipmos Technologies Inc 半導體結構
US9111817B2 (en) 2012-09-18 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure and method of forming same
US9230852B2 (en) * 2013-02-25 2016-01-05 Texas Instruments Incorporated Integrated circuit (IC) having electrically conductive corrosion protecting cap over bond pads
US9673131B2 (en) * 2013-04-09 2017-06-06 Intel Corporation Integrated circuit package assemblies including a glass solder mask layer
US9355980B2 (en) 2013-09-03 2016-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional chip stack and method of forming the same
US8877630B1 (en) * 2013-11-12 2014-11-04 Chipmos Technologies Inc. Semiconductor structure having a silver alloy bump body and manufacturing method thereof
US10163828B2 (en) * 2013-11-18 2018-12-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and fabricating method thereof
US9837368B2 (en) * 2014-03-04 2017-12-05 Maxim Integrated Products, Inc. Enhanced board level reliability for wafer level packages
JP2015170725A (ja) * 2014-03-07 2015-09-28 イビデン株式会社 複合基板
KR102212559B1 (ko) 2014-08-20 2021-02-08 삼성전자주식회사 반도체 발광소자 및 이를 이용한 반도체 발광소자 패키지
CN105374775B (zh) * 2014-09-02 2018-05-04 中芯国际集成电路制造(上海)有限公司 焊盘、半导体器件和半导体器件的制造工艺
US9583451B2 (en) 2015-06-19 2017-02-28 International Business Machines Corporation Conductive pillar shaped for solder confinement
US9754906B2 (en) * 2015-06-25 2017-09-05 Advanced Semiconductor Engineering, Inc. Double plated conductive pillar package substrate
CN106486444B (zh) * 2015-08-31 2019-10-01 中芯长电半导体（江阴）有限公司 凸块结构、封装组件及其形成方法
DE102016103585B4 (de) 2016-02-29 2022-01-13 Infineon Technologies Ag Verfahren zum Herstellen eines Package mit lötbarem elektrischen Kontakt
CN105762133B (zh) * 2016-03-30 2018-11-09 江苏长电科技股份有限公司 一种堆叠式封装结构及其工艺方法
US9935024B2 (en) * 2016-04-28 2018-04-03 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming semiconductor structure
US9871009B2 (en) * 2016-06-15 2018-01-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10115692B2 (en) 2016-09-14 2018-10-30 International Business Machines Corporation Method of forming solder bumps
KR102534735B1 (ko) * 2016-09-29 2023-05-19 삼성전자 주식회사 필름형 반도체 패키지 및 그 제조 방법
CN107968092B (zh) * 2017-11-16 2018-12-14 长江存储科技有限责任公司 3d nand中的金属间化合物保护层及其形成方法
US10811377B2 (en) 2017-12-14 2020-10-20 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with a barrier layer and method for forming the same
TWI709212B (zh) * 2019-03-05 2020-11-01 台灣積體電路製造股份有限公司 晶圓接合結構及其形成方法
US11581276B2 (en) 2019-09-28 2023-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Redistribution layers and methods of fabricating the same in semiconductor devices
CN112582276A (zh) 2019-09-28 2021-03-30 台湾积体电路制造股份有限公司 半导体结构及其制造方法
US11121088B2 (en) * 2019-10-16 2021-09-14 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method of manufacturing the same
US11183474B2 (en) 2019-11-04 2021-11-23 Advanced Semiconductor Engineering, Inc. Electronic device package and method for manufacturing the same
KR20210126188A (ko) * 2020-04-09 2021-10-20 삼성전자주식회사 반도체 소자
US20230063251A1 (en) * 2021-08-30 2023-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of forming the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200524025A (en) * 2003-11-25 2005-07-16 Shinko Electric Ind Co Semiconductor device and method of fabricating the same
TW200820406A (en) * 2006-10-19 2008-05-01 Novatek Microelectronics Corp Chip structure and wafer structure
TW200832641A (en) * 2006-11-08 2008-08-01 Casio Computer Co Ltd Semiconductor device having projecting electrode formed by electrolytic plating, and manufacturing method thereof

Family Cites Families (85)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4811082A (en) 1986-11-12 1989-03-07 International Business Machines Corporation High performance integrated circuit packaging structure
US4990462A (en) 1989-04-12 1991-02-05 Advanced Micro Devices, Inc. Method for coplanar integration of semiconductor ic devices
US5075253A (en) 1989-04-12 1991-12-24 Advanced Micro Devices, Inc. Method of coplanar integration of semiconductor IC devices
US5380681A (en) 1994-03-21 1995-01-10 United Microelectronics Corporation Three-dimensional multichip package and methods of fabricating
US5466635A (en) 1994-06-02 1995-11-14 Lsi Logic Corporation Process for making an interconnect bump for flip-chip integrated circuit including integral standoff and hourglass shaped solder coating
JPH0997791A (ja) 1995-09-27 1997-04-08 Internatl Business Mach Corp <Ibm> バンプ構造、バンプの形成方法、実装接続体
US6002177A (en) 1995-12-27 1999-12-14 International Business Machines Corporation High density integrated circuit packaging with chip stacking and via interconnections
US5736456A (en) 1996-03-07 1998-04-07 Micron Technology, Inc. Method of forming conductive bumps on die for flip chip applications
US5759910A (en) 1996-12-23 1998-06-02 Motorola, Inc. Process for fabricating a solder bump for a flip chip integrated circuit
US5962921A (en) 1997-03-31 1999-10-05 Micron Technology, Inc. Interconnect having recessed contact members with penetrating blades for testing semiconductor dice and packages with contact bumps
US6175161B1 (en) * 1998-05-22 2001-01-16 Alpine Microsystems, Inc. System and method for packaging integrated circuits
US6107180A (en) 1998-01-30 2000-08-22 Motorola, Inc. Method for forming interconnect bumps on a semiconductor die
US6213376B1 (en) 1998-06-17 2001-04-10 International Business Machines Corp. Stacked chip process carrier
JP3516592B2 (ja) 1998-08-18 2004-04-05 沖電気工業株式会社 半導体装置およびその製造方法
US6281042B1 (en) 1998-08-31 2001-08-28 Micron Technology, Inc. Structure and method for a high performance electronic packaging assembly
US6271059B1 (en) 1999-01-04 2001-08-07 International Business Machines Corporation Chip interconnection structure using stub terminals
US6461895B1 (en) 1999-01-05 2002-10-08 Intel Corporation Process for making active interposer for high performance packaging applications
US6229216B1 (en) 1999-01-11 2001-05-08 Intel Corporation Silicon interposer and multi-chip-module (MCM) with through substrate vias
TW442873B (en) 1999-01-14 2001-06-23 United Microelectronics Corp Three-dimension stack-type chip structure and its manufacturing method
JP3346320B2 (ja) 1999-02-03 2002-11-18 カシオ計算機株式会社 半導体装置及びその製造方法
US6243272B1 (en) 1999-06-18 2001-06-05 Intel Corporation Method and apparatus for interconnecting multiple devices on a circuit board
JP3239335B2 (ja) 1999-08-18 2001-12-17 インターナショナル・ビジネス・マシーンズ・コーポレーション 電気的接続用構造体の形成方法およびはんだ転写用基板
US6717245B1 (en) 2000-06-02 2004-04-06 Micron Technology, Inc. Chip scale packages performed by wafer level processing
US6355501B1 (en) 2000-09-21 2002-03-12 International Business Machines Corporation Three-dimensional chip stacking assembly
US7129575B1 (en) * 2000-10-13 2006-10-31 Bridge Semiconductor Corporation Semiconductor chip assembly with bumped metal pillar
US6562665B1 (en) 2000-10-16 2003-05-13 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology
KR100364635B1 (ko) 2001-02-09 2002-12-16 삼성전자 주식회사 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법
JP3767398B2 (ja) 2001-03-19 2006-04-19 カシオ計算機株式会社 半導体装置およびその製造方法
KR100394808B1 (ko) 2001-07-19 2003-08-14 삼성전자주식회사 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법
US20030107137A1 (en) 2001-09-24 2003-06-12 Stierman Roger J. Micromechanical device contact terminals free of particle generation
KR100435813B1 (ko) 2001-12-06 2004-06-12 삼성전자주식회사 금속 바를 이용하는 멀티 칩 패키지와 그 제조 방법
DE10200399B4 (de) 2002-01-08 2008-03-27 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Erzeugung einer dreidimensional integrierten Halbleitervorrichtung und dreidimensional integrierte Halbleitervorrichtung
US6756294B1 (en) 2002-01-30 2004-06-29 Taiwan Semiconductor Manufacturing Company Method for improving bump reliability for flip chip devices
US6887769B2 (en) 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
US6661085B2 (en) 2002-02-06 2003-12-09 Intel Corporation Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack
US6975016B2 (en) 2002-02-06 2005-12-13 Intel Corporation Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
DE50308874D1 (de) 2002-03-28 2008-02-07 Infineon Technologies Ag Method for producing a semiconductor wafer
US6803303B1 (en) 2002-07-11 2004-10-12 Micron Technology, Inc. Method of fabricating semiconductor component having encapsulated, bonded, interconnect contacts
US6600222B1 (en) 2002-07-17 2003-07-29 Intel Corporation Stacked microelectronic packages
US7285867B2 (en) 2002-11-08 2007-10-23 Casio Computer Co., Ltd. Wiring structure on semiconductor substrate and method of fabricating the same
US6790748B2 (en) 2002-12-19 2004-09-14 Intel Corporation Thinning techniques for wafer-to-wafer vertical stacks
US6908565B2 (en) 2002-12-24 2005-06-21 Intel Corporation Etch thinning techniques for wafer-to-wafer vertical stacks
US7015590B2 (en) 2003-01-10 2006-03-21 Samsung Electronics Co., Ltd. Reinforced solder bump structure and method for forming a reinforced solder bump
US6924551B2 (en) 2003-05-28 2005-08-02 Intel Corporation Through silicon via, folded flex microelectronic package
US6946384B2 (en) 2003-06-06 2005-09-20 Intel Corporation Stacked device underfill and a method of fabrication
US7320928B2 (en) 2003-06-20 2008-01-22 Intel Corporation Method of forming a stacked device filler
US20050026416A1 (en) 2003-07-31 2005-02-03 International Business Machines Corporation Encapsulated pin structure for improved reliability of wafer
KR100537892B1 (ko) 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
US7345350B2 (en) 2003-09-23 2008-03-18 Micron Technology, Inc. Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias
JP3757971B2 (ja) 2003-10-15 2006-03-22 カシオ計算機株式会社 半導体装置の製造方法
KR100621992B1 (ko) 2003-11-19 2006-09-13 삼성전자주식회사 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지
KR100570514B1 (ko) 2004-06-18 2006-04-13 삼성전자주식회사 웨이퍼 레벨 칩 스택 패키지 제조 방법
KR100618837B1 (ko) 2004-06-22 2006-09-01 삼성전자주식회사 웨이퍼 레벨 패키지를 위한 얇은 웨이퍼들의 스택을형성하는 방법
US7307005B2 (en) 2004-06-30 2007-12-11 Intel Corporation Wafer bonding with highly compliant plate having filler material enclosed hollow core
US7452803B2 (en) 2004-08-12 2008-11-18 Megica Corporation Method for fabricating chip structure
US7087538B2 (en) 2004-08-16 2006-08-08 Intel Corporation Method to fill the gap between coupled wafers
US20060055032A1 (en) 2004-09-14 2006-03-16 Kuo-Chin Chang Packaging with metal studs formed on solder pads
JP4843214B2 (ja) 2004-11-16 2011-12-21 株式会社東芝 モジュール基板およびディスク装置
TWI263856B (en) 2004-11-22 2006-10-11 Au Optronics Corp IC chip, IC assembly and flat display
JP2006228837A (ja) 2005-02-15 2006-08-31 Sharp Corp 半導体装置及びその製造方法
JP4526983B2 (ja) 2005-03-15 2010-08-18 新光電気工業株式会社 配線基板の製造方法
US20060211233A1 (en) 2005-03-21 2006-09-21 Skyworks Solutions, Inc. Method for fabricating a wafer level package having through wafer vias for external package connectivity and related structure
JP2006287048A (ja) 2005-04-01 2006-10-19 Rohm Co Ltd 半導体装置
US7317256B2 (en) 2005-06-01 2008-01-08 Intel Corporation Electronic packaging including die with through silicon via
US7557597B2 (en) 2005-06-03 2009-07-07 International Business Machines Corporation Stacked chip security
US7402515B2 (en) 2005-06-28 2008-07-22 Intel Corporation Method of forming through-silicon vias with stress buffer collars and resulting devices
JP4889974B2 (ja) 2005-08-01 2012-03-07 新光電気工業株式会社 電子部品実装構造体及びその製造方法
TWI273667B (en) 2005-08-30 2007-02-11 Via Tech Inc Chip package and bump connecting structure thereof
US7432592B2 (en) 2005-10-13 2008-10-07 Intel Corporation Integrated micro-channels for 3D through silicon architectures
US7528494B2 (en) 2005-11-03 2009-05-05 International Business Machines Corporation Accessible chip stack and process of manufacturing thereof
US7410884B2 (en) 2005-11-21 2008-08-12 Intel Corporation 3D integrated circuits using thick metal for backside connections and offset bumps
KR100660893B1 (ko) 2005-11-22 2006-12-26 삼성전자주식회사 정렬 마크막을 구비하는 반도체 소자 및 그 제조 방법
JP4251458B2 (ja) 2005-12-21 2009-04-08 Ｔｄｋ株式会社 チップ部品の実装方法及び回路基板
US7402442B2 (en) 2005-12-21 2008-07-22 International Business Machines Corporation Physically highly secure multi-chip assembly
US7279795B2 (en) 2005-12-29 2007-10-09 Intel Corporation Stacked die semiconductor package
US7576435B2 (en) 2007-04-27 2009-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Low-cost and ultra-fine integrated circuit packaging technique
US7820543B2 (en) 2007-05-29 2010-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Enhanced copper posts for wafer level chip scale packaging
US20090020869A1 (en) 2007-07-17 2009-01-22 Qing Xue Interconnect joint
KR101213175B1 (ko) 2007-08-20 2012-12-18 삼성전자주식회사 로직 칩에 층층이 쌓인 메모리장치들을 구비하는반도체패키지
US8269345B2 (en) * 2007-10-11 2012-09-18 Maxim Integrated Products, Inc. Bump I/O contact for semiconductor device
US8492263B2 (en) 2007-11-16 2013-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Protected solder ball joints in wafer level chip-scale packaging
US8299616B2 (en) 2010-01-29 2012-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. T-shaped post for semiconductor devices
US8318596B2 (en) 2010-02-11 2012-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar structure having a non-planar surface for semiconductor devices
US8241963B2 (en) 2010-07-13 2012-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Recessed pillar structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200524025A (en) * 2003-11-25 2005-07-16 Shinko Electric Ind Co Semiconductor device and method of fabricating the same
TW200820406A (en) * 2006-10-19 2008-05-01 Novatek Microelectronics Corp Chip structure and wafer structure
TW200832641A (en) * 2006-11-08 2008-08-01 Casio Computer Co Ltd Semiconductor device having projecting electrode formed by electrolytic plating, and manufacturing method thereof

Also Published As

Publication number Publication date
US8318596B2 (en) 2012-11-27
US20130056869A1 (en) 2013-03-07
US8546945B2 (en) 2013-10-01
CN102157473A (zh) 2011-08-17
CN102157473B (zh) 2013-11-06
US20110193220A1 (en) 2011-08-11
TW201128749A (en) 2011-08-16

Similar Documents

Publication Publication Date Title
TWI406375B (zh) 半導體裝置及其製造方法
US8921222B2 (en) Pillar structure having a non-planar surface for semiconductor devices
TWI429040B (zh) 半導體結構及半導體裝置的製造方法
TWI424543B (zh) 電子元件及其製作方法
US8227924B2 (en) Substrate stand-offs for semiconductor devices
TWI437679B (zh) 半導體裝置及其製造方法
CN102290379B (zh) 半导体结构及半导体装置的制造方法
US20110227216A1 (en) Under-Bump Metallization Structure for Semiconductor Devices
KR101224728B1 (ko) 기판 콘택트 개구
KR101570272B1 (ko) 상호접속 구조물 및 이의 제조 방법
US8405199B2 (en) Conductive pillar for semiconductor substrate and method of manufacture
TWI502667B (zh) 半導體元件的接合結構及半導體元件的製造方法
US9196529B2 (en) Contact pad for semiconductor devices
US20150255435A1 (en) Single Mask Package Apparatus
CN114388376A (zh) 半导体衬底