TWI399795B - 減少半導體磊晶中記憶體效應之方法 - Google Patents

減少半導體磊晶中記憶體效應之方法 Download PDF

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TWI399795B
TWI399795B TW098118587A TW98118587A TWI399795B TW I399795 B TWI399795 B TW I399795B TW 098118587 A TW098118587 A TW 098118587A TW 98118587 A TW98118587 A TW 98118587A TW I399795 B TWI399795 B TW I399795B
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Description

減少半導體磊晶中記憶體效應之方法
本發明係關於一種在半導體材料的磊晶生長期間，減少記憶體效應之方法，及更特定言之，係關於一種化學氣相沈積方法，該方法利用一氣體混合物以淨化在磊晶生長反應之間的反應室並提供該半導體的電性質之改良的再現性。
磊晶一般用於半導體工業中，及特定言之用於矽基半導體材料的製造中。在CVD磊晶中，通常使用一化學氣相沈積(CVD)程序，其包含傳送前驅體氣體至包含一基板(該基板已被選擇以界定所得CVD薄膜的晶體結構)的一生長或反應室，沈積/吸附基板表面上的反應物及解吸附被傳送至一排放口的副產品。另外，該磊晶層可在該生長過程期間被摻雜雜質，以便控制該層的電性質。碳化矽(SiC)半導體裝置可自磊晶生長於一SiC基板上的n及p摻雜SiC之連續層組態。摻雜物類型及濃度經常由字母「n」或「p」表示，其分別係指產生電子或電洞的雜質，且經常跟隨一「+」或一「-」，其分別係指高及低摻雜物濃度。高濃度通常在5×1017 cm-3 至1×1020 cm-3 範圍內，而低濃度在5×1013 cm-3 至5×1017 cm-3 範圍內。用於SiC、Si或SiGe CVD程序的典型摻雜物包含硼(前驅體氣體B2 H6 或BCl3 )、磷(前驅體氣體PH3 或(CH3 )3 P)及鋁(前驅體氣體(CH33 )3 Al及砷(AsH3 ))。
用於SiC CVD程序的典型氣體前驅體包含矽烷(Rx SiH(4-x) 或Rx SiCl(4-x) ，其中R可為H或烴基)及烴(CH4 、C3 H8 )。用於矽CVD程序的典型氣體前驅體為矽烷(Hx SiH(4-x) 或Hx SiCl(4-x) )。
用於GaAs CVD程序的典型摻雜物氣體為矽烷(Hx SiH(4-x) 或Hx SiCl(4-x) )、有機鋅化合物或含碳氣體(CH4 、CCl4 )及典型氣體前驅體為三甲基鎵及三甲基砷。
用於GaN CVD程序的典型摻雜物氣體為矽烷(Hx SiH(4-x) 或Hx SiCl(4-x) )、有機鎂化合物或含碳氣體(CH4 、CCl4 )及典型氣體前驅體為三甲基鎵、三甲基氮及/或三甲基氨。
然而，在該生長反應期間，部分反應的前驅體及/或摻雜物氣體可變得暫時在該反應室中低流動性區域內或多孔材料中被捕獲。另外，副沈積可形成在包含該摻雜物的反應單元壁上。該部分反應的前驅體及副沈積的潛在釋放及/或蒸發可導致該磊晶層的該等電性質的不可再現性。此現象通常稱為「記憶體效應」。舉例言之，當三甲基鋁(TMAl)摻雜物用於生長p型碳化矽時，該三甲基鋁可擴散入包括該CVD真空室的反應區域的石墨材料中。含鋁的SiC亦被形成於該反應單元壁上。在該反應室中該過程隨著時間之循環蒸發該等沈積物且將該「捕獲的」鋁摻雜物引回至該反應區域中，接著該摻雜物於此處被併入最新形成的磊晶層中。不希望該最新摻雜薄膜為一n型薄膜，因為自該副SiC沈積物之殘留的p型雜質亦將摻雜該SiC，有效消除該n型摻雜物的電效應，亦即該室已「記憶」該先前p型生長過程。
由於難以預知該記憶體效應現象及回至該過程中的TMAl摻雜物的量，該效應導致該磊晶層中該摻雜濃度的不可再現性。
雖然機械清潔或替換污染的CVD承座部分是一可能的解決方案，但是其對於一連續多層生長諸如一p+/p-結構為昂貴且不實際。
已做出其他嘗試以最小化SiC磊晶中的記憶體效應。舉例言之，在一p型SiC磊晶生長步驟之後，該室可以低濃度n型SiC塗佈。參看Bernd Thomas等人之「用於電力裝置的生產與發展的4H-SiC同質磊晶之進展(Advances in 4H-SiC Homoepitaxy for Production and Development of Power Devices)」Mater. Res. Soc. Symp. Proc. 2006年第911卷。此過程形成一塗佈在以副p型SiC覆蓋/滲入之該反應區域的面積上之薄膜，並阻止在一隨後磊晶過程中傳送該等p型雜質。然而，雖然此方法減少記憶體效應，但是其是效率低且昂貴，因為其可導致該反應區域組件的太早降級及過多微粒污染的早期形成。
因此，本技術中存在對一種用於減少在半導體材料的磊晶生長期間發生的該記憶體效應之方法的一需要，其容許半導體裝置結構的成功磊晶CVD生長，該生長具有電屬性的良好再現性。
本發明的實施例藉由提供一種藉由使用包括氫氣及一含鹵素之氣體的一氣體混合物在磊晶生長反應之間沖洗該CVD反應室而減少或消除可發生在磊晶生長期間的該記憶體效應之方法來滿足該需要。此方法有效地自該反應室消除殘留的摻雜物源。該方法已成功地被用於生長矽基結構，諸如具有良好再現性的n+SiC/n-SiC/p+SiC磊晶結構。該方法亦可用於改良包含SiC、GaN、GaAs及SiGe的半導體材料的磊晶生長再現性。
根據本發明的一態樣，提供一種在半導體材料的磊晶生長期間減少記憶體效應之方法，該方法包含提供一反應室；提供一半導體基板；提供一或多個前驅體氣體；在該反應室中執行一摻雜半導體材料的一磊晶CVD生長以形成一第一層；以包括氫氣及一含鹵素之氣體的一氣體混合物沖洗該反應室；及在該反應室中執行一第二摻雜半導體材料的一磊晶CVD生長以形成一第二層。
在該沖洗過程期間，該半導體基板可保留在該室中或可先於該沖洗過程被移除。或者，該半導體基板(於其上具有該第一層)可先於該沖洗過程被移除，且在沖洗過程之後可提供一新半導體基板用於該第二層的磊晶生長。
該反應室係在約450℃至1800℃之間之一溫度下被沖洗，更佳地，在約1000℃至1600℃之間或更高溫度下被沖洗，及最佳在約1300℃至1600℃之間之一溫度下被沖洗。該含鹵素之氣體可選自HCl、Cl2 、F2 、CF4 、ClF3 及HBr。
在本發明的另一實施例中，該方法包括：提供一反應室；提供一半導體基板；提供一或多個前驅體氣體；執行一n摻雜SiC層的一磊晶CVD生長；執行一p摻雜SiC層的一磊晶CVD生長；移除於其上具有該等層的該基板；以包括氫氣及一含鹵素之氣體的一氣體混合物沖洗該室；將於其上具有該等層的基板放回該室內；提供一或多個前驅體氣體；在該反應室中執行一n摻雜SiC層摻雜的半導體材料的一磊晶CVD生長；及在該反應室內執行一p摻雜SiC層摻雜的半導體材料的一磊晶CVD生長。
在本發明的另一實施例中，該方法包括：提供一反應室；提供一半導體基板；提供一或多個前驅體氣體；執行在該反應室中一第一p摻雜SiC層的一磊晶CVD生長；以包括氫氣及一含鹵素之氣體的一氣體混合物沖洗該反應室；及執行一第二p摻雜SiC層的磊晶CVD生長，該第二p摻雜SiC層具有比該第一p摻雜SiC層低之摻雜物濃度。
上面描述的該等方法可被應用於包括兩個或更多個磊晶層的SiC、GaAs、GaN或SiGe的結構。該方法亦可被應用於該基板及該等磊晶層包括基本上相同材料(同質磊晶)或不同材料(異質磊晶)之結構。
在一SiC基板結構是藉由該方法形成的實施例中，一SiC半導體裝置可形成於包含該等CVD生長磊晶層的該基板上。
因此，本發明的一特徵是提供一種在半導體材料的磊晶生長期間減少記憶體效應之方法。本發明的此等及其他特徵及優點將自下列詳細描述、附圖及附加請求項變得顯而易見。
本發明方法的實施例提供優於磊晶生長的先前方法的數個優點。我們已意外發現自SiC中殘留的p型雜質之不需要的摻雜可藉由併入磊晶生長過程之間之一高溫氣體沖洗而予以抑制以容許p-n結構的可重複連續生長。亦意外發現該記憶體效應被消除，而不明顯移除自該反應區域的副沈積物。
在用於CVD SiC磊晶之本發明的一較佳實施例中，在該化學氣相沈積反應室中之該溫度維持在約1550至1650℃之間之一溫度及約100毫巴至150毫巴之一壓力。用於該方法的適當矽源氣體包含二氯矽烷及三氯矽烷。一碳源氣體可包括丙烷。該載體氣體可包括氫氣。該n摻雜物氣體可包括氮氣，及該p摻雜物氣體可包括三甲基鋁。
在本發明方法之一實施例中，在形成一p摻雜磊晶層之後，以氫氣及一含鹵素之氣體的一混合物沖洗該反應室。該含鹵素之氣體可包括HCl、Cl2 、F2 、CF4 、ClF3 或HBr，且較佳使用在約0.001%與50%之間之一濃度，更佳地使用在約0.05%至20%之間之一濃度，及最佳使用在0.1%與10%之間之一濃度。然而，應暸解含鹵素之氣體的量可根據該反應室的大小及表面積而改變。在一較佳實施例中，該混合物包括約60slm H2 及100sccm HCl。
就「沖洗」而言，其意謂在不存在一主要前驅體物質，亦即不包含一沈積物質之情況下，該氣體混合物流動在該室中。在沖洗之後，接著可生長另一n摻雜磊晶層或p摻雜磊晶層。該等n型或p型層之任何一者的目標摻雜物濃度係較佳地在約5×1013 cm-3 與1×1019 cm-3 之間。
在該方法的另一實施例中，在一第一p摻雜磊晶層生長後，接著以該氫氣/含鹵素之氣體混合物沖洗，及接著生長一第二p摻雜磊晶層，其中該第二p摻雜層的該摻雜物濃度低於該第一層的摻雜物濃度。在此實施例中，該第一p摻雜層的該摻雜物濃度在約1×1016 cm-3 與1×1019 cm-3 之間，且該第二p摻雜層的摻雜物濃度在約5×1013 與1×1017 cm-3 之間。使用該氫氣/含鹵素的沖洗氣體混合物有效地移除該反應室中來自該先前磊晶生長過程的殘留雜質及顯著減少記憶體效應。只要該CVD反應室在每個連續磊晶過程之間被沖洗，該等連續n及p層或連續p+/p-層的摻雜濃度便為可重複。該方法可用於生長多種多層SiC裝置結構，諸如PiN二極體、MESFET、雙極接面電晶體等等。
應瞭解在SiC磊晶結構需要改變該摻雜物載體類型(亦即p-n)或需要一第三層例如n-p-n之生長順序之諸情形下，該沖洗可在每個生長過程之後被執行。注意該沖洗步驟在該基板在該沖洗過程期間保留在該室中之諸情況下可導致蝕刻該先前生長層的一部分。因此，為了獲得所需p層厚度，該層應最先生長為包含一額外厚度餘裕的一厚度，該額外厚度餘裕可在該沖洗期間被蝕刻掉致使達成所需最終厚度。可使用此相同技術以生長複數個p型層，其中每個連續層具有一較低摻雜物濃度。
為使本發明可更易於理解，參考下列實例，其旨在闡釋本發明但不限制其範疇。
實例1
一SiC磊晶生長過程係在下列過程條件下，在一多晶圓行星運動電感加熱的CVD反應室中執行。
緊隨包括n+(層1)n-(層2)/p+(層3)的一薄膜結構的一SiC CVD磊晶生長，該等基板自該反應室被移除，以一100sccm HCl氣體與60slm H2 的混合物沖洗該室。該HCl/H2 混合物在500毫巴之一壓力及1600℃之一溫度下被引入該SiC磊晶反應器中持續4小時。在該沖洗程序後，新的基板被裝載入該室中且執行用於低摻雜n型SiC的SiC CVD磊晶過程。該等結果係顯示在下文表1中。
該等結果顯示藉由三個連續n摻雜層生長運轉(134-136)及如藉由水銀探針C-V量測測定的約2×1015 cm-3 之連續產生的低淨摻雜建立一基線n型摻雜濃度。接著執行一p+層生長(運轉137)，繼而進行4小時HCl/H2 沖洗。其次，一n摻雜層在相似條件下生長，並獲得2.1×1015 cm-3 的n型的一淨摻雜濃度。此指示殘留的鋁自該反應室被移除及一清潔背景係以該HCl/H2 沖洗達成。在運轉138之後，該循環接連重複兩次以上。在該層中的該n摻雜物濃度的可重複性係指示在表1中。如可見的，在該n型層中該淨摻雜的控制維持在一因數2內。
樣本137係藉由SIMS(二次離子質譜法)分析及超過1×1019 cm-3 的一鋁濃度如圖1中顯示被檢測。樣本138亦係藉由SIMS分析且發現氮與鋁均低於如圖2及圖3中顯示的其等檢測限制(分別為2×1015 cm-3 及5×1013 cm-3 )。
可推斷在p+ SiC磊晶生長之後該H2 /HCl沖洗步驟有效移除自該反應室殘留的鋁源並極大減少摻雜記憶體效應。
已詳細地描述本發明且藉由參考其較佳實施例，將顯而易見的係在不脫離本發明的該範疇下修飾與變動是可能的。
圖1是繪示根據本發明的一實施例形成的一p+ SiC磊晶CVD層中鋁濃度的一圖表；
圖2是繪示在一n-SiC磊晶CVD形成層中鋁濃度的一圖表；及
圖3是繪示在一n-SiC磊晶CVD形成層中氮濃度的一圖表。
(無元件符號說明)

Claims (11)

  1. 一種在半導體材料的磊晶生長期間減少記憶體效應之方法，其包括：提供一反應室；提供一半導體基板；提供一或多個前驅體氣體；在該反應室中執行一摻雜半導體材料的一磊晶CVD生長以形成一第一層於該半導體基板上，其中部份經反應之氣體被補獲於該反應室中成為副沈積物；以包括氫氣及一含鹵素之氣體的一氣體混合物沖洗該反應室，但該副沈積物並無顯著地自反應區域移除；及在該沖洗後，在該反應室中執行一摻雜半導體材料的一磊晶CVD生長以形成一第二層於該半導體基板上，其中該半導體材料係SiC。
  2. 如請求項1之方法，其中該反應室在約450℃至1800℃之間的一溫度下被沖洗。
  3. 如請求項1之方法，其中該反應室在約1300℃至1600℃之間的一溫度下被沖洗。
  4. 如請求項1之方法，其中該鹵化氣體係選自HCl、Cl2 、F2 、CF4 、ClF3 及HBr。
  5. 如請求項1之方法，其中在該沖洗過程期間該半導體基板保留在該室中。
  6. 如請求項1之方法，其中該半導體基板係在該沖洗過程之前自該室被移除，且在該沖洗過程之後再放回去。
  7. 如請求項1之方法，其中該半導體基板係在該沖洗過程之前自該室被移除，且在該沖洗過程之後以一新半導體基板替換。
  8. 如請求項1之方法，其中摻雜半導體材料的該第一層包括n摻雜SiC，且摻雜半導體材料的該第二層包括p摻雜SiC。
  9. 如請求項1之方法，其中摻雜半導體材料的該第一層包括p摻雜SiC，且摻雜半導體材料的該第二層包括具有一比該第一層低之摻雜物濃度之p摻雜SiC。
  10. 如請求項1之方法，其中該含鹵素之氣體的該濃度在約0.1%與10%之間。
  11. 如請求項1之方法，其係用於形成碳化矽半導體裝置。
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