TWI391903B - 閘極驅動電路 - Google Patents

閘極驅動電路 Download PDF

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TWI391903B
TWI391903B TW097129882A TW97129882A TWI391903B TW I391903 B TWI391903 B TW I391903B TW 097129882 A TW097129882 A TW 097129882A TW 97129882 A TW97129882 A TW 97129882A TW I391903 B TWI391903 B TW I391903B
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output buffer
buffer unit
voltage level
driving circuit
gate driving
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TW097129882A
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TW201007671A (en
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Chao Chih Hsiao
Yen Po Chen
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Novatek Microelectronics Corp
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Priority to TW097129882A priority Critical patent/TWI391903B/zh
Priority to US12/264,187 priority patent/US7759979B2/en
Publication of TW201007671A publication Critical patent/TW201007671A/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82385—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Description

閘極驅動電路
本發明係指一種閘極驅動電路，尤指一種用以驅動液晶面板上的薄膜電晶體的閘極驅動電路。
目前陰極射線管(CRT)螢幕已逐漸被液晶螢幕(LCD)所取代，正如錄音帶被光碟片所取代之勢不可擋一般。液晶螢幕的驅動晶片一般包括源極驅動器(Source Driver)晶片、閘級驅動器(Gate Driver)晶片、以及時序控制器(Timing Controller)晶片等。其中，源極驅動器也被稱作資料驅動器(Data Driver)，而閘級驅動器另被稱為掃瞄驅動器(Scan Driver)。
請參考第1圖，第1圖為習知閘極驅動晶片之單一通道佈局1示意圖。單一通道佈局1包含垂直堆疊的一輸出緩衝器(Output Buffer)區10、一電壓位準轉換器(Level Shifter)區12及一低壓邏輯電路(Low Voltage Circuit)區14。電壓位準轉換器係用以將低壓邏輯電路的訊號由低電位轉換到高電位，再輸出給輸出緩衝器，之後輸出緩衝器將訊號輸出以控制液晶面板上的薄膜電晶體之閘極。
如圖所示，輸出緩衝器區10所佔的佈局高度為H1，而電壓位準轉換器區12所佔的佈局高度為H2，所以兩者所佔的佈局高 度為H1＋H2。此種垂直堆疊的佈局方式佔據相當大的面積，對於追求將閘極驅動晶片的面積最小化的業界來說，實有改進的必要。
因此，本發明之主要目的即在於提供一種將面積縮小化以降低生產成本的閘極驅動電路。
本發明揭露一種閘極驅動電路，包含有一第一輸出緩衝單元區、一電壓位準轉換器區及一低壓邏輯電路區。第一輸出緩衝單元區係形成於一平面，用以設置一第一輸出緩衝單元。電壓位準轉換器區係形成於該平面上並用以設置一電壓位準轉換器，且包含相連的一垂直分區及一水平分區，該垂直分區與該第一輸出緩衝單元區並列於該平面之一水平方向，該水平分區位於該垂直分區及該第一輸出緩衝單元區之下。低壓邏輯電路區，形成於該平面上，位於該水平分區之下，並與該水平分區並列於該平面之一垂直方向，用以設置一低壓邏輯電路。
本發明另揭露一種閘極驅動電路，包含有一第一輸出緩衝單元區、一電壓位準轉換器區及一低壓邏輯電路區。第一輸出緩衝單元區係形成於一平面，用以設置一第一輸出緩衝單元。電壓位準轉換器區係形成於該平面上並與該第一輸出緩衝單元區並列於該平面之一水平方向，用以設置一電壓位準轉換器。低壓邏輯電路區係形成於該平面上位於該電壓位準轉換器區及該第一輸出緩 衝單元區之下，並與該電壓位準轉換器區並列於該平面之一垂直方向，用以設置一低壓邏輯電路。
請參考第2圖，第2圖為本發明實施例一閘極驅動電路之單通道佈局20之示意圖。閘極驅動電路是用以驅動液晶面板上的薄膜電晶體，並以積體電路來實現，其包含有一第一輸出緩衝單元區22、一電壓位準轉換器區24及一低壓邏輯電路區26。
第一輸出緩衝單元區22係形成於一平面(圖未示)，用以設置一第一輸出緩衝單元228。電壓位準轉換器區24係形成於該平面上並用以設置一電壓位準轉換器242，且包含相連的一垂直分區244及一水平分區246，垂直分區244與第一輸出緩衝單元區22並列於該平面之一水平方向(如箭頭9所指之方向)，水平分區246位於垂直分區244及第一輸出緩衝單元區22之下。低壓邏輯電路區26係形成於該平面上，位於水平分區246之下，並與水平分區246並列於該平面之一垂直方向(如箭頭8所指之方向)，其係用以設置一低壓邏輯電路。
如圖所示，由於電壓位準轉換器242及第一輸出緩衝單元228皆為高壓元件，所以位於垂直分區244之電壓位準轉換器242之部分電路可以與第一輸出緩衝單元228共用一N型井〈N－Well〉及一P型井〈P－Well〉，如此的佈局方式可以縮小所佔面積，並降 低生產成本。與第1圖的先前技術相比較，本發明的第一輸出緩衝單元區22及電壓位準轉換器區24所佔的佈局高度小於H1＋H2，故確實可以將整個閘極驅動電路2的面積縮小化。
請參考第3圖，第3圖為本發明實施例之閘極驅動電路之雙通道佈局30之示意圖。與第2圖的差異在於，第3圖的閘極驅動電路另包含一第二輸出緩衝單元區28。第二輸出緩衝單元區28係形成於該平面上並與第一輸出緩衝單元區22及垂直分區244並列於水平方向，其係用以設置一第二輸出緩衝單元。相對應地，此時電壓位準轉換器242包含有一第一子電壓位準轉換單元及一第二子電壓位準轉換單元(圖未示)，用以分別耦接於第一輸出緩衝單元及第二輸出緩衝單元。在第3圖中，第二輸出緩衝單元區28是位於第一輸出緩衝單元區22與垂直分區244之間，但也可以如第4圖之變形，將垂直分區244設於第一輸出緩衝單元區22與第二輸出緩衝單元區28之間。
請繼續參考第5圖，第5圖為第2圖之變形。第5圖係將第2圖中的水平分區246整合入垂直分區244，也就是說，電壓位準轉換器區24是與第一輸出緩衝單元區22並列於該平面之水平方向，而低壓邏輯電路區26則位於電壓位準轉換器區24及第一輸出緩衝單元區22之下，並與電壓位準轉換器區24並列於該平面之垂直方向。相同的變化方式，第3圖可變化成如第6圖所示之方式，第4圖可變化成如第7圖所示之方式。
值得注意的是，前述是以閘極驅動電路之單通道佈局20及雙通道佈局30來作說明，然本領域具通常知識者當可據以做不同之變化，以應用至四通道或更多通道的佈局。
綜上所述，本發明之電壓位準轉換器與第一輸出緩衝單元共用N型井及P型井，如此的佈局方式可以縮小所佔面積，並降低生產成本，故確實能達成本發明之目的。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
20‧‧‧單通道佈局
22‧‧‧第一輸出緩衝單元區
228‧‧‧第一輸出緩衝單元
24‧‧‧電壓位準轉換器區
242‧‧‧電壓位準轉換器
244‧‧‧垂直分區
246‧‧‧水平分區
26‧‧‧低壓邏輯電路區
28‧‧‧第二輸出緩衝單元區
30‧‧‧雙通道佈局
8‧‧‧箭頭
9‧‧‧箭頭
第1圖為習知閘極驅動晶片之單一通道佈局示意圖。
第2圖為本發明實施例一閘極驅動電路之單一通道佈局之示意圖。
第3圖為本發明實施例之閘極驅動電路之雙通道佈局之示意圖。
第4圖為本發明實施例之閘極驅動電路之另一雙通道佈局之示意圖。
第5圖為第2圖之變形之示意圖。
第6圖為第3圖之變形之示意圖。
第7圖為第4圖之變形之示意圖。
20‧‧‧單通道佈局
22‧‧‧第一輸出緩衝單元區
228‧‧‧第一輸出緩衝單元
24‧‧‧電壓位準轉換器區
242‧‧‧電壓位準轉換器
244‧‧‧垂直分區
246‧‧‧水平分區
26‧‧‧低壓邏輯電路區
8‧‧‧箭頭
9‧‧‧箭頭

Claims (16)

  1. 一種閘極驅動電路，包含有：一第一輸出緩衝單元區，形成於一平面，用以設置一第一輸出緩衝單元；一電壓位準轉換器區，形成於該平面上並與該第一輸出緩衝單元區並列於該平面之一水平方向，用以設置一電壓位準轉換器；以及一低壓邏輯電路區，形成於該平面上位於該電壓位準轉換器區及該第一輸出緩衝單元區之下，並與該電壓位準轉換器區並列於該平面之一垂直方向，用以設置一低壓邏輯電路。
  2. 如請求項1所述之閘極驅動電路，其中該第一輸出緩衝單元與該電壓位準轉換器係共用一N型井〈N－Well〉。
  3. 如請求項1所述之閘極驅動電路，其中該第一輸出緩衝單元與該電壓位準轉換器係共用一P型井〈P－Well〉。
  4. 如請求項1所述之閘極驅動電路，其另包含一第二輸出緩衝單元區，形成於該平面上並與該第一輸出緩衝單元區及該電壓位準轉換器區並列於該水平方向，用以設置一第二輸出緩衝單元。
  5. 如請求項4所述之閘極驅動電路，其中該第二輸出緩衝單元區係位於該第一輸出緩衝單元區與該電壓位準轉換器區之間。
  6. 如請求項5所述之閘極驅動電路，其中該電壓位準轉換器包含有一第一子電壓位準轉換單元及一第二子電壓位準轉換單元，分別耦接於該第一輸出緩衝單元及該第二輸出緩衝單元。
  7. 如請求項4所述之閘極驅動電路，其中該電壓位準轉換器區係位於該第一輸出緩衝單元區與該第二輸出緩衝單元區之間。
  8. 如請求項7所述之閘極驅動電路，其中該電壓位準轉換器包含有一第一子電壓位準轉換單元及一第二子電壓位準轉換單元，分別耦接於該第一輸出緩衝單元及該第二輸出緩衝單元。
  9. 一種閘極驅動電路，包含有：一第一輸出緩衝單元區，形成於一平面，用以設置一第一輸出緩衝單元；一電壓位準轉換器區，形成於該平面上並用以設置一電壓位準轉換器，且包含相連的一垂直分區及一水平分區，該垂直分區與該第一輸出緩衝單元區並列於該平面之一水平方向，該水平分區位於該垂直分區及該第一輸出緩衝單 元區之下；以及一低壓邏輯電路區，形成於該平面上，位於該水平分區之下，並與該水平分區並列於該平面之一垂直方向，用以設置一低壓邏輯電路。
  10. 如請求項9所述之閘極驅動電路，其中該第一輸出緩衝單元與該電壓位準轉換器係共用一N型井〈N－Well〉。
  11. 如請求項9所述之閘極驅動電路，其中該第一輸出緩衝單元與該電壓位準轉換器係共用一P型井〈P－Well〉。
  12. 如請求項9所述之閘極驅動電路，其另包含一第二輸出緩衝單元區，形成於該平面上並與該第一輸出緩衝單元區及該垂直分區並列於該水平方向，用以設置一第二輸出緩衝單元。
  13. 如請求項12所述之閘極驅動電路，其中該第二輸出緩衝單元區係位於該第一輸出緩衝單元區與該垂直分區之間。
  14. 如請求項13所述之閘極驅動電路，其中該電壓位準轉換器包含有一第一子電壓位準轉換單元及一第二子電壓位準轉換單元，分別耦接於該第一輸出緩衝單元及該第二輸出緩衝單元。
  15. 如請求項12所述之閘極驅動電路，其中該垂直分區係位於該第一輸出緩衝單元區與該第二輸出緩衝單元區之間。
  16. 如請求項15所述之閘極驅動電路，其中該電壓位準轉換器包含有一第一子電壓位準轉換單元及一第二子電壓位準轉換單元，分別耦接於該第一輸出緩衝單元及該第二輸出緩衝單元。
TW097129882A 2008-08-06 2008-08-06 閘極驅動電路 TWI391903B (zh)

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TW097129882A TWI391903B (zh) 2008-08-06 2008-08-06 閘極驅動電路
US12/264,187 US7759979B2 (en) 2008-08-06 2008-11-03 Gate driving circuit

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TW200426769A (en) * 2003-02-19 2004-12-01 Sony Corp Display device and driving method thereof
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