TWI385941B - Method and apparatus for canceling channel interference - Google Patents

Method and apparatus for canceling channel interference Download PDF

Info

Publication number
TWI385941B
TWI385941B TW096138675A TW96138675A TWI385941B TW I385941 B TWI385941 B TW I385941B TW 096138675 A TW096138675 A TW 096138675A TW 96138675 A TW96138675 A TW 96138675A TW I385941 B TWI385941 B TW I385941B
Authority
TW
Taiwan
Prior art keywords
signal
domain
processing
data
circuit
Prior art date
Application number
TW096138675A
Other languages
Chinese (zh)
Other versions
TW200919994A (en
Inventor
Liang Wei Huang
Chih Yung Shih
Shieh Hsing Kuo
Original Assignee
Realtek Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Realtek Semiconductor Corp filed Critical Realtek Semiconductor Corp
Priority to TW096138675A priority Critical patent/TWI385941B/en
Priority to US12/250,528 priority patent/US7933196B2/en
Publication of TW200919994A publication Critical patent/TW200919994A/en
Application granted granted Critical
Publication of TWI385941B publication Critical patent/TWI385941B/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/32—Reducing cross-talk, e.g. by compensating
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H04L25/03038—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a non-recursive structure
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L2025/03433—Arrangements for removing intersymbol interference characterised by equaliser structure
    • H04L2025/03439—Fixed structures
    • H04L2025/03445—Time domain
    • H04L2025/03471—Tapped delay lines
    • H04L2025/03477—Tapped delay lines not time-recursive
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L2025/03433—Arrangements for removing intersymbol interference characterised by equaliser structure
    • H04L2025/03535—Variable structures
    • H04L2025/03547—Switching between time domain structures
    • H04L2025/03566—Switching between time domain structures between different tapped delay line structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Circuit For Audible Band Transducer (AREA)

Description

干擾消除裝置及其方法Interference cancellation device and method thereof

本發明係有關於一種通訊系統，尤指一種用以消除干擾之通訊系統及其方法。The present invention relates to a communication system, and more particularly to a communication system and method for eliminating interference.

乙太網路係利用4對無遮蔽式雙絞線(UTP)進行全雙工的傳輸，如第1圖所示。在第1圖顯示乙太網路中訊號互相干擾的情形，例如傳送器110a傳輸的訊號在接收器120a所造成的回音(Echo)，以及傳送器110b、110c、110d對接收器120a形成的近端串音(near end cross talk,NEXT)等干擾。Ethernet uses four pairs of unshielded twisted pair (UTP) for full-duplex transmission, as shown in Figure 1. Fig. 1 shows a situation in which signals in the Ethernet interfere with each other, for example, an echo (Echo) caused by the signal transmitted by the transmitter 110a at the receiver 120a, and a near-form formed by the transmitters 110b, 110c, 110d to the receiver 120a. Interference such as near end cross talk (NEXT).

為了消除這些干擾訊號，一般係以干擾消除模組(例如一濾波器)對接收訊號進行時間域(time－domain)上的處理，濾波器係依據傳送器110a、110b、110c、110d的傳輸訊號以及估計出的通道響應(channel impulse response)產生近似於該些干擾訊號的干擾消除訊號，而將接收訊號減去干擾消除訊號後即可得出接收器120a應接收的訊號。然回音(Echo)與近端串音(NEXT)的特性不相同，所以用以模擬回音(Echo)與近端串音(NEXT)的濾波器之閥數(tap)也不盡相同，例如在10G乙太網路的環境下，大約分別需要長度(或閥數(tap))為250－500以及800－1000的濾波器才能模擬出近端串音訊號以及回音訊號，無論是電路複雜度或功率消耗都很可觀。In order to eliminate these interference signals, the interference cancellation module (for example, a filter) generally performs time-domain processing on the received signals, and the filters are based on the transmission signals of the transmitters 110a, 110b, 110c, and 110d. And the estimated channel impulse response generates an interference cancellation signal that approximates the interference signals, and the received signal is subtracted from the interference cancellation signal to obtain a signal that the receiver 120a should receive. However, the characteristics of echo (Echo) and near-end crosstalk (NEXT) are different, so the number of filters used to simulate echo (Echo) and near-end crosstalk (NEXT) is not the same, for example, In the 10G Ethernet environment, filters with lengths (or taps) of 250-500 and 800-1000 are required to simulate near-end crosstalk signals and echo signals, whether it is circuit complexity or Power consumption is considerable.

本發明之目的之一係提出一種干擾消除裝置及其方法，以克服上述問題。One of the objects of the present invention is to provide an interference canceling apparatus and method thereof to overcome the above problems.

本發明之目的之一係提出一種干擾消除裝置及其方法，藉由將資料分群以降低轉換運算的大小，以減少電路的複雜度。One of the objects of the present invention is to provide an interference canceling apparatus and method thereof, which reduce the complexity of a circuit by grouping data to reduce the size of the conversion operation.

本發明之目的之一係提出一種干擾消除裝置及其方法，藉由將資料分群以降低轉換運算的大小，可改善干擾消除模組的長度不同的問題。One of the objects of the present invention is to provide an interference canceling apparatus and method thereof, which can improve the length of the interference canceling module by grouping the data to reduce the size of the conversion operation.

本發明之目的之一係提出一種干擾消除裝置及其方法，藉由共用轉換電路以降低成本。One of the objects of the present invention is to provide an interference canceling apparatus and method thereof, which reduce cost by sharing a conversion circuit.

本發明之目的之一係提出一種干擾消除裝置及其方法，藉由通道變動的情形來選擇較佳的資料分群長度，以提高系統效能。One of the objects of the present invention is to provide an interference cancellation apparatus and method thereof for selecting a better data grouping length by channel variation to improve system performance.

本發明係將干擾消除及通道等化的動作轉換至頻率域來操作。然回音(Echo)與近端串音(NEXT)的特性不相同，故FFT電路的長度必須遷就模擬回音Echo所需的長度，對於近端串音NEXT的模擬來說不但浪費亦會造成效能損失。此外，當所欲模擬之干擾訊號中高低頻成分差異大時(例如：回音訊號中高頻成分係多於低頻成分)，若以相同位元數來表示每一頻率上的訊號分布，則位元數的選擇就必須受限於高頻成分，對低頻成分來說亦是浪資。The present invention operates by shifting the interference cancellation and channel equalization actions to the frequency domain. However, the characteristics of echo (Echo) and near-end crosstalk (NEXT) are different, so the length of the FFT circuit must be the length required for the analog echo Echo. For the simulation of the near-end crosstalk NEXT, not only waste but also performance loss will be caused. . In addition, when the difference between the high and low frequency components in the interference signal to be simulated is large (for example, the high frequency component is more than the low frequency component in the echo signal), if the signal distribution on each frequency is expressed by the same number of bits, the number of bits The choice must be limited by the high frequency components, and for the low frequency components is also the wave.

若只考量1對傳輸線上的干擾時，請參閱第2圖，其係本發明之干擾消除裝置200之一實施例的示意圖。干擾消除裝置200係根據傳送器(例如是第1圖的傳送器110a或/及傳送器110b)的傳輸訊號以模擬出干擾訊號(例如前述之回音訊號或近端串音訊號)的一干擾消除訊號。If only one pair of interference on the transmission line is considered, please refer to FIG. 2, which is a schematic diagram of an embodiment of the interference cancellation device 200 of the present invention. The interference cancellation device 200 is based on a transmission signal of a transmitter (for example, the transmitter 110a or the transmitter 110b of FIG. 1) to simulate an interference cancellation of an interference signal (such as the aforementioned echo signal or near-end crosstalk signal). Signal.

為了簡化頻率域上運算的複雜度，干擾消除裝置200可包括有一時間域處理模組210(此模組可省略不用，仍可達到本發明的目的)對傳輸訊號進行簡單的處理，使處理後的訊號的頻率分佈近似於所欲模擬之干擾消除訊號的頻率分布。一實施例，時間域處理模組210包含有一增益(gain)控制模組212以及一整形(shaping)電路214，增益控制模組212係用來調整傳輸訊號的增益至一預設範圍內，整形電路214則對傳輸訊號進行整形處理，相較於傳輸訊號的頻率分佈，經過整形處理後的傳輸訊號的頻率分佈係較近似所欲模擬之干擾消除訊號的頻率分布。In order to simplify the complexity of the operation in the frequency domain, the interference cancellation device 200 can include a time domain processing module 210 (this module can be omitted, the object of the present invention can still be achieved), and the transmission signal is simply processed to be processed. The frequency distribution of the signal approximates the frequency distribution of the interference cancellation signal to be simulated. In one embodiment, the time domain processing module 210 includes a gain control module 212 and a shaping circuit 214. The gain control module 212 is configured to adjust the gain of the transmission signal to a predetermined range. The circuit 214 performs shaping processing on the transmission signal. Compared with the frequency distribution of the transmission signal, the frequency distribution of the shaped transmission signal is closer to the frequency distribution of the interference cancellation signal to be simulated.

在一實施例中，整形電路214係一複雜度低的前饋等化器(FFE)，可以有限脈衝響應(FIR)濾波器或無限脈衝響應(IIR)濾波器實現。實作上可先以習知的通道估計演算法粗略計算出濾波器的閥值(tap value)，再以適應性演算法對該些閥值進行微調。整形電路214的設計目的在於使消除信號產生模組250只需處理較均勻(uniform)的處理範圍，如此設計可使用較少的位元數來表示每一頻率上的訊號分布。舉例來說，由於回音訊號及近端串音訊號中高頻成分較多，整形電路214可設計成一高通濾波器，先在時間域上對傳輸訊號進行簡單的調整使其頻率分布近似於回音訊號或近端串音訊號的頻率分布，如此一來後續頻率域上的處理便無須特別放大高頻成分，如此設計便可以減少位元數，簡化複雜度。In one embodiment, shaping circuit 214 is a low complexity feedforward equalizer (FFE) that can be implemented with a finite impulse response (FIR) filter or an infinite impulse response (IIR) filter. In practice, the filter value of the filter can be roughly calculated by a conventional channel estimation algorithm, and the threshold values are fine-tuned by an adaptive algorithm. The shaping circuit 214 is designed to allow the cancellation signal generation module 250 to only process a more uniform processing range, such that a smaller number of bits can be used to represent the signal distribution at each frequency. For example, due to the high frequency component of the echo signal and the near-end crosstalk signal, the shaping circuit 214 can be designed as a high-pass filter, and the transmission signal is simply adjusted in the time domain to make the frequency distribution approximate to the echo signal or The frequency distribution of the near-end crosstalk signal, so that the processing in the subsequent frequency domain does not need to specifically amplify the high-frequency components, so that the design can reduce the number of bits and simplify the complexity.

增益控制模組212控制傳輸訊號的增益在一預設範圍內，故僅需設計一套消除信號產生模組250便可適用於各種干擾訊號的消除或各種通道的等化，減少系統開發及維護的成本與複雜度。在實作上，增益控制模組212可以一長度為1的數位自動增益控制器(Digital AGC)來加以實作(傳輸訊號係一數位訊號)，此外，增益控制模組212亦可耦接於訊號整形器214之後。The gain control module 212 controls the gain of the transmission signal within a predetermined range. Therefore, only one set of the cancellation signal generation module 250 can be designed to eliminate various interference signals or equalize various channels, thereby reducing system development and maintenance. Cost and complexity. In practice, the gain control module 212 can be implemented by a digital automatic gain controller (Digital AGC) of length 1 (the transmission signal is a digital signal), and the gain control module 212 can also be coupled to After the signal shaper 214.

在本實施例中，傳輸訊號係被傳送至一分群電路220，並由分群電路220(例如是串列/平行轉換器)將傳輸訊號分成複數筆子資料。接著一混疊(overlap)電路230依序對分群電路220的輸出進行混疊處理，再由一轉換電路240依序將混疊後的資料從時間域轉換至頻率域，由於輸入轉換電路240的資料已經過混疊處理，因此，轉換電路240所執行的循環旋積(circular convolution)在時間域上可等效為線性旋積(linear convolution)的結果。本發明之轉換電路240可使用任何具有時間域/頻率域轉換功能的運算，如快速傅立葉(FFT)轉換、正弦轉換(Sine transform)、餘弦轉換(Cosine transform)等。In this embodiment, the transmission signal is transmitted to a grouping circuit 220, and the grouping circuit 220 (for example, a serial/parallel converter) divides the transmission signal into a plurality of pieces of data. Then, an overlap circuit 230 sequentially performs an aliasing process on the output of the grouping circuit 220, and then the conversion circuit 240 sequentially converts the aliased data from the time domain to the frequency domain, due to the input conversion circuit 240. The data has been aliased, so the circular convolution performed by the conversion circuit 240 can be equivalent to the result of a linear convolution in the time domain. The conversion circuit 240 of the present invention can use any operation having a time domain/frequency domain conversion function, such as Fast Fourier Transform (FFT) conversion, Sine transform, Cosine transform, and the like.

接著，每一筆轉換後的子資料被依序送入消除信號產生模組250，消除信號產生模組250包含有至少一延遲電路以及複數個處理電路，其中延遲電路252用來依序延遲轉換後的第一子資料以產生複數筆延遲後的第一子資料，而複數個處理電路中包含有一第一處理電路254與至少一第二處理電路256，其中第一處理電路254係依序對該複數筆轉換後的第一子資料進行處理，以及第二處理電路256係依序對該複數筆延遲後的第一子資料進行處理。Then, each converted sub-data is sequentially sent to the cancellation signal generation module 250. The cancellation signal generation module 250 includes at least one delay circuit and a plurality of processing circuits, wherein the delay circuit 252 is used to sequentially delay the conversion. The first sub-data is used to generate the first sub-data after the plurality of delays, and the plurality of processing circuits include a first processing circuit 254 and at least one second processing circuit 256, wherein the first processing circuit 254 sequentially The first sub-data converted by the plurality of pens is processed, and the second processing circuit 256 sequentially processes the first sub-data delayed by the plurality of pens.

請注意，延遲電路252及第二處理電路256的個數係與傳輸訊號分群處理的數目有關，且轉換電路240所執行之轉換運算的長度及分群電路220輸出之子資料的長度亦與該分群數目有關，而分群的數目則是根據干擾消除訊號的特性，例如是模擬出該干擾消除訊號所需之濾波器的長度(或閥數)。舉例來說，模擬回音訊號，此時預定訊號處理長度約為900；若模擬近端串音訊號，此時預定訊號處理長度約為300。在本實施例中，以預定訊號處理長度為900的回音訊號為例，為了降低該轉換電路240(如：快速傅立葉轉換)的大小以減少成本，分群電路220將傳輸訊號分成3筆子資料，而消除信號產生模組250以2個延遲電路252、252’及3個處理電路(第一處理電路254以及第二處理電路256、256’)來依序處理這3筆子資料，因此，第一處理電路254及第二處理電路256、256’均為長度300(900除以3)的處理器，換言之，轉換電路240的大小則依據300來選擇。一另一實施例，轉換電路240的大小亦可採用256或512(係選擇與300較接近的2的冪次數值)。Please note that the number of the delay circuit 252 and the second processing circuit 256 is related to the number of transmission signal grouping processes, and the length of the conversion operation performed by the conversion circuit 240 and the length of the sub-data output by the grouping circuit 220 are also the number of the group. Related to, the number of clusters is based on the characteristics of the interference cancellation signal, such as the length (or number of valves) required to simulate the interference cancellation signal. For example, the analog echo signal, at this time, the predetermined signal processing length is about 900; if the near-end crosstalk signal is simulated, the predetermined signal processing length is about 300 at this time. In this embodiment, the echo signal with a length of 900 is processed by a predetermined signal as an example. In order to reduce the size of the conversion circuit 240 (eg, fast Fourier transform) to reduce the cost, the grouping circuit 220 divides the transmission signal into three pieces of data. The cancellation signal generation module 250 sequentially processes the three sub-subsequences by two delay circuits 252, 252' and three processing circuits (the first processing circuit 254 and the second processing circuit 256, 256'). A processing circuit 254 and a second processing circuit 256, 256' are processors of length 300 (900 divided by 3). In other words, the size of the conversion circuit 240 is selected according to 300. In another embodiment, the size of the conversion circuit 240 can also be 256 or 512 (the power value of 2 is selected to be closer to 300).

第2圖中的第一處理電路254及第二處理電路256、第二處理電路256’係分別對應至傳送器110a與接收器120a之間通道響應的一部份。在一實施例中，第一處理電路254及第二處理電路256、256’皆包括有乘法電路，將轉換後的子資料乘上權重係數(weighting coefficients)。一實施例，各處理電路254、256、256’所對應的權重係數可由適應性演算法估計該通道響應而得出，例如最小均方誤差演算法、遞迴最小平方(Recursive Least Square,RLS)演算法等等。等到轉換後的3筆資料都分別經過第一處理電路254、第二處理電路256及第二處理電路256’的處理後，其總和(加法器258的輸出)即為頻率域上的干擾消除訊號。簡單地說，子資料在消除信號產生模組250中的傳送流程係類似一濾波器內部的流程，分別經過各處理電路乘上對應的權重係數，由於頻率域上相乘的動作等效於在時間域上進行旋積，因此，加法器258的輸出等效於將子資料與該通道響應進行旋積得出之回音訊號。The first processing circuit 254 and the second processing circuit 256 and the second processing circuit 256' in Fig. 2 correspond to a portion of the channel response between the transmitter 110a and the receiver 120a, respectively. In one embodiment, the first processing circuit 254 and the second processing circuit 256, 256' each include a multiplying circuit that multiplies the converted sub-data by weighting coefficients. In one embodiment, the weight coefficients corresponding to the processing circuits 254, 256, 256' may be derived by estimating the channel response by an adaptive algorithm, such as a minimum mean square error algorithm, Recursive Least Square (RLS). Algorithms and more. After the converted three pieces of data are processed by the first processing circuit 254, the second processing circuit 256 and the second processing circuit 256', respectively, the sum (the output of the adder 258) is the interference cancellation signal in the frequency domain. . Briefly, the transmission process of the sub-data in the cancellation signal generation module 250 is similar to the internal flow of a filter, and each of the processing circuits is multiplied by a corresponding weight coefficient, since the multiplication in the frequency domain is equivalent to The convolution is performed on the time domain, so the output of the adder 258 is equivalent to the echo signal obtained by convolving the sub-data with the channel response.

而對消除信號產生模組250產生之頻率域上的干擾消除訊號進行反向處理(或稱逆處理)(在本實施例為：反轉換運算、混疊運算及解分群)之後，干擾消除裝置200即可得出時間域上的干擾消除訊號，其中反轉換電路260、混疊電路270及解分群電路280係對應於轉換電路250、混疊電路230及分群電路220進行反向處理，例如：轉換電路250係採用FFT轉換時，則該反轉換電路260即採用反快速傅立葉(IFFT)轉換。由於熟知此項技藝之人士應可輕易瞭解反轉換電路260、混疊電路270及解分群電路280的功效及運作，詳細的操作過程便在此省略不再贅述。After the interference cancellation signal in the frequency domain generated by the cancellation signal generation module 250 is inversely processed (or inversely processed) (in this embodiment, the inverse conversion operation, the aliasing operation, and the de-grouping), the interference cancellation device 200, the interference cancellation signal in the time domain is obtained, wherein the inverse conversion circuit 260, the aliasing circuit 270, and the de-segmenting circuit 280 are inversely processed corresponding to the conversion circuit 250, the aliasing circuit 230, and the grouping circuit 220, for example: When the conversion circuit 250 is FFT-converted, the inverse conversion circuit 260 employs an inverse fast Fourier (IFFT) conversion. Since the function and operation of the inverse conversion circuit 260, the aliasing circuit 270, and the de-segmenting circuit 280 should be easily understood by those skilled in the art, the detailed operation will not be repeated here.

由於各處理電路所使用的適應性演算法係針對每一筆子資料就更新一次權重係數，若子資料的長度太長，亦即轉換運算的長度太長，造成權重係數許久才更新一次，將會無法即時反應出通道的變化，使得干擾消除的效果不佳，因此，在設計轉換運算的長度時可依據通道特性變動的程度來選擇，即若偵測到通道特性變動很快，則選擇較小的轉換運算長度，反之則選擇較長的轉換運算長度，以達到最佳的系統效能。Since the adaptive algorithm used by each processing circuit updates the weight coefficient for each piece of data, if the length of the sub-data is too long, that is, the length of the conversion operation is too long, and the weight coefficient is updated for a long time, it will not be possible. Instantly reflecting the change of the channel makes the interference cancellation effect poor. Therefore, when designing the length of the conversion operation, it can be selected according to the degree of variation of the channel characteristics, that is, if the channel characteristic change is detected quickly, the smaller one is selected. Convert the length of the operation, otherwise choose a longer length of the conversion operation to achieve the best system performance.

考量在1對傳輸線時，尚有其他的干擾信號(例如是其他對傳輸線所造成的干擾)時，請參閱第3圖係本發明之消除複數種干擾訊號之一實施例的示意圖。如：干擾消除裝置300所產生之干擾消除訊號係用來消除傳送器110a所產生之回音訊號Echo_a以及傳送器110b所產生之近端串音訊號NEXT_ba，而傳輸訊號a係為傳送器110a的傳輸訊號，傳輸訊號b係為傳送器110b的傳輸訊號。相較於干擾消除裝置200，干擾消除裝置300另包含有一第二時間域處理模組310、一第二分群電路320、一第二混疊電路330以及一第二轉換電路340，用來將傳輸訊號b分成複數筆第二子資料並依序轉換至頻率域以產生複數筆轉換後的第二子資料，而消除信號產生模組350中另包含一第三處理電路352，依序將該複數筆轉換後的第二子資料乘上對應於傳送器110b及接收器120a間之通道響應的權重係數，以產生頻率域上的近端串音訊號NEXT_ba。When considering one pair of transmission lines, there are other interference signals (for example, other interference to the transmission line), please refer to FIG. 3 is a schematic diagram of an embodiment of the present invention for eliminating a plurality of interference signals. For example, the interference cancellation signal generated by the interference cancellation device 300 is used to cancel the echo signal Echo_a generated by the transmitter 110a and the near-end crosstalk signal NEXT_ba generated by the transmitter 110b, and the transmission signal a is the transmission of the transmitter 110a. The signal, the transmission signal b is the transmission signal of the transmitter 110b. Compared with the interference cancellation device 200, the interference cancellation device 300 further includes a second time domain processing module 310, a second grouping circuit 320, a second aliasing circuit 330, and a second conversion circuit 340. The transmission signal b is divided into a second sub-data of the plurality of pens and sequentially converted to the frequency domain to generate a second sub-data converted by the plurality of pens, and the third signal processing circuit 352 is further included in the cancellation signal generating module 350. The second sub-data converted by the plurality of pens is multiplied by a weight coefficient corresponding to the channel response between the transmitter 110b and the receiver 120a to generate a near-end crosstalk signal NEXT_ba in the frequency domain.

一實施例，第二轉換電路340所執行之轉換運算的大小係等於第一轉換電路240所執行之轉換運算的大小。在一實施例中，轉換運算的大小係依據回音訊號Echo_a以及近端串音訊號NEXT_ba兩者中最短的預定訊號處理長度而決定。舉例來說，回音訊號Echo_a的預定訊號處理長度為900，近端串音訊號NEXT_ba的預定訊號處理長度為300，因此，轉換運算的大小便為300或是靠近300的2的羃次數值來作選擇，例如是256或512，在這種情形下，模擬回音訊號Echo_a時使用3(900除以300)個處理電路(第一處理電路254及第二處理電路256、256’)來實現，模擬近端串音訊號NEXT_ba時使用一個處理電路(第三處理電路352)來實現，如此一來，相較於習知技術，本發明可改善因干擾訊號長度不同而浪費轉換運算長度的問題，且不會造成效能損失。同樣地，第三處理電路352的權重係數係可由適應性演算法估計傳送器110b與接收器120a之間的通道響應來得出。且尚可依據通道特性變動而改變轉換運算的長度以達到系統效能最佳化，由於熟知此項技藝之人士可依據本發明先前揭露之內容瞭解此變化設計，故在此省略不再贅述。In one embodiment, the size of the conversion operation performed by the second conversion circuit 340 is equal to the size of the conversion operation performed by the first conversion circuit 240. In one embodiment, the size of the conversion operation is determined according to the shortest predetermined signal processing length of both the echo signal Echo_a and the near-end crosstalk signal NEXT_ba. For example, the predetermined signal processing length of the echo signal Echo_a is 900, and the predetermined signal processing length of the near-end crosstalk signal NEXT_ba is 300. Therefore, the size of the conversion operation is 300 or a value of 2 times close to 300. The selection is, for example, 256 or 512. In this case, the analog echo signal Echo_a is implemented by using 3 (900 divided by 300) processing circuits (the first processing circuit 254 and the second processing circuit 256, 256') to simulate The near-end crosstalk signal NEXT_ba is implemented by using a processing circuit (the third processing circuit 352). As a result, the present invention can improve the problem of wasting the conversion operation length due to the difference in the length of the interference signal compared to the prior art. No loss of performance. Similarly, the weighting coefficients of the third processing circuit 352 can be derived from the adaptive algorithm estimating the channel response between the transmitter 110b and the receiver 120a. The length of the conversion operation may be changed according to the channel characteristics to achieve the system performance optimization. Since the person skilled in the art can understand the change design according to the content disclosed in the present disclosure, the description is omitted here.

若將前述之干擾消除系統應用於4對線的通訊系統(例如第1圖的架構)，其架構係如第4圖所示。第4圖中的Echo處理模組(如是Echo_a 401、Echo_b、Echo_c、Echo_d等處理模組)的架構係實質上相似於第3圖中的Echo處理模組；第4圖的NEXT處理模組(如是NEXT_ba、NEXT_ca、NEXT_da、…、NEXT_bd、NEXT_cd等處理模組)用來模擬近端串音訊號，其架構係實質上相似於第3圖中的NEXT處理模組。由於熟知此項技藝之人士可依據本發明先前揭露之內容瞭解此變化設計，故在此省略不再贅述。If the aforementioned interference cancellation system is applied to a 4-pair communication system (for example, the architecture of FIG. 1), the architecture is as shown in FIG. The architecture of the Echo processing module (such as Echo_a 401, Echo_b, Echo_c, Echo_d, etc.) in Figure 4 is substantially similar to the Echo processing module in Figure 3; the NEXT processing module in Figure 4 ( For example, NEXT_ba, NEXT_ca, NEXT_da, ..., NEXT_bd, NEXT_cd and other processing modules are used to simulate the near-end crosstalk signal, and the architecture is substantially similar to the NEXT processing module in FIG. Since the person skilled in the art can understand the change design according to the content disclosed in the present disclosure, the detailed description is omitted here.

以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

110a－110h．．．傳送器110a-110h. . . Transmitter

120a－120h．．．接收器120a-120h. . . receiver

200、300．．．干擾消除裝置200, 300. . . Interference cancellation device

210、310．．．時間域處理模組210, 310. . . Time domain processing module

212．．．增益控制模組212. . . Gain control module

214．．．整形電路214. . . Shaping circuit

220、320．．．分群電路220, 320. . . Group circuit

230、270、330．．．混疊電路230, 270, 330. . . Aliasing circuit

240、340．．．轉換電路240, 340. . . Conversion circuit

250、350．．．消除信號產生模組250, 350. . . Elimination signal generation module

252、252’．．．延遲電路252, 252’. . . Delay circuit

254．．．第一處理電路254. . . First processing circuit

256、256’．．．第二處理電路256, 256’. . . Second processing circuit

258、354．．．加法器258, 354. . . Adder

260．．．反轉換電路260. . . Reverse conversion circuit

280．．．解分群電路280. . . De-grouping circuit

352．．．第三處理電路352. . . Third processing circuit

401．．．Echo_a處理模組401. . . Echo_a processing module

402．．．NEXT_ba處理模組402. . . NEXT_ba processing module

403．．．NEXT_ca處理模組403. . . NEXT_ca processing module

第1圖係為利用4對線進行全雙工傳輸的示意圖。Figure 1 is a schematic diagram of full duplex transmission using 4 pairs of lines.

第2圖係本發明之干擾消除系統之一實施例的示意圖。Figure 2 is a schematic illustration of one embodiment of an interference cancellation system of the present invention.

第3圖係本發明之干擾消除系統之另一實施例的示意圖。Figure 3 is a schematic illustration of another embodiment of the interference cancellation system of the present invention.

第4圖係本發明之干擾消除系統之另一實施例的示意圖。Figure 4 is a schematic illustration of another embodiment of the interference cancellation system of the present invention.

200．．．干擾消除裝置200. . . Interference cancellation device

210．．．時間域處理模組210. . . Time domain processing module

212．．．增益控制模組212. . . Gain control module

214．．．整形電路214. . . Shaping circuit

220．．．分群電路220. . . Group circuit

230、270．．．混疊電路230, 270. . . Aliasing circuit

240．．．轉換電路240. . . Conversion circuit

250．．．消除信號產生模組250. . . Elimination signal generation module

252、252’．．．延遲電路252, 252’. . . Delay circuit

254．．．第一處理電路254. . . First processing circuit

256、256’．．．第二處理電路256, 256’. . . Second processing circuit

258．．．加法器258. . . Adder

260．．．反轉換電路260. . . Reverse conversion circuit

280．．．解分群電路280. . . De-grouping circuit

Claims (41)

一種干擾消除裝置，該裝置包含：一第一干擾消除模組，包括：一第一處理電路，包括：一分群電路，用來將所接收到的資料分成複數個第一子資料；一第一轉換電路，耦接於該第一處理電路，用來將該複數個第一子資料依序由一第一定義域(domain)轉換至一第二定義域以產生複數個第一轉換子資料，其中該第一定義域為時間域，且該第二定義域為頻率域；一第一消除信號產生電路，耦接於該第一轉換電路，其包括：一延遲單元，用來依序延遲該複數個第一轉換子資料以產生複數個延遲子資料；以及一第一處理單元與一第二處理單元，該第一處理單元係依據該複數個轉換子資料以輸出一第一處理信號，以及該第二處理單元係依據該複數個延遲子資料以輸出一第二處理信號；其中，該第一消除信號產生電路依據該第一處理信號與該第二處理信號以輸出一第一消除信號，該第一消除信號係為對應於一第一對傳輸線之一第一干擾信號的預估信號。 An interference cancellation device, comprising: a first interference cancellation module, comprising: a first processing circuit, comprising: a grouping circuit, configured to divide the received data into a plurality of first sub-data; a conversion circuit coupled to the first processing circuit, configured to sequentially convert the plurality of first sub-data from a first domain to a second domain to generate a plurality of first sub-data, The first domain is a time domain, and the second domain is a frequency domain. A first cancellation signal generating circuit is coupled to the first conversion circuit, and includes: a delay unit, configured to sequentially delay the a plurality of first conversion sub-data to generate a plurality of delay sub-data; and a first processing unit and a second processing unit, the first processing unit is configured to output a first processing signal according to the plurality of conversion sub-data, and The second processing unit outputs a second processing signal according to the plurality of delay sub-data; wherein the first cancellation signal generating circuit outputs the second processing signal according to the first processing signal and the second processing signal A first cancellation signal, the first signal line to eliminate the interference signal corresponding to a first one of a first pair of transmission line signal estimates. 如第1項所述之裝置，該第一消除信號產生電路還包括： 一第三處理單元，接收複數個第二轉換子資料，並依據該複數個第二轉換子資料以輸出一第二消除信號，其中，該第二消除信號係為該第一對傳輸線之一第二干擾信號的預估信號；以及一加總電路，用以接收該第一以及該第二消除信號以產生一第一干擾消除信號。 The device of claim 1, the first cancellation signal generating circuit further comprising: a third processing unit receives a plurality of second conversion sub-data, and outputs a second cancellation signal according to the plurality of second conversion sub-data, wherein the second cancellation signal is one of the first pair of transmission lines And a summing circuit for receiving the first and second canceling signals to generate a first interference canceling signal. 如第1或第2項所述之裝置，其中該第一處理電路還包括：一混疊電路，耦接於該分群電路與該第一轉換電路間，用以混疊該複數個第一子資料；以及該干擾消除裝置還包括有：一反混疊電路，係為該混疊電路的反向運算。 The device of claim 1 or 2, wherein the first processing circuit further comprises: an aliasing circuit coupled between the grouping circuit and the first converting circuit for aliasing the plurality of first sub- And the interference cancellation device further includes: an anti-aliasing circuit, which is an inverse operation of the aliasing circuit. 如第1或第2項所述之裝置，其中，該干擾消除裝置還包括有：一解分群電路，耦接該第一消除信號產生電路，係為該分群電路的反向運算。 The device of claim 1 or 2, wherein the interference cancellation device further comprises: a de-segmenting circuit coupled to the first cancellation signal generating circuit, which is an inverse operation of the grouping circuit. 如第1或第2項所述之裝置，還包括有：一第一反轉換電路，耦接該第一消除信號產生電路，用以將該第一消除信號產生電路的輸出由該第二定義域轉換至該第一定義域。 The device of claim 1 or 2, further comprising: a first inverse conversion circuit coupled to the first cancellation signal generating circuit for outputting the output of the first cancellation signal generating circuit by the second definition The domain is converted to the first domain. 如第1或第2項所述之裝置，其中該第一轉換電路的轉換運算的大小係依據該第一干擾信號的特性而定。 The device of claim 1 or 2, wherein the size of the conversion operation of the first conversion circuit is dependent on the characteristics of the first interference signal. 如第1或第2項所述之裝置，還包括：一第二干擾消除模組，用以輸出對應於一第二對傳輸線之干擾信號的預估信號。 The device of claim 1 or 2, further comprising: a second interference cancellation module for outputting an estimated signal corresponding to the interference signal of the second pair of transmission lines. 如第7項所述之裝置，還包括：一第三干擾消除模組，用以輸出對應於一第三對傳輸線之干擾信號的預估信號；以及一第四干擾消除模組，用以輸出對應於一第四對傳輸線之干擾信號的預估信號。 The device of claim 7, further comprising: a third interference cancellation module for outputting an estimated signal corresponding to an interference signal of a third pair of transmission lines; and a fourth interference cancellation module for outputting An estimated signal corresponding to an interference signal of a fourth pair of transmission lines. 如第8項所述之裝置，其係應用於一乙太網路系統。 The device of item 8, which is applied to an Ethernet system. 如第1項所述之裝置，其中該第一轉換電路所執行之轉換運算的大小係小於該第一干擾訊號於該第二定義域中最長預定訊號的處理長度。 The device of claim 1, wherein the conversion operation performed by the first conversion circuit is smaller than the processing length of the longest predetermined signal of the first interference signal in the second defined domain. 一種干擾消除裝置，包含：一第一干擾消除模組，包括：一分群電路，用來將一第一資料分成複數個第一子資料；一轉換電路，用來將該複數個第一子資料依序由一第一定義域(domain)轉換至一第二定義域以產生複數個轉換子資料，其中該第一定義域為時間域，且該第二定義域為頻率域； 一延遲電路，用來依序延遲該複數個轉換子資料以產生複數個延遲子資料；以及一處理電路，包括有一第一處理單元與一第二處理單元用以分別對該複數筆轉換子資料與該複數筆延遲子資料進行處理以分別產生一第一處理信號以及一第二處理信號，該處理電路依據該第一處理信號以及該第二處理信號以輸出一干擾消除信號；一反轉換電路，耦接該處理電路，用以將該干擾消除信號由該第二定義域轉換至該一第一定義域；以及一解分群電路，耦接該反轉換電路，係用以接收該反轉換電路之經轉換的該干擾消除信號，以及用以輸出對應於一第一對傳輸線之干擾信號的預估信號，其中，該解分群電路係為該分群電路的反向運算。 An interference cancellation device includes: a first interference cancellation module, comprising: a grouping circuit for dividing a first data into a plurality of first sub-data; and a conversion circuit for using the plurality of first sub-data Converting from a first domain to a second domain to generate a plurality of conversion sub-data, wherein the first domain is a time domain, and the second domain is a frequency domain; a delay circuit for sequentially delaying the plurality of conversion sub-data to generate a plurality of delay sub-data; and a processing circuit including a first processing unit and a second processing unit for respectively converting the sub-sub-sub-data And processing the plurality of delay sub-data to generate a first processing signal and a second processing signal, the processing circuit outputting an interference cancellation signal according to the first processing signal and the second processing signal; and an inverse conversion circuit And the processing circuit is configured to convert the interference cancellation signal from the second domain to the first domain; and a de-segment circuit coupled to the inverse conversion circuit for receiving the inverse conversion circuit The interference cancellation signal converted and the prediction signal for outputting an interference signal corresponding to a first pair of transmission lines, wherein the de-segment circuit is an inverse operation of the grouping circuit. 如第11項所述之裝置，還包括：一第二干擾消除模組，用以輸出對應於一第二對傳輸線之干擾信號的預估信號。 The device of claim 11, further comprising: a second interference cancellation module for outputting an estimated signal corresponding to the interference signal of the second pair of transmission lines. 如第12項所述之裝置，還包括：一第三干擾消除模組，用以輸出對應於一第三對傳輸線之干擾信號的預估信號；以及一第四干擾消除模組，用以輸出對應於一第四對傳輸線之干擾信號的預估信號。 The device of claim 12, further comprising: a third interference cancellation module for outputting an estimated signal corresponding to the interference signal of the third pair of transmission lines; and a fourth interference cancellation module for outputting An estimated signal corresponding to an interference signal of a fourth pair of transmission lines. 如第11項所述之裝置，還包括：一混疊電路，耦接於該分群電路與該第一轉換電路間，用以對該複數個第一子資料進行混疊處理。 The device of claim 11, further comprising: an aliasing circuit coupled between the grouping circuit and the first converting circuit for performing aliasing processing on the plurality of first sub-data. 如第11項所述之裝置，該處理電路還包括：一第三處理單元，用以接收複數個第二轉換子資料，並依據該複數個第二轉換子資料以輸出一第二消除信號，其中，該第二消除信號係為該第一對傳輸線之一第二干擾信號的預估信號。 The device of claim 11, the processing circuit further comprising: a third processing unit, configured to receive the plurality of second conversion sub-data, and output a second cancellation signal according to the plurality of second conversion sub-data, The second cancellation signal is a prediction signal of the second interference signal of one of the first pair of transmission lines. 如第11項所述之裝置，還包括：一時域處理模組，用以對該第一資料進行增益與整形處理的至少其中一種的處理後再輸出至該第一干擾消除模組。 The device of claim 11, further comprising: a time domain processing module, configured to perform processing on at least one of gain and shaping processing on the first data, and then output to the first interference cancellation module. 一種干擾消除方法，包含有：將所接收之一第一資料進行分群的處理以分成複數個第一子資料；將該複數個第一子資料由一第一定義域轉換至一第二定義域以產生複數個第一轉換子資料，其中該第一定義域為時間域，且該第二定義域為頻率域；延遲該複數個第一轉換子資料以產生複數個第一延遲子資料；分別對該複數個第一轉換子資料與該複數個第一延遲子資料進行處理以產生複數個處理信號；以及 加總該複數個處理信號來產生一第一消除信號，其中該第一消除信號係為對應於一第一對傳輸線之一第一干擾信號的預估信號。 An interference cancellation method includes: dividing a received first data into a plurality of first sub-data; and converting the plurality of first sub-data from a first domain to a second domain Generating a plurality of first conversion sub-data, wherein the first domain is a time domain, and the second domain is a frequency domain; delaying the plurality of first conversion sub-data to generate a plurality of first delay sub-data; respectively Processing the plurality of first conversion sub-data and the plurality of first delay sub-data to generate a plurality of processing signals; And summing the plurality of processing signals to generate a first cancellation signal, wherein the first cancellation signal is an estimated signal corresponding to the first interference signal of one of the first pair of transmission lines. 如第17項所述之方法，其中該進行分群之步驟，還包含：將該複數個第一子資料予以進行混疊的處理。 The method of claim 17, wherein the step of performing grouping further comprises: processing the plurality of first sub-data to be aliased. 如第17項所述之方法，還包含有：將所接收之一第二資料進行分群的處理以分成複數個第二子資料；將該複數個第二子資料由該第一定義域轉換至該第二定義域以產生複數個第二轉換子資料；處理該複數個第二子資料以產生一第二消除信號，其中該第二消除信號係為對應於該第一對傳輸線之一第二干擾信號的預估信號。 The method of claim 17, further comprising: processing the received one of the second data into a plurality of second sub-data; converting the plurality of second sub-data from the first domain to the first domain The second domain is configured to generate a plurality of second conversion sub-data; processing the plurality of second sub-data to generate a second cancellation signal, wherein the second cancellation signal is corresponding to one of the first pair of transmission lines The estimated signal of the interference signal. 如第19項所述之方法，還包含有：加總複數個消除信號來產生一第一干擾消除信號，其中該複數個消除信號包含有該第一消除信號與該第二消除信號。 The method of claim 19, further comprising: adding a plurality of cancellation signals to generate a first interference cancellation signal, wherein the plurality of cancellation signals include the first cancellation signal and the second cancellation signal. 如第20項所述之方法，還包含有：將該第一干擾消除信號由該第二定義域轉換至該第一定義域；對該第一干擾消除信號予以進行混疊的反向處理；以及 對該第一干擾消除信號予以進行分群的反向處理。 The method of claim 20, further comprising: converting the first interference cancellation signal from the second domain to the first domain; and performing inverse processing of the first interference cancellation signal; as well as The first interference cancellation signal is subjected to group inverse processing. 如第17項所述之方法，其中該第一定義域與該第二定義域間的轉換運算的大小係依據該第一干擾信號的特性而定。 The method of claim 17, wherein the size of the conversion operation between the first domain and the second domain is dependent on the characteristics of the first interference signal. 如第17項所述之方法，其中該第一定義域與該第二定義域間的轉換運算的大小係小於該第一干擾信號於該第二定義域中最長預定信號的處理長度。 The method of claim 17, wherein the size of the conversion operation between the first domain and the second domain is less than the processing length of the longest predetermined signal of the first interference signal in the second domain. 如第17項所述之方法，其中該第一定義域與該第二定義域間的轉換運算的大小係等於2N ，N為一正整數。The method of item 17, wherein the size of the conversion operation between the first domain and the second domain is equal to 2 N , and N is a positive integer. 如第19項所述之方法，其係應用於一乙太網路系統。 The method of claim 19, which is applied to an Ethernet system. 一種干擾消除裝置，用來依據一輸入信號產生一干擾估測結果，該裝置包含有：一第一定義域處理模組，包含有一增益控制模組或一整形電路之至少其一，係分別用以對該輸入信號予以進行增益調整或整形處理，以產生一經處理的信號；一轉換模組，耦接於該第一定義域處理模組，用來將該經處理的信號由第一定義域轉換至一第二定義域以產生一經轉換的信號；以及一第二定義域處理模組，耦接於該轉換模組，用來依據該經轉 換的信號產生該干擾估測結果；其中該第一定義域處理模組係為一時間域處理模組，且該第二定義域處理模組係為一頻率域處理模組。 An interference cancellation device for generating an interference estimation result according to an input signal, the device comprising: a first domain processing module, comprising at least one of a gain control module or a shaping circuit, respectively The input signal is subjected to gain adjustment or shaping processing to generate a processed signal; a conversion module is coupled to the first domain processing module for using the processed signal by the first domain Converting to a second domain to generate a converted signal; and a second domain processing module coupled to the converter module for The converted signal generates the interference estimation result; wherein the first domain processing module is a time domain processing module, and the second domain processing module is a frequency domain processing module. 如第26項所述之裝置，其中該第一定義域處理模組另包含有：一分群電路，用以接收該輸入信號，並將該輸入信號分成複數個第一子資料。 The device of claim 26, wherein the first domain processing module further comprises: a grouping circuit for receiving the input signal and dividing the input signal into a plurality of first sub-data. 如第27項所述之裝置，其中該轉換模組係將該複數個第一子資料轉換成複數個轉換子資料。 The device of claim 27, wherein the conversion module converts the plurality of first sub-data into a plurality of conversion sub-data. 如第26項或第27項所述之裝置，其中該第一定義域處理模組另包含有：一混疊電路，用以接收該複數個第一子資料，並予以進行混疊。 The device of claim 26, wherein the first domain processing module further comprises: an aliasing circuit for receiving the plurality of first sub-data and performing aliasing. 如第26項所述之裝置，其係應用於一乙太網路系統。 The device of item 26, which is applied to an Ethernet system. 如第30項所述之裝置，其係應用於10GBase-T系統或1000Base-T系統。 The device according to item 30 is applied to a 10GBase-T system or a 1000Base-T system. 如第26項所述之裝置，其中該輸入信號在經過整形處理後之頻率分布較未經整形處理之該輸入信號的頻率分布來得較接近於該干擾估測結果的頻率分布。 The device of claim 26, wherein the frequency distribution of the input signal after the shaping process is closer to the frequency distribution of the interference estimation result than the frequency distribution of the input signal that is not shaped. 一種干擾消除方法，用來依據一輸入信號產生一干擾估測結果，該方法包含有：於一第一定義域，對該輸入信號予以進行增益調整或整形處理之至少其一，以產生一經處理的信號；對該經處理的信號由該第一定義域轉換至一第二定義域以產生一經轉換的信號；以及於該第二定義域，對該經轉換的信號進行一第二定義域上的處理，以產生該干擾估測結果；其中該第一定義域係為時間域，而該第二定義域係為頻率域。 An interference cancellation method for generating an interference estimation result according to an input signal, the method comprising: performing at least one of gain adjustment or shaping processing on the input signal in a first domain to generate a processed a signal; the processed signal is converted by the first domain to a second domain to generate a converted signal; and in the second domain, the converted signal is subjected to a second domain Processing to generate the interference estimation result; wherein the first domain is a time domain and the second domain is a frequency domain. 如第33項所述之方法，其中該於一第一定義域下之步驟，更包含有：對該輸入信號進行一分群的處理以分成複數個第一子資料。 The method of claim 33, wherein the step of the first domain further comprises: performing a grouping process on the input signal to divide into a plurality of first sub-data. 如第33項所述之方法，其中該於一第一定義域下之步驟，更包含有：對該複數個第一子資料予以進行一混疊的處理。 The method of claim 33, wherein the step of the first domain further comprises: performing an aliasing process on the plurality of first sub-data. 如第33項所述之方法，其係應用於乙太網路系統。 The method of item 33, which is applied to an Ethernet system. 如第36項所述之方法，其係應用於10GBase-T系統或1000Base-T系統。 The method of item 36, which is applied to a 10GBase-T system or a 1000Base-T system. 如第33項所述之方法，其中該輸入信號在經過整形處理後之頻率分布，會較未經整形處理之該輸入信號的頻率分布來得較接近於該干擾估測結果的頻率分布。 The method of claim 33, wherein the frequency distribution of the input signal after the shaping process is closer to the frequency distribution of the interference estimation result than the frequency distribution of the input signal without the shaping process. 如第33項所述之方法，其中該對該經處理的信號由該第一定義域轉換至一第二定義域之步驟係為將該複數個第一子資料轉換成複數個轉換子資料。 The method of claim 33, wherein the step of converting the processed signal from the first domain to the second domain is to convert the plurality of first sub-data into a plurality of conversion sub-data. 一種干擾消除裝置，用來依據一輸入信號產生一干擾估測結果，該裝置包含有：一第一定義域處理模組，包含有一分群電路，用以接收該輸入信號，並將該輸入信號進行分群以產生一經處理的信號；一轉換模組，耦接於該第一定義域處理模組，用來將該經處理的信號由第一定義域轉換至一第二定義域以產生一經轉換的信號；以及一第二定義域處理模組，耦接於該轉換模組，用來依據該經轉換的信號產生該干擾估測結果；其中該第一定義域處理模組係為一時間域處理模組，且該第二定義域處理模組係為一頻率域處理模組。 An interference cancellation device for generating an interference estimation result according to an input signal, the device comprising: a first domain processing module, including a grouping circuit for receiving the input signal, and performing the input signal Segmenting to generate a processed signal; a conversion module coupled to the first domain processing module for converting the processed signal from the first domain to a second domain to generate a converted And the second domain processing module is coupled to the conversion module, and configured to generate the interference estimation result according to the converted signal; wherein the first domain processing module is a time domain processing The module, and the second domain processing module is a frequency domain processing module. 如第40項所述之裝置，其中該第一定義域處理模組另包含有一增益控制模組或一整形電路之至少其一，係分別用以對該輸入信號予以進行增益調整或整形處理。The device of claim 40, wherein the first domain processing module further comprises at least one of a gain control module or a shaping circuit for performing gain adjustment or shaping processing on the input signal.
TW096138675A 2007-10-16 2007-10-16 Method and apparatus for canceling channel interference TWI385941B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW096138675A TWI385941B (en) 2007-10-16 2007-10-16 Method and apparatus for canceling channel interference
US12/250,528 US7933196B2 (en) 2007-10-16 2008-10-13 Method and apparatus for canceling channel interference

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW096138675A TWI385941B (en) 2007-10-16 2007-10-16 Method and apparatus for canceling channel interference

Publications (2)

Publication Number Publication Date
TW200919994A TW200919994A (en) 2009-05-01
TWI385941B true TWI385941B (en) 2013-02-11

Family

ID=40534091

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096138675A TWI385941B (en) 2007-10-16 2007-10-16 Method and apparatus for canceling channel interference

Country Status (2)

Country Link
US (1) US7933196B2 (en)
TW (1) TWI385941B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10476631B2 (en) * 2017-01-18 2019-11-12 Cable Television Laboratories, Inc. Systems and methods for multi-carrier signal echo management using pseudo-extensions
US11863366B2 (en) 2017-01-18 2024-01-02 Cable Television Laboratories, Inc. Systems and methods for OFDM duobinary transmission

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200423650A (en) * 2003-03-03 2004-11-01 Interdigital Tech Corp Multi user detection using equalization and successive interference cancellation
TW200729804A (en) * 2005-08-22 2007-08-01 Qualcomm Inc Reverse link interference cancellation
TW200737858A (en) * 2006-02-03 2007-10-01 Qualcomm Inc Baseband transmitter self-jamming and intermodulation cancellation device

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9522737D0 (en) * 1995-11-07 1996-01-10 West End System Corp Noise cancellation in twisted pairs
US6477200B1 (en) * 1998-11-09 2002-11-05 Broadcom Corporation Multi-pair gigabit ethernet transceiver
GB9929442D0 (en) * 1999-12-13 2000-02-09 Element 14 Inc Interference cancellaton equipment
JP3389240B2 (en) * 1999-12-21 2003-03-24 松下電器産業株式会社 Plasma display panel and method of manufacturing the same
WO2001084736A1 (en) * 2000-04-28 2001-11-08 Massana Research Limited Echo and crosstalk cancellation
US20040213354A1 (en) * 2003-04-28 2004-10-28 Jones William W. Mixed domain cancellation
US7002897B2 (en) 2003-04-28 2006-02-21 Solarflare Communications, Inc. Multiple channel interference cancellation
US7227883B2 (en) 2003-10-28 2007-06-05 Teranetics, Inc. Method and apparatus for domain transformation multiple signal processing
US7471670B1 (en) * 2004-01-20 2008-12-30 Marvell International Ltd. Method and apparatus for reducing echo and crosstalk in a communication system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200423650A (en) * 2003-03-03 2004-11-01 Interdigital Tech Corp Multi user detection using equalization and successive interference cancellation
TW200729804A (en) * 2005-08-22 2007-08-01 Qualcomm Inc Reverse link interference cancellation
TW200737858A (en) * 2006-02-03 2007-10-01 Qualcomm Inc Baseband transmitter self-jamming and intermodulation cancellation device

Also Published As

Publication number Publication date
US20090097394A1 (en) 2009-04-16
TW200919994A (en) 2009-05-01
US7933196B2 (en) 2011-04-26

Similar Documents

Publication Publication Date Title
US7590077B2 (en) Canceller device and data transmission system
US8804794B2 (en) Adjustable latency transceiver processing
CN106936407B (en) Frequency domain block least mean square adaptive filtering method
US6829296B1 (en) Spectrally flat time domain equalizer and methods
US20100142604A1 (en) Method and apparatus of frequency domain echo canceller
CN113541733B (en) Equalization and echo cancellation device, method, computer device and storage medium
CN101471694A (en) Device and method for eliminating interference
TWI385941B (en) Method and apparatus for canceling channel interference
TWI360305B (en) Sub-block domain transformation multiple signal pr
CN111835383B (en) Echo and near-end crosstalk elimination system
US7327808B2 (en) Pipelined adaptive decision feedback equalizer
TWI237789B (en) Predicated parallel branch slicer and corresponding method
JP4324676B2 (en) Adaptive filter
TWI733488B (en) Signal processing circuit in digital domain and method thereof
TWI793486B (en) Echo cancellation device and echo cancellation method thereof applied in communication device
TWI435575B (en) Receiver and method for equalizing received signal
CN108322410B (en) Time domain equalizer and signal processing method thereof
WO2012104828A1 (en) A method and apparatus for hierarchical adaptive filtering
Chen et al. Cost-effective echo and NEXT canceller designs for 10GBASE-T ethernet system
TW202301846A (en) Method of configuring equalizers
Chen et al. Low-complexity echo and NEXT cancellers for high-speed ethernet transceivers
CN116935910A (en) Signal processing method and device for memory system interface circuit
KR100519317B1 (en) Method for frequency domain equalizer
Nongpiur et al. Application of NLMS, PNLMS, and i-PNLMS algorithms for NEXT cancellation in xDSL systems
Chen et al. Cost-effective joint echo-NEXT canceller designs for 10GBase-T ethernet systems based on a shortened impulse response filter (SIRF) scheme