TWI237789B

TWI237789B - Predicated parallel branch slicer and corresponding method

Info

Publication number: TWI237789B
Application number: TW92107344A
Authority: TW
Inventors: Meng-Da Yang; An-Yeu Wu; Murphy Chen
Original assignee: Via Tech Inc
Priority date: 2003-04-01
Filing date: 2003-04-01
Publication date: 2005-08-11
Also published as: TW200421181A

Abstract

A predicated parallel branch slicer (the present slicer) and a method of using the same, both are adapted to an adaptive decision feedback equalizer. The present slicer has M<n> adders, M<n> simple slicers, a multiplexer and n delay-units in series. The method has the following steps: M<n> adders receive a common signal and M<n> predetermined values respectively, and then producing M<n> output signals by adding operation; M<n> simple slicer receive the output signals respectively, and then producing M<n> quantum signals with M levels; the multiplexer receive the quantum signals; the n delay units receive the outputting signals of the multiplexer and then produce n choose signals with different delay-period to the multiplexer; finial, one of the quantum signals received by the multiplexer is output.

Description

1237789 五、發明說明（1) ’X明所屬之技術領域本案係為一種預測並行分支量階器與量階方法，尤指應用於一可調適性決定反饋等化器中之預測並行分支量階器與量階方法先前技術近年來’國際電子電機工程師學會（IEEE)訂定了十億位元乙太網路（Gigabit Ethernet)的傳輸標準。在此一傳輸標準中’利用不具遮蔽之雙絞纜線—第五類（Unshield1237789 V. Description of the invention (1) The technical field to which X Ming belongs belongs to a predictive parallel branch scaler and a scale method, especially a predictive parallel branch scale used in an adaptive decision feedback equalizer. Device and Ordering Method Prior Art In recent years, the International Institute of Electronic and Electrical Engineers (IEEE) has established a transmission standard for Gigabit Ethernet. In this transmission standard, ‘the use of unshielded twisted-pair cables—type 5 (Unshield

Twisted Pair-Category 5，UTP-CAT5)傳輸線中的四條線來傳送每秒十億位元的資料。而為能符合如此快速的傳輸速率’每個網路節點之傳送接收器（transceiver)必須克服符碼間干擾（Inter-Symbol Interference，ISI)、回聲 (Echo)、近端串音（Near-end Cross Talk，NEXT)及遠端串音（Far-end Cross Talk，FEXT)等現象所造成之雜訊。請參見第一圖（a )，其係十億位元乙太網路中一網路節點之傳送接收器（t r ansce i ve r )之功能方塊示意圖，其中於信號接收路徑上，係為將一類比信號經過不具遮蔽之雙絞鏡線-第五類（Unshield Twisted Pair - Category 5， UTP-CAT5)傳輸線10、混合器（hybrid)ll、類比前端 (Analog Front End，AFE)12 與類比數位轉換器（Analog -to-Digital Converter，ADC)13 之處理後，形成一僅具有Twisted Pair-Category 5, (UTP-CAT5) four of the transmission lines to transmit gigabits of data per second. In order to comply with such a fast transmission rate, the transmitting receiver of each network node must overcome Inter-Symbol Interference (ISI), echo (Echo), and near-end Noise caused by phenomena such as Cross Talk (NEXT) and Far-end Cross Talk (FEXT). Please refer to the first diagram (a), which is a functional block diagram of a transmission receiver (tr ansce ve r) of a network node in a billion-bit Ethernet network. In the signal receiving path, it is a An analog signal passes through an unshielded twisted-pair mirror line-Category 5 (Unshield Twisted Pair-Category 5, UTP-CAT5) transmission line 10, hybrid (ll), analog front end (AFE) 12 and analog digital After the converter (Analog-to-Digital Converter, ADC) 13 is processed,

12377891237789

付碼間干擾現象（Inter-Symbol Interference，ISI)之數位資料信號x (η )(遠端串音可被忽略）而送入後續之可調適性決定反饋等化器（Adaptive Decision Feedback Equalizer ，ADFE)16進行處理，藉以去除該符碼間干擾現象後，再送入後段之解碼器（dec〇der)17、封包與資訊胞交換器（Packet and Cell Switch，PCS)18與媒體存取控制器（Medium Access Controller)19進行處理，最後將則將處理完成之數位資料送至網路節點本身（本例為一個人電腦20)。並且，封包與資訊包交換器18也會輸出一些訊號，並分別經由一可調適性回聲消除裝置（Adaptive Echo Cancel ler) 14與一可調適性近端串音消除裝置 (Adaptive NEXT Canceller)15而被送至可調適性決定反饋等化器16。而第一圖（b)係表示出一數位資料信號x(n) 之通道脈衝響應波形示意圖，其中虛線之左側通常被稱為前段符碼間干擾（Precursor ISI)，而虛線之右側則被稱為後段符碼間干擾（Postcursor ISI)。再请參見第二圖（a)，其係第一種習用可調適性決定反饋等化器1 6之功能方塊示意圖，其主要係由前饋等化器 21(Feed Forward Equalizer，FFE)與反饋等化器 22(FeedInter-Symbol Interference (ISI) digital data signal x (η) (far-end crosstalk can be ignored) and sent to the subsequent adaptive decision feedback equalizer (ADFE ) 16 to remove the inter-symbol interference phenomenon, and then send it to the decoder (decOder) 17, packet and cell switch (PCS) 18 and media access controller ( Medium Access Controller) 19 for processing, and finally sends the processed digital data to the network node itself (a personal computer 20 in this example). In addition, the packet and packet switch 18 also outputs some signals, and passes through an adaptive echo cancellation device (Adaptive Echo Canler) 14 and an adaptive near-end crosstalk cancellation device (Adaptive NEXT Canceller) 15 respectively. It is sent to the adaptability decision feedback equalizer 16. The first figure (b) is a schematic diagram of the channel impulse response waveform of a digital data signal x (n). The left side of the dotted line is usually called Precursor ISI, and the right side of the dotted line is called It is the post-symbol interference (Postcursor ISI). Please refer to the second figure (a), which is a functional block diagram of the first conventional adaptability determination feedback equalizer 16, which is mainly composed of the feed forward equalizer 21 (Feed Forward Equalizer, FFE) and feedback Equalizer 22 (Feed

Back Equalizer，FBE)來完成，前饋等化器21與反饋等化器2 2之主要功能係分別用以消除前段符碼間干擾 (Precursor ISI)與後段符碼間干擾（p〇stcursor ISI)，而前饋等化器21與反饋等化器22之係數係分別由第一係數更新器2 3與第二係數更新器2 4根據誤差信號e (n )與其本身Back Equalizer (FBE), the main functions of feedforward equalizer 21 and feedback equalizer 22 are to eliminate the pre-symbol interference (Precursor ISI) and the post-symbol interference (P0stcursor ISI). The coefficients of the feedforward equalizer 21 and the feedback equalizer 22 are respectively determined by the first coefficient updater 23 and the second coefficient updater 24 according to the error signal e (n) and itself.

1237789 五、發明說明（3) 之舊值荨資料來運异出新值以進行更新，至於量階器2 5則將信號y (η)量階化後得回數位資料信號d (n)。而此可調適性决疋反饋荨化1 6主要係執行一最小均方演算法 (Least-Mean-Square Algorithm，LMS 演算法），下列式子係表示出各信號與係數間之數學關係。 y(n)= - k)wk(n)- Y^d{n-k)fk{n) Λ-〇 jui 咖=Q[洲办)=办)-咖 ^k{n + \)-wk{n)+ ^x(n-k)e(n) Λ(^ + !)= Λ(«)+ // d{n - k)e(n) 而上述之可調適性決定反饋等化器1 6之資料處理速度係受限於第二圖（a)所示之決定反饋迴路（Decision Feedback Loop，DLP )之有限頻寬而無法增快，而為能改善此一缺失，管線化處理（pi pel ine)是一不錯的發展方向，於是，如第二圖（b)所示之第二種習用可調適性決定反饋等化器便被發展出來，其詳細内容可參見Naresh R. Shanbhag, Keshab K. Parhi, "Pipelined adaptive DFE architectures using relaxed look-ahead, f, IEEE Trans. Signal Processing, vol. 43, No. 6, pp. 1368-1385，June 1995·，故在此不與贅述。而其與第一種習用技術之主要不同處在於決定反饋迴路（Decision1237789 V. Invention description (3) The old value of the net data is used to transport the new value for updating. As for the scaler 25, the digital data signal d (n) is obtained after the signal y (η) is scaled. The adaptability decision feedback netting 16 mainly implements a Least-Mean-Square Algorithm (LMS algorithm). The following equations show the mathematical relationship between each signal and the coefficient. y (n) =-k) wk (n)-Y ^ d (nk) fk (n) Λ-〇jui coffee = Q (洲办) = 办)-咖啡 ^ k (n + \)-wk (n ) + ^ x (nk) e (n) Λ (^ +!) = Λ («) + // d (n-k) e (n) and the above-mentioned adaptability determines the information of the feedback equalizer 16 The processing speed is limited by the limited bandwidth of the Decision Feedback Loop (DLP) shown in the second figure (a) and cannot be increased. To improve this deficiency, pipeline processing (pi pel ine) Is a good development direction, so, as shown in the second figure (b), the second adaptive adaptability decision feedback equalizer has been developed, and its details can be found in Naresh R. Shanbhag, Keshab K. Parhi , " Pipelined adaptive DFE architectures using relaxed look-ahead, f, IEEE Trans. Signal Processing, vol. 43, No. 6, pp. 1368-1385, June 1995, so I will not repeat them here. The main difference from the first conventional technology is the decision feedback loop.

第9頁 1237789Page 9 1237789

五、發明說明（4)V. Description of the invention (4)

Feedback Loop，DLP )中被額外增加了 η個延遲單元，為求清楚表示，該等η個延遲單元於圖中被晝於反饋等化器 22(Feed Back Equalizer，FBE)之外，但實際上，額外辦加之該等η個延遲單元往往是被安排到反饋等化器22(Fe^ Back Equalizer，FBE)之中，以求把原本反饋等化器22之電路&分為n+1群子電路（即每一群子電路間皆具有一延遲單元），進而可利用該n+1群子電路進行管線化作業，進而提昇整體之處理速度。但如此一來，不當增加的延遲時間將使得反饋等化器22(Feed Back Equalizer，FBE)所看到之波形響應示例圖如第二圖（c )所示，由於額外增加之n個延遲單το，將使得與前η個單位延遲時間有關的後段符碼間干擾（Postcursor ISI)被限制於零（如箭頭所指處），造成反饋等化器22(Feed Back Equalizer，FBE)無法正確地運作而使得系統整體之訊噪比將大幅縮減。因此，雖然上述方法可使反饋等化器22得以進行管線化運作而讓處理速度，加，卻也使得系統整體之訊嗓比將大幅縮減而導致信，品質下降，為能解決不當增加的延遲時間所造成之問題’此習用技術手段中之前饋等化器21(Fee(i Forward Equalizer ’FFE)必須相對應進行設計變更來進行補償，Feedback Loop (DLP) is added with an additional η delay unit. For clarity, these η delay units are outside the Feed Back Equalizer (FBE) in the figure, but actually In addition, these n delay units are often arranged in the feedback equalizer 22 (Fe ^ Back Equalizer, FBE), in order to divide the circuit & of the original feedback equalizer 22 into n + 1 groups. Sub-circuits (that is, there is a delay unit between each group of sub-circuits), and the n + 1 group of sub-circuits can be used for pipeline operations, thereby improving the overall processing speed. But in this way, the improperly increased delay time will make the waveform response example shown in the feedback equalizer 22 (Feed Back Equalizer, FBE) as shown in the second figure (c). το, will make the post-symbol interference (Postcursor ISI) related to the first η unit delay time be limited to zero (as indicated by the arrow), causing the feedback equalizer 22 (Feed Back Equalizer, FBE) to be incorrect The overall signal-to-noise ratio of the system will be greatly reduced due to operation. Therefore, although the above method enables the feedback equalizer 22 to perform pipelined operation and increase processing speed, it also makes the overall system's signal-to-voice ratio significantly reduced, leading to a decrease in letter and quality. In order to solve the undue increase in delay, The problem caused by time 'Fee (i Forward Equalizer' FFE) in this conventional technical means must be designed to compensate accordingly,

仁如此將使得月ί〗饋等化器2i(Feed Forward Equalizer， FFE)之電路更為複雜，而且還是無法完全解決信號品質下降之問題。發明内容This will make the circuit of the Feed Forward Equalizer (FFE) 2i more complex, and it will still not completely solve the problem of signal quality degradation. Summary of the Invention

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有鑑於上述之習知技術缺失’進而發展出一具有高訊噪元乙太網路需求之可調適性決案之主要目的。失’為能徹底改善上述缺比且處理速度可符合十億位定反饋等化器，係為發展本本案係為一種預測並行分支量階器，應用於一性決定反饋等化器中’該預測並行分支量階器包：次方個固定係數的加法器’其係共同接收一待處理的: 及分別接收相對應之Μ的n次方個預設值後，分別進〜運算後得致Μ的η次方個輸出信號，而Μ為大於丨之整數·ϋ/In view of the above-mentioned lack of conventional technology, the main purpose of developing an adaptability solution with high noise and Ethernet network requirements has been developed. "Missing" is an equalizer that can completely improve the above-mentioned deficiency ratio and the processing speed can meet the 1 billion bit constant feedback equalizer. It is to develop this case as a predictive parallel branch quantizer, which is applied to the univariate feedback equalizer. Predictive Parallel Branch Scaler Package: The adders with fixed coefficients of the power of three are collectively receiving a to-be-processed: and the n preset powers of the corresponding M are respectively received, and then obtained by ~ The output signal of η to the power of M, and M is an integer greater than 丨 ϋ /

的η次方個量階器，分別信號連接至該等加法器，其係’八別接收並處理該等輸出信號，進而分別輸出Μ的11次方個刀且 ^的^欠方階準位之量階化信號；—第—多工器，信號連接至該Μ的η次方個量階器，其係用以接收該等量階化信號，以及串接之η個延遲單元，信號連接至該第一多工器，其係接收該第一多工器之輸出信號而相對應產生11個不同延遲時間之選擇信號輸至該第一多工器，進而選出該第一多工器所接收之該等量階化信號中之一予以輸出。根據上述構想，本案所述之預測並行分支量階器，其The η-th power scaler is connected to the adders respectively, which is used to receive and process the output signals, and then output the 11th power of M and the ^ -negative level of ^ The quantizer signal;-the first multiplexer, the signal is connected to the η-th power quantizer, which is used to receive the quantized signal, and the η delay units connected in series, the signal connection To the first multiplexer, it receives the output signal of the first multiplexer and correspondingly generates 11 selection signals with different delay times to the first multiplexer, and then selects the first multiplexer. One of the received quantized signals is output. According to the above idea, the predictive parallel branch quantizer described in this case, which

中更包含一第二多工器，信號連接至該Μ的η次方個量階器與串接之η個延遲單元，其係用以接收該等量階器所分別輸出之Μ的η次方個誤差信號，並根據串接之^個延遲單元所輸之該選擇信號，選出所接收之該等誤差信號中之一予以輸出。The middle multiplexer includes a second multiplexer, and the signal is connected to the η-th power scaler of the M and the η delay units connected in series, which are used to receive the η-th power of the M outputted by the power scaler respectively. Square an error signal, and select one of the received error signals for output according to the selection signal input by the ^ delay units connected in series.

第11頁 1237789 五、發明說明（6) 本案之另一方面係為一種預測並行分支量階方法，應用於一可调適性決定反饋等化器中，該方法包含下列步驟·接收一待處理信號以及Μ的η次方個預設值後，分別進行加法運算後得致Μ的η次方個輸出信號，而μ為大於1之整數；分別接收並對該等輸出信號進行量階化處理，進而分別輸出Μ的η次方個具有μ的Ν次方階準位之量階化信號；以及根據η個不同延遲時間之選擇信號而於該等量階化信號中擇一輸出。 ~ 根據上述構想，本案所述之預測並行分支量階方法，其中更包含下列步驟：分別接收並對該等輸出信號進行量階化處理’進而分別輸出Μ的η次方個誤差信號；以及根據 η個不同延遲時間之選擇信號而於該等誤差信號中擇一輸出。與習知技術相比較，本發明一方面透過額外增加的η 個L遲單元使彳寸反饋等化器可進行管線化操作，達到使得處理速度增加之目的；另一方面透過使用特殊設計之可預 ’貝J並行分支量階器3 〇來使得系統整體之訊噪比維持在一定水準而不影響信號品質太多；並且所使用之電路的複雜度亦在$制範圍内（基本上僅增設一些量階器與多工器）。如此確實可以有效改善習用手段之缺失，進而達成發展之主要目的。實施方式Page 11 1237789 V. Description of the invention (6) Another aspect of this case is a method for predicting parallel branch magnitude, which is applied to an adaptive decision feedback equalizer. The method includes the following steps: receiving a signal to be processed After the preset values of η to the power of M, the output signals of η to the power of M are obtained after the addition operations, respectively, and μ is an integer greater than 1; the output signals are received and quantized respectively. Furthermore, output the quantized signals of the nth power of N and the nth power level of μ respectively; and select one of the quantized signals according to the selection signals of n different delay times. ~ According to the above conception, the predictive parallel branch ordering method described in this case further includes the following steps: receiving and ordering the output signals separately, and then outputting the error signal of the nth power of M; and n selection signals with different delay times are output from one of the error signals. Compared with the conventional technology, the present invention enables the 操作 inch feedback equalizer to perform pipelined operation through the additional η L-latency units on the one hand, and achieves the purpose of increasing the processing speed; on the other hand, by using a special design, Pre-J parallel branch scaler 30 to keep the overall signal-to-noise ratio of the system at a certain level without affecting the signal quality too much; and the complexity of the circuit used is also in the range of $ (basically only additional Some scalers and multiplexers). This can indeed effectively improve the lack of customary means, and thus achieve the main purpose of development. Implementation

麵第12頁Noodles page 12

1237789 五、發明說明（7) 請參見第三圖，其係本案所發展出之可調適性決定反饋等化器功能方塊示意圖，其主要係以一預測並行分支量階器 30(Predicted Parallel Branch Slicer)來取代習用手段中單純之量階器，進而可使額外增加之η個延遲單元 3 6不致影響系統之訊噪比。為能較清楚了解本案之技術精神，請先參見第四圖（a)(b)(c)(d)，其係IEEE所訂定之十億位元乙太網路傳輸標準中，於不同長度（分別為25、 50、75及100公尺）之不具遮蔽之雙絞纜線—第五類 (Unshield Twisted Pair-Category 5，UTP-CAT5)傳輸線上所測得之通道脈衝響應（channel impulse response)之波形示意圖，而由圖中吾人可觀察出，其波形隨傳輸線長度之增加雖有變化但並不太大，於是吾人便可根據所觀察到之波形，預先設定出不為〇之η個固定值係數，用以模擬通道與前饋等化器31組合後之響應波形（即反饋等化器22 (Feed Back Equalizer，FBE)所看到之波形）的前η個係數。接著我們固定FBF的前η項係數，並使用LMS演算法得到其餘的等化器係數。靠著這樣前n項的p〇st —curs〇r ISI 將會被FBF前η個固定係數所消除（這個部份的硬體稍後會被轉換成預測並行分支量階器，3〇)，剩下的p〇st —curs〇f ISI會被FBF後面可調適的係數，32,所消除。例如，當n = 2，固定值係數分別為C1、。時，反饋等化器22(Feed1237789 V. Description of the invention (7) Please refer to the third figure, which is a functional block diagram of the adaptability decision feedback equalizer developed in this case. It mainly uses a predictive parallel branch slicer 30 (Predicted Parallel Branch Slicer). ) To replace the simple scaler in the conventional method, so that the additional n delay units 36 can not affect the signal-to-noise ratio of the system. For a clearer understanding of the technical spirit of this case, please refer to the fourth figure (a) (b) (c) (d), which is a billion-bit Ethernet transmission standard set by the IEEE in different lengths. (Unshielded Twisted Pair-Category 5 (UTP-CAT5) transmission line of unshielded twisted pair cables (25, 50, 75, and 100 meters respectively)-channel impulse response measured on the transmission line ), And we can observe from the figure that although the waveform changes with the increase of the length of the transmission line, it is not too big, so we can set η that is not 0 in advance according to the observed waveform. The fixed-value coefficients are used to simulate the first n coefficients of the response waveform (that is, the waveform seen by the Feedback Back Equalizer (FBE)) after the channel is combined with the feedforward equalizer 31. Then we fix the coefficients of the first η term of the FBF and use the LMS algorithm to obtain the remaining equalizer coefficients. Relying on the first n terms of p0st-curs〇r ISI will be eliminated by the first n fixed coefficients of FBF (the hardware of this part will be converted to a predictive parallel branch scaler later, 3), The remaining p0st —curs0f ISI will be eliminated by an adjustable coefficient behind the FBF, 32. For example, when n = 2, the fixed value coefficients are C1, respectively. , The feedback equalizer 22 (Feed

Blc^mzer，FBE)所看到之波形便如第五圖所示，前 %到、-1ΐ分接近最佳化的結果。靠著這樣做我們可以付到-個非常接近最佳化結果的等化器係數，然、而因為習The waveform seen by Blc ^ mzer (FBE) is shown in the fifth figure, and the first% to and -1ΐ are close to the optimized result. By doing this we can pay an equalizer coefficient that is very close to the optimization result, but because

1237789 五、發明說明（8) "" — 用技術2中必須將FBF中的前η個係數固定為零，可是最佳化=别η項係數並不為零因此會造成訊雜比的大量損失，因靠著我們的做法可以大幅改善習用手段中訊噪比過低之缺失。接著我們必須再將前Ν個固定係數的等化器轉換成並行刀支Ϊ階态，3 0，去管線化F B F。其詳細說明如下所示：再凊參見第六圖（a)，其係本案針對η = 2而信號χ(η)為五個準位（例如_2, ―1，〇,丨，2)之脈波振幅調變信號（pulse a^li^ude modulation，PAM)時所發展出關於預測並行分支置階器3 0内部之功能方塊示意圖，其中主要係由2 5 ( 5 的2次方）個加法器60與25個量階器61所構成之並行分支來組成。其中每個加法器60之輸入端所接收之值β丁，其係為最佳化係數Ve=[Cl，C2]與先前兩階信號之準位值T=[a(n — 1 )，a(n-2)]之乘積，而τ於五個準位之情況下便有25種可能之排列，相對地，於決定反饋迴路中便可額外增加兩個延遲單元62、63以供運用。而由圖中可清楚看出，前饋等化器 31(Feed Forward Equalizer，FFE)所輸出之信號 b (η)係分別於25種可能之信號組合值νςτ預先進行加法^算與量階化，進而得出25種可能之量階化資料信號d及相對應之誤差信號e，以分別輸出至兩個25-to〜i之多工器64、 65以供選擇。而選擇之原則便分別視兩個延遲單元w 之輸出x(n-1)，χ(η-2)為25種可能之排列中之何者。至、該等兩個延遲單元62、63便可安排至反饋等化"器32内，& 而把原本反饋等化器32之電路可區分為三群子電路以進行1237789 V. Description of the invention (8) — In technology 2, the first η coefficients in the FBF must be fixed to zero, but optimization = the coefficients of other η terms are not zero, which will cause the signal-to-noise ratio. A large amount of losses, because our approach can greatly improve the lack of low signal-to-noise ratio in conventional methods. Then we must convert the equalizers of the first N fixed coefficients to the parallel knife-and-chief unitary state, 30, and de-pipeline F B F. The detailed description is as follows: Again, referring to the sixth figure (a), this case is for η = 2 and the signal χ (η) is five levels (for example, _2, -1, 0, 丨, 2). Pulse block modulation signal (pulse a ^ li ^ ude modulation, PAM) developed a schematic block diagram of the internal prediction of the parallel branch arbiter 3 0, which is mainly composed of 2 5 (5 to the power of 2) The adder 60 is composed of parallel branches formed by 25 scalers 61. The value β D received by the input of each adder 60 is an optimization coefficient Ve = [Cl, C2] and a level value T = [a (n — 1), a (n-2)], and there are 25 possible arrangements for τ at five levels. In contrast, two delay units 62, 63 can be added to the decision feedback loop for use. It can be clearly seen from the figure that the signal b (η) output by the feed forward equalizer 31 (Feed Forward Equalizer (FFE)) is added in advance at 25 possible signal combination values ντ and calculated in advance. Then, 25 kinds of possible quantization data signals d and corresponding error signals e are obtained to output to two 25-to ~ i multiplexers 64 and 65 for selection. The selection principle depends on the output x (n-1) and χ (η-2) of the two delay units w, respectively, among the 25 possible arrangements. So, the two delay units 62 and 63 can be arranged in the feedback equalizer 32, and the circuit of the original feedback equalizer 32 can be divided into three groups of sub-circuits for

1237789 五、發明說明（9) 管線化運作而讓處理速度增加再睛參見第六圖（b)，其係本案針對n = 3而信號χ(η)為兩個準位（例如-1，1)之脈波振幅調變信號（ρΑΜ)時所發展出關於預測並行分支量階器3 〇内部之功能方塊示意圖，其 =主要係由8 (2的3次方）個固定係數的加法器7〇與8個量階器71所構成之並行分支來組成。其中每個加法器7 〇之輸入 j ^接收之值vJt，其係為最佳化係數Ve = [cl，C2, C3]與先前三階信號之準位值T=[a(n-1)，a(n —2)，a(n —3)]之乘積，而T於兩個準位之情況下便有8種可能之排列，相對地於决疋反饋迴路中便可額外增加三個延遲單元7 2、、74以供運用。而由圖中可清楚看出，前饋等化器31 Equalizer，FFE)所輸出之信號b(n)係分 1 ;種可能之信號組合值\/〗了預先進行加法運算與量 $呈進而得出8種可能之量階化資料信號χ(η)及相對應之號e，以分別輸出至兩個ho-1之多工器75、76以供、擇。而選擇之原則便分別視三個延遲單元？2、 ;輸；x二1i，x(n_2)，x(n-3)為8種可能之排列中之何者。至於該等三個延遲單元72、73、74 17 化器32内，進而把原本反饋等反饋等子電路以推扞其硷仆、蓄从二从之電路可區分為四群卞％路以進仃官線化運作而讓處理速度增加。矸直二上：述僅為本發明之較佳實施例，凡依本發明申& 專利槌圍所做之均等變化與修飾，月申4 蓋範圍。白應屬本發明專利之涵1237789 V. Description of the invention (9) Increased processing speed due to pipelined operation See Figure 6 (b). This case is for n = 3 and the signal χ (η) is two levels (for example, -1, 1 The pulse wave amplitude modulation signal (ρΑΜ) was developed to predict the internal function block diagram of the parallel branch quantizer 3 〇, which is mainly composed of 8 (the third power of 2) adder 7 〇 and 8 scalers 71 are composed of parallel branches. The input j ^ received value vJt of each adder 70 is an optimization coefficient Ve = [cl, C2, C3] and the level value of the previous third-order signal T = [a (n-1) , A (n-2), a (n-3)], and T has two possible permutations in the case of two levels, and three more can be added to the feedback loop Delay units 72, 74 are available for use. And it can be clearly seen from the figure that the signal b (n) output by the feedforward equalizer 31 Equalizer (FFE) is divided into 1; the possible signal combination values \ / 〖have been added in advance and the amount $ was presented Eight possible quantization data signals χ (η) and corresponding numbers e are obtained to output to two ho-1 multiplexers 75 and 76 respectively for selection and selection. And the principle of selection depends on the three delay units? 2 .; Lose; x 2 1i, x (n_2), x (n-3) is one of the 8 possible arrangements. As for the three delay units 72, 73, 74, 17 and 32, and the sub-circuits such as the original feedback and other feedback circuits to push and defend their servants and accumulators can be divided into four groups: Eunuchs operate in line to increase processing speed.矸 Straight up: The description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the invention & patent mallet are covered by the monthly application. Bai Ying belongs to the invention patent

第15頁 1237789 五、發明說明（ίο) 圖式簡單說明本案得藉由下列圖式及詳細說明，俾得更深入了解：第一圖（a ):其係十億位元乙太網路中一網路節點之傳送接收器（transceiver)之功能方塊示意圖。第一圖（b ):其係表示出一數位資料信號χ ( n)之通道脈衝響應波形示意圖第二圖（a ):其係第一種習用可調適性決定反饋等化器之功能方塊不意圖。第二圖（b ):其係第二種習用可調適性決定反饋等化器之功能方塊示意圖。第二圖（c )··其係不當增加的延遲時間所造成波形響應變化之示例圖。第三圖：其係本案所發展出之可調適性決定反饋等化器功能方塊示意圖。第四圖（a)(b)(c)(d):其係IEEE所訂定之十億位元乙太網路傳輸標準中，於不同長度（分別為25、50、75及100公尺）之不具遮蔽之雙絞繞線-第五類（Unshield Twisted Pair-Category 5 ’UTP-CAT5)傳輸線上量測之通道脈衝響應（channel impulse response)波形示意圖。第五圖：其係本案較佳實施例中反饋等化器所看響應變化之示例圖。 / y 第六圖（a) (b):其係本案較佳實施例針對預測並一八階器所發展出之兩種内部功能方塊示意圖。订刀里Page 15 1237789 V. Explanation of the invention (ίο) Schematic description This case can be understood in more depth by the following diagrams and detailed descriptions: The first diagram (a): it is a billion-bit Ethernet network A functional block diagram of a network node's transceiver. The first figure (b): it is a schematic diagram showing the channel impulse response waveform of a digital data signal χ (n). The second figure (a): it is the functional block of the first adaptive adaptability determining feedback equalizer. intention. The second figure (b): it is a functional block diagram of the second conventional adaptive decision feedback equalizer. The second graph (c) is an example of the change in waveform response caused by an improperly increased delay time. The third picture: it is the schematic diagram of the adaptability decision feedback equalizer function developed in this case. The fourth figure (a) (b) (c) (d): It is a billion-bit Ethernet transmission standard stipulated by the IEEE in different lengths (25, 50, 75, and 100 meters, respectively) Unshielded Twisted Pair-Category 5 (UTP-CAT5) transmission line measured channel impulse response waveform diagram. Fifth Figure: This is an example of the response changes seen by the feedback equalizer in the preferred embodiment of the present case. / y Sixth diagram (a) (b): It is a schematic diagram of two internal function blocks developed by the preferred embodiment of the case for prediction and an eighth-order device. Inside the knife

12377891237789

案所揭示之調適性決定反饋等本案圖式中所包含之各元件列示如下·· 不具遮蔽之雙絞纜線—第五類傳輸線J 〇混合器11 類比前端1 2 可調適性回聲消除裝置1 4 可調適性決定反饋等化器1 6 封包與資訊胞交換器i 8 個人電腦2 〇反饋等化器2 2 第二係數更新器2 4 η個延遲單元26 反饋等化器3 2 第二係數更新器3 4 η個延遲單元36 量階器6 1 多工器64 、65 量階器7 1 多工器75 、類比數位轉換器1 3 可調適性近端串音消除裝置1 5 解碼器1 7 媒體存取控制器1 9 前饋等化器2 1 第一係數更新器2 3 量階器25 前饋等化器3 1 第一係數更新器3 3 預測並行分支量階器3 0 加法器6 0 延遲單元62、63 加法器7 0 延遲單元72、73、74The components included in the plan of this case, such as the adaptation decision feedback disclosed in the case, are listed as follows: · Unshielded twisted-pair cable-Type 5 transmission line J 〇 Mixer 11 Analog front end 1 2 Adjustable adaptive echo cancellation device 1 4 Adjustable adaptability feedback equalizer 1 6 Packet and information cell converter i 8 Personal computer 2 〇 Feedback equalizer 2 2 Second coefficient updater 2 4 n delay units 26 Feedback equalizer 3 2 Second Coefficient updater 3 4 n delay units 36 scaler 6 1 multiplexer 64, 65 scaler 7 1 multiplexer 75, analog digital converter 1 3 adjustable adaptable near-end crosstalk cancellation device 1 5 decoder 1 7 Media Access Controller 1 9 Feedforward Equalizer 2 1 First Coefficient Updater 2 3 Scaler 25 Feedforward Equalizer 3 1 First Coefficient Updater 3 3 Predictive Parallel Branch Scaler 3 0 Addition 6 0 delay units 62, 63 adder 7 0 delay units 72, 73, 74

第17頁 1237789 圖式簡單說明第一圖（a )··其係十億位元乙太網路中一網路節點之傳送接收器（t r a n s c e i v e r )之功能方塊示意圖。第一圖（b):其係表示出一數位資料信號χ(η)之通道脈衝響應波形示意圖第二圖（a):其係第一種習用可調適性決定反饋等化器之功能方塊示意圖。第二圖（b):其係第二種習用可調適性決定反饋等化器之功能方塊示意圖。第二圖（c):其係不當增加的延遲時間所造成波形響應變化之示例圖。Page 17 1237789 Brief description of the diagram The first diagram (a) ... It is a functional block diagram of a transmission receiver (t r a n s c e i v e r) of a network node in a billion-bit Ethernet network. The first diagram (b): it is a schematic diagram showing the channel impulse response waveform of a digital data signal χ (η). The second diagram (a): it is the functional block diagram of the first adaptive adaptability decision equalizer. . The second figure (b): It is a functional block diagram of the second type of adaptive adaptability decision feedback equalizer. The second figure (c): it is an example of the waveform response change caused by improperly increased delay time.

第三圖：其係本案所發展出之可調適性決定反饋等化哭功能方塊示意圖。第四圖（a)(b)(c)(d):其係IEEE所訂定之十億位元乙太網路傳輸標準中，於不同長度（分別為25、50、75及1〇〇公尺）之不具遮蔽之雙絞纔線-第五類（Unshield TwistedThe third picture: it is a schematic block diagram of the adaptive cryback function developed in this case. The fourth figure (a) (b) (c) (d): It is a billion-bit Ethernet transmission standard stipulated by the IEEE in different lengths (25, 50, 75, and 100 km respectively). Ruler) Unshielded Twisted Pair-Category 5 (Unshield Twisted

Pair-Category 5 ’UTP-CAT5)傳輸線上量測之通衝響應（channel impulse response )波开》示意圖。曰第五圖：其係本案較佳實施例中反饋等化考 ▼丨^命所看到之浊开多響應變化之示例圖。胃j ^ π ~Pair-Category 5’UTP-CAT5) Schematic diagram of the channel impulse response measured on the transmission line. Figure 5: This is an example of the response change in the feedback equalization test in the preferred embodiment of this case. Stomach j ^ π ~

第六圖（a)(b):其係本案較佳實施例針對頂測並行去景階器所發展出之兩種内部功能方塊示意圖。叮刀文里第七圖··其係習用手段與本案所揭示之調適性化器的學習曲線比較示意圖。决疋反饋寺Figure 6 (a) (b): It is a schematic diagram of two internal function blocks developed by the preferred embodiment of this case for the top-testing parallel de-viewing device. Dingdao Wenli Figure 7: Comparison of the learning curve between the conventional method and the adaptor disclosed in this case. Jueyu feedback temple

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Claims

1237789 仲1f Μ 案號92107344 年月日修正_ 六、申請專利範圍 1. 一種預測並行分支量階器，應用於一可調適性決定反饋等化器中，該預測並行分支量階器包含： Μ的η次方個加法器，用以共同接收一待處理信號以及分別接收相對應之Μ的η次方個預設值後，分別進行加法運算後得致Μ的η次方個輸出信號，而Μ為大於1之整數； Μ的η次方個量階器，分別一對一地信號連接至該等加法器，用以在分別接收並處理該等輸出信號後，進而分別輸出Μ的η次方個具有Μ的Ν次方階準位之信號；一多工器，信號連接至該Μ的η次方個量階器，用以接收具有Μ的Ν次方階準位之該等信號；以及相互串接之η個延遲單元，信號連接至該多工器，用以接收該多工器之至少一輸出信號而相對應產生η個不同延遲時間之選擇信號輸至該多工器，進而選出該多工器所接收之具有Μ的Ν次方階準位之該等信號之一予以輸出。 2 .如申請專利範圍第1項所述之預測並行分支量階器，該些Μ的η次方個加法器係為具有固定係數的Μ的η次方個加法器。 3 .如申請專利範圍第1項所述之預測並行分支量階器，具有Μ的Ν次方階準位之該等信號至少包含具有Μ的Ν次方階準位之多數資料信號以及相對應之具有Μ的Ν次方階準位之多數誤差信號。 4.如申請專利範圍第1項所述之預測並行分支量階器，其中該多工器係為一第一多工器與一第二多工器之組合，在此該第一多工器與該第二多工器皆分別信號連接至該Μ的η1237789 Zhong 1f Μ Case No. 92107344 Rev. _ Date of patent application 1. A predictive parallel branch scaler is applied to an adaptive decision feedback equalizer. The predictive parallel branch scaler includes: Μ Η-th power adders are used to collectively receive a signal to be processed and to receive the corresponding η-th power preset values of M, respectively, and then perform addition operations to obtain η-th power output signals of M, and M is an integer greater than 1; the nth power scaler of M is connected to the adders one-to-one, respectively, for receiving and processing the output signals respectively, and then outputting n times of M respectively. A signal having an N-th order level of M; a multiplexer, the signal is connected to the n-th order magnituder of the M, for receiving the signals having an N-th order level of M; And n delay units connected in series, the signal is connected to the multiplexer, and is used for receiving at least one output signal of the multiplexer and correspondingly generating η selection signals with different delay times to the multiplexer, and further Select the multiplexer to receive One of order Ν power level of these signals have Μ be the output. 2. The predictive parallel branch quantizer as described in item 1 of the scope of the patent application, wherein the η-th power adders of M are fixed η-th power adders of M. 3. The predictive parallel branch quantizer as described in item 1 of the scope of patent application, the signals having the Nth order level of M include at least most of the data signals with the Nth order level of M and the corresponding Most error signals with N-th order level of M. 4. The predictive parallel branch quantizer according to item 1 of the scope of patent application, wherein the multiplexer is a combination of a first multiplexer and a second multiplexer, and the first multiplexer is here And the second multiplexer are respectively signal-connected to the η of Μ

第19頁 1237789 案號 92107344 Λ_ 曰修正六、申請專利範圍次方個量階器 5.如申請專利有Μ的Ν次方階位之多數資料數誤差信號。 6 .如申請專利範圍第一多工器係接收號以器係之該些資料信而該第二多工準位之該些誤號，並且該弟收，並且該第 7. 如申請專利有Μ的Ν次方階決於該些延遲些信號的何者 8. 如申請專利有Μ的Ν次方階決於該些延遲些資料信號的 9. 如申請專利有Μ的Ν次方階決於該些延遲些誤差信號的與串接之η個延遲單元。範圍第4項所述之預測並行分支量階器，具準位之該等信號至少包含具有Μ的Ν次方階準信號以及相對應之具有Μ的Ν次方階準位之多第5項所述之預測並行分支量階器，該來自該些量階器之具有Μ的Ν次方階準位及來自該些延遲單元之該些選擇信號，接收來自該些量階器之具有Μ的Ν次方階差信號以及來自該些延遲單元之該些選擇信一多工器之輸出會先被該第二多工器所接二多工器會據以產生該些輸出信號。範圍第1項所述之預測並行分支量階器，具準位之該些信號中是何者被選擇輸出，係取單元之輸出最接近具有Μ的Ν次方階準位之該〇範圍第7項所述之預測並行分支量階器，具準位之該些信號中是何者被選擇輸出，係取單元之輸出最接近具有Μ的Ν次方階準位之該何者。範圍第7項所述之預測並行分支量階器，具準位之該些信號中是何者被選擇輸出，係取單元之輸出最接近具有Μ的Ν次方階準位之該何者。 _Page 19 1237789 Case No. 92107344 Λ_ said Amendment 6. Range of patent application Power of order scaler 5. If the patent application has the majority of data of order N of the M number error signal. 6. If the scope of the patent application for the first multiplexer is to receive the information letter of the device and the number of the wrong number of the second multiplex level, and the brother received, and the seventh. The order of the Nth power of M depends on which ones of these signals are delayed. 8. For example, the order of Nth power that has an application for M depends on the data signals that are delayed by 9. The order of Nth power that applies for a patent depends on The n delay units connected in series to delay the error signals. The predictive parallel branch quantizer described in the fourth item of the range, the signals with a level include at least the N-th order signal with M and the corresponding fifth number of the N-th order level with M The predictive parallel branch scaler, the N-th order level with M from the scalers and the selection signals from the delay units receive the M with the M from the scalers. The N-th order variance signal and the selection signals from the delay units. The output of a multiplexer will be generated by the multiplexer connected to the second multiplexer first. The predictive parallel branch quantizer described in the first item of the range, which of the signals with the level is selected to be output, is the output of the unit closest to the 0th level of the 0th level with the M level. In the predictive parallel branch quantizer described in the item, which of the signals with the level is selected to be output is the output of the unit closest to which of the N-th order level with M. The predictive parallel branch quantizer described in item 7 of the range, which of the signals with the potential is selected for output, is the one whose output of the unit is closest to the level of the Nth power with M. _

第20頁 1237789 _案號92107344_年月曰修正_ 六、申請專利範圍 1 0 .如申請專利範圍第1項所述之預測並行分支量階器，對第K個加法器而言，其所接收之預設值係為一 η階最佳化係數與先前η階信號之準位值的乘積，在此Κ為正整數。 1 1 .如申請專利範圍第1 0項所述之預測並行分支量階器，其中上述之η階最佳化係數係為以η個固定係數模擬I ΕΕΕ所制定之十億位元乙太網路傳輸標準之傳輸線上通道脈衝響應之波形時，所得到的η個固定係數。 1 2. —種預測並行分支量階方法，應用於一可調適性決定反饋等化器中，該方法包含下列步驟：跟據通道特性，得到FBF的前η項係數，進而計算出Μ 的η次方個預設值；接收一待處理信號以及Μ的η次方個該些預設值後，分別進行加法運算後得致Μ的η次方個輸出信號，而Μ為大於1之整數；分別接收並對該等輸出信號進行量階化處理，進而分別輸出Μ的η次方個具有Μ的Ν次方階準位之信號；根據Μ的η次方個具有Μ的Ν次方階準位之信號以產生經量階化處理後之一輸出信號；以及根據經量階化處理後之該輸出信號以及η個不同延遲處理，產生η個不同延遲時間之多數選擇信號，進而在該等信號中擇一輸出。 1 3 .如申請專利範圍第1 2項所述之預測並行分支量階方法，係根據於該些延遲單元之輸出最接近具有Μ的Ν次方階準位之該些信號的何者，來決定具有Μ的Ν次方階準位之該Page 20 1237789 _Case No. 92107344_ Year Month Amendment_ VI. Patent Application Range 1 0. The predictive parallel branch quantizer described in item 1 of the patent application range, for the Kth adder, its The received preset value is a product of an n-th order optimization coefficient and a previous level value of the n-th order signal, where K is a positive integer. 1 1. The predictive parallel branch quantizer as described in item 10 of the scope of patent application, wherein the above-mentioned η-order optimization coefficient is a billion-bit Ethernet network formulated by η fixed coefficients to simulate I ΕΕΕ When the waveform of the channel impulse response on the transmission line of the standard transmission channel is obtained, η fixed coefficients are obtained. 1 2. A predictive parallel branch ordering method applied to an adaptability decision feedback equalizer. The method includes the following steps: According to the channel characteristics, the first η term coefficient of the FBF is obtained, and then η of M is calculated. The power is a preset value; after receiving a pending signal and the η-th power of these preset values, performing addition operations respectively to obtain the η-th power output signal of M, and M is an integer greater than 1; Receive and perform quantization processing on these output signals, respectively, and then output signals of the η-th power of M having an N-th order level of M; according to the η-th power of M having an N-th order level of M Bit signal to generate an output signal after quantization processing; and according to the output signal after quantization processing and η different delay processing, to generate a majority selection signal of η different delay times, and then Select one of the signals to output. 1 3. The method of predicting parallel branch magnitudes as described in item 12 of the scope of the patent application is determined based on which of the signals of the delay units is closest to the signals with the Nth power level of M With the N-th order level of M

第21頁 1237789 案號 92107344 曰修正六、申請專利範圍些信號中是何者被選擇輸出。 1 4.如申請專利範圍第1 2項所述之預測並行分支量階方法，其中上述之產生具有Μ的Ν次方階準位之信號，係至少產生具有Μ的Ν次方階準位之多數資料信號以及相對應之具有Μ的Ν次方階準位之多數誤差信號。 1 5 .如申請專利範圍第1 4項所述之預測並行分支量階方法，係根據於該些延遲單元之輸出最接近具有Μ的Ν次方階準位之該些資料信號的何者，來決定具有Μ的Ν次方階準位之該些資料信號中是何者被選擇輸出。 1 6 .如申請專利範圍第1 4項所述之預測並行分支量階方法，係根據於該些延遲單元之輸出最接近具有Μ的Ν次方階準位之該些誤差信號的何者，來決定具有Μ的Ν次方階準位之該些誤差信號中是何者被選擇輸出。 1 7 .如申請專利範圍第1 2項所述之預測並行分支量階方法，所接收到之任一個預設值係為一 η階最佳化係數與先前η階信號之準位值的乘積。 1 8 .如申請專利範圍第1 7項所述之預測並行分支量階方法，其中上述之η階最佳化係數係為以η個固定係數模擬 I Ε Ε Ε所制定之十億位元乙太網路傳輸標準之傳輸線上通道脈衝響應之波形時，所得到的η個固定係數。 1 9 .如申請專利範圍第1 4項所述之預測並行分支量階方法，係先量階化處理具有Μ的Ν次方階準位之該些資料信號與該些選擇信號，再量階化處理具有Μ的Ν次方階準位之該些誤差信號與該些選擇信號，最後再綜合產生產生經量階Page 21 1237789 Case No. 92107344 Amendment 6. Scope of patent application Which of these signals is selected for output. 1 4. The method of predicting parallel branch magnitudes as described in item 12 of the scope of patent application, wherein the above-mentioned signal generating an order with an Nth power level of M is at least an signal having an Nth power level with M Most data signals and corresponding majority error signals with an N-th order level of M. 1 5. The predictive parallel branch ordering method described in item 14 of the scope of the patent application is based on which of the data signals with the output of the delay units closest to the Nth order level of M comes It is determined which of the data signals having the N-th order level of M is selected for output. 16. The predictive parallel branch ordering method described in item 14 of the scope of the patent application is based on which of the error signals whose output of the delay units is closest to the Nth order level of M, It is determined which of the error signals having the Nth order level of M is selected for output. 17. According to the predictive parallel branch ordering method described in item 12 of the scope of patent application, any one of the preset values received is a product of an n-th order optimization coefficient and a previous n-th order signal level value . 18. The method for predicting parallel branch magnitudes as described in item 17 of the scope of patent application, wherein the above-mentioned η-order optimization coefficient is a billion bit B formulated by η fixed coefficients to simulate I Ε Ε Ε Η fixed coefficients obtained when the impulse response waveform of the channel on the transmission line of the Ethernet network. 19. The predictive parallel branch ordering method described in item 14 of the scope of patent application, first ordering the data signals and the selection signals with the Nth order level of M, and then ordering The error signals and the selection signals with the Nth-order level of M are processed, and finally synthesized to generate a magnitude order.

第22頁 1237789 案號 92107344 曰修正六、申請專利範圍化處理後之一輸出信號。 2 0 .如申請專利範圍第1 9項所述之預測並行分支量階方法，在量階化處理具有Μ的N次方階準位之該些誤差信號與該些選擇信號時，也會參考量階化處理具有Μ的Ν次方階準位之該些資料信號與該些選擇信號所產生之結果。Page 22 1237789 Case No. 92107344 said Amendment 6. Output signal after one of the patent application scopes. 20. According to the prediction parallel branch ordering method described in item 19 of the scope of patent application, when the ordering processing of the error signals and the selection signals with the Nth order level of M is also referred, The result of the quantization processing on the data signals and the selection signals having the N-th order level of M.

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