TWI384751B - 可消除直流電壓偏移之運算放大器 - Google Patents
可消除直流電壓偏移之運算放大器 Download PDFInfo
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- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
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- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
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Description
本發明係指一種運算放大器,尤指一種具有直流偏移消除功能的運算放大器。
全差動式運算放大器(Fully differential operational amplifier)廣泛地用於各種高速傳輸應用,如通訊系統、語音及影像資料處理中。常見的全差動式運算放大器是由一輸入級與一輸出級組成,輸入級提供高增益,輸出級則提供足夠的電壓擺幅。請參考第1圖,第1圖為習知一運算放大器10之示意圖。運算放大器10為全差動式運算放大器,由一輸入級11及一A類輸出級12組成。輸入級11包含有p型電晶體MP1~MP4及n型電晶體MN1~MN5,組成四個差動對及一共模回饋(Common mode feedback)電路100,用來產生輸入級11之輸出共模電壓。輸出級12包含有p型電晶體MP6、MP7、n型電晶體MN6、MN7、電容CM1、CM2及一共模回饋電路102。偏壓VBP1、VBP2、VBN1、VBN2、VBN3用於輸入級11及輸出級12中的差動對。輸入級11接收差動輸入訊號INP及INN,並且產生差動輸出訊號VOP及VON;輸出級12接收輸入級11產生之差動輸出訊號,以產生差動輸出訊號OUTP及OUTN。
運算放大器10有以下缺點:輸出級12的互導(Transconductance)很小,並且由於電晶體MP6及MP7的使用,造成寄生極點降低。由於控制電晶體MN6、MN7之閘極的偏壓VBN3固定,電晶體MN6及MN7的吸收電流(Sink current)只能為固定值。此外,輸入級11之輸出共模電壓是由輸出級12之輸入共模電壓而決定,此電路設計容易導致輸入級11的電壓餘量(Headroom)不足,使電晶體MP1~MP4進入三極體(Triode)工作區。輸入級11的輸出共模電壓亦受到製程、供應電源及溫度的影響,其變動範圍可達數百毫伏特。因此,運算放大器10很難於低供應電壓的環境下實現預期的放大效果。
請參考第2圖,第2圖為習知一運算放大器20之示意圖。運算放大器20係2007年發表於ISSCC期刊之論文“A 0.8V 10bit 80MS/s 6.5mW Pipelined ADC with Regulated Overdrive Voltage Biasing”所提出。運算放大器20是由一輸入級21、一AB類輸出級22及一開關電容式電壓轉換電路(Switched capacitor level shifter)23所組成。輸入級21包含有p型電晶體MP1~MP4、n型電晶體MN~MN5及一共模回饋電路200。輸出級22包含有p型電晶體MP6~MP7、n型電晶體MN6~MN9、電容CM1、CM2及一共模回饋電路202。開關電容式電壓轉換電路23由開關S1~S16及電容C1~C8組成,用來將輸入級21與輸出級22進行解耦,因此輸入級21之輸出共模電壓不再根據輸出級22之輸入共模電壓而決定,進而解決電壓餘量可能不足的問題。輸入級21使用偏壓VBP1、VBP2、VBN1及VBN2,開關電容式電壓轉換電路23另外使用了偏壓VBP3、VBN3及VC。
相較於第1圖之運算放大器10,運算放大器20改善了輸入級之電壓餘量不足的問題。然而,運算放大器20仍有不少缺點,舉例來說,開關電容式電壓轉換電路23所需的開關及電容數量很多,對於面積成本而言是一大負擔。輸出級22之共模回饋電路202利用電晶體MN8及MP8做為共模迴路增益放大器,這二個電晶體造成較大的電容性負載,使運算放大器20的頻寬變小,進而使相位邊際(Phase margin)變小,降低了運算放大器20的穩定性。此外,由於開關電容式電壓轉換電路23的存在,運算放大器20只能用於開關電容式電路,如管線式(Pipelined)類比數位轉換器,且需要額外的電路來控制開關S1~S16,而無法用於連續式電路,如主動RC濾波電路。
上述運算放大器10及運算放大器20的應用廣泛,可程式增益放大器(Programmable gain amplifier)即為其中一例。請參考第3圖,第3圖為習知一可程式增益放大器30之示意圖。可程式增益放大器30具有直流偏移消除(DC offset cancellation)功能,常用於需要高增益的系統,如無線通訊系統中。可程式增益放大器30由一運算放大器300、電阻R1~R4、RH1、RH2及電容CH1、CH2所組成,其中運算放大器300可為前述運算放大器10或運算放大器20。電阻RH1、RH2及電容CH1、CH2形成一高通濾波電路,用來消除運算放大器300之差動輸出訊號中的直流電壓偏移。根據第3圖,假設電阻RH1及RH2的阻值為RH
,電容CH1及CH2的容值為CH
,電阻R1及R2的阻值為R1
及R2
,可程式增益放大器30之輸出訊號Vo
對輸入訊號Vi
的轉換函式表示如下:
其中,A表示運算放大器300的增益。當A值很大時,式1簡化如下:
s為複變頻率,高通濾波電路的轉角頻率(Corner frequency)等於1/RH
CH
。
請參考第4圖,第4圖為習知一可程式增益放大器40之示意圖。可程式增益放大器40係以主動積分器的架構實現高通濾波功能,以消除直流偏移。可程式增益放大器40由運算放大器400、402、電阻R1~R6、RH1、RH2及電容CH1、CH2所組成。假設電阻RH1及RH2的阻值為RH
,電容CH1及CH2的容值為CH
,可程式增益放大器40之輸出訊號Vo
對輸入訊號Vi
的轉換函式與上述式1及式2相同。
由上可知,若電路中串接多個可程式增益放大器,其中設於運算放大器外部之直流偏移消除電路的元件數量亦等倍增加,必須耗費大量的電路成本才能達到消除直流電壓偏移之目的。
因此,本發明之主要目的即在於提供一種內建直流偏移消除功能之運算放大器。
本發明揭露一種運算放大器,包含有一輸入級、一輸出級及一高通濾波電路。該輸入級根據一第一差動輸入訊號對,產生一第一差動輸出訊號對。該輸出級根據至少一第二差動輸入訊號對,產生一第二差動輸出訊號對。該高通濾波電路耦接於該輸入級與該輸出級之間,用來對該第一差動輸出訊號對進行高通濾波處理,以產生該至少一第二差動輸入訊號對。
請參考第5圖,第5圖為本發明實施例一運算放大器50之示意圖。運算放大器50包含有一輸入級51、一高通濾波電路52及一輸出級53。輸入級51接收差動輸入訊號INP及INN,並且根據差動輸入訊號INP及INN產生差動輸出訊號VON及VOP。輸出級53根據高通濾波電路52所輸出的訊號,產生差動輸出訊號OUTP及OUTN。高通濾波電路52包含有電容CH1、CH2及電阻RH1、RH2,電容CH1與電阻RH1形成一高通濾波單元,耦接於輸入級51之一負輸出端與輸出級53之一正輸出端之間;電容CH2與電阻RH2形成另一高通濾波單元,耦接於輸入級51之一正輸出端與輸出級53之一負輸入端之間。電阻RH1的一端耦接於電容CH1,另一端耦接於一偏壓VC,電阻RH2的一端耦接於電容CH2,另一端亦耦接於偏壓VC。高通濾波電路52用以濾除差動輸出訊號VON及VOP中的直流成分,因此也消除了訊號中的直流偏移量;同時,偏壓VC將高通濾波電路52所輸出的差動訊號控制在相同的共模電壓上。對輸出級53而言,輸出級53的差動輸入訊號不包含直流偏移,因此運算放大器50相當適用於需要高增益並且對直流電壓偏移敏感的電路,如無線通訊系統所使用的主動RC濾波器及可程式增益放大器。
請參考第6圖,第6圖為本發明實施例一可程式增益放大器60之示意圖,可程式增益放大器60由一運算放大器600及電阻R1~R4所組成。運算放大器600包含有一輸入級610、一高通濾波電路620及一輸出級630,其中高通濾波電路620包含有電容CH1、CH2及電阻RH1、RH2。運算放大器600與第5圖之運算放大器50相同,其中類似元件的耦接關係及相關訊號在此不贅述。假設輸入級610的增益為A1
,輸出級630的增益為A2
,電阻R1及R2的阻值為R1
及R2
,電阻RH1及RH2的阻值為RH
,電容CH1及CH2的容值為CH
,複變頻率以s表示,可程式增益放大器60之輸出訊號Vo
對輸入訊號Vi
的轉換函式表示如下:
當運算放大器600的總增益A=A1×A2的值很大時,式3可簡化為:
由式4可知,與習知可程式增益放大器30相較,本發明實施例之高通濾波電路620的轉角頻率由原本的1/RH
CH
降低至。電容增強因子等於AR2
/(R1
+R2
)。以一般的增益設計,如運算放大器600的總增益為1000,並且可程式增益放大器60之增益R2
/R1
為20的情形為例,高通濾波電路620之轉角頻率為習知技術所得之轉角頻率的五十分之一;或者,電容CH1及CH2的元件面積較習知技術降低五十倍。
在習知技術中,若電路中串接多個可程式增益放大器,設置於運算放大器外部的高通濾波電路的元件數量將成倍增加,儘管可消除直流電壓偏移,但電路成本無法降低。相較之下,本發明將高通濾波電路設置於運算放大器的輸入級與輸出級之間,因此,使用本發明之運算放大器之可程式增益放大器不須於外部另設置直流偏移消除電路。較佳地,本發明之運算放大器所使用之高通濾波電容的元件面積,遠比習知用於運算放大器外部之電容面積更為節省,當電路中串接之可程式增益放大器越多,本發明節省成本的效果也越明顯。
請注意,第5圖之運算放大器50係本發明最精簡之實施例,本發明進一步提供下述實施例,以說明運算放大器之輸入級、輸出級及高通濾波電路的實現方式。請參考第7圖,第7圖為本發明實施例一運算放大器70之示意圖。運算放大器70包含有一輸入級71、一高通濾波電路72及一AB類輸出級73。輸入級71包含有p型電晶體MP1~MP4、n型電晶體MN1~MN5及一共模回饋電路700。高通濾波電路72包含有電阻RH1~RH4及電容CH1~CH4,共形成四個高通濾波單元。輸出級73包含有p型電晶體MP6、MP7、n型電晶體MN6、MN7、電容CM1、CM2及一共模回饋電路702。在第7圖中,節點A~J表示部份輸出端、輸入端及元件的耦接點。
在輸入級71中,電晶體MP1及MP2形成一差動對,電晶體MP1及MP2的源極耦接於一電壓VDD,閘極耦接於共模回饋電路700,由共模回饋電路700所輸出的一偏壓VBP1所控制。電晶體MP3及MP4形成一差動對,電晶體MP3及MP4的閘極耦接於一偏壓VBP2,電晶體MP3的源極耦接於電晶體MP1的汲極,電晶體MP4的源極耦接於電晶體MP2的汲極。電晶體MN1及MN2形成一差動對,電晶體MN1及MN2的閘極耦接於一偏壓VBN2,電晶體MN1的汲極耦接於電晶體MP3的汲極,其耦接點標示為一節點A,係輸入級71之一負輸出端,輸出一負差動輸出訊號VON;電晶體MN2的汲極耦接於電晶體MP4的汲極,其耦接點標示為一節點B,係輸入級71之一正輸出端,輸出一正差動輸出訊號VOP。電晶體MN3及MN4形成一差動對,電晶體MN3及MN4的閘極為輸入級71之差動輸入端,分別接收差動輸入訊號INP及INN,電晶體MN3的汲極耦接於電晶體MN1的源極,電晶體MN4的汲極耦接於電晶體MN2的源極。電晶體MN5的汲極耦接於電晶體MN3及MN4的源極,源極耦接於一地端,閘極耦接於一偏壓VBN1。
共模回饋電路700耦接於節點A、B及電晶體MP1、MP2的閘極,用來產生控制電晶體MP1及MP2之閘極的偏壓VBP1。如第7圖右所示,共模回饋電路700由p型電晶體MP8~MP10及n型電晶體MN8、MN9等組成,控制電晶體MP9之閘極的偏壓VCM即預設的共模輸出電壓。透過共模回饋電路700的運作,輸入級71的共模輸出電壓等於偏壓VCM。共模回饋電路的做法為本領域具通常知識者所熟知,在此不詳述。
為便於說明,輸出級73之差動輸入端為電晶體MP6、MP7、MN6、MN7的閘極,依序標示為節點C、D、E、F。在高通濾波電路72中,電容CH1與電阻RH1形成一高通濾波單元HPF1,電容CH1耦接於節點A與節點C,電阻RH1耦接於節點C與一節點G之間,節點G耦接於一偏壓VBP3。電容CH2與電阻RH2形成一高通濾波單元HPF2,電容CH2耦接於節點B與節點D之間,電阻RH2耦接於節點D與節點G之間。高通濾波單元HPF1及HPF2分別將輸入級71之差動輸出訊號VON及VOP進行高通濾波,產生輸出級73之第一對差動輸入訊號;同時,偏壓VBP3用來提供第一對差動輸入訊號的輸入共模電壓。
類似地,電容CH3與電阻RH3形成一高通濾波單元HPF3,電容CH3耦接於節點A與節點E之間,電阻RH3耦接於節點E與一節點H之間,節點H耦接於一偏壓VBN3。電容CH4與電阻RH4形成一高通濾波單元HPF4,電容CH4耦接於節點B與節點F之間,電阻RH4耦接於節點F與節點H之間。高通濾波單元HPF3及HPF4分別將輸入級71之差動輸出訊號VON及VOP進行高通濾波,產生輸出級73之第二對差動輸入訊號;同時,偏壓VBN3用來提供第二對差動輸入訊號的輸入共模電壓。
在輸出級73中,電晶體MP6的汲極耦接於電晶體MN6的汲極,其耦接點標示為一節點I,係輸出級73之一正輸出端,輸出一正差動輸出訊號OUTP。電晶體MP7的汲極耦接於電晶體MN7的汲極,其耦接點標示為一節點J,係輸出級73之一負輸出端,輸出一負差動輸出訊號OUTN。電晶體MP6及MP7的源極耦接於電壓VDD,電晶體MN6及電晶體MN7的源極耦接於地端。電容CM1及CM2為米勒補償(Miller Compensation)電容,電容CM1耦接於節點B與節點J之間,電容CM2耦接於節點A與節點I之間。共模回饋電路702耦接於節點I、節點J及節點H,用來產生偏壓VBN3,回饋至節點H,共模回饋電路702的電路及運作方式與輸入級71之共模回饋電路700相同。透過共模回饋電路700的運作,輸出級73的共模輸出電壓等於預設之偏壓。
簡言之,高通濾波電路72對輸入級71的差動輸出訊號進行高通濾波,濾除了差動輸出訊號中的直流偏移,並且透過偏壓VBP3及VBN3提供共模電壓,控制輸出級73的差動輸入訊號保持相同的直流電壓準位。以另一角度而言,高通濾波電路72的作用等於將輸入級71與輸出級73解耦,輸入級71的差動輸出訊號不再被輸出級73的差動輸入訊號影響。相較於第1圖之運算放大器10,運算放大器70解決了輸入級之電壓餘量不足的問題,可使低供應電壓下的電路設計較容易。
此外,在運算放大器10中,輸出級12之差動輸入訊號僅控制p型電晶體差動對;而在運算放大器70中,輸出級73的差動輸入訊號同時控制了p型及n型電晶體差動對,因此輸出級73的增益是習知輸出級12的二倍。另一方面,雖然第2圖之運算放大器20也能夠將輸入級與輸出級解耦,但其中開關電容式電壓轉換電路所需的元件數量遠多於運算放大器70中的高通濾波電路72,並且僅能用於開關電容式的電路應用中,如管線式類比數位轉換器,無法使用於連續式電路如主動RC濾波器。此外,運算放大器20之輸出級22所使用之電晶體MN8及MP8會導致相位邊際變小,而運算放大器70由於不需使用類似的元件,因此能夠提升相位邊際。相較之下,運算放大器70除了在元件成本上更節省,應用範圍也更廣。
請注意,第7圖之高通濾波電路72中的電阻RH1~RH4可使用其它電阻性元件替代。請參考第8圖,第8圖為本發明實施例一運算放大器80之示意圖。運算放大器80包含有一輸入級81、一高通濾波電路82及一輸出級83。輸入級81包含有p型電晶體MP1~MP4、n型電晶體MN1~MN5及一共模回饋電路800。輸出級83包含有p型電晶體MP6、MP7、n型電晶體MN6、MN7、電容CM1、CM2及一共模回饋電路802。輸入級81與輸出級83之元件耦接方式及各節點標示與第7圖相同,在此不贅述。高通濾波電路82包含有p型電晶體MR1、MR2、n型電晶體MR3、MR4及電容CH1~CH4,電晶體MR1~MR4係金氧半導體場效電晶體(Metal-Oxide-Semiconductor Field Effect Transistor),其工作於三極體區時等效於電阻。換言之,第7圖中的電阻RH1~RH4可分別用第8圖中的電晶體MR1~MR4替代。電晶體MR1之源極耦接於節點G,汲極耦接於節點C;電晶體MR2之源極耦接於節點G,汲極耦接於節點D;電晶體MR3之源極耦接於節點H,汲極耦接於節點E;電晶體MR4之源極耦接於節點H,汲極耦接於節點F。透過高通濾波電路82,運算放大器80可實現與前述運算放大器70相同的效果。
請注意,運算放大器70及運算放大器80為本發明之實施例,本領域具通常知識者當可據以做不同的變化及修飾。以第7圖之運算放大器70而言,共模回饋電路702所輸出的電壓可用來控制輸出級73其中任一差動輸入訊號的共模電壓。換言之,共模回饋電路702所輸出的電壓除了回饋至節點H,亦可改為回饋至節點G。運算放大器70、80之輸入級為一伸縮式(Telescopic)放大器架構,輸入級可有不同的做法,如使用摺疊疊接式(Folded-cascode)放大器架構等,不影響本發明之高通濾波電路的功能。本發明實施例中的輸出級亦不限於特定放大器如A類或AB類放大器,凡於輸入級與輸出級之間使用高通濾波電路以達成直流偏移消除功能者,皆屬於本發明實施例之範圍內。
綜上所述,本發明利用運算放大器之輸入級與輸出級之間的高通濾波電路,將輸入級與輸出級解耦,並且消除輸入級之差動輸出訊號中的直流電壓偏移。相較於習知技術,本發明使運算放大器之輸入級與輸出級的分別設計更具彈性,同時以最精簡的元件達到消除直流偏移之目的。
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。
10、20、300、400、402、50、600、70、80...運算放大器
11、21、51、610、71、81...輸入級
52、620、72、82...高通濾波電路
12、22、53、630、73、83...輸出級
100、102、200、202、700、702、800、802...共模回饋電路
23...開關電容式電壓轉換電路
30、40、60...可程式增益放大器
S1~S16...開關
RH1~RH4、R1~R8...電阻
CH1~CH4、C1~C8、CM1、CM2...電容
MP1~MP4、MP6~MP10、MN1~MN9、MR1~MR4...電晶體
A、B、C、D、E、F、G、H、I、J...節點
VBP1、VBN1、VBP2、VBN2、VBN3、VBP3、VC、VCM...偏壓
INP、INN、VON、VOP、OUTP、OUTN...差動訊號
第1圖及第2圖為習知運算放大器之示意圖。
第3圖及第4圖為習知可程式增益放大器之示意圖。
第5圖為本發明實施例一運算放大器之示意圖。
第6圖為本發明實施例一可程式增益放大器之示意圖。
第7圖及第8圖為本發明實施例運算放大器之示意圖。
50...運算放大器
51...輸入級
52...高通濾波電路
53...輸出級
CH1、CH2...電容
RH1、RH2...電阻
INP、INN、VON、VOP、OUTP、OUTN...差動訊號
Claims (5)
- 一種運算放大器,包含有:一輸入級,用來根據一第一差動輸入訊號對,產生一第一差動輸出訊號對;一輸出級,用來根據至少一第二差動輸入訊號對,產生一第二差動輸出訊號對;以及一高通濾波電路,耦接於該輸入級與該輸出級之間,用來對該第一差動輸出訊號對進行高通濾波處理,以產生該至少一第二差動輸入訊號對;其中,該高通濾波電路另耦接於至少一偏壓,該至少一偏壓中每一偏壓係該至少一第二差動輸入訊號對其中一第二差動輸入訊號對之一共模電壓,且該輸出級包含有一共模回饋電路,用來產生該至少一偏壓其中一偏壓。
- 如請求項1所述之運算放大器,其中該高通濾波電路包含有複數個高通濾波單元,每一高通濾波單元耦接於該輸入級之複數個輸出端之一輸出端,該輸出級之複數個輸入端之一輸入端,以及一偏壓。
- 如請求項1所述之運算放大器,其中該高通濾波電路包含有複 數個高通濾波單元,每一高通濾波單元包含有:一電容,耦接於該輸入級之複數個輸出端之一輸出端與該輸出級之複數個輸入端之一輸入端之間;以及一電阻性元件,耦接於一偏壓與該輸入端之間,該偏壓係該至少一第二差動輸入訊號對其中一第二差動輸入訊號對之一共模電壓。
- 如請求項3所述之運算放大器,其中該電阻性元件係一電阻。
- 如請求項3所述之運算放大器,其中該電阻性元件係一金氧半導體場效電晶體。
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US11349443B2 (en) | 2019-09-10 | 2022-05-31 | Mediatek Inc. | Operational amplifier using single-stage amplifier with slew-rate enhancement and associated method |
TWI767311B (zh) * | 2019-09-10 | 2022-06-11 | 聯發科技股份有限公司 | 運算放大器及信號放大方法 |
US11664774B2 (en) | 2019-09-10 | 2023-05-30 | Mediatek Inc. | Operational amplifier using single-stage amplifier with slew-rate enhancement and associated method |
TWI825833B (zh) * | 2022-07-06 | 2023-12-11 | 瑞昱半導體股份有限公司 | 放大器 |
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US20110018633A1 (en) | 2011-01-27 |
US7999612B2 (en) | 2011-08-16 |
TW201105030A (en) | 2011-02-01 |
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