TWI384614B - 形成鰭狀場效電晶體裝置中之結構的方法 - Google Patents

形成鰭狀場效電晶體裝置中之結構的方法 Download PDF

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TWI384614B
TWI384614B TW093109021A TW93109021A TWI384614B TW I384614 B TWI384614 B TW I384614B TW 093109021 A TW093109021 A TW 093109021A TW 93109021 A TW93109021 A TW 93109021A TW I384614 B TWI384614 B TW I384614B
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fin structure
fin
semiconductor device
dielectric
single crystal
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TW200501393A (en
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Ming-Ren Lin
Haihong Wang
Bin Yu
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Advanced Micro Devices Inc
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Description

形成鰭狀場效電晶體裝置中之結構的方法
本發明一般係有關於半導體製造，尤其係有關於形成鰭狀場效電晶體裝置。
隨著在超大尺寸積體半導體裝置領域對高密度及高性能需求的逐漸增強，在諸如閘極長度等設計特徵上呈現對小於100nm的技術，高可靠性能和不斷增加生產率的需求，這種在設計特徵尺寸(design features)減小到100nm以下後，對傳統方法論的極限提出了挑戰。
例如，當傳統的平面型金屬氧化物半導體場效電晶體(MOSFET)的閘極長度小於100nm時，短通道效應引起的例如源極及汲極間的過量洩漏電流(excessive leakage)問題，變得越來越難克服。此外，移動率降低及許多製程處理方面的問題也使得傳統MOSFET很難掌握對尺寸不斷減小的裝置特性的兼容。因此急待研發一種新裝置結構以改善FET的性能及容許裝置規模更進一步減小。
雙閘極MOSFET描述一種新的結構，該結構已經被認為是替代目前平面型MOSFET的最佳結構。在雙閘極MOSFET內，可使用兩個閘極控制短通道效應。而鰭狀場效電晶體(FinFET)是雙閘極結構，其有很好的短通道效應行為，該FinFET包括有形成於垂直鰭片(Fin)中之通道。該FinFET結構也可用類似於傳統平面型MOSFET的佈線及製程技術製造。
與本發明之原理相一致之實施例係提供單晶矽鰭結構，該結構形成於介電鰭結構之相對側上，該介電鰭結構之材料係經選擇以在該單晶矽材料中引致有效應力，從而可增強移動率。
如這裡所包含及廣泛描述的與本發明相一致之目的一樣，一半導體裝置包括第一鰭結構，其包含介電材料且具有第一側表面及第二側表面；第二鰭結構，其包含單晶矽材料且形成於鄰近該第一鰭結構之第一側表面；第三鰭結構，其包含該單晶矽材料且形成於鄰近該第一鰭結構之第二側表面；形成於該第一、第二及第三鰭結構之一端之源極區；形成於該第一、第二及第三鰭結構之相對端之汲極區；以及至少一閘極。
在與本發明原理相一致之另一實施例中，揭示一種製造半導體裝置之方法，該半導體裝置包括基材及形成於該基材上之介電層。該方法包括：蝕刻該介電層以形成第一鰭結構；沉積非晶矽層；蝕刻該非晶矽層以形成鄰近於該第一鰭結構之第一側表面之第二鰭結構及鄰近該第一鰭結構之第二相對側表面之第三鰭結構；至少在該第二鰭結構及該第三鰭結構之上表面上沉積金屬層；實施金屬引致晶化(metal-induced crystallization)操作，使該第二鰭結構及該第三鰭結構內之非晶矽轉變單晶矽材料；形成源極區及汲極區；在該第一、第二及第三鰭結構上面沉積閘極材料；以及圖案化及蝕刻該閘極材料以形成至少一閘極電極。
在與本發明原理相一致之再一實施例中，揭示一種半導體裝置，該半導體裝置包括第一鰭結構、第二鰭結構及第三鰭結構。該第一及第二鰭結構包括單晶矽材料。該第三鰭結構位於該第一鰭結構及第二鰭結構之間，且該第三鰭結構包括介電材料。該第三鰭結構使應力於該第一鰭結構及第二鰭結構之單晶矽材料中引致。
對與本發明相一致之實施例將參考附圖作如下詳細說明。在不同的附圖中，相同的參考數字可標示相同的或相似的元件，並且如下詳細說明並非用於限制本發明，相反，本發明之範圍如權利要求及其對等的實施例所定義。
與本發明之原理相一致之實施例係提供形成於介電鰭結構相對側上之單晶矽鰭結構。該介電鰭結構之材料係經選擇，以在該單晶矽材料中引致有效應力，藉以增強移動率。
第1圖說明與本發明之原理相一致之實施例中形成鰭狀場效電晶體裝置之鰭結構之典型方法，第2圖至第9圖為說明根據第1圖所示之方法製造鰭狀場效電晶體裝置之典型視圖，鰭狀場效電晶體裝置的製造將在下文中說明，然而須了解，這裡所說明的技術可相等地應用於形成更多的鰭狀場效電晶體裝置。
參考第1圖及第2圖(步驟105)，製程可開始於在半導體裝置之基材200上形成介電鰭結構210。在一實施例中，該基材200可由矽組成。在一與本發明相一致之可替換的實 施例中，該基材200可由諸如鍺之其它半導體材料或例如矽鍺之結合半導體材料組成。在其它實施例中，基材200可包含例如氧化物層之絕緣物形成於矽或鍺基材上。該介電鰭結構210可包含介電材料，該介電材料在雙鰭結構中產生有效張應力(應變)，該雙鰭結構形成於鄰近該介電鰭結構210。在一個實施例中，該介電鰭結構210可包含氧化物或氮化物。
該介電鰭結構210可用傳統的方法形成。例如，在該基片200上沉積介電材料，沉積的厚度在大約200Å到大約1000Å之範圍。在部分之介電材料上可形成遮罩(mask)，且接著可用傳統的方法蝕刻該介電材料，至該基材200結束以形成該介電鰭結構210。該所得的介電鰭結構210之寬度在大約100 Å到大約1000Å之範圍。
在形成該介電鰭結構210之後，如第3圖所示(步驟110)，可在該半導體裝置上沉積非晶矽層(amorphous silicon layer)310。在一與本發明之原理相一致之實施例中，該非晶矽層310可沉積至在大約100 Å到大約1000Å之範圍之厚度。
接著，如第4圖所述(步驟115)，可用傳統的方法蝕刻該非晶矽層310至該基片200結束以形成非晶矽間隔物(鰭)結構410。每一非晶矽鰭結構410之高度可在大約200 Å到大約1000Å之範圍，及其寬度在大約100 Å到大約1000Å之範圍。
如第5圖所示(步驟120)，可在該半導體裝置上沉積 介電層510。在一與本發明之原理相一致之實施例中，該介電層510可沉積的厚度在大約200 Å到大約1000Å之範圍，該介電層510可包含氧化物或其他介電材料。
如第6圖所示(步驟120)，可用化學機械抛光(CMP)(或其他技術)對該半導體裝置進行抛光，以平面化該半導體裝置之上表面，使得每個非晶矽鰭結構410之上表面外露。在化學機械抛光過程中，部分之該介電鰭結構210及非晶矽鰭結構410之上表面可加以移除，以外露出每一非晶矽鰭結構410之上表面。例如，化學機械抛光之後，該鰭210及410的高度可在大約150 Å到大約200Å之範圍。
如第7圖所示(步驟125)，可在該半導體裝置上沉積例如鎳之金屬層710。在一個實施例中，鎳層710可沉積至大約20Å之厚度。
接著，可實施金屬引致晶化(MIC)操作。如第8圖所示(步驟130)該MIC操作可包括在大約500℃到大約550℃溫度對該鎳層710退火數小時，其作用就是使鎳金屬擴散到該非晶矽內，使得該鰭結構410中之非晶矽轉變成單晶矽810。在MIC操作結果，鎳矽(NiSi)化合物薄層820可形成於基材200及單晶矽鰭結構810之間。在一個實施例中，該鎳矽層820之厚度可在大約20 Å到大約200Å之範圍。
在該單晶矽鰭結構810形成之後，可利用習用的FinFET製造處理以完成該電晶體(例如對該FinFET裝置形成源極及汲極區、接觸件(contact)、互連件(interconnect)及層間介電質(inter-level dielectric))。例如，該介電層 510可加以移除，例如像氮化矽或氧化矽之保護介電層，可形成於該鰭210及810之上表面，接著，在該單晶矽鰭結構810之側表面形成閘極介電質。然後，在該鰭210及810各自端部形成源極區及汲極區，接著，形成一個或多個閘極。例如，矽層、鍺層、矽和鍺之結合或各種金屬可作為該閘極材料用。接著該閘極材料可加以圖案化及蝕刻以形成閘極電極。例如，第9圖說明源極/汲極區及閘極形成之後，與本發明之原理相一致之半導體裝置之典型的頂部視圖。如圖所示，該半導體裝置包括具有鰭210及810之雙閘極結構、源極及汲極區910及920、以及閘極電極930及940。
然後，根據特定端裝置要求，可以n型或p型雜質摻雜該源極/汲極區910及920。此外，根據特殊的電路要求，側壁間隔物可選擇性形成於該源極/汲極離子植入前，藉以控制源極/汲極結的位置。接著可進行活化退火以活化該源極/汲極區910及920。
如上所述之本發明形成許多的鰭結構。須了解，根據特殊的電路要求，與本發明相一致之方法可用於形成任一數量之鰭。
因此，依照本發明之原理，可形成單晶矽鰭結構，該單晶矽鰭結構具有位於該單晶矽鰭結構之間之介電鰭結構。該介電鰭結構之材料可加以選擇，以致在該單晶矽鰭結構中引致有效應力(應變)，從而達到增強該單晶矽鰭結構中的移動率。
(其他實施例)
第10圖至第15圖說明在與本發明之原理相一致之替換的實施例中形成多個鰭結構之示意圖。參閱第10圖，製程可從半導體裝置之處理開始，該半導體裝置包括形成於基材1000上之氧化物層1010。該基材1000可由矽或由諸如鍺之其它半導體材料，或矽鍺之組合半導體材料所組成。該氧化物層1010之高度可在大約200 Å到大約1000Å之範圍。
如第10圖所示，可蝕刻該氧化物層1010以形成一溝槽(trench)1020。在一個實施例中，該溝槽1020的寬度可在大約200 Å到大約2000Å之範圍。接著如第11圖所述，可沉積非晶矽及蝕刻該非晶矽以形成非晶矽間隔物1110。每個非晶矽間隔物1110之寬度可在大約100 Å到大約1000Å之範圍。如第12圖所述，介電材料1210可沉積在非晶矽間隔物1110之間的間隙內。該介電材料可包含氧化物或其他介電材料。
如第13圖所示，在非晶矽間隔物1110之上表面可沉積鎳層1310。該鎳層1310的厚度可大約為20Å。接著可實施金屬引致晶化(MIC)操作。如第14圖所示，該MIC操作可包括在大約500℃到550℃對該鎳層1310退火數小時，以使該非晶矽間隔物1110轉變成單晶矽鰭結構1410。在MIC操作的結果，鎳矽(NiSi)化合物薄層1420可形成於基材1000及單晶矽鰭結構1410之間。在一個實施例中，該鎳矽層1420之厚度可在大約20 Å到大約200Å之範圍。
接著如第15圖所示，該氧化物層1010可用習用方法移 除，從而，可產生間隔物引致合併的場效電晶體(spacer-induced merged FET)。
在另一實施例中，間隔物(spacer)可用於產生一窄溝槽(trench)，藉以提供在該溝槽兩側之間的耦合效應(coupling effect)。如第16圖所示，半導體裝置可包括一氧化物層1610，該氧化物層1610形成於基材上(未圖示)，且矽層1620形成於該氧化物層1610上。可沉積諸如氮化矽、氧化矽等材料並加以圖案化該材料以形成硬質遮罩(hard mask)1640。接著可沉積諸如氮化矽、氧化矽材料或其它材料之間隔物材料，並蝕刻該材料以在硬質遮罩之側表面形成間隔物1630。接著如第17圖所示，可用該間隔物1630及該硬質遮罩1640作為遮罩來蝕刻該矽層1620，以形成窄溝槽1710。該溝槽1710之寬度可在大約100 Å到大約1000Å之範圍。該溝槽1710有利於在位於溝槽1710兩側之鰭1620間提供耦合效應。
與本發明之原理相一致之實施例提供單晶矽鰭結構，該結構形成於介電鰭結構之相對側上。該介電矽鰭結構之材料可加以選擇以致在該單晶矽材料中引致有效應力，藉此達到強化移動率。
如前所述的本發明之典型實施例提供說明及描述，但並不詳盡或用於限定本發明至所揭示之精密成形範圍。根據上述的技術可對本發明作出修改、變更，或從本發明之實踐中而能習得。例如，為了徹底的了解本發明，在上述中，許多特殊細節被提出，例如像特殊材料，結構，化學 物，方法等。然而，不使用這裡所提出的特殊細節，本發明也可被實踐。在其他範例中，為了不模糊本發明之要點，衆所周知的處理結構未被詳細公佈。在本發明的實踐中，傳統的沉積，光刻及蝕刻技術可被應用，因此，在這裡，這些技術之細節並沒有詳細提出。
在與本發明相一致之其他實施例中，於第1圖中所揭示的一系列步驟次序可加以改變，而且，無相互依賴的步驟可平行實施。
除非於此明確說明，本申請之描述中無元件動作或指令的使用，應被解釋為本發明的關鍵的或必要部分。並且，這裡所使用的冠詞“一(a)”意指包括一項或更多項之措詞。在僅意指某一項物件的地方，可使用該冠詞“一個(one)”或類似的術語。
本發明之範圍如權利要求及其他對等的實施例所定義。
105,110,115,120,125,130‧‧‧步驟
200‧‧‧基材
210‧‧‧介電鰭結構
310‧‧‧非晶矽層
410‧‧‧非晶矽間隔物(鰭)結構
510‧‧‧介電層
710‧‧‧鎳層
810‧‧‧單晶矽鰭結構
820‧‧‧鎳矽化合物
910‧‧‧源極區
920‧‧‧汲極區
930,940‧‧‧閘極電極
1000‧‧‧基材
1010‧‧‧氧化物層
1020‧‧‧溝槽
1110‧‧‧非晶矽間隔物
1210‧‧‧介電材料
1310‧‧‧鎳層
1410‧‧‧單晶矽鰭結構
1420‧‧‧鎳矽化合物
1610‧‧‧氧化物層
1620‧‧‧矽層/鰭
1640‧‧‧硬質遮罩
1630‧‧‧間隔物
1710‧‧‧溝槽
以下附圖，係用以併入並作為組成說明書的一部分，其闡明本發明之實施例，並一起描述、說明本發明，其中，第1圖說明在與本發明之原理相一致之實施例中形成鰭狀場效電晶體裝置中之鰭結構之典型製程；第2圖至第9圖說明根據第1圖所示之製程所製造的鰭狀場效電晶體裝置之典型視圖；第10圖至第15圖說明在與本發明之原理相一致之替換的實施例中形成多鰭結構之典型視圖；以及 第16圖及第17圖說明依據本與發明之原理相一致之替換的實施例產生溝槽(trench)之典型視圖。
210‧‧‧介電鰭結構
810‧‧‧單晶矽鰭結構
910‧‧‧源極區
920‧‧‧汲極區
930‧‧‧閘極電極
940‧‧‧閘極電極

Claims (10)

  1. 一種半導體裝置，包含：第一鰭(Fin)結構(210)，該第一鰭結構包含介電材料且包括有第一側表面及第二側表面；第二鰭結構(810)，該第二鰭結構包含單晶矽材料且形成於鄰近該第一鰭結構(210)之該第一側表面；第三鰭結構(810)，該第三鰭結構包含該單晶矽材料且形成於鄰近該第一鰭結構(210)之該第二側表面；源極區(910)，該源極區形成於該第一鰭結構(210)、該第二鰭結構(810)及該第三鰭結構(810)之一端；汲極區(920)，該汲極區形成於該第一鰭結構(210)、該第二鰭結構(810)及該第三鰭結構(810)之相對端；以及至少一閘極(930,940)。
  2. 如申請專利範圍第1項之半導體裝置，其中，該第一鰭結構(210)之寬度在大約200Å到大約1000Å之範圍。
  3. 如申請專利範圍第1項之半導體裝置，其中，該介電材料包括氧化物及氮化物之其中一者。
  4. 如申請專利範圍第1項之半導體裝置，其中，各該第二鰭結構(810)及第三鰭結構(810)之寬度在大約100Å到大約1000Å之範圍。
  5. 一種製造半導體裝置之方法，該半導體裝置包括基材(200)及形成於該基材(200)上之介電層(210)，該方法包 含：蝕刻該介電層(210)以形成第一鰭結構(210)；沉積非晶矽層(310)；蝕刻該非晶矽層(310)以形成鄰近於該第一鰭結構(210)之第一側表面之第二鰭結構(410)及鄰近於該第一鰭結構(210)之第二相對二側表面之第三鰭結構(410)；至少在該第二鰭結構(410)及該第三鰭結構(410)之上表面上沉積金屬層(710)；實施金屬引發晶化操作，使該第二鰭結構(410)及該第三鰭結構(410)中之非晶矽轉變成單晶矽材料；形成源極區(910)及汲極區(920)；在該第一、第二及第三鰭結構(210,410)上沉積閘極材料；以及圖案化及蝕刻該閘極材料以形成至少一閘極電極(930,940)。
  6. 如申請專利範圍第5項之方法，其中，該介電層(210)包含氧化物及氮化物之其中至少一者。
  7. 一種半導體裝置，包含：第一鰭結構(810)，該第一鰭結構包含單晶矽材料；第二鰭結構(810)，該第二鰭結構包含該單晶矽材料；以及位於該第一鰭結構(810)及該第二鰭結構(810)之間之第三鰭結構(210)，該第三鰭結構(210)包含介電材料，該第三鰭結構(210)使應力於該第一鰭結構(810)及 該第二鰭結構(810)之該單晶矽材料中引致。
  8. 如申請專利範圍第7項之半導體裝置，其中，各該第一鰭結構(810)及第二鰭結構(810)之寬度在大約100Å到大約1000Å之範圍。
  9. 如申請專利範圍第8項之半導體裝置，其中，該第三鰭結構(210)之寬度在大約100Å到大約1000Å之範圍。
  10. 如申請專利範圍第9項之半導體裝置，其中，該介電材料包含氧化物及氮化物之其中至少一者。
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US20040198031A1 (en) 2004-10-07
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TW200501393A (en) 2005-01-01
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JP5009611B2 (ja) 2012-08-22
US6762448B1 (en) 2004-07-13
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US6852576B2 (en) 2005-02-08
CN100413038C (zh) 2008-08-20

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