TWI380375B - Method for fabricating semiconductor device with vertical channel - Google Patents
Method for fabricating semiconductor device with vertical channel Download PDFInfo
- Publication number
- TWI380375B TWI380375B TW096141333A TW96141333A TWI380375B TW I380375 B TWI380375 B TW I380375B TW 096141333 A TW096141333 A TW 096141333A TW 96141333 A TW96141333 A TW 96141333A TW I380375 B TWI380375 B TW I380375B
- Authority
- TW
- Taiwan
- Prior art keywords
- forming
- insulating layer
- hard mask
- substrate
- pillars
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 71
- 239000004065 semiconductor Substances 0.000 title claims description 25
- 239000000758 substrate Substances 0.000 claims description 45
- 238000005530 etching Methods 0.000 claims description 30
- 239000002131 composite material Substances 0.000 claims description 23
- 239000012535 impurity Substances 0.000 claims description 19
- 238000004519 manufacturing process Methods 0.000 claims description 19
- 150000004767 nitrides Chemical class 0.000 claims description 8
- 230000002093 peripheral effect Effects 0.000 claims description 8
- 125000006850 spacer group Chemical group 0.000 claims description 8
- 230000004888 barrier function Effects 0.000 claims description 6
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 238000011049 filling Methods 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims description 2
- 238000004528 spin coating Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 210000004027 cell Anatomy 0.000 description 3
- 229910052770 Uranium Inorganic materials 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- JFALSRSLKYAFGM-UHFFFAOYSA-N uranium(0) Chemical compound [U] JFALSRSLKYAFGM-UHFFFAOYSA-N 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 210000003771 C cell Anatomy 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
- H10B12/0383—Making the capacitor or connections thereto the capacitor being in a trench in the substrate wherein the transistor is vertical
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/39—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench
- H10B12/395—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench the transistor being vertical
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020070062782A KR100869353B1 (ko) | 2007-06-26 | 2007-06-26 | 수직 채널 트랜지스터를 구비한 반도체 소자의 제조 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200901328A TW200901328A (en) | 2009-01-01 |
TWI380375B true TWI380375B (en) | 2012-12-21 |
Family
ID=40161109
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW096141333A TWI380375B (en) | 2007-06-26 | 2007-11-02 | Method for fabricating semiconductor device with vertical channel |
Country Status (5)
Country | Link |
---|---|
US (1) | US8183112B2 (ko) |
JP (1) | JP2009010314A (ko) |
KR (1) | KR100869353B1 (ko) |
CN (1) | CN101335243B (ko) |
TW (1) | TWI380375B (ko) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100900148B1 (ko) * | 2007-10-31 | 2009-06-01 | 주식회사 하이닉스반도체 | 반도체 소자 및 그 제조 방법 |
KR101055747B1 (ko) | 2008-11-13 | 2011-08-11 | 주식회사 하이닉스반도체 | 수직 채널 트랜지스터를 구비하는 반도체 장치의 제조방법 |
KR101075492B1 (ko) | 2009-03-23 | 2011-10-21 | 주식회사 하이닉스반도체 | 수직트랜지스터를 구비한 반도체장치 및 그 제조 방법 |
KR101094371B1 (ko) | 2009-07-03 | 2011-12-15 | 주식회사 하이닉스반도체 | 수직트랜지스터를 구비한 반도체장치 제조 방법 |
US8283715B2 (en) * | 2010-08-12 | 2012-10-09 | Rexchip Electronics Corporation | Method and apparatus for buried word line formation |
KR101133701B1 (ko) * | 2010-09-10 | 2012-04-06 | 주식회사 하이닉스반도체 | 매립비트라인을 구비한 반도체장치 제조 방법 |
KR101699442B1 (ko) * | 2010-10-13 | 2017-01-25 | 삼성전자 주식회사 | 수직 채널 트랜지스터를 구비한 반도체 소자의 제조 방법 |
KR20130055983A (ko) * | 2011-11-21 | 2013-05-29 | 에스케이하이닉스 주식회사 | 반도체 소자 및 그 제조 방법 |
US9076824B2 (en) | 2012-11-02 | 2015-07-07 | Micron Technology, Inc. | Memory arrays with a memory cell adjacent to a smaller size of a pillar having a greater channel length than a memory cell adjacent to a larger size of the pillar and methods |
TWI509689B (zh) * | 2013-02-06 | 2015-11-21 | Univ Nat Central | 介電質材料形成平台側壁的半導體製造方法及其半導體元件 |
JP6437351B2 (ja) | 2015-03-13 | 2018-12-12 | 東芝メモリ株式会社 | 半導体記憶装置及び半導体装置の製造方法 |
CN111261700A (zh) * | 2020-01-21 | 2020-06-09 | 中国科学院微电子研究所 | C形沟道部半导体器件及其制造方法及包括其的电子设备 |
CN114121818B (zh) * | 2021-11-15 | 2023-05-26 | 长鑫存储技术有限公司 | 半导体器件及其形成方法 |
CN116209258B (zh) * | 2022-11-01 | 2024-03-29 | 北京超弦存储器研究院 | 存储单元的存储结构和制备方法 |
CN116209259B (zh) * | 2022-11-01 | 2024-03-15 | 北京超弦存储器研究院 | 存储单元阵列结构和制备方法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0834302B2 (ja) * | 1990-04-21 | 1996-03-29 | 株式会社東芝 | 半導体記憶装置 |
US6034389A (en) | 1997-01-22 | 2000-03-07 | International Business Machines Corporation | Self-aligned diffused source vertical transistors with deep trench capacitors in a 4F-square memory cell array |
US6670642B2 (en) | 2002-01-22 | 2003-12-30 | Renesas Technology Corporation. | Semiconductor memory device using vertical-channel transistors |
US7242057B2 (en) * | 2004-08-26 | 2007-07-10 | Micron Technology, Inc. | Vertical transistor structures having vertical-surrounding-gates with self-aligned features |
KR100618875B1 (ko) * | 2004-11-08 | 2006-09-04 | 삼성전자주식회사 | 수직 채널 mos 트랜지스터를 구비한 반도체 메모리소자 및 그 제조방법 |
KR100734266B1 (ko) * | 2005-07-15 | 2007-07-02 | 삼성전자주식회사 | 콘택 저항이 개선된 수직 채널 반도체 소자 및 그 제조방법 |
KR100675285B1 (ko) * | 2005-10-10 | 2007-01-29 | 삼성전자주식회사 | 수직 트랜지스터를 갖는 반도체소자 및 그 제조방법 |
KR100660881B1 (ko) * | 2005-10-12 | 2006-12-26 | 삼성전자주식회사 | 수직 채널 트랜지스터를 구비한 반도체 소자 및 그 제조방법 |
KR100688576B1 (ko) * | 2005-10-14 | 2007-03-02 | 삼성전자주식회사 | 수직채널 트랜지스터를 갖는 반도체 메모리 장치 및 그제조방법 |
JP4315943B2 (ja) * | 2005-10-18 | 2009-08-19 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
KR100723527B1 (ko) * | 2006-02-13 | 2007-05-30 | 삼성전자주식회사 | 수직 채널 트랜지스터를 구비한 반도체 소자의 제조방법 및그에 의해 제조된 반도체 소자 |
-
2007
- 2007-06-26 KR KR1020070062782A patent/KR100869353B1/ko not_active IP Right Cessation
- 2007-11-02 TW TW096141333A patent/TWI380375B/zh not_active IP Right Cessation
- 2007-11-27 JP JP2007306153A patent/JP2009010314A/ja active Pending
- 2007-12-05 US US11/951,218 patent/US8183112B2/en not_active Expired - Fee Related
- 2007-12-29 CN CN2007103083843A patent/CN101335243B/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
TW200901328A (en) | 2009-01-01 |
US8183112B2 (en) | 2012-05-22 |
CN101335243B (zh) | 2010-06-16 |
KR100869353B1 (ko) | 2008-11-19 |
US20090004861A1 (en) | 2009-01-01 |
CN101335243A (zh) | 2008-12-31 |
JP2009010314A (ja) | 2009-01-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI380375B (en) | Method for fabricating semiconductor device with vertical channel | |
KR102304926B1 (ko) | 서포터들을 갖는 반도체 소자 및 그 제조 방법 | |
US8283714B2 (en) | Semiconductor memory device having vertical channel transistor and method for fabricating the same | |
KR100843715B1 (ko) | 반도체소자의 콘택 구조체 및 그 형성방법 | |
US9634012B2 (en) | Method of forming active patterns, active pattern array, and method of manufacturing a semiconductor device | |
USRE44473E1 (en) | Method for fabricating semiconductor device with vertical channel transistor | |
KR101116353B1 (ko) | 수직셀을 구비한 반도체장치 및 그 제조 방법 | |
KR100618819B1 (ko) | 오버레이 마진이 개선된 반도체 소자 및 그 제조방법 | |
JP2009239285A (ja) | 半導体素子の垂直チャネルトランジスタ及びその形成方法 | |
KR20150044646A (ko) | 반도체 소자 및 그 제조 방법 | |
KR100924007B1 (ko) | 반도체 소자의 수직 채널 트랜지스터 형성 방법 | |
US20140377934A1 (en) | Method of Manufacturing Semiconductor Device Having Embedded Conductive Line | |
KR20200072313A (ko) | 집적회로 소자 | |
JP4391060B2 (ja) | 集積回路メモリ素子及びその製造方法 | |
KR101959388B1 (ko) | 반도체 소자 및 그 제조 방법 | |
US6856024B2 (en) | Semiconductor device with wiring embedded in trenches and vias | |
KR20220167542A (ko) | 콘택 플러그를 갖는 반도체 소자 | |
US6750098B2 (en) | Integrated semiconductor memory and fabrication method | |
US20090008694A1 (en) | Integrated circuit and corresponding manufacturing method | |
JP2001298167A (ja) | 半導体メモリ装置の製造方法 | |
TWI843223B (zh) | 去耦電容結構和包括其的半導體裝置 | |
JP2013187386A (ja) | 半導体装置及びその製造方法 | |
TW202347629A (zh) | 半導體裝置 | |
KR101139463B1 (ko) | 반도체 소자의 제조 방법 | |
KR101016956B1 (ko) | 반도체 소자의 수직 채널 트랜지스터 형성 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |