TWI334184B - Fabricating process for window bga packages to improve ball bridging - Google Patents

Fabricating process for window bga packages to improve ball bridging Download PDF

Info

Publication number
TWI334184B
TWI334184B TW096116177A TW96116177A TWI334184B TW I334184 B TWI334184 B TW I334184B TW 096116177 A TW096116177 A TW 096116177A TW 96116177 A TW96116177 A TW 96116177A TW I334184 B TWI334184 B TW I334184B
Authority
TW
Taiwan
Prior art keywords
ball
window
substrate
grid array
ball grid
Prior art date
Application number
TW096116177A
Other languages
Chinese (zh)
Other versions
TW200845242A (en
Inventor
Yi Hsin Chuang
Yung Hsiang Chen
Ping Hua Chu
Original Assignee
Walton Advanced Eng Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Walton Advanced Eng Inc filed Critical Walton Advanced Eng Inc
Priority to TW096116177A priority Critical patent/TWI334184B/en
Publication of TW200845242A publication Critical patent/TW200845242A/en
Application granted granted Critical
Publication of TWI334184B publication Critical patent/TWI334184B/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0612Layout
    • H01L2224/0615Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06154Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/06155Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0612Layout
    • H01L2224/0615Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06154Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/06156Covering only the central area of the surface to be connected, i.e. central arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

Disclosed is a fabricating process for window BGA packages. Initially, a substrate is provided, which has at least a window in each unit. Passing through die-attachment, electrical connection and encapsulation, an encapsulant is formed and has a plurality of protrusions aligned with the windows. Next, a flux is disposed on the ball pads of the substrate. Utilizing a ball-mounting jig, a plurality of solder balls are placed on the ball pads, where the jig has a plurality of suction holes in a plane and a get-in groove located above the protrusions to prevent from stress from the jig. Accordingly, each of the solder balls will be fixed on the corresponding one of the ball pads with one to one connection during reflowing so that the reject radio of ball bridging will be reduced dramatically.

Description

1334184 九、發明說明: 【發明所屬之技術領域】 本發明係有關於能明顯降低不良率之積體電路封穿技 術’特別係有關於一種改善球橋接之窗口型球格陣列封 程。 【先前技術】 球橋接(ball bridging),或稱雙重球(doubie ball),是指在 • 球格陣列封裝製程之回鋅步驟中,原本相鄰兩銲球熔接成一 顆,導致了一個大銲球的形成,與預定的銲球規格不相符 合,而大銲球的周邊更會留下一個空球墊,屬於製程缺陷。 若強制進行修補,則需要補球與再回銲,重覆的熱處理影響 了產品可靠度。並且,不符規格的大銲球甚難修補,會造成 非平面的表面接合與應力不平衡,容易有假焊點發生。因 此,球橋接問題引起的不良率應作確實且必要的改善工程。 如第1及2圖所示,一種習知的窗口型球格陣列封裝構 _ 造主要包含一基板110、一晶片120、一封膠體14〇以及複 數個銲球160。通常該基板11〇係具有複數個周邊窗口 111(可稱為small window)與一中央槽孔! 13。常見的晶片12〇 係為動態隨機存取記憶體晶片,如DDR2(雙倍資料傳輸速 度)。該晶片120之主動面貼附於該基板u〇之内表面而 使該晶片120之銲墊外露於該基板11〇之周邊窗口 與一 中央槽孔113,以供複數條銲線13〇通過並電性連接至該基 板110。而該封膠體140除了形成在該基板11()之内表面以 密封該晶片120,更會具有突出於該基板11〇外表面之複數 5 1334184 個周邊突部Hi與-中央突部142,其係分別對應於該些周 邊窗口 ill與該中央槽孔113,以密封該些鲜線13〇。該基 板110之外表面形成有複數個球墊112。該些銲球16〇係2 著於該些㈣112。然、而在實際封裝製程中會有球橋接的問 題0 如第3圖所示’經分析,所謂「球橋接」的現象通常發 生在接近該封膠體M0之突部141與142之區域,特別是接 • 近周邊突部M1的區域。原本皆應植球之球墊112中會有少 數的無銲球球墊112Α,其係接近周邊突部141。而無銲球球 墊112Α之周邊更會產生了一雙重銲球16〇Α,其球徑大於一 般所預定規格之銲球160。這表示了原本在無鲜球球塾112Α 上的銲球有位移的現象,並在回銲時與另一銲球熔合成上述 雙重銲球160Α。請參閱帛8圖之前半部7〇3與7〇4所表示 者,為目前依據習知的窗口型球格陣列封裝製程,因球橋接 引起的不良率約介於600至1〇〇〇 ΡΡΜ,並不符合預計的不 •:率目標值("Ο PPM),導致封裝成本無法降低。特別是隨 著先進封裝製程的演進,當該封膠體14〇之周邊突部141之 數量會增加’球橋接的不良率更加明顯昇高並且修補製程 已明確不被客戶所接受,故為首要解決的課題。 、,如第4圖所示,經過了進一步分析與研究,發現傳統的 、’面植球/0具1〇不適用於先進的窗口型球格陣列封裝製 =s知的植球治具10係在一平面12開設複數個吸球孔 以在植球步驟中吸附銲球16(^再將銲球16〇放置在窗 求格陣列封裝構造之球塾112,在理論上,每一銲球1 6 0 6 1334184 應被對應球墊112上的助熔劑! 5〇所沾附。然而,在實際上, 銲球160之一部份會嵌入該植球治具1〇之吸球孔u,又該 封膠體140在固化後會影響該基板11〇之翹曲度,所以該植 球治具10之平面12會碰觸到該封膠體14〇之周邊突部 141,導致在放置銲球時,部分接近該周邊突部141之銲球 會有位移與相互接觸之情事,故而在回銲時會熔合成如第3 圖所示的雙重銲球160A,而該些無銲球球墊n2A也將因此 而生。 【發明内容】 本發明之主要目的係在於提供一種窗口型球格陣列封裝 製程,能大幅降低球橋接之不良率,以符合不良率目標值: 本發明之次一目的係在於提供一種窗口型球格陣列封裝 製程,不會受到基板周邊窗口之數量而增加球橋接之不良 率 〇 本發明的目的及解決其技術問題是採用以下技術方案來 實現的。依據本發明之一種窗口型球格陣列封裝製程,首先 提供一基板,該基板係具有一内表面、一外表面以及在每一 單元區内之至少一窗口’其中該外表面係設有複數個球墊。 之後’設置複數個晶片於該基板之内表面。並電性連接該些 晶片至該基板。之後,形成至少—封㈣,其係覆蓋該基板 之内表面並填入該窗口,該封膠體並形成有至少一稍突出於 該外表面且對應於該窗口之突部H㈣形成於該些球 墊之後,藉由一植球治具,設置複數個銲球於該些球墊上, 該植球治具係具有一設有複數個吸球孔之平面以及至少一 7 1334184 位於該突部上之讓位槽,以避免該植球治具壓迫至該突部。 之後,進行一回銲步驟,以使該些銲球以一對一連接方式固 著於對應球墊。 本發明的目的及解決其技術問題還可採用以下技術措施 進一步實現。 在前述的窗口型球格陣列封裝製程中,該讓位槽相對於 該平面之深度係不小於該些吸球孔之吸球廉_埋深度。 在前述的窗口型球格陣列封裝製程中,該讓位槽相對於 該平面之深度係可不小於該些銲球之球徑三分之一。 在前述的窗口型球格陣列封裝製程中,該窗口係可為周 邊小窗口,並為複數個對稱排列,而該基板更具有在每一單 元區内之一中央槽孔。 在前述的窗口型球格陣列封裝製程中,該些窗口係可位 於兩平行於該中央槽孔之單元區側邊之中央。 在前述的窗口型球格陣列封裝製程中,該些窗口係可位 於對應單元區之角隅。 在前述的窗口型球格陣列封装製程中,在電性連接步驟 中每®口内可形成有至少一銲線,以電性連接該晶片與 該基板。 在則述的窗π型球格陣列封裝製程中,該封膠體係可密 封該些晶片與該些銲線。 “在刖述的囪口型球格陣列封裝製程中豸讓位槽係可沿 著該基板在單元區之間的切割道上方延伸。 【實施方式】 8 1334184 依據本發明之第一具體實施例,揭示一種窗口型球格陣 列封裝製程。請參閱第5圖所示,該封裝製裎主要包含:「提 供基板」步驟1、「設置晶片」步驟2、「電性連接」步驟3、 「封膠」步驟4、「形成助熔劑」步驟5、「植球」步驟6以 及「回銲」步驟7。 首先,在「提供基板」步驟1中,如第6A圖所示,提供 基板210’該基板210係具有一内表面211、一外表面212 以及在每一單元區内之至少一窗口 213,其中該外表面212 係設有複數個球墊214〇該内表面211為晶片設置面,而該 外表面212則為銲球設置面。「單元區」所指者為單顆封裝 構造的形成區域,通常一基板210在封裝製程中係一體構成 有複數個单元區》該基板210係具有一層以上的線路圖案, 可為硬質的印刷電路板或是軟質的電路薄膜。在本實施例 中’該些窗口 213可為周邊小窗口(peripheral small window) 並為對稱排列,可位於該基板210每一單元區之邊緣,該基 板210在每一單元區之中央區域更具有一中央槽孔215(或稱 為中央窗口)。更具體架構中,該些窗口 213係可位於兩平 行於該中央槽孔215之單元區側邊之中央。 之後’在「設置晶片」步驟2中,如第6B圖所示,設置 複數個晶片220於該基板210之内表面211。可利用一黏晶 層223黏貼該些晶片220之主動面至該内表面211。並使得 該些晶片220之周邊銲墊221與中央銲塾222分別顯露在該 些窗口 213與該中央槽孔215。 之後’在「電性連接」步驟3中,如第6C圖所示,可利 9 1334184 用打線技術形成複數個詳線230,其係通過該些窗口 213電 性連接該些晶片220之周邊銲墊221至該基板210;以及通 過該中央槽孔2 1 5電性連接該些晶片220之中央銲塾222至 該基板210。在本實施例中,每一窗口 213内可形成有至少 一銲線230。 之後,在「封膠」步驟4中,如第6D圖所示,可利用轉 移成型(transfer mold)技術形成至少一封膠體24〇,其係覆蓋 該基扳210之内表面211並填入該些窗口 213與該些中央槽 孔215。該封膠體240更形成有複數個稍突出於該外表面212 且對應於該些窗口 213之周邊突部241以及複數個對應於該 些中央槽孔215之中央突部242,以密封該些銲線23〇。然 而該封膠體240應不覆蓋該些球墊214。因此,在本實施例 中’該封膠體240係可密封該些晶片220與該些銲線230。 之後’在「形成助熔劑」步驟5中,如第6E圖所示,可 利用點印、網刷或鋼版印刷的方式形成一助熔劑25〇於該些 球塾214。該助熔劑250能降低銲球之熔點並能在回焊前沾 附銲球。 之後’在「植球」步驟6中’如第6F圖所示,藉由—植 球治具20,吸附複數個銲球26〇在對應吸球孔21之開口。 配合參閱第7圖,該些吸球孔2 1係設置於該植球治具2〇之 —平面22’並連通至一真空腔室(圖未繪出該植球治具 係更具有至少一位於該些周邊突部241上方之讓位槽23。如 第6G圖所示’當該植球治具2〇往該基板210壓合時,能避 免該植球治具20之平面22壓迫至該些周邊突部241上方。 10 1334184 因此,該些銲球260能順利設置於對應之該些球墊214上, 不會有位移與相互碰觸的情事在本實施例中,該植球治具 2〇更具有對應於每一單元區中央之中央凹槽24,以使該植 球治具20不會壓迫該封膠體24〇之中央突部242。而該讓位 槽23係可沿著該基板21 〇在單元區之間的切割道上方延伸。 最後,進行回銲步驟7,將已沾附有銲球26〇之該基板 21〇置入一回銲爐。如第6H圖所示,該些銲球26〇係以—1334184 IX. Description of the Invention: [Technical Field] The present invention relates to an integrated circuit sealing technique capable of significantly reducing a defective rate, particularly relating to a window type ball grid array sealing for improving ball bridging. [Prior Art] Ball bridging, or doubie ball, means that in the zinc backing process of the ball grid array packaging process, the original two adjacent solder balls are welded into one, resulting in a large soldering. The formation of the ball does not conform to the predetermined solder ball specifications, and the periphery of the large solder ball will leave an empty ball pad, which is a process defect. If the repair is mandatory, the ball needs to be refilled and re-returned. The repeated heat treatment affects the reliability of the product. Moreover, large solder balls that do not conform to the specifications are difficult to repair, resulting in non-planar surface bonding and stress imbalance, and it is easy to have false solder joints. Therefore, the defect rate caused by the ball bridging problem should be a necessary and necessary improvement project. As shown in Figures 1 and 2, a conventional window type ball grid array package mainly comprises a substrate 110, a wafer 120, a gel 14 〇, and a plurality of solder balls 160. Usually, the substrate 11 has a plurality of peripheral windows 111 (which can be called a small window) and a central slot! 13. A common wafer 12 is a dynamic random access memory chip such as DDR2 (double data transfer speed). The active surface of the wafer 120 is attached to the inner surface of the substrate u to expose the pad of the wafer 120 to the peripheral window of the substrate 11 and a central slot 113 for the plurality of bonding wires 13 to pass through and Electrically connected to the substrate 110. The encapsulant 140 is formed on the inner surface of the substrate 11 to seal the wafer 120, and has a plurality of 5 1334184 peripheral protrusions Hi and a central protrusion 142 protruding from the outer surface of the substrate 11 . Corresponding to the peripheral window ill and the central slot 113 respectively, to seal the fresh lines 13〇. A plurality of ball pads 112 are formed on the outer surface of the substrate 110. The solder balls 16 are attached to the (four) 112. However, there is a problem of ball bridging in the actual packaging process. As shown in Fig. 3, the phenomenon of so-called "ball bridging" usually occurs in the region close to the protrusions 141 and 142 of the encapsulant M0, in particular It is the area near the peripheral protrusion M1. There will be a small number of solderless ball pads 112 原 in the ball pad 112 that would otherwise be implanted, which is close to the peripheral protrusion 141. The periphery of the solderless ball pad 112 has a double solder ball 16 〇Α which has a larger ball diameter than the solder ball 160 of a predetermined size. This indicates that the solder ball on the original ball 塾 112Α is displaced, and the other solder ball is fused to the other solder ball 160 在 during reflow. Please refer to the previous paragraphs 7〇3 and 7〇4 of Figure 8 for the current window-type ball grid array packaging process. The defect rate due to ball bridging is about 600 to 1〇〇〇ΡΡΜ. , does not meet the expected non-: rate target value (" Ο PPM), resulting in packaging costs can not be reduced. In particular, with the evolution of advanced packaging processes, when the number of peripheral protrusions 141 of the encapsulant 14〇 increases, the defect rate of the ball bridge is more significantly increased and the repair process is clearly not accepted by the customer, so it is the primary solution. Question. As shown in Figure 4, after further analysis and research, it is found that the traditional, 'surface ball/0 1〇 is not suitable for advanced window type ball grid array packaging system. A plurality of suction holes are opened in a plane 12 to adsorb the solder balls 16 in the ball implantation step (^ and then the solder balls 16 are placed on the ball 塾 112 of the window array structure, in theory, each solder ball 1 6 0 6 1334184 should be adhered by the fluxing agent 5〇 on the corresponding ball pad 112. However, in practice, one part of the solder ball 160 is embedded in the suction hole u of the ball-fixing fixture. Moreover, the encapsulant 140 affects the warpage of the substrate 11 after curing, so the plane 12 of the ball fixture 10 will touch the peripheral protrusion 141 of the encapsulant 14〇, resulting in the placement of the solder ball. The solder balls partially close to the peripheral protrusions 141 may be displaced and in contact with each other, so that the double solder balls 160A as shown in FIG. 3 are melted during reflow, and the solderless ball pads n2A are also SUMMARY OF THE INVENTION The main object of the present invention is to provide a window type ball grid array packaging process capable of large Reducing the bad rate of ball bridging to meet the defect rate target value: The second object of the present invention is to provide a window type ball grid array encapsulation process that does not increase the ball bridge connection defect rate by the number of windows around the substrate. The purpose and solution of the technical problem are achieved by the following technical solutions. According to a window type ball grid array packaging process of the present invention, a substrate is first provided, the substrate having an inner surface, an outer surface and each unit At least one window in the area, wherein the outer surface is provided with a plurality of ball pads. Then, a plurality of wafers are disposed on the inner surface of the substrate, and the wafers are electrically connected to the substrate. Thereafter, at least a seal is formed. Covering the inner surface of the substrate and filling the window, the encapsulant is formed with at least one protrusion H (s) slightly protruding from the outer surface and corresponding to the window, formed by the ball pads, by a plant a ball fixture, a plurality of solder balls are disposed on the ball pads, the ball fixture has a plane with a plurality of suction holes and at least one 1 1334184 is located a retaining groove on the protrusion to prevent the ball-clamping tool from being pressed to the protrusion. Thereafter, a re-welding step is performed to fix the solder balls to the corresponding ball pad in a one-to-one connection. The purpose and the solution to the technical problem can be further achieved by the following technical measures. In the foregoing window type ball grid array packaging process, the depth of the yielding groove relative to the plane is not less than that of the suction holes. _ buried depth. In the foregoing window type ball grid array packaging process, the depth of the yielding groove relative to the plane may be not less than one third of the ball diameter of the solder balls. The window type ball grid array package described above In the process, the window can be a peripheral small window and arranged in a plurality of symmetric manners, and the substrate further has a central slot in each unit area. In the foregoing window type ball grid array packaging process, the windows The window system can be located in the center of the sides of the unit area parallel to the central slot. In the aforementioned window type ball grid array packaging process, the windows may be located at the corners of the corresponding cell area. In the above-described window type ball grid array packaging process, at least one bonding wire may be formed in each of the ® ports in the electrical connection step to electrically connect the wafer and the substrate. In the window π-type ball grid array packaging process, the encapsulation system can seal the wafers and the bonding wires. "In the description of the scalloped ball grid array encapsulation process, the entanglement slot system may extend along the scribe line between the cell regions along the substrate. [Embodiment] 8 1334184 According to the first embodiment of the present invention A window type ball grid array encapsulation process is disclosed. Referring to FIG. 5, the package structure mainly includes: "providing the substrate" step 1, "setting the wafer" step 2, "electrically connecting" step 3, "sealing" Glue Step 4, "Forming Flux" Step 5, "Balling" Step 6 and "Reflow" Step 7. First, in the "providing the substrate" step 1, as shown in FIG. 6A, the substrate 210' is provided. The substrate 210 has an inner surface 211, an outer surface 212, and at least one window 213 in each cell region, wherein The outer surface 212 is provided with a plurality of ball pads 214. The inner surface 211 is a wafer setting surface, and the outer surface 212 is a solder ball mounting surface. The "unit area" refers to a formation area of a single package structure. Generally, a substrate 210 is integrally formed with a plurality of unit areas in a packaging process. The substrate 210 has more than one line pattern and can be a hard printed circuit. The board is either a soft circuit film. In the embodiment, the windows 213 may be a peripheral small window and arranged symmetrically, and may be located at an edge of each unit area of the substrate 210. The substrate 210 has a central area in each unit area. A central slot 215 (or central window). In a more specific architecture, the windows 213 can be located in the center of the sides of the unit area that are parallel to the central slot 215. Thereafter, in the "set wafer" step 2, as shown in Fig. 6B, a plurality of wafers 220 are disposed on the inner surface 211 of the substrate 210. A die layer 223 can be adhered to the active surface of the wafers 220 to the inner surface 211. The peripheral pads 221 and the center solder pads 222 of the wafers 220 are exposed to the windows 213 and the central slot 215, respectively. Then, in step 3 of the "Electrical Connection", as shown in FIG. 6C, a plurality of detailed lines 230 are formed by the wire bonding technique, which are electrically connected to the peripheral portions of the wafers 220 through the windows 213. Pad 221 to the substrate 210; and electrically connecting the central solder pads 222 of the wafers 220 to the substrate 210 through the central slot 2 115. In the present embodiment, at least one bonding wire 230 may be formed in each of the windows 213. Thereafter, in the "sealing" step 4, as shown in FIG. 6D, at least one colloid 24 形成 can be formed by a transfer mold technique, which covers the inner surface 211 of the base 210 and fills in the The windows 213 are opposite to the central slots 215. The encapsulant 240 is further formed with a plurality of peripheral protrusions 241 protruding slightly from the outer surface 212 and corresponding to the windows 213 and a plurality of central protrusions 242 corresponding to the central slots 215 to seal the solders Line 23〇. However, the encapsulant 240 should not cover the ball pads 214. Therefore, in the present embodiment, the encapsulant 240 can seal the wafers 220 and the bonding wires 230. Thereafter, in step 5 of "forming a flux", as shown in Fig. 6E, a flux 25 may be formed on the balls 214 by means of dot printing, net brush or stencil printing. The flux 250 reduces the melting point of the solder balls and can adhere to the solder balls before reflow. Thereafter, in the "planting ball" step 6, as shown in Fig. 6F, a plurality of solder balls 26 are adsorbed to the opening of the corresponding suction hole 21 by the ball-clamping tool 20. Referring to FIG. 7 , the suction holes 21 are disposed on the plane 22' of the ball-fixing fixture and connected to a vacuum chamber (the figure is not depicted as having at least one The retaining groove 23 is located above the peripheral protrusions 241. As shown in Fig. 6G, when the ball-fixing tool 2 is pressed against the substrate 210, the plane 22 of the ball-fixing fixture 20 can be prevented from being pressed to Above the peripheral protrusions 241. 10 1334184 Therefore, the solder balls 260 can be smoothly disposed on the corresponding ball pads 214 without displacement and mutual contact. In this embodiment, the ball processing The second recess 24 has a central recess 24 corresponding to the center of each unit area, so that the ball fixture 20 does not press the central protrusion 242 of the sealant 24, and the retaining groove 23 can be along The substrate 21 is extended over the scribe line between the cell regions. Finally, a reflow step 7 is performed to place the substrate 21 to which the solder balls 26 are adhered into a reflow oven, as shown in Fig. 6H. , the solder balls 26 are tied to -

對一連接方式固著於該基板210對應之該些球墊214。 較佳地,上述讓位槽23相對於該平面22之深度係不小 。而「吸球嵌埋深度」約 。也就是說,該讓位槽23 於該些銲球260之球徑三 於該些吸球孔2 1之吸球嵌埋深度 為該些銲球260之球徑三分之一 相對於該平面22之深度係可不小 分之一。 在具體生產中可分析出利用習知製程與本發明之窗口型 球格陣列封裝製程兩者明顯差異。請參閱第8圖圖中7〇3 與704所表者為採用習知的製程所得到的球橋接不良率,介 於600至1000 PPM,圖中71〇、711、712與η]所表者為 採用本發明之窗口型球格陣列封裝製程所得到的球橋接不 良率,可大幅降低球橋接之不良率,介於〇至1〇〇聰,更 符合預定的不良率目標值(15G PPM卜本發明之功效至為昭 顯,符合先進積體電路封裝製造的利益與需求。 依據本發明之第二具體實施例,所揭示之—種 格陣列封裝製程與第一實施例所述者為相同,其製程步驟亦 如第5圖所示。-基板310係具有—内表面、一外表面3ιι 11 1334184 以及在每一單元區内之複數個窗口 312,装由 共中該外表面3 11 係設有複數個球墊(圖未繪出)。在本實施例中,每一單元區 之窗口 312數量多於第一具體實施例之窗口 213數量,可分 佈位於對應單元區之邊緣與角隅。該基板31〇更具有一中央 槽孔3 13。 'A pair of ball pads 214 corresponding to the substrate 210 are fixed to a connection. Preferably, the depth of the retaining groove 23 relative to the plane 22 is not small. And "sucking ball embedded depth" is about. In other words, the ball-sinking depth of the ball-slots 260 is less than the ball-hole diameter of the ball-sucking holes 260, and the ball-splitting depth of the balls 260 is one-third of the ball diameter of the solder balls 260 relative to the plane. The depth of 22 can be no less than one. Significant differences between the conventional process and the window type ball grid array package process of the present invention can be analyzed in a specific production. Please refer to the figure 7 to 3 and 704 in Figure 8 for the ball bridge failure rate obtained by the conventional process, between 600 and 1000 PPM, in the figure 71〇, 711, 712 and η] In order to adopt the window type ball grid array encapsulation process of the present invention, the ball bridging defect rate can greatly reduce the defect rate of the ball bridging, which is in the range of 〇 to 1〇〇聪, and more consistent with the predetermined defect rate target value (15G PPM) The effect of the present invention is obvious to meet the interests and needs of advanced integrated circuit package manufacturing. According to the second embodiment of the present invention, the disclosed array array packaging process is the same as that described in the first embodiment. The process steps are also as shown in Fig. 5. The substrate 310 has an inner surface, an outer surface 3 ι 11 11334184, and a plurality of windows 312 in each unit area, which are mounted on the outer surface 3 11 A plurality of ball pads are provided (not shown). In this embodiment, the number of windows 312 per unit area is larger than the number of windows 213 of the first embodiment, and may be distributed at the edge and corner of the corresponding unit area. The substrate 31 has a central slot 13. 3 '

在經過「設置晶片」步驟2、「電性連接」步驟3、「封膠 步驟4之後,一封膠體係覆蓋該基板31〇之内表面並填入該 些窗口 312’該封膠體並形成有複數個稍突出於該外表面 且對應於該些窗口 312之周邊突部341以及對應於該中央槽 孔3Π之中央突部342。利用如第7圖所示之植球治具2〇曰, 設置複數個銲ί求360於該基板3 10之球塾±,由於該植球治 具20不會壓迫至該些周邊突部34卜故在回銲步驟7中該 些銲球360能以一對一連接方式固著於對應之球墊。After the "set wafer" step 2, the "electrical connection" step 3, and the "sealing step 4, an adhesive system covers the inner surface of the substrate 31 and fills the windows 312' to form the sealant. a plurality of peripheral protrusions 341 slightly protruding from the outer surface and corresponding to the windows 312 and a central protrusion 342 corresponding to the central slot 3。. Using the ball-fixing fixture 2 shown in FIG. A plurality of solders are provided to the ball 3 of the substrate 3, and since the ball fixture 20 does not press to the peripheral protrusions 34, the solder balls 360 can be used in the reflow step 7 A connection is fixed to the corresponding ball pad.

由上述可知,第一具體實施例在每一單元區内之窗口 Si] 數量间於第-具體實施例。然:而,經統計其球橋接不良率卻 不會如同1知製程隨之等比昇高,故本發明之另—功效即為 窗口 312之數量增加而不會等比例增加球橋接之不良率。 此外,本發明之窗口型球格陣列封裝製程並不局限窗口 的位置與數量’亦可運用至傳統無周邊小窗口的窗口型球格 陣列封裝構造。如第1G圖所示,與第二具體實施例中第9 圖的’·。構比較’僅省略了周邊小窗口 312及周邊突部⑷, 故2件圖號沿用之…基板31G具有—中央槽孔313(或稱中 央由口)同樣地’在該基板31〇之内表面設有一晶片並形 成封膠體(圖未緣出),封膠體具有一中央突部342,其係 12 1334184 突出於該基板31〇之外表面311並填滿該中央槽孔3i3。複 數個薛球360係設於該基板31G之外表面311。利用本發明 之本發明之窗口型球格陣列封裝製程在製造上述之窗口型 球格陣列封裝構造亦能大幅降低球橋接之不良率。 以上所述,僅是本發明的較佳實施例而已,並非對本發 明作任何形式上的限制,本發明技術方案範圍當依所附申請 專利範圍為準。任何熟悉本專㈣技術人員可㈣上述揭示 的技術内容作出些許更動或修飾為等同變化的等效實施 例’但凡是未脫離本發明技術方案的内容,依據本發明的技 術實質對以上實施例所作的任何簡單修改、等同變化盥 飾,均仍屬於本發明技術方案的範圍内。 ^ 【圖式簡單說明】 第1圖:習知窗口型球格陣列封裝構造之截面示意圖。 =2圖:習知窗口型球格陣列封裝構造之基板外表面示意圖。 第U知h型球格陣列封裝構造發生球橋接之局部立 體示意圖。 第4圖.習知窗口型球格陣列封裝構造在植球時與植球治具 之截面示意圖。 、 種窗口型球格陣列 第5圖:依據本發明之-具體實施例, 封裝之製造流程圖。 第^至阳圖:依據本發明之窗口型球格陣列封裝製程之 一基板截面圖。 第7圖.依據本發明之一且I*. &amp; 具體實施例,所使用之植球治呈之 立體示意圖。 〃 13 1334184 第8圖:本發明之窗口型球格陣列封裝製程相對於習知製程 由球橋接引起不良率比較對照表β 第9圖:依據本發明之窗口型球格陣列封裝製程另一種可 運用之窗口型球格陣列封裝構造之基板外表面示 意圖。 第圖··依據本發明之窗π型球格陣列封裝製程,另一種 可運用之窗口型球格陣列封裝構造之基板外表面 不意圖。 【主要元件符號說明】 1 提供基板 2 設置晶片 3 電性連接 4 封膠 5 形成助·溶劑 6 植球 7 回銲 10 植球治具 11 吸球孔 12 平面 20 植球治具 21 吸球孔 22 平面 23 讓位槽 24 中央凹槽 110 基板 111 窗口 112 球墊 112Α無銲球球墊 113 中央槽孔 120 晶片 130 銲線 140 封膠體 141 周邊突部 142 中央突部 150 助熔劑 160 銲球 160Α雙重銲球 14 1334184 210 基板 211 内表面 212 外表面 213 窗口 214 球墊 215 中央槽孔 220 晶片 221 週邊銲墊 222 中央銲墊 223 黏晶層 230 銲線 240 封膠體 241 周邊突部 242 中央突部 250 助熔劑 260 銲球 310 基板 311 外表面 312 窗口 313 中央槽孔 341 周邊突部 342 中央突部 360 銲球 15From the above, it can be seen that the first embodiment has a number of windows Si] in each cell region in the first embodiment. However, by statistically, the ball bridge failure rate is not as high as that of the known process, so the other effect of the present invention is that the number of windows 312 is increased without increasing the ball bridge connection rate. . In addition, the window type ball grid array package process of the present invention is not limited to the position and number of windows, and can be applied to a conventional window type grid array package structure without a peripheral small window. As shown in Fig. 1G, and in the ninth drawing of the second embodiment. The structure comparison 'only the peripheral small window 312 and the peripheral protrusions (4) are omitted, so the two pieces of the figure are used... the substrate 31G has a central slot 313 (or a central port) similarly 'on the inner surface of the substrate 31' A wafer is formed and formed into a sealant (not shown). The sealant has a central protrusion 342 which protrudes from the outer surface 311 of the substrate 31 and fills the central slot 3i3. A plurality of Xue balls 360 are disposed on the outer surface 311 of the substrate 31G. The window type ball grid array package process of the present invention of the present invention can also greatly reduce the defective rate of ball bridge in the fabrication of the above-described window type ball grid array package structure. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. The technical scope of the present invention is subject to the scope of the appended claims. Any person skilled in the art (4) may make a slight modification or modification to the equivalent embodiment of the technical content disclosed above. However, without departing from the technical solution of the present invention, the above embodiments are made according to the technical essence of the present invention. Any simple modification or equivalent modification is still within the scope of the technical solution of the present invention. ^ [Simple description of the figure] Fig. 1 is a schematic cross-sectional view of a conventional window type grid array package structure. = 2 picture: Schematic diagram of the outer surface of the substrate of the conventional window type ball grid array package structure. The U-shaped h-type ball grid array package structure is a partial schematic diagram of the ball bridge. Fig. 4 is a schematic cross-sectional view showing a conventional window type lattice array package structure at the time of ball implantation and a ball-fixing fixture. Window Type Grid Array Figure 5: Manufacturing flow diagram of a package in accordance with an embodiment of the present invention. Fig. 4 is a cross-sectional view of a substrate of a window type lattice array package process in accordance with the present invention. Fig. 7 is a perspective view showing the use of a ball in accordance with one of the present invention and the I*. &amp; specific embodiment. 〃 13 1334184 Fig. 8: Comparison of the defect rate caused by the ball bridge in the window type ball grid array package process of the present invention compared with the conventional process. FIG. 9 is a view of the window type ball grid array package process according to the present invention. Schematic diagram of the outer surface of the substrate using the window type grid array package structure. Fig. </ RTI> According to the window π-type ball grid array encapsulation process of the present invention, another applicable outer surface of the substrate of the window type ball grid array package structure is not intended. [Main component symbol description] 1 Provide substrate 2 Set wafer 3 Electrical connection 4 Sealant 5 Form help solvent 6 Ball 7 Reflow 10 Ball fixture 11 Sucker hole 12 Plane 20 Ball fixture 21 Sucker hole 22 Plane 23 Retaining groove 24 Central groove 110 Substrate 111 Window 112 Ball pad 112 Α Solderless ball pad 113 Central slot 120 Wafer 130 Bond wire 140 Encapsulant 141 Peripheral protrusion 142 Central protrusion 150 Flux 160 Solder ball 160Α Double solder ball 14 1334184 210 substrate 211 inner surface 212 outer surface 213 window 214 ball pad 215 central slot 220 wafer 221 peripheral pad 222 central pad 223 bonding layer 230 bonding wire 240 encapsulant 241 peripheral protrusion 242 central protrusion 250 Flux 260 solder ball 310 substrate 311 outer surface 312 window 313 central slot 341 peripheral protrusion 342 central protrusion 360 solder ball 15

Claims (1)

1334184 十、申請專利範面: 1、一種窗口型球格陣列封裝製程,包含: 提供一基板’該基板係具有一内表面、一外表面以及在 每一單元區内之至少一窗口,其中該外表面係設有複數 個球墊; 設置複數個晶片於該基板之内表面; 電性連接該些晶片至該基板;1334184 X. Patent application plane: 1. A window type ball grid array packaging process, comprising: providing a substrate having an inner surface, an outer surface, and at least one window in each unit area, wherein The outer surface is provided with a plurality of ball pads; a plurality of wafers are disposed on the inner surface of the substrate; and the wafers are electrically connected to the substrate; 形成至少一封膠體,其係覆蓋該基板之内表面並填入該 ©口,該封膠體並形成有至少一稍突出於該外表面且對 應於該窗口之突部; 形成一助嫁劑於該些球塾; 藉由一植球治具,設置複數個銲球於該些球墊上,該植 球治具係具有一設有複數個吸球孔之平面以及至少一位 於該大部上之讓位槽,以避免該植球治具壓迫至該突 部;以及Forming at least one colloid covering the inner surface of the substrate and filling the opening, the encapsulant being formed with at least one protrusion slightly protruding from the outer surface and corresponding to the window; forming a parenting agent a ball ball; a plurality of solder balls are disposed on the ball pads by a ball fixture, the ball fixture having a plane having a plurality of suction holes and at least one of the plurality of holes a groove to prevent the ball fixture from being pressed to the protrusion; 進行1銲步驟,以使該些銲球以—對一連接方式 於對應之該些球塾。 2、 如申請專利範圍第1項所述之窗口型球格陣列封袭製 程,其中該讓位槽相對於該平面之深度係不小於該此吸 球孔之吸球嵌埋深度。 通二及 3、 如申請專利範圍第丨 甘丄 項所述之固口型球格陣列封穿劁 程,其中該讓位槽相對於該、 球之球徑三分之… 於該些銲 4、 如申請專利範圍第丨 項所述之由口型球格陣列封裝製 16 其中該_ 口係為周邊小窗口,並為複數個對稱排列, 而該基板更具有在每一單元區内之一中央槽孔。 如申叫專利範圍第4項所述之窗口型球格陣列封裝製 程其中該些窗口係位於兩平行於該中央槽孔之單元區 側邊之中央。 6、如申請專利範圍第4項所述之窗口型球格陣列封裝製 程,其中該些窗口係位於對應單元區之角隅。 鲁中請專利H圍第i項所述之窗口型球格陣列封裝製 程,其中在電性連接步驟中’每一窗口内形成有至少一 銲線,以電性連接該晶片與該基板。 申-月專利範圍第7項所述之窗D型球格陣列封裝製 程,其中該封膠體係密封該些晶片與該些鲜線。 請專利範圍第i項所述之窗σ型球格陣列封裝製 程,其中該讓位槽係、沿著該基板在單元區之間的 上方延伸。 17A soldering step is performed to cause the solder balls to be connected in a corresponding manner to the corresponding balls. 2. The window type ball grid array sealing process according to claim 1, wherein the depth of the yielding groove relative to the plane is not less than the depth of the suction ball of the suction hole. Tong 2 and 3, as described in the patent application section 丨 丄 之 之 之 球 球 球 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , as described in the scope of the patent application, the lip-shaped array of the package 16 wherein the _ port is a peripheral small window, and is a plurality of symmetrically arranged, and the substrate has one of each unit area Central slot. The window type ball grid array packaging process of claim 4, wherein the windows are located at the center of the side of the unit area parallel to the central slot. 6. The window type ball grid array packaging process of claim 4, wherein the windows are located at corners of the corresponding unit area. In the window type ball grid array encapsulation process described in the above-mentioned item, in the electrical connection step, at least one bonding wire is formed in each window to electrically connect the wafer and the substrate. The window D-type ball grid array packaging process of claim 7, wherein the encapsulation system seals the wafers and the fresh lines. The window sigma type ball grid array packaging process of claim i, wherein the yielding trench extends along the substrate between the cell regions. 17
TW096116177A 2007-05-07 2007-05-07 Fabricating process for window bga packages to improve ball bridging TWI334184B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW096116177A TWI334184B (en) 2007-05-07 2007-05-07 Fabricating process for window bga packages to improve ball bridging

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW096116177A TWI334184B (en) 2007-05-07 2007-05-07 Fabricating process for window bga packages to improve ball bridging

Publications (2)

Publication Number Publication Date
TW200845242A TW200845242A (en) 2008-11-16
TWI334184B true TWI334184B (en) 2010-12-01

Family

ID=44209812

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096116177A TWI334184B (en) 2007-05-07 2007-05-07 Fabricating process for window bga packages to improve ball bridging

Country Status (1)

Country Link
TW (1) TWI334184B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI406377B (en) * 2010-12-27 2013-08-21 Powertech Technology Inc Ball grid array package with three-dimensional pin 1 mark and its manufacturing method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8378476B2 (en) * 2010-03-25 2013-02-19 Stats Chippac Ltd. Integrated circuit packaging system with stacking option and method of manufacture thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI406377B (en) * 2010-12-27 2013-08-21 Powertech Technology Inc Ball grid array package with three-dimensional pin 1 mark and its manufacturing method

Also Published As

Publication number Publication date
TW200845242A (en) 2008-11-16

Similar Documents

Publication Publication Date Title
US7816183B2 (en) Method of making a multi-layered semiconductor device
TWI311352B (en) Fabricating process of leadframe-based bga packages and leadless leadframe utilized in the process
JP5227501B2 (en) Stack die package and method of manufacturing the same
TW200416787A (en) Semiconductor stacked multi-package module having inverted second package
TWI245392B (en) Leadless semiconductor package and method for manufacturing the same
TW200939421A (en) Multi-window ball grid array package
TWI278079B (en) Pillar grid array package
TWI334184B (en) Fabricating process for window bga packages to improve ball bridging
TW200807682A (en) Semiconductor package and method for manufacturing the same
JP5547703B2 (en) Manufacturing method of semiconductor device
JP2007221045A (en) Semiconductor device employing multi-chip structure
US20030180988A1 (en) Semiconductor device and method of manufacturing the same
TW201025554A (en) Multiple flip-chip package
TWI355731B (en) Chips-between-substrates semiconductor package and
TWI288463B (en) Semiconductor package substrate and semiconductor package having the substrate
TWI250623B (en) Chip-under-tape package and process for manufacturing the same
TWI417039B (en) Semiconductor package for improving ground connection of electromagnetic shielding layer
TWI250597B (en) Method for manufacturing multi-chip package having encapsulated bond-wires between stack chips
TWI501379B (en) Pop device with co-used encapsulant
TWI801483B (en) Package structure of simple circuit board and chip
JP2001332681A (en) Semiconductor device
US20130264714A1 (en) Semiconductor device and method of assembling same
TWI326907B (en) Ball grid array package for preventing mold flash
TWI337393B (en) Bga packaging method and bga package
TWI581383B (en) Semiconductor chip package having double sided ball planting and the method for fabricating the same