TW200845242A - Fabricating process for window BGA packages to improve ball bridging - Google Patents

Fabricating process for window BGA packages to improve ball bridging Download PDF

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Publication number
TW200845242A
TW200845242A TW096116177A TW96116177A TW200845242A TW 200845242 A TW200845242 A TW 200845242A TW 096116177 A TW096116177 A TW 096116177A TW 96116177 A TW96116177 A TW 96116177A TW 200845242 A TW200845242 A TW 200845242A
Authority
TW
Taiwan
Prior art keywords
ball
window
substrate
grid array
solder balls
Prior art date
Application number
TW096116177A
Other languages
Chinese (zh)
Other versions
TWI334184B (en
Inventor
Yi-Hsin Chuang
Yung-Hsiang Chen
Ping-Hua Chu
Original Assignee
Walton Advanced Eng Inc
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Filing date
Publication date
Application filed by Walton Advanced Eng Inc filed Critical Walton Advanced Eng Inc
Priority to TW096116177A priority Critical patent/TWI334184B/en
Publication of TW200845242A publication Critical patent/TW200845242A/en
Application granted granted Critical
Publication of TWI334184B publication Critical patent/TWI334184B/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0612Layout
    • H01L2224/0615Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06154Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/06155Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0612Layout
    • H01L2224/0615Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06154Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/06156Covering only the central area of the surface to be connected, i.e. central arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

Disclosed is a fabricating process for window BGA packages. Initially, a substrate is provided, which has at least a window in each unit. Passing through die-attachment, electrical connection and encapsulation, an encapsulant is formed and has a plurality of protrusions aligned with the windows. Next, a flux is disposed on the ball pads of the substrate. Utilizing a ball-mounting jig, a plurality of solder balls are placed on the ball pads, where the jig has a plurality of suction holes in a plane and a get-in groove located above the protrusions to prevent from stress from the jig. Accordingly, each of the solder balls will be fixed on the corresponding one of the ball pads with one to one connection during reflowing so that the reject radio of ball bridging will be reduced dramatically.

Description

200845242 九、發明說明: 【發明所屬之技術領域】 本發明係有關於能明顯降低不良率之積體電路封裝技 術,特別係有關於一種改善球橋接之窗口型球格陣 程。 衣 【先前技術】 球橋接(ball bridging) ’或稱雙重球(d〇uMe baU),是指在 球格陣列封裝製程之回銲步驟巾,原本相鄰兩銲球炼接成一 f 顆了一 固大銲S的形纟,與預定的鲜球規格不相符 2 ’而大銲S的周邊更會留下一個空球塾,屬於製程缺陷。 右強制進行修補,則需要補球與再回銲,重覆的熱處理影響 了產品可靠度。並且,不符規格的大銲球甚難修補,會造成 非平面的表面接合與應力不平衡,容易有假焊點發生。因 此,球橋接問題引起的不良率應作確實且必要的改善工程。 如第1及2圖所示,一種習知的窗口型球格陣列封裝構 ( 造主要包含一基板110、一晶片120、一封膠體140以及複 數個銲球160。通常該基板11〇係具有複數個周邊窗口 1 u(可稱為small window)與一中央槽孔113。常見的晶片12〇 係為動態隨機存取記憶體晶片,如DDR2(雙倍資料傳輸速 度)。該晶片120之主動面貼附於該基板11〇之内表面,而 使邊晶片120之銲墊外露於該基板丨丨〇之周邊窗口 u丨與一 中央槽孔113,以供複數條銲線130通過並電性連接至該基 板110。而該封膠體140除了形成在該基板u〇之内表面以 密封該晶片120,更會具有突出於該基板11〇外表面之複數 5 200845242 個=邊突部141與一中央突部142,其係分別對應於該些周 邊窗口 111與該中央槽孔113,以密封該些銲線13〇。該基 板110之外表面形成有複數個球墊112。該些銲球16〇係固 著於該些球墊112。然而在實際封裝製程中會有球橋接的問 題。 如第3圖所示,經分析,所謂「球橋接」的現象通常發 生在接近該封膠體140之突部141與142之區域,特別是接 近周邊突部141的區域。原本皆應植球之球墊丨丨2中會有少 ί 數的無銲球球墊112Α,其係接近周邊突部141。而無銲球球 墊112Α之周邊更會產生了一雙重銲球16〇Α,其球徑大於一 般所預定規格之銲球160。這表示了原本在無銲球球墊η2Α 上的銲球有位移的現象,並在回銲時與另一銲球熔合成上述 雙重銲球160Α。請參閱第8圖之前半部7〇3與7〇4所表示 者,為目前依據習知的窗口型球格陣列封裝製程,因球橋接 引起的不良率約介於600至1〇〇〇 ΡΡΜ,並不符合預計的不 〇 良率目標值(150 PPM),導致封裝成本無法降低。特別是隨 著先進封裝製程的演進,當該封膠體14〇之周邊突部141之 數量會增加’球橋接的不良率更加明顯昇高,並且修補製程 已明確不被客戶所接受,故為首要解決的課題。 如第4圖所示,經過了進一步分析與研究,發現傳統的 平面植球治具10不適用於先進的窗口型球格陣列封裝製 程。習知的植球治具10係在一平面12開設複數個吸球孔 11,以在植球步驟中吸附銲球160。再將銲球160放置在窗 口型球格陣列封裝構造之球墊112,在理論上,每一銲球16〇 6 200845242 應被對應球墊112上的助熔劑丨50所沾附。然而,在實際上, 銲球160之一部份會嵌入該植球治具1〇之吸球孔u,又該 封膠體1 40在固化後會影響該基板丨丨〇之翹曲度,所以該植 球治具10之平面12會碰觸到該封膠體14〇之周邊突部 141,導致在放置銲球時,部分接近該周邊突部141之銲球 會有位移與相互接觸之情事,故而在回銲時會熔合成如第\ 圖所示的雙重銲球160A,而該些無銲球球墊U2a也將因此 而生。 Γ 【發明内容】 本發明之主要目的係在於提供一種窗口型球格陣列封裝 製程,能大幅降低球橋接之不良率,以符合不良率目標值。 本發明之次一目的係在於提供一種窗口型球格陣列封裝 製程,不會受到基板周邊窗口之數量而增加球橋接之不良 率。 本發明的目的及解決其技術問題是採用以下技術方案來 I 實現的。依據本發明之一種窗口型球袼陣列封裝製程,首先 、提供一基板,該基板係具有一内表面、一外表面以及在每一 單元區内之至少一窗口,其中該外表面係設有複數個球墊。 之後,設置複數個晶片於該基板之内表面。並電性連接該些 晶片至該基板。之後,形成至少一封膠體,其係覆蓋該基板 之内表面並填入該窗口,該封膠體並形成有至少一稍突出於 該外表面且對應於該窗口之突部。當一助熔劑形成於該些球 墊之後,籍由一植球治具,設置複數個銲球於該些球墊上, 該植球治具係具有一設有複數個吸球孔之平面以及至少一 7 200845242 以避免該植球治具壓迫至該突部。 以使該些銲球以一對一連接方式固 位於該突部上之讓位槽, 之後,進行一回銲步驟, 著於對應球墊。 以下技術措施 本發明的目的及紐、、五甘# J次解决其技術問題還可採用 進一步實現。 在前述的窗Π型球格陣列封裝製程中,該讓位槽相對於 該平面之深錢不小於該些吸球孔线球欲埋深度。 Ο 1: 在前述的窗口型球格陣列封裝製程中,該讓位槽相對於 該平面之深度係以小於該些銲球之球徑三分之一。 在前述的窗Π型球格陣列封裝製程中,該窗口係可為周 邊小窗Π,並為複數個對稱排列,而該基板更具有在每一單 元區内之一中央槽孔。 在前述的窗口型球格陣列封裝製程中,該些窗口係可位 於兩平行於該中央槽孔之單元區侧邊之中央。 在前述的窗口型球格陣列封裝製程中,該些窗口係可位 於對應單元區之角隅。 在前述的窗口型球格陣列封裝製程中,在電性連接步驟 中,每一窗口内可形成有至少一銲線,以電性連接該晶片與 該基板。 在前述的窗口型球格陣列封裝製程中,該封膠體係可密 封該些晶片與該些銲線。 在前述的窗口型球格陣列封裝製程中,該讓位槽係可沿 著該基板在單元區之間的切割道上方延伸。 【實施方式】 8 200845242 依據本發明之第一具體實施例,揭示一種窗口型球格陣 列封裝製程。請參閱第5圖所示,該封裝製程主要包含:「提 供基板」步驟1、「設置晶片」步驟2、「電性連接」步驟3、 「封膠」步驟4、「形成助熔劑」步驟5、「植球」步驟6以 及「回銲」步驟7。 首先’在「提供基板」步驟1中,如第6A圖所示,提供 一基板210,該基板21〇係具有一内表面211、一外表面212 以及在每一單元區内之至少一窗口 213,其中該外表面212 ( 係設有複數個球墊214。該内表面211為晶片設置面,而該 外表面212則為銲球設置面。「單元區」所指者為單顆封裝 構造的形成區域,通常一基板210在封裝製程中係一體構成 有複數個單元區。該基板210係具有一層以上的線路圖案, 可為硬質的印刷電路板或是軟質的電路薄膜。在本實施例 中’該些窗口 213可為周邊小窗口(peripheral small window) 並為對稱排列,可位於該基板210每一單元區之邊緣,該基 I 板2 10在每一單元區之中央區域更具有一中央槽孔215(或稱 為中央窗口)。更具體架構中,該些窗口 213係可位於兩平 行於該中央槽孔215之單元區側邊之中央。 之後’在「設置晶片」步驟2中,如第6B圖所示,設置 複數個晶片220於該基板210之内表面211。可利用一黏晶 層223黏貼該些晶片220之主動面至該内表面211。並使得 該些晶片220之周邊銲墊221與中央銲墊222分別顯露在該 些窗口 213與該中央槽孔215。 之後,在「電性連接」步驟3中,如第6C圖所示,可利 9 200845242 用打線技術形成複數個銲線230,其係通過該些窗口 2i3電 性連接該些晶片220之周邊銲墊22〗至該基板21〇;以及通 過該中央槽孔215電性連接該些晶片220之中央銲墊222至 該基板210。在本實施例中,每一窗口 213内可形成有至少 一銲線230。 之後,在「封膠」步驟4中,如第6D圖所示,可利用轉 移成型(transfer mold)技術形成至少一封膠體24〇,其係覆蓋 、 該基板21〇之内表面211並填入該些窗口 213與該些中央槽 f 孔21 5。該封膠體240更形成有複數個稍突出於該外表面2i2 且對應於該些窗口 213之周邊突部241以及複數個對應於該 , 些中央槽孔215之中央突部242,以密封該些鮮線230。然 而該封膠體240應不覆蓋該些球墊214。因此,在本實施例 中,該封膠體240係可密封該些晶片22〇與該些銲線23〇。 之後,在「形成助熔劑」步驟5中,如第6E圖所示,可 利用點印、網刷或鋼版印刷的方式形成一助熔劑25〇於該些 〇 球墊214。該助熔劑250能降低銲球之熔點並能在回焊前沾 附輝球。 之後,在「植球」步驟6中,如第6F圖所示,藉由一植 球治具20,吸附複數個銲球26〇在對應吸球孔以之開口。 配合參閱第7圖,該些吸球孔21係設置於該植球治具⑽之 —平面22,並連通至一真空腔室(圖未繪出)。該植球治具2〇 係更具有至少一位於該些周邊突部241上方之讓位槽23。如 第6G圖所示,當該植球治具2〇往該基板21〇壓合時,能避 免該植球治具20之平面22壓迫至該些周邊突部241上方。 10 200845242 因此’該些銲ί求260能順利言史置於對應之該些球塾2i4上, 不會有位移與相互碰觸的情事。在本實施例中,該植球治具 20更具有對應於每-單元區中央之中央凹# 24,以使該植 球治具20不會壓迫該封膠體24〇之中央突部⑷。而該讓位 槽23係可沿著該基板21〇在單元區之間的切割道上方延伸。 最後’進行回銲步驟7,將已沾附有銲球260之該基板 210置入一回銲爐。如第6H圖所示,該些銲球260係以一 對連接方式固著於該基板21〇對應之該些球塾川。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit packaging technology capable of significantly reducing a defective rate, and more particularly to a window type ball grid array for improving ball bridging. [Previous technology] Ball bridging, or double ball (d〇uMe baU), refers to the reflow step towel in the ball grid array packaging process. The original two adjacent solder balls are welded into one f. The shape of the solid welding S does not match the predetermined size of the fresh ball 2 'and the periphery of the large welding S will leave an empty ball 塾, which is a process defect. If the right is forced to be repaired, the ball needs to be refilled and re-returned. The repeated heat treatment affects the reliability of the product. Moreover, large solder balls that do not conform to the specifications are difficult to repair, resulting in non-planar surface bonding and stress imbalance, and it is easy to have false solder joints. Therefore, the defect rate caused by the ball bridging problem should be a necessary and necessary improvement project. As shown in FIGS. 1 and 2, a conventional window type ball grid array package mainly includes a substrate 110, a wafer 120, a gel 140, and a plurality of solder balls 160. Typically, the substrate 11 has A plurality of peripheral windows 1 u (which can be called a small window) and a central slot 113. A common wafer 12 is a dynamic random access memory chip such as DDR2 (double data transmission speed). The surface is attached to the inner surface of the substrate 11 , and the pad of the edge wafer 120 is exposed to the peripheral window 丨 of the substrate 丨 and a central slot 113 for the plurality of bonding wires 130 to pass through and electrically The sealing body 140 is formed on the inner surface of the substrate u to seal the wafer 120, and further has a plurality of 5 200845242 = edge protrusions 141 and one protruding from the outer surface of the substrate 11 The central protrusions 142 respectively correspond to the peripheral windows 111 and the central slot 113 to seal the bonding wires 13A. The outer surface of the substrate 110 is formed with a plurality of ball pads 112. The solder balls 16 The tether is fixed to the ball pads 112. However, in actual packaging There is a problem of ball bridging in the process. As shown in Fig. 3, after analysis, the phenomenon of "ball bridging" usually occurs in a region close to the projections 141 and 142 of the encapsulant 140, particularly the region close to the peripheral projection 141. In the original ball ball 丨丨 2, there will be a small number of non-welding ball pads 112 Α, which are close to the peripheral protrusion 141. The outer edge of the non-welding ball pad 112 更 will produce a double welding. The ball is 16 inches, and its ball diameter is larger than the ball 160 of the general predetermined specification. This indicates that the solder ball originally on the solder ball pad η2Α is displaced, and is melted with another ball during reflow. The above double solder ball 160Α. Please refer to the front half of Fig. 8 7〇3 and 7〇4. For the current window type ball grid array packaging process, the defect rate due to ball bridging is about 600. To 1〇〇〇ΡΡΜ, it does not meet the expected target rate of unsuccessful yield (150 PPM), which leads to the inability to reduce the cost of packaging. Especially with the evolution of advanced packaging processes, when the sealing body 14 〇 peripheral protrusion 141 The number will increase 'the bad rate of ball bridging is more obvious And the repair process has been clearly accepted by customers, so it is the primary problem. As shown in Figure 4, after further analysis and research, it is found that the traditional flat ball fixture 10 is not suitable for advanced window balls. The array ball-carrying process 10 has a plurality of suction holes 11 in a plane 12 for adsorbing the solder balls 160 in the ball-planting step. The solder balls 160 are then placed in the window-type ball grid array package. The ball pad 112 is constructed. In theory, each solder ball 16〇6 200845242 should be adhered by the flux crucible 50 on the corresponding ball pad 112. However, in practice, one part of the solder ball 160 is embedded in the suction hole u of the ball fixture, and the seal body 140 affects the warpage of the substrate after curing, so The plane 12 of the ball-fixing fixture 10 touches the peripheral protrusion 141 of the sealing body 14〇, so that when the solder ball is placed, the solder balls which are partially close to the peripheral protrusion 141 may be displaced and contact with each other. Therefore, during the reflow, the double solder balls 160A as shown in Fig. 1 are melted, and the solderless ball pads U2a will also be born. SUMMARY OF THE INVENTION The main object of the present invention is to provide a window type ball grid array packaging process which can greatly reduce the defect rate of ball bridge to meet the target value of the defect rate. A second object of the present invention is to provide a window type ball grid array package process which does not increase the ball bridge connection defect rate by the number of windows around the substrate. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. According to a window type dome array packaging process of the present invention, first, a substrate is provided, the substrate having an inner surface, an outer surface, and at least one window in each unit region, wherein the outer surface is provided with a plurality of Ball mats. Thereafter, a plurality of wafers are disposed on the inner surface of the substrate. And electrically connecting the wafers to the substrate. Thereafter, at least one colloid is formed which covers the inner surface of the substrate and fills the window, and the encapsulant is formed with at least one protrusion slightly protruding from the outer surface and corresponding to the window. After a flux is formed on the ball pads, a plurality of solder balls are disposed on the ball pads by a ball fixture, and the ball fixture has a plane with a plurality of suction holes and at least one 7 200845242 to avoid pressing the ball fixture to the protrusion. The solder balls are fixed to the landing grooves on the protrusions in a one-to-one connection manner, and then a reflow step is performed on the corresponding ball pads. The following technical measures can be further achieved by the purpose of the present invention and the technical problems of New Zealand and Wugan #J times. In the foregoing window lattice type ball grid array packaging process, the depth of the yielding slot relative to the plane is not less than the depth of the suction ball. Ο 1: In the foregoing window type ball grid array packaging process, the depth of the yielding groove with respect to the plane is less than one third of the ball diameter of the solder balls. In the foregoing window lattice type ball grid array packaging process, the window may be a small window 周 and arranged in a plurality of symmetric directions, and the substrate further has a central slot in each cell area. In the aforementioned window type ball grid array packaging process, the windows may be located at the center of the side of the cell region parallel to the central slot. In the aforementioned window type ball grid array packaging process, the windows may be located at the corners of the corresponding cell area. In the foregoing window type ball grid array packaging process, in the electrical connection step, at least one bonding wire may be formed in each window to electrically connect the wafer and the substrate. In the aforementioned window type ball grid array packaging process, the encapsulation system can seal the wafers and the bonding wires. In the aforementioned window type ball grid array packaging process, the yielding trenches may extend over the dicing streets between the cell regions along the substrate. [Embodiment] 8 200845242 According to a first embodiment of the present invention, a window type ball grid array encapsulation process is disclosed. Please refer to FIG. 5, the package process mainly includes: "providing the substrate" step 1, "setting the wafer" step 2, "electrically connecting" step 3, "sealing" step 4, "forming the flux" step 5 Step 6 of "Balling the Ball" and Step 7 of "Reflow". First, in the "providing the substrate" step 1, as shown in FIG. 6A, a substrate 210 is provided. The substrate 21 has an inner surface 211, an outer surface 212, and at least one window 213 in each unit area. The outer surface 212 is provided with a plurality of ball pads 214. The inner surface 211 is a wafer mounting surface, and the outer surface 212 is a solder ball mounting surface. The "unit area" refers to a single package structure. Forming a region, usually a substrate 210 is integrally formed with a plurality of unit regions in a packaging process. The substrate 210 has more than one line pattern, which may be a hard printed circuit board or a soft circuit film. In this embodiment The windows 213 may be a peripheral small window and arranged symmetrically, and may be located at the edge of each unit area of the substrate 210. The base I board 20 has a central portion in the central area of each unit area. a slot 215 (or a central window). In a more specific architecture, the windows 213 can be located in the center of the side of the unit area parallel to the central slot 215. Then in the "set wafer" step 2, As in section 6B As shown, a plurality of wafers 220 are disposed on the inner surface 211 of the substrate 210. A die layer 223 can be used to adhere the active faces of the wafers 220 to the inner surface 211, and the peripheral pads 221 of the wafers 220 are The central solder pads 222 are respectively exposed to the windows 213 and the central slot 215. Thereafter, in the "electrical connection" step 3, as shown in FIG. 6C, a plurality of soldering wires 230 are formed by the wire bonding technique. And connecting the peripheral pads 22 of the wafers 220 to the substrate 21 through the windows 2i3; and electrically connecting the central pads 222 of the wafers 220 to the substrate 210 through the central slots 215 In this embodiment, at least one bonding wire 230 may be formed in each window 213. Thereafter, in the "sealing" step 4, as shown in FIG. 6D, at least a transfer mold technique may be used to form at least a colloid 24 覆盖 covers the inner surface 211 of the substrate 21 and fills the windows 213 and the central slots f 215. The encapsulant 240 is further formed with a plurality of protrusions slightly protruding from the outer surface. 2i2 and corresponding to the peripheral protrusions 241 of the windows 213 And a plurality of central protrusions 242 corresponding to the central slots 215 to seal the fresh lines 230. However, the seal body 240 should not cover the ball pads 214. Therefore, in this embodiment, the seals The colloid 240 can seal the wafers 22 and the bonding wires 23〇. Thereafter, in the “forming flux” step 5, as shown in FIG. 6E, a dot printing, a net brush or a stencil printing method can be used. A flux 25 is formed on the ball pads 214. The flux 250 can lower the melting point of the solder balls and can adhere to the glow balls before reflow. Thereafter, in the "balling" step 6, as shown in Fig. 6F, a plurality of solder balls 26 are sucked and opened at the corresponding suction holes by a ball bonding tool 20. Referring to Figure 7, the suction holes 21 are disposed on the plane 22 of the ball-fixing fixture (10) and communicated to a vacuum chamber (not shown). The ball-fixing fixture 2 further has at least one retaining groove 23 located above the peripheral protrusions 241. As shown in Fig. 6G, when the ball-fixing jig 2 is pressed against the substrate 21, the flat surface 22 of the ball-fixing jig 20 can be prevented from being pressed above the peripheral protrusions 241. 10 200845242 Therefore, these soldering 260 can be smoothly placed on the corresponding ball 塾 2i4, there will be no displacement and mutual contact. In the present embodiment, the ball-clamping fixture 20 further has a fovea #24 corresponding to the center of each unit cell so that the ball-clamping fixture 20 does not press the central protrusion (4) of the encapsulant 24. The yielding groove 23 is extendable along the cutting path between the unit areas along the substrate 21〇. Finally, the reflow step 7 is performed, and the substrate 210 to which the solder balls 260 have been attached is placed in a reflow furnace. As shown in Fig. 6H, the solder balls 260 are fixed to the ball 塾chuan corresponding to the substrate 21 by a pair of connections.

L 較佳地,上述讓位槽23相對於該平面22之深度係不小 於該些吸球孔21之吸球嵌埋深度。而「吸球丧埋深度」約 為該些桿球2 6 0之跋你-八— . 心衣仫二为之一。也就是說,該讓位槽23 相對於該平面22之淫疮总-r τ t # 之冰度係可不小於該些銲球26〇之球徑三 分之一。 一 在具體生產中可分析出利用習知製程與本發明之窗口型 球格陣列封裝製程兩者明顯差異。請參閱第8圖,圖中心Preferably, the depth of the retaining groove 23 relative to the plane 22 is not less than the depth of the suction ball of the suction holes 21. The "sucking ball burying depth" is about the poles of the ball 2 - 60. You are one of the two. That is, the ice level of the yielding groove 23 relative to the plane 22 may be not less than one third of the ball diameter of the solder balls 26〇. A significant difference between the conventional process and the window type ball grid array package process of the present invention can be analyzed in a specific production. Please refer to Figure 8, center of the diagram

與7〇4所表者為採用習知的製程所得到的球橋接不良率,介 於 600 至 1〇〇〇 pDAyr m L λ ΡΡΜ,圖中71〇、川、712與713所表者為 採用本發明之窗口型球格陣列封裝製程所得到的球橋接不 々率可大巾W降低球橋接之不良率,介於〇至1〇〇 ρρΜ,更 ,合預定的不良率目標值(15() ppM)。本發明之功效至為昭 顯,符合先進積體電路封裝製造的利益與需求。 據本發明之第二具體實施例,所揭示之一種窗口型球 格陣列封裝製程與第—實施例所述者為相同,其製程步驟亦 如第5圖所示。—基板310係具有一内表面、-外表面311 11 200845242 以及在每一單元區内之複數個窗口 312,其中該外表面311 係設有複數個球墊(圖未繪出)。在本實施例中,每一單元區 之窗口 312數量多於第一具體實施例之窗口 213數量,可分 佈位於對應單元區之邊緣與角隅。該基板3 1〇更具有一中央 槽孔3 1 3。 在經過「設置晶片」步驟2、「電性連接」步驟3、「封膠」 步驟4之後,一封膠體係覆蓋該基板31〇之内表面並填入該 些窗口 312’該封膠體並形成有複數個稍突出於該外表面The ball bridge failure rate obtained by using the conventional process with 7〇4 is between 600 and 1〇〇〇pDAyr m L λ ΡΡΜ. In the figure, 71〇, Sichuan, 712 and 713 are used. The ball bridge connection rate obtained by the window type ball grid array encapsulation process of the invention can reduce the defect rate of the ball bridge, and the target value of the defect rate is 15 (( ) ppM). The effect of the present invention is obvious, in line with the interests and needs of advanced integrated circuit package manufacturing. According to a second embodiment of the present invention, a window type grid array package process disclosed is the same as that described in the first embodiment, and the process steps are also as shown in FIG. The substrate 310 has an inner surface, an outer surface 311 11 200845242, and a plurality of windows 312 in each unit region, wherein the outer surface 311 is provided with a plurality of ball pads (not shown). In this embodiment, the number of windows 312 per unit area is larger than the number of windows 213 of the first embodiment, and can be distributed at the edges and corners of the corresponding unit area. The substrate 3 1 〇 further has a central slot 3 1 3 . After the "set wafer" step 2, the "electrical connection" step 3, and the "sealing" step 4, an adhesive system covers the inner surface of the substrate 31 and fills the windows 312' the sealant and forms There are a plurality of protrusions slightly protruding from the outer surface

且對應於該些窗口 312之周邊突部341以及對應於該中央槽 孔313之中央突部342。利用如第7圖所示之植球治具2〇, 設置複數個銲球360於該基板31〇之球墊上,由於該植球治 八20不會壓迫至该些周邊突部34丨。故在回銲步驟7中,該 些銲球360能以一對一連接方式固著於對應之球墊。 由上述可知,第二具體實施例在每一單元區内之窗口 312 數量高於第一具體實施例。然而’經統計其球橋接不良率卻 :會如同習知製程隨之等比昇高’故本發明之另—功效即為 匈口 312之數量增加而不會等比例增加球橋接之不良率。 此外’本發明之窗口型球格陣列封裝製程並不局限窗口 的位置與數量,亦可運用至傳統無周邊小窗口的窗口型球格 車歹J封裝構造。如第1G圖所示’與第:具體實施例中第9 圖的’。構比較’僅省略了周邊小窗口 及周邊突部川, 件圖破沿用之…基板31G具有—中央槽孔313(或稱中 :窗口 ),同樣地’在該基板31〇之内表面設有一晶片並形 成-封膠體(圖未繪出)’封膠體具有一中央突部⑷,其係 12 200845242 突出於該基板310之外表s 311並填滿該中央槽孔313。複 數個銲球360係設於該基板31〇之外表面311。利用本發明 之本發明之窗口型球格陣列封裝製程在製造上述之窗口型 求格陣列封裝構造亦能大幅降低球橋接之不良率。 明你以上所述,僅是本發明的較佳實施例而已,並非對本發 任何形式上的限制,本發明技術方案範圍當依所附申請 的:範園為準。任何熟悉本專業的技術人員可利用上述揭示 術内容作出些許更動或修飾為等同變化的等效實施 術實;=脫實離本發明技術方案的内容,依據本㈣^And corresponding to the peripheral protrusion 341 of the window 312 and the central protrusion 342 corresponding to the central slot 313. With the ball-clamping tool 2 shown in Fig. 7, a plurality of solder balls 360 are disposed on the ball pad of the substrate 31, since the ball-fitting treatment 20 does not press to the peripheral protrusions 34丨. Therefore, in the reflow step 7, the solder balls 360 can be fixed to the corresponding ball pads in a one-to-one connection. As can be seen from the above, the number of windows 312 in each unit area of the second embodiment is higher than that of the first embodiment. However, by statistically, the ball bridge failure rate is: as the conventional process increases, so the other effect of the invention is that the number of Hunkou 312 increases and does not increase the ball bridge connection rate. In addition, the window type ball grid array packaging process of the present invention does not limit the position and number of windows, and can also be applied to a conventional window type jewellery J package structure without a surrounding small window. As shown in Fig. 1G' and 'the ninth figure in the specific embodiment'. The structure comparison 'only omits the peripheral small window and the peripheral protrusions, and the fragment is used... the substrate 31G has a central slot 313 (or a middle: window), and similarly, 'the inner surface of the substrate 31 is provided with a The wafer and the encapsulant (not shown) have a central protrusion (4), and the system 12 200845242 protrudes from the outer surface of the substrate 310 and fills the central slot 313. A plurality of solder balls 360 are provided on the outer surface 311 of the substrate 31. The window type ball grid array packaging process of the present invention of the present invention can also greatly reduce the defective rate of ball bridging in fabricating the above-described window type grid array package structure. It is to be understood that the above description of the preferred embodiments of the present invention is not intended to limit the scope of the present invention. Any person skilled in the art can use the above disclosure to make some modifications or modifications to the equivalent implementation of the equivalent implementation; = the content of the technical solution of the present invention, according to the (four) ^

飾,均仍屬於本發明技術方案的範圍内。 、L 【圖式簡單說明】 第1圖:習知窗口型球格陣 第2圖:習知〜, 旧裝構造之截面不意圖。 各去由口型球格陣列封裝 第3圖:f知& , 衣構&之基板外表面示意圖。 型球格陣列封裝構造發生球橋接之局部立 體示意圖。 第4圖·::窗π型球袼陣列封裝構造在植球時與植 之載面示意圖。 、 第5圖:依據本發明之一呈The decoration is still within the scope of the technical solution of the present invention. , L [Simple description of the figure] Figure 1: Conventional window type grid array Figure 2: Conventional ~, the cross section of the old structure is not intended. Each is packaged by a lip-shaped array of spheres. Figure 3: Schematic diagram of the outer surface of the substrate of the fabric & A partial schematic diagram of a ball bridge in a ball grid array package construction. Fig. 4:: Schematic diagram of the window π-type ball grid array package structure during the ball placement and the plant surface. Figure 5: According to one of the present invention

封裝之製造流程圖。 J 第6A至6H圖:依 一基板戴面圖 肉口型球格陣列封裝製程之 第7圖:依據本發明之一具 具體實施例,所使用之植球治具之 立體不意圖。 心 200845242 第9圖 發月之齒口型球格陣列封裝製程相對於習知製程 由球橋接引起不良率比較對照表。 :依據本發明之窗口型球格陣列封裝製程,另一種可 ί用之窗口型球格陣列封裝構造之基板外表面示 思、圖。 另一種 外表面 第10圖:依據本發明之窗σ型球格陣列封裝製程 可運用之窗口型球格陣列封裝構造之基相 示意圖。Manufacturing flow chart of the package. J. Figs. 6A to 6H: Fig. 7 is a diagram of a meat-filled ball grid array packaging process according to a substrate. Fig. 7 is a perspective view of a ball-clamping tool used according to a specific embodiment of the present invention. Heart 200845242 Fig. 9 The tooth-toothed grid array package process of the month is compared with the conventional process. According to the window type ball grid array encapsulation process of the present invention, another external view of the substrate of the window type ball grid array package structure can be used. Another outer surface Fig. 10: Schematic diagram of the base phase of a window type grid array package structure that can be used in accordance with the window sigma type grid array package process of the present invention.

C 【主要元件符號說明】 1 提供基板 2 设置晶片 3 電性連接 4 封膠 5 形成助熔劑 6 植球 7 回銲 10 植球治具 11 吸球孔 12 平面 20 植球治具 21 吸球孔 22 平面 23 讓位槽 24 中央凹槽 110 基板 111 窗口 112 球墊 112Α無銲球球墊 113 中央槽孔 120 晶片 130 銲線 140 封膠體 141 周邊突部 142 中央突部 150 助溶劑 160 銲球 160Α雙重銲球 14 200845242 210 基板 211 213 窗口 214 220 晶片 221 223 黏晶層 230 240 封膠體 241 250 助熔劑 260 310 基板 311 313 360 中央槽孔 鲜球 341 内表面 212 外表面 球塾 215 中央槽孔 週邊銲墊 222 中央銲墊 銲線 周邊突部 242 中央突部 鲜球 外表面 312 窗口 周邊突部 342 中央突部 15C [Main component symbol description] 1 Provide substrate 2 Set wafer 3 Electrical connection 4 Sealing glue 5 Forming flux 6 Planting ball 7 Reflow 10 Ball-clamping fixture 11 Sucking hole 12 Plane 20 Ball-clamping fixture 21 Sucking hole 22 Plane 23 Retaining groove 24 Central groove 110 Substrate 111 Window 112 Ball pad 112 Α Solderless ball pad 113 Central slot 120 Wafer 130 Wire bond 140 Sealant 141 Peripheral protrusion 142 Central protrusion 150 Solvent 160 Solder ball 160Α Double solder ball 14 200845242 210 substrate 211 213 window 214 220 wafer 221 223 bonding layer 230 240 sealing body 241 250 flux 260 310 substrate 311 313 360 central slot fresh ball 341 inner surface 212 outer surface ball 215 central slot peripheral pad 222 central pad bond wire peripheral protrusion 242 central protrusion fresh ball outer surface 312 window peripheral protrusion 342 central protrusion 15

Claims (1)

200845242 十、申請專利範圍: 1、一種窗口型球格陣列封裝製程,包含: 提供一基板,該基板係具有一内表面、一外表面以及在 每一單元區内之至少一窗口,其中該外表面係設有複數 個球墊; 6又置複數個晶片於該基板之内表面; 電性連接該些晶片至該基板; Γ200845242 X. Patent Application Range: 1. A window type ball grid array packaging process, comprising: providing a substrate having an inner surface, an outer surface, and at least one window in each unit area, wherein the outer surface The surface is provided with a plurality of ball pads; 6 a plurality of wafers are disposed on the inner surface of the substrate; and the wafers are electrically connected to the substrate; 形成至少一封膠體,其係覆蓋該基板之内表面並填入該 ® 口,該封膠體並形成有至少一稍突出於該外表面且對 應於該窗口之突部; 形成一助熔劑於該些球墊; 藉由一植球治具,設置複數個銲球於該些球墊上,該植 球治具係具有—設有複數個吸球孔之平面以及至少一位 於該突部上之讓位槽,以避免該植球治具壓迫至該突 部;以及 進行-回銲㈣’以使該些銲球m連接方式固著 於對應之該些球塾。 2 4 、如申請專利範圍第i項所述之窗口型球格陣列封裝製 程,其中該讓位槽相對於該平面之深度係不小於該些吸 球孔之吸球嵌埋深度。 、如申請專利範圍第1項所;+、*〜 巧所述之自口型球袼陣列封裝製 程,其中該讓位槽相對於該芈 成十面之深度係不小於該些銲 球之球徑三分之一。 、如申請專利範圍第1項 斤迷之1¾ 口型球格陣列封裝製 16 200845242 争為周邊小® 口,並為複數個對稱排列, 而該基板更具有在每一單亓F由 母单兀區内之一中央槽孔。 5、广申請專利範圍第4項所述之窗口型球袼陣列封裝製 程其令該些窗口係位於兩平行於兮由a城 側邊之中央。 斜订於料央槽孔之單元區 6、如申請專利範圍第4項所述之窗口型球格陣列封裝製 程,其令該些窗口係位於對應單元區之角隅。 C 7程如申請專利範圍第,項所述之窗口型球格陣列封装製 ^ 在電性連接步驟巾,每-窗口㈣成有至少一 銲線,以電性連接該晶片與該基板。 8、 。如申請專利範圍第7項所述之窗σ型球格陣列封裝製 私,其中該封膠體係密封該些晶片與該些銲線。 9、 如中請專利範圍第1項所述之窗口型球格陣列封 程’其中該讓位槽係沿著該基板在單元區之 上方延伸。 ^ 〇 17Forming at least one colloid covering the inner surface of the substrate and filling the ® port, the encapsulant being formed with at least one protrusion slightly protruding from the outer surface and corresponding to the window; forming a flux for the a ball pad; a plurality of solder balls are disposed on the ball pads by a ball fixture, the ball fixture having a plane having a plurality of suction holes and at least one letting position on the protrusion a groove to prevent the ball fixture from being pressed to the protrusion; and performing a reflow (four)' to fix the solder balls m to the corresponding ball. The window type ball grid array packaging process of claim i, wherein the depth of the yielding groove relative to the plane is not less than the depth of the suction ball of the suction holes. For example, the self-porting ball-end array packaging process described in the first paragraph of the patent application scope is: +, *~, wherein the depth of the yielding groove is not less than the depth of the solder balls. One third of the path. For example, the patent application scope 1st item of the 13⁄4 mouth type ball grid array package system 16 200845242 is for the surrounding small ® mouth, and for a plurality of symmetric arrangement, and the substrate is more in each single frame F by the mother unit One of the central slots in the area. 5. The window type ballast array packaging process of the fourth application of the patent application scope is such that the windows are located in two parallel to the center of the side of the city. The unit area of the window-type grid array package as described in claim 4, wherein the window is located at the corner of the corresponding unit area. In the case of the electrical connection step, each window (four) has at least one bonding wire electrically connected to the wafer and the substrate. 8, . The window sigma-type ball grid array package described in claim 7 is wherein the encapsulation system seals the wafers and the bonding wires. 9. The window type ball grid array package of claim 1, wherein the yielding groove extends above the cell area along the substrate. ^ 〇 17
TW096116177A 2007-05-07 2007-05-07 Fabricating process for window bga packages to improve ball bridging TWI334184B (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI585871B (en) * 2010-03-25 2017-06-01 星科金朋有限公司 Integrated circuit packaging system with stacking option and method of manufacture thereof

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TWI406377B (en) * 2010-12-27 2013-08-21 Powertech Technology Inc Ball grid array package with three-dimensional pin 1 mark and its manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI585871B (en) * 2010-03-25 2017-06-01 星科金朋有限公司 Integrated circuit packaging system with stacking option and method of manufacture thereof

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