TWI326907B - Ball grid array package for preventing mold flash - Google Patents
Ball grid array package for preventing mold flash Download PDFInfo
- Publication number
- TWI326907B TWI326907B TW095146340A TW95146340A TWI326907B TW I326907 B TWI326907 B TW I326907B TW 095146340 A TW095146340 A TW 095146340A TW 95146340 A TW95146340 A TW 95146340A TW I326907 B TWI326907 B TW I326907B
- Authority
- TW
- Taiwan
- Prior art keywords
- substrate
- slot
- grid array
- array package
- ball grid
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
1326907 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種琰格 M ^ ％格陣列封裝構造，特別1326907 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a 琰格 M ^ % lattice array package structure, in particular
關於一種防止溢膠之窗口琊 特另J 【先前技術】 】封裝構造》 按，球格陣列封裝構& &係可藉由一模封 (moldmg compound)，作為 1曰日月之密封保護，習知 穋體之形成方法係為壓模方★ 模方式將已黏貼晶片之基 於上下模具之間，再注入形 〜成模封膠體之前趨物， 封該晶片。然而在封膠過程中，會 τ 賞因該基板與下模 間無法緊密貼合而易有溢膠之金 吵<現冢，使得球墊受污 影響銲接性與電性品質。 如第1圖所示，一種習知球格陣列封裝構造ι〇〇 3 —基板110、一晶片120、複數個銲線13〇、一 膠體140以及複數個銲球150。該基板11〇係具有 表面111、一下表面112、一槽孔113以及複數個 於該下表面112之球墊114。該晶片120之一主動击 係利用黏晶材料貼設在該基板110之上表面111 中’該主動面121係設有複數個銲墊123，其係對 該槽孔11 3内。該些銲線1 30係通過該槽孔11 3並 連接該些銲墊123至該基板110»該模封膠體Μ0 成於該基板110之該上表面111與該槽孔113内， 別密封該晶片120與該些銲線130。由於該模封膠费 係可更覆蓋該晶片120之一背面122，以完全密封 係有 膠體 模封 板置 以密 具之 染而 係包 模封 一·上 設置 I 121 。其 準在 電性 係形 以分 [140 該晶 5 I3269Q7 片120。該些銲球150係設置於該些球墊114，以供對 外接合。然而’在進行封膠時，上模具不可壓貼該晶片 120之背面122’故該基板ι1〇與該下模具密合度不足 而會發生溢膠現象。此一溢膠現象會污染該基板11〇之 該些球墊114’導致該些銲球15〇無法完整地銲接至該 基板110而影響該球格陣列封裝構造1〇〇的鮮接性與電 性品質。 如第2圖所示，另一種習知球格陣列封裝構造2〇〇 , 係包含一基板210、一晶片220、複數個銲線230、一 模封膠體240以及複數個銲球25〇。該基板21〇係具有 一上表面211、一下表面212、一槽孔213以及複數個 設置於該下表面212之球墊214。該晶片220之一主動 面221係貼設於該基板210之上表面211〇該主動面221 係設有複數個銲墊223，其係對準在該槽孔2丨3内。該 法錄線230係通過該槽孔213並電性連接該些銲塾223 至該基板210。該模封膠體24 0係形成於該基板210之 籲該上表面211與該槽孔213内，以分別密封該晶片220 與該些銲線230’但須顯露該晶片220之一背面222， 以供一上模具壓合》該些銲球250係設置於該些球墊 214’以供對外接合。其中’該基板21〇之該下表面212 係另設有複數個擋條2 1 5，其係分別位於該槽孔2 1 3之 兩側。並藉由上模具壓合該晶片22〇之背面222，方能 使該些擋條215能緊貼至下模具，可增加該基板21〇與 /下模具之密合度，以防止在封膠時，該模封膠體24〇 6 j 32690-7 對該些球墊2 1 4之間產生溢膠之問題。然而，μ 右上具 無法壓合該晶片220之背面222時，該些擔條21 、 5之防 溢膝功能則不明顯，仍有溢膠之虞。該球格陣列封裝 造2 00僅適用於裸晶背之封裝產品，對於需要全密封構 片之模流溢膠防範並無實質助益。 阳 【發明内容】 本發明之主要目的係在於提供一種球格陣列封裝構Regarding a window for preventing overflow of glue, a special J [Prior Art] 】Package structure 》, Grid array package && can be sealed by a moldmg (moldmg compound) The formation method of the conventional carcass is a stamping method. The mode is to seal the wafer based on the upper and lower molds, and then inject the shape into a mold before sealing the film. However, in the process of sealing, the τ rewards the metal and the lower mold, and it is easy to have the gold of the glue. Now, the ball mat is contaminated, which affects the weldability and electrical quality. As shown in FIG. 1, a conventional ball grid array package structure ι 3 - substrate 110, a wafer 120, a plurality of bonding wires 13A, a colloid 140, and a plurality of solder balls 150. The substrate 11 has a surface 111, a lower surface 112, a slot 113, and a plurality of ball pads 114 on the lower surface 112. One of the wafers 120 is actively attached to the upper surface 111 of the substrate 110 by a die-bonding material. The active surface 121 is provided with a plurality of pads 123 which are disposed in the slots 11 3 . The bonding wires 1 30 pass through the slots 11 3 and connect the pads 123 to the substrate 110 » the molding compound Μ 0 is formed in the upper surface 111 of the substrate 110 and the slot 113, and the sealing is not sealed. The wafer 120 and the bonding wires 130. Since the mold encapsulation fee can cover one of the back faces 122 of the wafer 120, the fully encapsulated colloidal mold plate is coated with a dense mold and the mold is sealed. It is in the electrical system to divide [140] crystal 5 I3269Q7 piece 120. The solder balls 150 are disposed on the ball pads 114 for external engagement. However, when the encapsulation is performed, the upper mold cannot be pressed against the back surface 122 of the wafer 120. Therefore, the adhesion between the substrate ι1 and the lower mold is insufficient, and an overflow phenomenon occurs. The overflowing phenomenon may contaminate the ball pads 114' of the substrate 11 such that the solder balls 15〇 cannot be completely soldered to the substrate 110, thereby affecting the freshness and power of the ball grid array package structure. Sexual quality. As shown in FIG. 2, another conventional ball grid array package structure includes a substrate 210, a wafer 220, a plurality of bonding wires 230, a molding compound 240, and a plurality of solder balls 25A. The substrate 21 has an upper surface 211, a lower surface 212, a slot 213, and a plurality of ball pads 214 disposed on the lower surface 212. An active surface 221 of the wafer 220 is attached to the upper surface 211 of the substrate 210. The active surface 221 is provided with a plurality of pads 223 which are aligned in the slots 2丨3. The recording line 230 passes through the slot 213 and electrically connects the pads 223 to the substrate 210. The molding compound 205 is formed on the upper surface 211 of the substrate 210 and the slot 213 to seal the wafer 220 and the bonding wires 230 ′, respectively, but the back surface 222 of the wafer 220 must be exposed. For an upper mold press, the solder balls 250 are disposed on the ball pads 214' for external bonding. The lower surface 212 of the substrate 21 is further provided with a plurality of strips 2 15 , which are respectively located on both sides of the slot 2 1 3 . And pressing the back surface 222 of the wafer 22 by the upper mold, so that the strips 215 can be closely attached to the lower mold, and the adhesion of the substrate 21 to the lower mold can be increased to prevent the sealing. The molding compound 24〇6 j 32690-7 has a problem of overflowing between the ball pads 2 1 4 . However, when the right upper side of the wafer 220 cannot be pressed against the back surface 222 of the wafer 220, the anti-spike function of the strips 21 and 5 is not obvious, and there is still a flaw in the overflow. The grid array package is only suitable for bare-back package products, and it does not really help the mold-flow protection of the fully-sealed structure. [Abstract] The main object of the present invention is to provide a ball grid array structure
造，利用基板之槽孔中央區之設計變化達到防止溢膠在 基板下表面之功效。 本發明之次一目的係在於提供一種球格陣列封裝構 造，利用基板之槽孔之-區段設置之障礙物達到防止溢 勝在基板下表面之功效。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。依據本發明，一種球格陣列封裝構造包含 =基板、一晶片、複數個銲線、一模封膠體以及複數個 銲球。該基板係具有一上表面、一下表面以及至少一槽 孔。該晶片係設置於該基板之該上表面並具有複數個對 準在該槽孔内之銲墊。該些銲線係通過該槽孔以電性連 接該些銲墊至該基板。該模封膠體係具有一方形體與至 少-條形體’該方形體係形成於該基板之該上表面以密 封該晶片，該條形體係形成於該槽孔内與該基板之該下 表面之部位以密封該些銲線。該些銲球係設置於該基 之〜下表面。其中，該基板於該槽孔之一區段係形成 有-縮口，其係較窄於該槽孔之平均寬度以減緩該模 7 I326907 封膠體於該槽孔之注膠流速。在另一賁施例中，町以别 用障礙物使該基板之槽孔於一區段產生較小孔徑，以形 成縮口。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現❶ 在前述的球格陣列封裝構造中，該條形體之雨瑞係 可一體連接至該方形體。 在前述的球格陣列封裝構造中’該方形體係圩爲長 方形體。 在前述的球格陣列封裝構造中，該槽孔係可“该 基板之一中心線上。 在前述的球格陣列封裝構造中，該緣 係可為「〕〔〕形或「】[」形。 在前述的球格陣列封裝 欲 俜可為「>< 裝構造中，該縮口之兩側邊緣 保了為 > < 」形或「）（」形。 【實施方式】 依據本發明之第一具 冉趙實施例，揭示一陣列 封裝構造。第3圖係為却種球檢 β-音m # ”、。東格陣列封裝構造於_扎横切 之截面不意圖。第4阐後 吁味於槽作 禾4圖係為該球格陣列 口 橫切之截面示意圖、裝構造於縮 币）圖係為該玻坆陆 基板在黏晶後及在封膠前之下 格陣列封裝構逡之 該球格陣列封裝構造 面不意囷。第 取傅k之基板在封 项係為 圖。第7圖係為該球格 後之下表面千i %格陣列封裝構 ^ % 孔之載面示意圖。 在模封注膠眛、， 8 1326907 如第3及4圖所示’該球格陣列封裝構造3〇〇係主 要包含一基板310、一晶片320'複數個銲線33〇、一 模封膠體3 4 0以及複數個鲜球350。該基板310係具有 一上表面311、一下表面312以及至少一槽孔313。其 中’該基板310係另具有複數個球塾314，其係設置於 該基板310之該下表面312’以供接合該些鮮球35〇。 在本實施例中’該槽孔313係可位於該基板31〇之一中 心線上（如第5圖所示）。 • 再如第3圖所示，該晶片320係具有一主動面321 以及一背面322 °可刊用已知黏晶材料之黏晶層360將 該晶片320黏著於該基板310之該上表面311，複數個 錄塾323係設於該主動面321，以作為晶片電極。此外， 在黏晶時該晶片320之該主動面321係朝向該基板31〇 而使該晶片320之該些銲墊323對準在該槽孔313内。 可利用該些銲線330係通過該槽孔3丨3以電性連接該些 銲墊323至該基板310。 * 如第3及4圖所示，該模封膠體34〇係具有—方形 體341與至少一條形體342’該方形體341係形成於該 基板310之該上表面311以密封該晶片32〇β在本實施 例中’該方形體341係覆蓋至該晶片32〇之背面322。 此外，配合參閱第5及6圖’該條形體342係形成於該 槽孔313内與該基板310之該下表面312之一部位以密 封該些鲜線330。在本實施例中，該方形體341係可為 長方形體。較佳地’配合參閱第7圖，該條形體342之 9 1326907 兩端係可一體連接至該方形體341，可在模封注膠形成 該方形體341時，該條形體342可同時形成於該槽孔 313内與該基板310之局部該下表面312。 如第4圖所示，該些銲球35〇係設置於該基板31〇 之該下表面312之該些球墊314〇在具體應用上，該球 格陣列封裝構造300係藉由該些銲球35〇之回銲而接合 至一外部印刷電路板（圖中未繪出）。 如第5圖所示，其中，該基板31〇於該槽孔313之 • 一區段係形成有一縮口 316,其係較窄於該槽孔313之 平均寬度’以減緩該模封膠體340於該槽孔313之注膠 流速’即減緩該條形趙3 4 2之形成以構成上下模流壓力 差，以防止溢膠（容後詳述）。在本實施例中，該縮口 3 j 6 之兩側邊緣3 17係可為「 > <」形或「）（」形。 因此，該球格陣列封裝構造3 00係利用該基板3 i 〇 本身在槽孔313處所形成之該縮口 316，以減緩該模封 膠體340於該槽孔313内（即條形體342)之注膠流速。 鲁 如第7圖所示’該模封膠體340於該槽孔313内之注膠 -流速係較慢於該模封膠體3 40於該基板310之該上表面 3 1 1(即方形體341)之注膠流速，導致上模流壓力大於下 模流壓力。故會使形成於該基板310之該上表面311之 該模封膠體340會對該基板310產生向下壓力，使該基 板310之該下表面312更加緊貼於下模具（圖中未令 出），故可使該基板310之該些球墊314與該下模具之 間具有良好的密合度，故封膠時該模封膠體3 4〇不會溢 10 丄326907 2至該些球塾314而達到防止溢膠之功效，又可完全密 封該晶片320。因此，可確保後續設置於該球塾314上 之該些銲球350具彳良好的焊接效果，冑得封裝後之該 球格陣列封裝構造300具可靠的電性連接品質。〜The design of the central region of the slot of the substrate is used to prevent the glue from overflowing on the lower surface of the substrate. A second object of the present invention is to provide a ball grid array package structure that utilizes an obstacle provided by a slot-slot of a substrate to prevent the effect of overflow on the lower surface of the substrate. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. In accordance with the present invention, a ball grid array package construction includes a substrate, a wafer, a plurality of bonding wires, a molding compound, and a plurality of solder balls. The substrate has an upper surface, a lower surface, and at least one slot. The wafer is disposed on the upper surface of the substrate and has a plurality of pads aligned in the slots. The bonding wires are electrically connected to the pads through the slots. The molding compound system has a square body and at least a strip body formed on the upper surface of the substrate to seal the wafer, and the strip system is formed in the slot and the lower surface of the substrate Seal the wire bonds. The solder balls are disposed on the lower surface of the base. Wherein, the substrate is formed with a constriction in one of the slots, which is narrower than the average width of the slot to slow the injection flow rate of the sealant of the mold 7 I326907. In another embodiment, the slab causes the slot of the substrate to create a smaller aperture in a section by using an obstacle to form a sag. The object of the present invention and the technical problem thereof can be further achieved by the following technical measures. In the foregoing ball grid array package structure, the strip body can be integrally connected to the square body. In the aforementioned ball grid array package configuration, the square system is a rectangular body. In the above-described ball grid array package structure, the slot can be "on one of the center lines of the substrate. In the above-described ball grid array package structure, the edge can be "] shaped or "" [" shaped. In the above-described ball grid array package, the both sides of the neck are protected as ><<<> or ") (" shape. The first embodiment of Zhao Zhao reveals an array package structure. The third figure is a kind of ball inspection β-tone m # ”. The layout of the Dongge array package is not intended to be cross-section. After the groove is made in the groove, the figure is a cross-sectional view of the cross-section of the grid array, and the structure is set in the coinage. The figure is the frame of the glass substrate after the die-bonding and before the sealing. The structure of the grid array package is unintentional. The substrate of the first step is the figure of the sealing system. The seventh picture shows the surface of the frame after the frame. In the form of a molded encapsulant, 8 1326907, as shown in Figures 3 and 4, the ball grid array structure 3 mainly includes a substrate 310, a wafer 320', a plurality of bonding wires 33, and a The mold seal body 310 and the plurality of fresh balls 350. The substrate 310 has an upper surface 311, a lower surface 312, and at least one groove. 313. The substrate 310 has a plurality of balls 314 disposed on the lower surface 312' of the substrate 310 for engaging the fresh balls 35. In the embodiment, the slot 313 is It can be located on one of the center lines of the substrate 31 (as shown in Fig. 5). • As shown in Fig. 3, the wafer 320 has an active surface 321 and a back surface 322 °. The die layer 360 adheres the wafer 320 to the upper surface 311 of the substrate 310, and a plurality of recording pads 323 are disposed on the active surface 321 to serve as a wafer electrode. Further, the active of the wafer 320 during die bonding The surface 321 is directed toward the substrate 31 to align the pads 323 of the wafer 320 in the slot 313. The bonding wires 330 can be electrically connected to the solder through the slots 3丨3. Pad 323 to the substrate 310. * As shown in Figures 3 and 4, the molding compound 34 has a square body 341 and at least one body 342'. The square body 341 is formed on the upper surface 311 of the substrate 310. In order to seal the wafer 32 〇β, in the present embodiment, the square body 341 covers the back surface 322 of the wafer 32. In addition, the strip 342 is formed in the slot 313 and a portion of the lower surface 312 of the substrate 310 to seal the fresh lines 330. In this embodiment, the strip is formed. The shape 341 can be a rectangular body. Preferably, the reference is made to Fig. 7, and the two sides of the strip body 342 can be integrally connected to the square body 341. When the square body 341 is formed by molding the glue, The strip 342 can be formed in the slot 313 and the lower surface 312 of the substrate 310 at the same time. As shown in FIG. 4, the solder balls 35 are disposed on the lower surface 312 of the substrate 31, and the ball pads 314 are used in a specific application. The ball grid array structure 300 is soldered by the solder balls. The ball 35 is reflowed and bonded to an external printed circuit board (not shown). As shown in FIG. 5, the substrate 31 is formed with a constriction 316 in the section of the slot 313, which is narrower than the average width of the slot 313 to slow the molding compound 340. The injection flow rate of the slot 313 slows down the formation of the strip shape to form a pressure difference between the upper and lower molds to prevent overflow (details are detailed later). In this embodiment, the side edges 3 17 of the constrict 3 j 6 may be " ><<<> or ") (". Therefore, the grid array package structure 300 uses the substrate 3 i 〇 itself is formed at the slot 313 to reduce the injection flow rate of the molding compound 340 in the slot 313 (ie, the strip 342). As shown in Figure 7, the mold seal The injection-flow rate of the colloid 340 in the slot 313 is slower than the injection flow rate of the molding compound 340 on the upper surface 31 of the substrate 310 (ie, the square body 341), resulting in upper mold flow pressure. The mold cavity 340 formed on the upper surface 311 of the substrate 310 causes downward pressure on the substrate 310, so that the lower surface 312 of the substrate 310 is more closely attached to the lower mold. (Not shown in the figure), so that the ball pads 314 of the substrate 310 and the lower mold can have a good degree of adhesion, so the molding compound 3 4 〇 does not overflow when sealing the glue 丄 326907 2 The ball 314 is reached to prevent the glue from overflowing, and the wafer 320 can be completely sealed. Therefore, the subsequent setting on the ball 314 can be ensured. The solder balls 350 have a good soldering effect, and the packaged grid array package structure 300 has a reliable electrical connection quality.
在本發明之第二具體實施例中，請參閱第8及9圖， 揭示另一種球格陣列封裴構造，其包含之晶片銲線 330、模封膠體以及銲球與第一具體實施例中大致相 同，可沿用相同圖號且不再贅述。該球格陣列封裝構造 之基板370係具有一上表面、一下表面372以及至少一 槽孔373。該槽孔373係顯露該晶片32〇之該些銲墊 323。其中，該基板37〇於該槽孔373之一區段係形成 有一縮口 376，其係較窄於該槽孔3 73之平均寬度，以 減緩該模封膠體340於該槽孔373之注膠流速，產生之 上下模流壓力差，有利於封膠時提昇基板37〇下表面與 下模具之緊貼性，以防止溢膠。在本實施例中，該縮口 370之兩側邊緣377係可為「〕〔」形或「][」形。 該基板370另具有複數個球墊374，其係設置於該基板 370之該下表面372，以供接合銲球。 在本發明之第三具體實施例中，請參閱第1〇及η 圖’揭示另一種球格陣列封裝構造4〇〇，主要包含一基 板410、一晶片420、複數個銲線430、一模封膠體44〇 以及複數個銲球450。該基板410係具有一上表面41卜 一下表面412以及至少一槽孔413。其中，該基板41〇 係另具有複數個球墊414，其係設置於該基板410之該 11 1326907 下表面412，以供接合該些銲球450。 如第10圖所示，該晶片420係設置於該基板 該上表面411並具有複數個對準在該槽孔413内 423’該些銲墊423係設置於該晶片420之一主動 並對準於該槽孔413内。該些銲線43 0係通過 413以電性連接該些銲墊423至該基板410。 該模封膠體440係具有一方形體441與至少 體442。該方形體441係形成於該基板410之該 41 1以密封該晶片420，可包含該晶片420之 422。該條形體442係形成於該槽孔413内與該基 之該下表面412之一部位以密封該些銲線430。 球450係設置於該基板410之該下表面412之該 4 1 4，使該球格陣列封裝構造4〇〇可對外連接。 其中，如第11圖所示，該基板410於該槽孔 一區段係設置一障礙物418，以形成一縮口 416 徑係較小於該槽孔4丨3之孔徑，以減緩該模封膠 於該槽孔413之注膠流速，可有效地增進該些球 與一下模具之密合度，而得以充分改善封膠時 題。再如第11圓所示，該障礙物418係可為一 460之一部份，以降低製造成本。在本實施例中 晶層460係可黏接該晶片420之該主動面421與 41〇之上表面411。在不同實施例中，該障礙物 可為另一種點塗膠體。 以上所述· ’僅是本發明的較佳實施例而已， 410之 之銲墊 面421 該槽孔 一條形 上表面 一背面 板410 該些銲 些球墊 413之 ，其口 體440 墊4 1 4 溢膠問 黏晶層 ，該黏 該基板 418亦 並非對 12 132690.7 本發明作任何形式上的限制，雖然本發明已以較佳實施 例揭露如上，然而並非用以限定本發明，任何熟悉本專 業的技術人員，在不脫離本發明技術方案範圍内，當可 利用上述揭示的技術内容作出些許更動或修飾為等同 變化的等效實施例，但凡是未脫離本發明技術方案的内 容，依據本發明的技術實質對以上實施例所作的任何簡 單修改、等同變化與修飾，均仍屬於本發明技術方案的 範圍内。 【圖式簡單說明】 第1圖：一種習知球格陣列封裝構造之截面示意圖。 第2圖··另一種習知球格陣列封裝構造之戴面示意圖。 第3圖：依據本發明之第_具體實施例，一種防止溢膠 之球格陣列封裝構造於槽孔橫切之截面示意 圖。In a second embodiment of the present invention, reference is made to FIGS. 8 and 9 to disclose another ball grid array sealing structure including a wafer bonding wire 330, a molding compound, and a solder ball in the first embodiment. Roughly the same, the same drawing number can be used and will not be described again. The substrate 370 of the ball grid array package has an upper surface, a lower surface 372 and at least one slot 373. The slot 373 exposes the pads 323 of the wafer 32. The substrate 37 is formed with a cutout 376 in a section of the slot 373, which is narrower than the average width of the slot 373 to slow the injection of the molding compound 340 into the slot 373. The glue flow rate produces a pressure difference between the upper and lower mold streams, which is advantageous for improving the adhesion between the lower surface of the substrate 37 and the lower mold during the sealing to prevent overflow. In this embodiment, the two side edges 377 of the cutout 370 can be ""[" or "][". The substrate 370 further has a plurality of ball pads 374 disposed on the lower surface 372 of the substrate 370 for bonding solder balls. In the third embodiment of the present invention, please refer to FIG. 1 and FIG. 2 to disclose another ball grid array package structure, which mainly includes a substrate 410, a wafer 420, a plurality of bonding wires 430, and a die. The encapsulant 44 is a plurality of solder balls 450. The substrate 410 has an upper surface 41 and a surface 412 and at least one slot 413. The substrate 41 has a plurality of ball pads 414 disposed on the lower surface 412 of the substrate 410 for bonding the solder balls 450. As shown in FIG. 10, the wafer 420 is disposed on the upper surface 411 of the substrate and has a plurality of alignments in the slot 413. The pads 423 are disposed on the wafer 420 to be active and aligned. In the slot 413. The bonding wires 430 are electrically connected to the pads 410 through the 413 to the substrate 410. The molding compound 440 has a square body 441 and at least a body 442. The square body 441 is formed on the substrate 41 of the substrate 410 to seal the wafer 420, and may include 422 of the wafer 420. The strip 442 is formed in the slot 413 and a portion of the lower surface 412 of the base to seal the bonding wires 430. The ball 450 is disposed on the lower surface 412 of the substrate 410 to allow the ball grid array package structure 4 to be externally connected. As shown in FIG. 11, the substrate 410 is provided with an obstacle 418 in a section of the slot to form a hole 416 having a diameter smaller than the aperture of the slot 4丨3 to slow the mode. The injection flow rate of the sealant in the slot 413 can effectively improve the adhesion between the balls and the lower mold, and can fully improve the sealing time. As shown in the eleventh circle, the obstacle 418 can be a part of a 460 to reduce manufacturing costs. In this embodiment, the crystal layer 460 is adhered to the upper surface 411 of the active surface 421 and 41 of the wafer 420. In various embodiments, the obstacle can be another point coating gel. The above description is only a preferred embodiment of the present invention. The pad surface 421 of the 410 has a slot-shaped upper surface and a back plate 410. The ball pads 413 are soldered to the body 440 pad 4 1 4, the adhesive layer, the substrate 418 is not intended to limit the invention in any way, although the invention has been disclosed in the preferred embodiments, but is not intended to limit the invention, any familiar A person skilled in the art can make some modifications or modifications to equivalent embodiments by using the above-disclosed technical contents without departing from the technical scope of the present invention. The present invention is not limited to any simple modifications, equivalent changes and modifications of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a conventional ball grid array package structure. Fig. 2 is a schematic view showing the wearing of another conventional ball grid array package structure. Fig. 3 is a cross-sectional view showing a cross-cutting of a slot array of a spill prevention gel according to a first embodiment of the present invention.
4圖.依據本發明之第一具體實施例，該球格陣列封 裝構造於縮口橫切之截面示意圖。 5圖：依據本發明之第一具體實施例，該球格陣列封 裝構造之基板在黏晶後且在封膠前之下表面 示意圖。 第6圖··依據本發明之p具趙實施例，該球格陣列封 裝構造之基板在封膠後之下表面示意圓。 第7圖：依據本發明之笛 f 第具體實施例，該球格陣列封 裝構造在模封注膠時沿槽孔之截面示意圖β 第8圖：依據本發_ 令I β之第一具體實施例，另一種球格陣 13 1326907 列封裝構造之基板在黏晶後且在封膠前之下 表面示意圊。 第9圖：依據本發明之第二具鳢實施例，該球格陣列封 裝構造之基板在封膠後之下表面示意圖。 第1 〇圖：依據本發明之第三具體實施例，—種防止溢 膠之球格陣列封裝構造於槽孔橫切之載面示 意圖。4 is a cross-sectional view showing the cross-cut of the lattice array package in accordance with the first embodiment of the present invention. 5 is a schematic view showing the surface of the substrate of the grid array package structure after the die bonding and before the sealant according to the first embodiment of the present invention. Fig. 6 is a view showing a substrate of the grid array package structure in which the surface under the seal is schematically rounded in accordance with the embodiment of the present invention. Figure 7 is a cross-sectional view of the lattice array package structure along the slot when molding the glue injection according to the specific embodiment of the present invention. Figure 8: According to the first embodiment of the present invention For example, another substrate of the lattice array 13 1326907 column package structure is shown after the die-bonding and under the surface before the sealing. Figure 9 is a schematic view showing the lower surface of the substrate of the grid array package structure after sealing after the second embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS In accordance with a third embodiment of the present invention, a ball grid array package structure for preventing overfilling is shown in a cross-section of a slot.
第11圖：依據本發明之第三具體實施例’該球格陣列 封裝構造於縮口橫切之截面示意圖。 【主要元件符號說明】 10 0球格陣列封裝構造 112下表面 122背面Fig. 11 is a cross-sectional view showing the structure of the grid array package according to the third embodiment of the present invention. [Main component symbol description] 10 0 grid array package structure 112 lower surface 122 back
110 基板 111 上表面 113 槽孔 114 球墊 120 晶片 121 主動面 123 銲墊 130 銲線 140 模封膠體 200 球格陣列 封裝構造 210 基板 211 上表面 213 槽孔 214 球墊 220 晶片 221 主動面 223銲墊 230銲線 240模封膠體 150銲球 212下表面 215擋條 2 2 2背面 300球格陣列封裝構造 31〇基板 311上表面 250銲球 312下表面 14 1326907110 substrate 111 upper surface 113 slot 114 ball pad 120 wafer 121 active surface 123 pad 130 wire bonding 140 molding compound 200 ball grid array package structure 210 substrate 211 upper surface 213 slot 214 ball pad 220 wafer 221 active surface 223 welding Pad 230 bonding wire 240 molding gel 150 solder ball 212 lower surface 215 bar 2 2 2 back 300 ball grid array package structure 31 〇 substrate 311 upper surface 250 solder ball 312 lower surface 14 1326907
313 槽孔 314 317 邊緣 320 晶片 321 323 銲墊 330 340 模封膠體 341 350 銲球 360 370 基板 372 374 球塾 376 400 球格陣列 封裝構造 410 基板 411 413 槽孔 414 418 障礙物 420 晶片 421 423 銲墊 430 440 模封膠體 441 450 銲球 460 球墊 316 縮口 主動面 322 背面 銲線 方形體 342 條形體 黏晶層 下表面 373 槽孔 縮口 377 邊緣 上表面 412 下表面 球墊 416 縮口 主動面 422 背面 銲線 方形體 442 條形體 黏晶層 15313 Slot 314 317 Edge 320 Wafer 321 323 Pad 330 340 Mold Seal 341 350 Solder Ball 360 370 Substrate 372 374 Ball 塾 376 400 Grid Array Structure 410 Substrate 411 413 Slot 414 418 Obstacle 420 Wafer 421 423 Solder Pad 430 440 Molding gel 441 450 Solder ball 460 Ball pad 316 Shrinking active surface 322 Back wire square body 342 Strip body viscous layer Lower surface 373 Slot hole 377 Edge upper surface 412 Lower surface ball pad 416 Shrinking active Face 422 back wire square body 442 strip body layer 15
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW095146340A TWI326907B (en) | 2006-12-11 | 2006-12-11 | Ball grid array package for preventing mold flash |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW095146340A TWI326907B (en) | 2006-12-11 | 2006-12-11 | Ball grid array package for preventing mold flash |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200826255A TW200826255A (en) | 2008-06-16 |
| TWI326907B true TWI326907B (en) | 2010-07-01 |
Family
ID=44772338
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW095146340A TWI326907B (en) | 2006-12-11 | 2006-12-11 | Ball grid array package for preventing mold flash |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI326907B (en) |
-
2006
- 2006-12-11 TW TW095146340A patent/TWI326907B/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| TW200826255A (en) | 2008-06-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI405274B (en) | Clipless and wireless semiconductor die package and method for making the same | |
| TWI255020B (en) | Stacked die semiconductor device | |
| TWI311352B (en) | Fabricating process of leadframe-based bga packages and leadless leadframe utilized in the process | |
| TW200845351A (en) | Semiconductor device, leadframe and manufacturing method of semiconductor device | |
| TW201230212A (en) | Manufacturing method of semiconductor device | |
| JP2003007766A (en) | Semiconductor electronic part | |
| TWI278079B (en) | Pillar grid array package | |
| TW483134B (en) | Micro BGA package | |
| JP4579258B2 (en) | BGA type package | |
| TWI274406B (en) | Dual gauge leadframe | |
| TWI326907B (en) | Ball grid array package for preventing mold flash | |
| TWI253730B (en) | Semiconductor package with heat dissipating structure | |
| JP2004146577A (en) | Semiconductor device and its manufacturing method | |
| JP2022143167A (en) | Semiconductor device | |
| TWI387080B (en) | Qfn package structure and method | |
| TWI334184B (en) | Fabricating process for window bga packages to improve ball bridging | |
| TWI250623B (en) | Chip-under-tape package and process for manufacturing the same | |
| TWI285407B (en) | LOC (lead-on-chip) IC package | |
| TW200950015A (en) | Leadless semiconductor package | |
| JP7423197B2 (en) | semiconductor equipment | |
| TWI440146B (en) | Semiconductor package having internal heatsink prevented from contamination of mold flash | |
| TW495941B (en) | Method for packaging BGA for a voiding molding flash | |
| TW480688B (en) | Window BGA package structure | |
| TWI230448B (en) | Hybrid integrated circuit package and method of the same | |
| CN2570975Y (en) | Film crystal coating packaging arrangement |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |