TWI329982B - Single package multi-chip rf power amplifier - Google Patents

Single package multi-chip rf power amplifier Download PDF

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TWI329982B
TWI329982B TW092134068A TW92134068A TWI329982B TW I329982 B TWI329982 B TW I329982B TW 092134068 A TW092134068 A TW 092134068A TW 92134068 A TW92134068 A TW 92134068A TW I329982 B TWI329982 B TW I329982B
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amplifier
input
chip
power amplifier
peak
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TW092134068A
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TW200427218A (en
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Raymond Sydney Pengelly
Simon Maurice Wood
John Phillip Quinn
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Cree Microwave Llc
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/60—Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
    • H03F3/602—Combinations of several amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
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    • H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
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    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Description

1329982 (1) 玖、發明說明 相關申請案之相互參考 本申請案有關於2002年1月28日申請之共同審查中 之申請案第1 0/059，8 6 6號，該案名稱爲”N-WAY RF POWER AMPLIFIER WITH INCREASED BACKOFF POWER AND POWER ADDED EFFICIENCY”，該案讓渡給本案之 受讓人，且其全部內容援引爲本案之參考。 【發明所屬之技術領域】 本發明大體而言係關於一種多晶片射頻（RF)功率放大 器，且具體言之，本發明係關於封裝一多晶片射頻功率放 大器。 【先前技術】 半導體功率放大器通常包含複數個半導體晶片，且每 一晶片可具體實施爲一電晶體放大器，諸如一矽橫向擴散 MOS場效電晶體（LDMOSFET)。該電晶體放大器可以並聯 操作，以提供一增加的功率放大器輸出，或者該電晶體放 大器可包含一用於最大化補償功率操作之主要或載波放大 器及複數個輔助或峰値放大器，其可因應增加的功率需求 而被適當偏壓以依序開始操作。此一功率放大器係揭露在 上述共同審查中之申請案第10/059，866號中。 習知的實務係將每一電晶體放大器各別封裝在一外殼 中，然後將已封裝之電晶體放大器經由阻抗匹配網路及信 -5- (2) (2)1329982 號分路器而連接至一共同輸入部0然而，使用各別晶片封 裝會增加製造成本，且會增加在一支撐基板上之總封裝佔 據面積。此外，數個封裝之安裝需要增加電晶體間距及在 電晶體之間的信號相位差。 【發明內容】 依照本發明，複數個各別電晶體放大器晶片係安裝在 一單一封裝中，且每一晶片具有其各自的輸入及輸出引 線。該等晶片具有不相等的周長及閘極寬度，如一般使用 在一道候悌放大器中一樣，且每一晶片可以在封裝中針對 其輸入、輸出及偏壓引線來預先匹配。經預先匹配之電晶 體晶粒然後便可使用在高效率的放大器設計中，諸如在一 道候悌構形中之載頻及峰値放大器。 本發明提供製造效益且降低整體封裝的佔據面積。此 外，該電晶體晶粒係緊密相鄰，藉此可減少在數個電晶體 中之信號間的相位差。針對一道候悌應用，該封裝必須具 有兩倍於在該封裝中之晶片數量的引線。這使得每一電晶 體可在封裝中各別地預先匹配及各別地偏壓。 本發明及其目的與特徵可以配合圖式而由以下之詳細 說明及後附之申請專利範圍中獲得瞭解。 【實施方式】 圖1係在上述共同審查中之申請案第1 0/05 9,8 66號 中所揭露之功率放大器的功能方塊圖，其採用複數個各別 -6 - (3) (3)1329982 包裝之功率放大器晶片’該等功率放大器晶片包括一載頻 放大器20及三個峰値放大器21、22、23，且該載頻放大 器經由90°變壓器24、25、26而連接至一輸出負載28» —90°變壓器30將一四路分路器32連接至載頻放大器 20°藉由將每一峰値放大器上之DC偏壓設定爲適當値， 該峰値放大器便可延伸一道候悌（Doherty)動作。針對已添 加高於前者之每一峰値放大器，其在功率範圍中將會對應 增加6dB，藉此將可維持該峰値效率。該四路放大.器可將 有效功率擴充至18dB之理論値。在使用調變架構之數位 通訊系統中，此一擴充極爲重要，其峰値對平均功率比率 可高達13dB。一個120瓦特峰値放大器可由一個四路道 fe；悌配置所提供’且每一路徑（載波及三個峰値放大器+)使 用3 0瓦特之電晶體。 各別功率放大器並不一定要具有相同尺寸，且晶片可 具有不相等的周長或閘極寬度。然而，每一功率放大器必 須阻抗匹配輸出値，並且加以適當偏壓，使得放大器的依 序操作得以在一較寬的功率操作範圍中來實現。 圖2係依照本發明之一封裝的平面視圖，其中複數個 功率放大器晶片20-23被安裝在外殼36中。每一晶片具 有其各自的輸入引線（射頻輸入]-射頻輸入4)及輸出引線 (射頻輸出1·射頻輸出4)。此外，每一電晶體晶片20-23 具有各自針對輸入的阻抗匹配（整體以38標示），以及針 對輸出的阻抗匹配（整體以40標示），並且針對一場效電 晶體（FET)之閘極及汲極來各別偏壓此兩者（針對一雙極裝 (5) (5)1329982 【圖式簡單說明】 圖1係一射頻功率放大器的功能方塊圖，該功率放大 器可在一較寬的功率範圍內來放大一射頻信號，且採用複 數個在共同審查中之申請案第】0/05 9，8 6 6號中所揭露之 各別封裝之功率放大器。 圖2係依照本發明之一實施例之一相同於圖】之功率 放大器的平面視圖。 圖3係圖2之功率放大器連接爲一個四路道候悌放大 器的功能方塊圖。 元件符號對照表. 20載頻放大器 21峰値放大器 2 2峰値放大器 2 3峰値放大器 24 90°變壓器 25 90°變壓器 26 90°變壓器 2 8輸出負載 30 90°變壓器 3 2四路分路器 36外殼 3 8阻抗匹配 4 0阻抗匹配 -9- (6) (6)1329982 5 0兩路分路器 5 2兩路分路器 54兩路分路器 5 6阻抗匹配電路 5 8阻抗匹配電路 60射頻輸出
-10-

Claims (1)

1329982 附件5A 拾、申請專利範圍 第92 1 3 406 8號專利申請案 中文申請專利範圍無劃線替換本 牛月 19 Η 年月曰疹正本 1 ·—種多晶片功率放大器，包含：L--- a) ~外殻’具有複數個輸入引線及複數個輸出引線，
b) 安裝在該外殼中之複數個半導體晶片，每一晶片包 含~電晶體放大器， c) 複數個第一匹配網路，每一匹配網路係在該外殼中 並將半導體晶片連結至輸入引線，及 d) 複數個第二匹配網路，每一網路係在該外殼中並將 半導體晶片連結至輸出引線，藉此使每一晶片具有其各自 的輸入引線及輸出引線。
2.如申請專利範圍第1項之多晶片功率放大器，其中 每一晶片包含具有源極、汲極及閘極元件之場效電晶體、 將閘極元件連結至輸入引線之第一匹配網路及將汲極元件 連結至輸出引線之第二匹配網路。 3 .如申請專利範圍第2項之多晶片功率放大器，其中 該場效電晶體係矽LDMOSFET。 4.如申請專利範圍第2項之多晶片功率放大器’其中 該場效電晶體包含MESFET。 5-如申請專利範圍第1項之多晶片功率放大器’其中 每一晶片包含： 具有集極、基極及射極元件之雙極電晶體、將基極元 1329982 件連結至輸入引線之第一匹配網路及將集極元件連結至_ 出引線之第二匹配網路。 6.如申請專利範圍第5項之多晶片功率放大器’其中 該雙極電晶體包含矽雙極電晶體。 7 .如申請專利範圍第5項之多晶片功率放大器，其中 該雙極電晶體包含III-V異質接面雙極電晶體。 8 .如申請專利範圍第5項之多晶片功率放大器，其中 φ該雙極電晶體包含HEM T。 9 ·如申請專利範圍第1項之多晶片功率放大器，其中 該功率放大器係道候悌（Doherty)放大器，其中一晶片提供 載頻放大器且至少一晶片提供峰値放大器。 1 0 ·如申請專利範圍第9項之多晶片功率放大器，其 中複數個晶片提供複數個峰値放大器，且每一峰値放大器 視輸入信號振幅而定來加以偏壓，以依序致動來放大輸入 信號。 11.一種放大器電路，其包含： a) 信號分路器，用以將輸入信號分路成N信號， b) 外殼，包括N電晶體放大器晶片安裝於其中且具有 N輸入引線及N輸出引線， c) 輸入連結構件，用以將N信號連結至N輸入引 線， d) 位在該外殻中之輸入匹配網路，用以將N輸入引線 中的每一引線連結至N電晶體放大器晶片中之一，及 e) 位在該外殼中之N輸出匹配網路，用以將N輸出 -2- 1329982 引線中每一輸出引線連結至N電晶體放大器晶片中之 _ 〇 12. 如申請專利範圍第μ項之放大器電路，其中每一 晶片包含具有源極、汲極及閘極元件之場效電晶體、將閘 極元件連結至輸入引線之第一匹配網路及將汲極元件連結 - 至輸出引線之第二匹配網路。 · 13. 如申請專利範圍第12項之放大器電路，其中該場 效電晶體係矽LDMOSFET。 φ 1 4.如申請專利範圍第丨2項之放大器電路，其中該場 效電晶體包含MESFET。 15. 如申請專利範圍第11項之放大器電路，其中每一 晶片包含具有集極、基極及射極元件之雙極電晶體、將基 極元件連結至輸入引線之第一匹配網路及將集極元件連結 至輸出引線之第二匹配網路。 16. 如申請專利範圍第15項之放大器電路，其中該雙 極電晶體包含矽雙極電晶體。 # 17. 如申請專利範圍第15項之放大器電路，其中該雙 極電晶體包含III-V異質接面雙極電晶體。 18. 如申請專利範圍第15項之放大器電路，其中該雙 極電晶體包含ΗΕΜΤ。 19. 如申請專利範圍第11項之放大器電路，其中該功 率放大器係道候悌（Doherty)放大器，以一晶片提供載頻放 大器且至少一晶片提供峰値放大器。 20. 如申請專利範圍第19項之放大器電路，其中複彭[ -3- 1329982 個晶片提供複數個峰値放大器，複數個峰値放大器視輸入 信號振幅而被偏壓，以依序啓動來放大輸入信號。
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