TWI327360B - Stacked semiconductor package assembly having hollowed substrate - Google Patents

Stacked semiconductor package assembly having hollowed substrate Download PDF

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Publication number
TWI327360B
TWI327360B TW095119408A TW95119408A TWI327360B TW I327360 B TWI327360 B TW I327360B TW 095119408 A TW095119408 A TW 095119408A TW 95119408 A TW95119408 A TW 95119408A TW I327360 B TWI327360 B TW I327360B
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TW
Taiwan
Prior art keywords
package
substrate
die
frame
stacked
Prior art date
Application number
TW095119408A
Other languages
English (en)
Other versions
TW200703600A (en
Inventor
Young Gue Lee
Original Assignee
Stats Chippac Ltd
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Publication date
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Publication of TW200703600A publication Critical patent/TW200703600A/zh
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Publication of TWI327360B publication Critical patent/TWI327360B/zh

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    • H—ELECTRICITY
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    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Combinations Of Printed Boards (AREA)

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1327360 九、發明說明： 【發明所屬之技術領域】 本發明係關於半導體封裝。 【先前技術】 箝如仃動電 · 4和0丨升久分種》月買2压偈帚型電 子產品需要以最低的成本以有限的佔據面積與最小的厚度 及重里具有更高的半導體功能性與效能。此已驅使工業界 增加對個別半導體晶片的整合。 在一種增加封裝中之功能性與效能的方法中，整合在"ζ 轴上（即，藉由堆疊晶片）實施，I已使用在一封裝中多達 。。個曰曰片之堆疊。此方式提供一緻密晶片結構，其具有— 早晶=封裝之伯據面積，且獲得已不斷減少的厚度。一堆 疊j曰曰粒封裝之成本相比單一晶粒封裝之成本係僅僅增量 更咼且組件良率係足夠高以保證一與在個別封裝中封裝晶 粒相比之競爭性的最終成本。 -對於可在一堆疊式晶粒封裝中堆疊的晶片之數 際限制係堆疊式S#壯 . 弋Βθ粒封裝的低最終測試良率。不可避免 地’某些在封裝中之S♦宜 是级心 曰曰粒某種程度上將為不良品，且因此 最終封裝測試良率將為個別晶 體封裝测試良率之I h Λ民丰之乘積’該等個 晶粒在-封始終低於_。即使僅有兩個 具有低良率，、此方=之一者因為設計複雜性或技術 在"丄:二仍：定言之為1題。 登口的另一方法係堆 封裝模組。堆聶4& 且曰日粒封裝以形成一多 且式封裝與堆叠式晶教封裝相比可提供許多 'H698-980S22.doc 1327360 優點。習知堆疊式球狀柵格陣列封裝之實例描述於（例如 美國專利第7,064,426號之背景中。 舉例而言，在封裝經堆疊之前，具有其晶粒之每一封裝 可經電測試，且被拒絕除非其展示滿意的效能。結果使最 終的堆疊式多封裝模組的良率最大化。
每一晶粒或一個以上晶粒可使用對於晶片類型及組態最 具效率的第一級互連技術（諸如焊線或覆晶）而封裝在堆疊 中的個別封裝中以將效能最大化並將成本最小化。 且 在一堆疊式多封裝模組中的封裝之間的z互連係一自製 造能力、設計靈活性及成本的觀點來看的關鍵技術。已提 出的Z互連包括外圍焊球連接。用於在堆疊式多封裝模組中 之z互連的外圍焊球之使用限制可製得的連接之數量，且限 制設計的靈活性，且導致一更厚且成本更高之封裝。 圖！係說明-習知多封裝模組之—實例之結構的剖視圖 之不意圖，其通常而言已知為一"層疊封裝"
(package-on_paekage)組件，其中在該等堆整式封裝之間^ 互連藉由焊球製得。在此實财之m'(，，底部"封裝） 可為一習知球狀栅格陣列封裝，纟包括-使用-晶粒黏著 黏著劑安裝在一"底部"封裝基板12之-晶粒黏著表面上的 晶粒。底部封裝基板具有至少—金屬層（在說明於^中之 實例中展示了兩個）。底部封裝晶粒藉由焊線電連接至底部 基板，且底部封萝$知盘 - ^ 封閉在一模蓋中。底部封裝 =此：例中藉由第二級互連焊球18電互連至其中配置 裝裝置中的電路，諸如例如-母板(未展示在此實例 111698-980522.doc 1327360 、封裝("頂部"封裝)包括兩個晶粒，其一個在另一個 上方女裝且使用—晶粒黏著黏著劑附著在— =上。底部封裝基板具有至少一金屬層(在說明於= • a的實例中展示為兩個）。頂部封裝晶粒藉由焊線電互連至頂 ' ==二頂部基板之晶粒黏著表面及安敦在其上之所有 、.‘。構破㈣。因而在此實例中，頂部封裝在底部封裝上堆 .叠且在結構方面類似於底部封裝（除了頂部封裝中的z • 科16佈置在頂部封裝基板14之外圍之外），使得其在益需 頂料裝基板干擾底部封裝之模蓋的情況下而實現z互連。 * P焊劑在基板12、14之表面處的金屬層上經圖案化以曝 ⑬在用於電連接的接合位點處的下伏金屬，例如焊線位點 及用於接合焊線與焊球的接合襯墊。 ' S1之層疊封裝模組中的2互連藉由將附著於在頂部封裝 基板Μ之下金屬層上的外圍接合襯塾之焊_回浮在底邱 封裝基板12之上金屬層上的外圍接合襯塾上而達成。在此 ，組態中’在頂部封裝與底部封裝之間的間距h必須至 • 模蓋高度一樣大’該間距h(視在其他因素令底部 封裝B曰粒的厚度與成型材料的流動特性而定)可為0.3 mm .或更多，且通常而言在0·5 _W.5 _之間之—範圍中或 更多。Z互連焊球16必須因此具有一充分大的直徑當以 連浮球16回焊時，其使得與底部基板之接合襯塾良好接 觸；即，d連焊球直徑*須大於封裝高度…更大的球直 徑指示-更大的球間距’其反過來限制適合於可用，，中 的球之數量，從而限制在封裝之間可製得的z互連的數量。 III698-980522.doc 1327360 在-給定間距處的更多數量的球可藉由增加額外列之球而 容納；但此方4需要將額外的基板區域專用於2互連且對 於一給定的底部封裝晶粒大小此方式導致在封裝佔據面積 中的-增加。在底部封裝包括作為增加至全部模蓋厚度之 額外晶粒的兩個或兩個以上堆疊式晶粒時，該問題惡化。 對於某些底部封裝組態，—使用外圍焊球2互連的習知層叠 封裝組態可能為行不通的。 【發明内容】 本發明係關於具有一"中空"基板的可堆疊半導體封裝； 即’該基板具備一開口 ’該開口經設定尺寸以容納在一底 部封裝中之—模蓋’該可堆疊封裝將使用外圍焊球Z互連安 裝該底部封裝上。 在一_態樣中’本發明以—可堆疊封裝基板為特徵， 該可堆疊封裝基板具有一大體而言位於中央的開口該開 口經成形與設定尺寸以容納一 釕裒之一模盍，該可堆疊封 女：於°亥封裝上。因此，該基板具有-圍繞-開口之 兮門 |曰曰粒黏者表面上，該框架基板容納-鄰近 = 邊緣的至少部分的邊際晶粒黏著邊；及大體平行 一外框架邊緣以兩個或兩個以上的列佈置或排列的 .击各 用於女裝在該框架上的晶粒之電互 連。在與該晶粒黏著表面相對 Λ, , . 了 1^表面上’該框架基板衮 納至 >、一列Ζ互連球狀襯墊，Α 之該基板上之對應2互連襯㈣ς佈^㈣㈣在一封裝 該封裝上。 連视墊對準，該可堆疊封裝將安裝於 111698-980522.doc 1327360 在另一通用態樣中，本發明以一 疊封裝為特徵。 在另-通用態樣中，本發明以—堆疊式封裝組件為特 該堆疊式封裝組件包括一使用外圍焊球z互連而安裝在 一第-封裝上之第二封裝，該第—封裝（其可稱作"底部二封 裝）包括附著於-第-封裝基板之一晶粒黏著表面之至少 個a曰粒，其中該晶粒藉由一模蓋封閉。該第二封裝（其可
稱作"頂部”封裝）包括安裝在一框架基板上之至少一個晶 粒二該框架基板具有一圍繞一開口之框架之形式。在晶粒 黏者表面上’該框架基板容納—鄰近該開口之邊緣的至少 部分的m粒黏著邊；及大體平行於至少―外框架邊緣 :置或排列的至少-列焊線位點以用於安裝在該框架上的 晶粒之電互連。在與該晶粒黏著表面相對之該表面上，該 框架基板容納至少—列z互連球狀襯塾，其經佈置或排列以 與在一封裝之該基板上之對應z互連襯墊對準，該可堆疊封
具有該框架基板的可堆 裝將安裝於該封I上。該基板中之該開Π經成形與設定尺 寸以當该等封裂安裝時容納在該底部封裝上之該模蓋； 即’在該組件中該模蓋突出進入使得在該框架基板中之該 開口内可用的空間中。 在某二實施例中’開口通常而言係矩形(例如通常而言為 正方形）以容納—通常而言為矩形或正方形的模蓋。開口必 須至/足夠大M容許當z互連已經完成時突出的模蓋。在某 二實施例中1 α係至少與模蓋的佔據面積—樣大，其中 蓋符&下封裝基板表面；纟某些實施例中，其中模蓋具 111698-980522.doc 1327360 有傾斜側面，開口相比模蓋的佔據面積可為稍小’該門口 具有-在模蓋佔據面積的大小與模蓋之上表面的大小: 的範圍中的尺寸。 间 在某些實施例中，第一（底部）封裝係-球狀柵格陣列封 裝’其具有安裝在第一封裝基板上且藉由焊線與第一封裝 基板互連的一或多個晶粒，或具有藉由覆晶互連而安裝在、 基板上的一或多個晶粒。 在另-通用態樣中’本發明以—製造—堆疊式層疊封裝 組件的方法為特徵，其藉由：提供—模製的第—封裝，^ 具有在晶粒與模蓋形成於上的表面上成—列或__陣列的^ 圍Z互連焊球墊片；提供一可堆疊第二封裝，其藉由：提供 -框架基板’其具有—晶粒黏著側面與—相對表面及—經 成形與設定尺寸以容納模蓋之開口，且在㈣㈣面上且 有成-列或-陣列之2互連焊球襯塾，將至少一個晶粒安裝 在該框架基板之該晶粒黏著侧面上且藉由焊線將該晶粒電 互連在該基板之該晶粒點著側面i，將在該才匡架基板之該 晶粒黏著側面上之該晶粒與互連密封，及將Z互連焊球安裝 在該相對側面上之該等焊球襯墊上；將該第二封裝與該第 一封裝對準以使得在該第二封裝上之該等z互連焊球與在 該第-封裝上之個別焊球襯塾對準，及將焊球與球狀概塾 接觸且回焊以完成第一封裝基板與第二封裝基板的安裝與 電互連。在某些實施例中組件可過度模塑。 【實施方式】 本發明現將藉由參看圖式來進一步地詳細描述，其說明 111698-980522.doc 1327360 本發明之替代實施例。該等圖式係圖解的，其展示本發明 • t特徵及其與其他特徵及結構的關係，且該等圖式並未按 比例纷製。為改良表達的簡明性，在說明本發明之實施例 • 的圖中，對應於在其他圖式中所展示的元件之元件未全部 • 特別地指定，雖然該等元件在所有圖中可容易地識別。 . 5見轉至圖2,在-示意性剖視圖中展示-根據本發明之一 . 態樣的一堆疊式封裝組件的實例》 • 在此實例中第-(·，底部")封裝21係-經模製的堆疊式晶 粒球狀柵格陣列封裝。其包括兩個晶粒，一安裝在"底部" 封裝基板22之一晶粒黏著表面上的下晶粒，及一安裝在下 晶粒上的上晶粒。在此實例中底部封裝基板具有兩個金屬 ·· 層，每一金屬層在一介電層之每一側面上。該等金屬層藉 ' 由通道連接。一阻焊劑覆蓋每一金屬層，且經圖案化以曝 露在用於電連接之在金屬層上的位點，諸如焊線位點及焊 球襯墊"晶粒使用一諸如一晶粒黏著環氧樹脂或一薄膜黏 • 著劑的晶粒黏著黏著劑而安裝。晶粒藉由焊線將在晶粒上 的襯墊連接至曝露在底部基板之晶粒黏著表面中的金屬層 上的位點而電互連至底部基板22，且晶粒與焊線藉由在一 . 模蓋中的封裝而封閉。一標準的球狀柵格陣列封裝描述於 (例如）美國專利第7,064 426號之背景中。 在圖2之本發明之實施例中，"頂部"封裝23具有在一"框 架"基板24上的兩個晶粒。即，頂部封裝基板“具有一環繞 一開口之框架之形式，其展示於在圖4 A及圖4B中的剖視圖 與平面圖中。在晶粒黏著表面上（在"上"側面），輕架基你容 lU698-980522.doc •11- 納一鄰近開口之邊缝 、甘 緣的至少部分的邊際晶粒黏著巴蛣.Λ 沿著至少一外框芊邊绥伏$ 4 邾者Q域，及 I朱邊緣佈置或排列的至少 用於安裝在框架上的日扣+兩 坏線位點以 而m… 電互連。在此實例令開口通常 而5係正方形，當該等 容納-大F女裝時，该開口經設定尺寸以 、’ 。為正方形的底部封裝模蓋； 模蓋突出進入在框牟甚&由+ 在、，且件中 h架基❹之開口内的已製成的可用空間 中。同樣在此實例中，Β如私#广i I财BB粒黏者區域包括在正方形開口之 所有四個側面上的邊。尤 。 在藉由圖4B中展示的虛線46所指示 的區域内，第-晶粒使用一晶粒黏著黏著劑附著於開口之 邊。第二晶粒使用一晶粒黏著黏著劑附著於第—晶粒，且 BB粒藉由焊線將在晶粒上之襯墊連接至曝露在頂部基板之 晶粒黏著表面中的金屬層上的位點而互連至頂部基板24。 在與晶粒黏著表面相對之表面上，框架基板24容納至少一 列2互連球狀襯墊，其經佈置或排列以與在底部封裝之基板 上之對應的z互連襯墊對準。2互連焊球26安裝在球狀襯墊 上’且接著經自焊以形成在頂部基板24與底部基板22之間 的互連。為了將組件互連至覆蓋諸如一母板之下伏電路， 第二級互連焊球28附著於在底部基板22之下（"焊盤"）側面 上的第二級互連位點。 現特定地參看圖4A與圖4B，其展示一具有一開口 40之框 架基板44。該框架基板具有一晶粒黏著（”上”）側面45，其具 備外圍地排列的接合指48，該等接合指48在此實例中鄰近 基板44之外邊緣43。一在圖4B中藉由虛線46界定的晶粒黏 著區域位於框架基板44之一内部邊處，鄰近在框架基板44 H1698-980522.doc 1327360 中的開口 40之邊緣41。 如圖2展示，在根據本發明的組件令，底部封裝模蓋突出 進入在框架基板中的開口 t。該等焊球具有―大小該大 小足以提供在模蓋之頂部與在開口處的頂㈣裝±的第_ 晶粒之下面之間的間隙；且該開口經設定尺寸使得在開口 之邊緣與模蓋之間存在間隙。在某些實施例中(例如見圖 6)’組件經過度模塑，且在此等實施例中必須在模蓋與 晶粒之間’及在模蓋與開口之邊緣之間提供充足間距以允 許在封裝過程期間模製材料之流動。 同樣如圖2展示，在此實例中，,級互連焊球經設定大小 以在頂部封裝與底部封裝之間提供-如在圖!之習知封裝 中之間距h。因為根據本發明頂部封裝基板係一框架基板: 所以在圖2之實例中容納的一模蓋(在此實例中，其遮蓋兩 個堆疊式晶粒）相比可在―習知層疊封裝模組中容納之模
蓋厚得多。此方式S供在組件+的底㈣$中之增加、 導體裝置密度。 -旦封裝形成且z互連完成，如在圖2中所展示，為了組 件與其中配置組件的裝置中的電路(諸如-母板；未展示) 之互連，第二級互連球28安裝在第一封裝基板之下面上的 焊球概墊上。 在圖3中展示本發明之另一實施例之一實例。在此實施例 中底部封裝31具有單一晶粒，且模蓋具有與在例如在圖^ 中所展不的習知層疊封裝模組中之模蓋相同之厚度。此 處，然而，因為根據本發明頂部封裝33基板Μ係一框架基 H1698-980522.do. •13· 1327360 板，所以模蓋可容納於開口内。因此可製得的在頂部基板 與底部基板之間的間距t相比在習知層疊封裝組件中之間 距（h)可較小。此方式使較小的2互連焊球刊之使用為可能。 較小的z互連球之使用反過來容許一較小的球間距，從而能 夠使用t抵集的互連路;^，且II此在無需將任何額外基 板區域專用於互連之情況下（或，在某些設計中需要將較 少的基板區域專用於互連），提供相比在習知組件中更多數 量的在封裝之間的互連。為了將組件互連至諸如一母扳的 下伏電路，第二級互連焊球38附著於在底部基板32之下（" 桿盤"）側面上的第二級互連位點。 根據本發明之頂部封裝可通常而言以（例如）在圖5 A至圖 5E中所展示的階段而製得，且根據本發明之一組件可如（例 如）在圖5E、圖5F及圖5G中所展示而製得。圖5八展示一頂 部基板框架44,其可由習知基板材料（其中金屬層經適合地 圖案化）製得，且開口可使用習知工具沖孔或鋸開而製得。 在此展示的實例中之基板具有兩個金屬層（在兩者之間具 有一介電層），且該等金屬層藉由通過介電層的通道連接。 其他基板類型可用於頂部基板’例如包括：一具有2至6個 金屬層的層壓板、或一具有4至8個金屬層的組裝基板、戍 一具有1至2個金屬層的可撓性聚醯亞胺帶、或一陶究多層 基板。一般而言，基板可藉由圖案化及組裝之習知方法建 構’其中該（等）金屬層之設計考慮開口；且開口可藉由鑛開 或沖孔製得。通常地，基板以在一條帶中的一列或陣列之 基板而形成’自其個體封裝在完成之某些階段經鋸開或沖 H1698-980522.doc • 14· 1327360 孔而切單。 如在圖5B中展示，第一晶粒5 14使用一晶粒黏著黏著劑 513安裝在框架基板之開口的邊緣之邊處的晶粒黏著區域 晶粒主動側向上地安裝。在某些實施例中，晶粒附著
於鄰近開口之整個邊緣（或所有邊緣）的邊。在其他實施例中 晶粒可具有一比開口窄的尺寸，且在此等實施例令，晶粒 可附著於鄰近開口之僅僅部分處的邊緣（舉例而言，如在一 通常而言為矩形或正方形的開口之相對邊緣處）之邊。一第 二晶粒524使用一晶粒黏著黏著劑523主動側向上地安裝在 第一晶粒之朝上的主動表面上。如在圖5C所展示，第一晶 粒與第一晶粒藉由在晶粒上的襯墊與曝露在頂部基板之上 側面上的金屬層上之圖案化的阻焊劑中的焊線位點之間的 焊線58連接至框架基板，且如在圊5]〇中所展示，頂部框架 基板之晶粒黏著表面與安裝在晶粒黏著表面上的所有特徵 (包括晶粒與線）使用一封裝材料57密封。接著z互連焊球Μ 女裝在頂部框架基板之相對側面上之焊球襯墊上以製得在 圖5E中所展示的頂部可堆疊封裝23。 如在圖5E中所展示’頂部可堆疊封裝接著與一底部模製 封裝22對準，且如由在圖财的虛線所展示，兩個封裝移 動在一起以使得在頂部封裝上的z互連焊球與在底部封裝 之晶粒黏著表面上的對應的2互連焊球襯㈣觸。接 經回焊以完成互連’從而形成在圖汀中所展示的組件％。 在藉由圖5E中之實例展示的實例中，底部封袭21 疊式晶粒封裝，其具有安裝在底部封裝基板上方且藉由谭 III698-980522.doc •15· 1^27360 • 線”底。卩封裝基板22互連的第_與第二晶粒214。底部封裝 =模製以形成一模蓋217。本發明預期其他模製的底部封裝 組態；例如，底部封裝可僅具有一個晶粒，或兩個以上晶 . ’’立丨及’例如’在底部封裝，的至少-個晶粒可為一覆晶 . 晶粒。 • 〜如可瞭解，組件可形成直至如在圖5”所展示的一階 奴但省略第二級互連球28。模組至另一裝置或至在裝置 籲（其中配置模組）中的電路的互連可藉由除焊球互連外之構 件製得；例如，襯塾或焊線可視最終用途之環境而定而使
實務上’頂部封裝與底部封裝兩者可以一列或陣列形 成其以-列或陣列基板條帶開始。根據本發明的頂部封 裝可以列或陣列基板條帶開始而製得，且可在條帶上形 成，直至在圖5C中所展示的階段；接著整個的列或陣列之 封褒可經密封且封裝硬化，且個別封裝可經㈣而切單。 底部封裝可以-列或陣列之基板條帶開始直至並包括穴模 製之形成模蓋而製得1部封裝在底部封裝上的 組合可接著在底部封裝之條帶或陣列上進行，且接著該等 *、且件可藉由通過底部基板沖孔（例如）而切單。 在某些實施例中組件經過度模塑；即，一模製材 裝材料67經塗覆以填充在頂部封裝與底部封裝之間的* 間’及同樣填充在側面之—薄層中及頂部封裝之頂部以= 成（例如）在圖6中所展示的過度模塑模組6〇。在想要卢 模塑模組時與組件以條帶或陣列形式形成時，料可藉^ M1698-980522.doc -16- 1327360 帶或陣列之組件密封而完成’且接著經拉鑛而切 獲传如在圖6中所展示的個別模組。 ^發明之多封裝模組可使諸任何不同的多種應用卜 • =，電腦、攜帶型通信裝置、消費型產品。 .太^ 考之所有㈣與專射㈣Μ用的方式併入 不文中。 • 【圖式簡單說明】 •甚=係一以一剖視圖形式之示意圖’其展示-藉由在封裝 基板之間的外圍焊球而具有ζ連 裝模組。 ㈣备知層疊封裝"多封 之一以一剖視圖形式的示意圖，其展示一根據本發明 樣之-層叠封褒組件的實例，其中一通過頂部封裝 ' 基板之開口經設定尺寸以容納在一 之模蓋。 堆®式晶粒底部封裝中 之圖一圖形式的示意圖’其展示一根據本發明 裝組件之實例，其中-通過頂部封裝 .基板之開口經設定尺寸以容納在-底部封裝中之模蓋，該 實例允許更小直徑的2互連球之使用。 •月圖剖視圖形式的示意圖’其展示一根據本發 明之^樣的可堆疊封裝基板，其具有—在該處通過以容 納一藉由外圍焊球將安裝可 的開口。 1封裝於上的封裝之-模蓋 圖4Β係一以一平面圖形式 中之基板。 之丁意圖，其展示-如在圖4Α I11698-980522.doc -17- 1327360 圖5 A至5F係以剖視圖之形式的示意圖，其展示根據本發 明之一態樣的在一可堆疊頂部封裝之構造中的产自^又。 圖6係一以一剖視圖形式的示意圖，其展示根據本發明之 一態樣的一層疊封裝組件之一實例，類似於說明於圖2中之 實例，其具過度模塑。 【主要元件符號說明】
12 底部封裝基板 14 頂部封裝基板 16 z互連焊球 18 第二級互連焊球 21 第一（底部）封裝 22 底部封裝基板 23 頂部封裝 24 頂部封裝基板/框架基板 26 z互連焊球 28 第二級互連焊球 31 底部封裝 32 底部基板 36 Z互連焊球 38 第二級互連焊球 40 開口 41 邊緣 43 外邊緣 44 框架基板 111698-980522.doc -18 - 1327360 45 晶粒黏著（上）側面 48 接合指 50 組件 57 封裝材料 58 焊線 60 過度模塑模組 67 模製材料或封裝材料 214 第一與第二晶粒
217 模蓋 513 晶粒黏著黏著劑 514 第一晶粒 523 晶粒黏著黏著劑 524 第二晶粒
111698-980522.doc -19-

Claims (1)

1327360 % ’月2^日 第095119408號專利申請案 .中文申請專利範圍替換本(99年1月） 十、申請專利範圍： L種堆疊式封裝組件，其包含—使用外圍焊球z互連而安 裝在第封裝上之第二封裝，其中該第一封裝包含附 著於-第一封裝基板之一晶粒毒占著表面之至少一個第一 封裝曰曰粒’該第—封裝晶粒藉由-模蓋封閉，且其中該 第封裝包3女裝在一框架基板之一晶粒黏著側面上之 至；一個第二封裝晶粒，該框架基板具有一圍繞一開口 忙架之形式，當该第二封裝以該框架基板容納鄰近該 $之邊緣的至少部份的—邊際晶粒黏著區域而被安裝 於該第-封裝基板時’該開口經成形與設定尺寸以容納 在該第一封裝上之該模蓋。 :长項1之堆疊式封裝組件，其中該框架基板在該晶粒 黏著側面上包含鄰近該開σ之邊緣之至少部分的一邊際 晶粒黏著邊。 3. 如f求項1之堆疊式封裝組件，其中該框架基板在該晶粒 黏著側面上包含’沿著至少—外框架邊緣之至少一列焊 線位點以用於該第二封裝晶粒之電互連。 4. 如請，項1之堆疊式封裝組件，其中該框架基板在與該晶 粒黏著側面相對之側面上包含複數個z互連球狀概塾，其 =置以與在該第—封裝之該基板上之對應2互連概塾 5·如°月求項1之堆疊式封裝組件，其中該模蓋突出進入在該 框架基板中之該開口内之該空間中。 如月求項1之堆疊式封裝組件，其中該開口大體而言係矩 111698-990122.doc 如請求W之堆疊式封裝 方形 組件，其中該開口大體而言係正 8·如請求項丨之堆最 蓋之-佔據*二大裝組件’其中該開σ係至少與該模 9. =!ΓΓ:式封裝組件，其—係至少與該模 衣面一樣大。 10. 如請求項丨之堆疊式 大於兮心 料組件，其中該模蓋之-佔據面積 兀尽忒模盍之一表面， 佔Μ 其中6玄開口具有在一在該模蓋 佔據面積之大小與該 供益t上表面之大小之間之範圍中 t尺寸。 其中該第一封裝係一球狀 u.如請求項1之堆疊式封裝組件 柵格陣列封裝。 12.如請求们之堆疊式封褒組件其中該第一封裝包含安裝 在該第-封裝基板上且藉由料與㈣—封裝基板互連 之至少一個晶粒。 13. —種製造一可堆疊半導體封裝之方法，其包含： 提供一框架基板，其具有一晶粒黏著側面與一相對表 面及一經成形與設定尺寸之開口以容納一封裝之一模蓋 並將容納鄰近該開口之邊緣的至少部份的一邊際晶粒黏 著區域的該框架基板安裝至該封裝之基板，且在該相對 表面上具有成一列或一陣列之Z互連焊球襯墊， 將至少一個晶粒安裝在該框架基板之該晶粒黏著側面 之一晶粒黏著區域上且藉由焊線將該晶粒電互連在該某 111698-990122.doc 14. 板之該晶粒黏著側面上，將在該框架基板之該晶粒黏著 側面上與互連密封’及將z互連焊球安裝在該相 對表面上之該等焊球襯墊上。 -種製造-堆疊式封裝組件之方法，其包含： 提供-經模製之第一封裝，其包括一安裝在一第一封 該模蓋側面上之外圍Z互連焊球襯墊；
裝基板之一模蓋側面上之晶粒 該第一封裝基板具有在 提供一如請求項13製造之可堆疊第二封裝， 將Z互連焊球安裝在該框架基板之該相對側面上之該 等焊球襯墊上； 將該第一封裝與該第一封裝對準以使得在該第二封裝 上之該等Z互連焊球與在該第一封裝上之個別焊球襯墊 對準；及 使該等焊球與該等球狀襯墊接觸且回焊以完成該第一 封襄基板與該第二封裝基板之該安裝與電互連。
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