TW480688B - Window BGA package structure - Google Patents

Window BGA package structure Download PDF

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Publication number
TW480688B
TW480688B TW090113424A TW90113424A TW480688B TW 480688 B TW480688 B TW 480688B TW 090113424 A TW090113424 A TW 090113424A TW 90113424 A TW90113424 A TW 90113424A TW 480688 B TW480688 B TW 480688B
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Taiwan
Prior art keywords
integrated circuit
circuit board
window
chip
wafer
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TW090113424A
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Chinese (zh)
Inventor
Cho-Liang Chung
Yao-Jeng Lee
Camille Lin
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Chipmos Technologies Inc
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Priority to TW090113424A priority Critical patent/TW480688B/en
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Publication of TW480688B publication Critical patent/TW480688B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73207—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92127—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

An integrated circuit package comprises: a chip, a circuit board, a plurality of metal bonding wires, a plurality of solder balls, a package body, and a plurality of bump spacers. The circuit board has a die-attaching surface, a ball-planting surface, and at least a window. The solder balls bond on the ball-planting surface. The chip locates on the die-attaching surface. The metal bonding wires connect the chip and the circuit board through the window. The bump spacers are between the chip and the circuit board to form an interval for the pre-curing package body flowing.

Description

480688480688

【發明領域】 本發明係有關於一種窗口 bga封裝結構及其封裝方 法’特別是有關於一種晶片尺寸封裝之窗口 BGA封裝結 構0 【先前技術】[Field of the invention] The present invention relates to a window bga packaging structure and a packaging method ', and more particularly to a wafer-size package window BGA packaging structure. 0 [Previous technology]

、在美國專利第6, 177, 723號「積體電路封裝及其平板 【模過程」中’揭示一種具窗口 封裝〔wind〇w Ball Grid Array package〕型態之積體電路封裝結構，第8圖 為該積體電路封裝結構3 00之截面圖，第9圖為該積體電與 f裝結構300之頂視圖，該積體電路封裝結構30 0包含有一 晶片310、一電路板32〇、複數個金屬導線33〇、複數個焊 球340、一封膠體35 0及一膠膜36〇，其中電路板32〇係為一 種多層印刷電路板，除了本體外另包含第二層板32 i、第 三層板322及一窗口 323，在第二層板321上形成有複數個 引接線324以及在第三層板3 22上形成有巴士條325，以 為電路板320對金屬導線330之連接點，在窗口 323上方带 成一階梯狀開放之上開口 328，在窗口 323之下方形成一以 槽326，而晶片310係以兩面黏性之膠膜36〇黏貼於電路 320之凹槽326内，在焊接複數個焊球34〇之前先以壓模 〔molding〕方式形成封膠體35〇，由於封膠體35〇必須 時填充於凹槽32 6、窗口 323及上開口以8，因此窗口32 長度須略大於晶片310之長度，而構成在窗口 323上下 被晶片310覆蓋之間距327〔如第9圖所示〕，以構成 凹槽326與上開口 328之通料槽道，使得在壓模灌膠時，In U.S. Patent No. 6,177,723, "Integrated Circuit Package and Its Flat Panel [Molding Process]" reveals an integrated circuit package structure with a window package [window ball grid array package] type, No. 8 The figure is a cross-sectional view of the integrated circuit packaging structure 300, and FIG. 9 is a top view of the integrated circuit and f-mount structure 300. The integrated circuit packaging structure 300 includes a chip 310, a circuit board 32, A plurality of metal wires 33o, a plurality of solder balls 340, a colloid 350 and a film 36o, among which the circuit board 32o is a multilayer printed circuit board, which includes a second layer board 32i in addition to the body. The third layer board 322 and a window 323. A plurality of lead wires 324 are formed on the second layer board 321 and a bus bar 325 is formed on the third layer board 322, which are the connection points of the circuit board 320 to the metal wires 330. A stepped opening 328 is formed above the window 323, and a groove 326 is formed below the window 323, and the wafer 310 is adhered to the groove 326 of the circuit 320 with an adhesive film 36 on both sides. Weld a plurality of solder balls 34 ° before using a stamper (mold ing] method is used to form the sealing compound 35. Since the sealing compound 35 must be filled in the groove 32 6, the window 323, and the upper opening with 8, the length of the window 32 must be slightly longer than the length of the wafer 310, and the upper and lower sides of the window 323 are formed. Wafer 310 covers a gap of 327 (as shown in FIG. 9) to form a feed channel of groove 326 and upper opening 328, so that when the mold is filled with glue,

第5頁 480688 五、發明說明（2)Page 5 480688 V. Description of the invention (2)

膠體350能同時填充凹槽326與上開口 328，但其缺點為電 路板320之窗口323在設計上其長度須略大於晶片31〇之長 度’使得電路板320之機械強度較差而容易輕曲，甚至無 法適用於晶片尺寸封裝〔Chip Scale Package〕，即電路 板3 2 0之尺寸無法小於晶片3 1 0尺寸之一點三倍，此外，利 用膠膜360黏貼晶片310不但成本較高，並且晶片31〇與電 路板320因熱膨脹不同引起之熱應力也無法有效消除。 【發明目的及概要】 本發明之主要目的在於提供一種具窗口 BG A封裝型態 之積體電路封裝結構，利用複數個間隔墊塊係位於電路板 之黏晶表面與晶片之積體電路形成面之間，提供在電路板 與晶片之一間距，以供未固化前封膠體之流動，使得電路 板之窗口尺寸設計不再受制於晶片尺寸，導致電路板之窗 口可有效縮小’達到增進電路板機械強度，甚至可供晶片 尺寸封裝之功效。 本發明之次一目的在於提供一種具窗口 BGA封裝型態 之積體電路封裝結構，利用複數個低成本之間隔墊塊係^立 於電路板之黏晶表面與晶片之積體電路形成面之間，以取 代習用高價之兩面黏性膠膜，以降低成本， 電路板之熱應力作用，以防止㈣。 ^ 本發明之再一目的在於提供一種具窗口 BGA封裝型態 之積體電路之封裝方法，在黏晶時利用複數個間隔墊塊^系 位於電路板之黏晶表面與晶片之積體電路形成面之間，以 取代習用之兩面黏性膠膜，以形成一在電路板與晶片之間The gel 350 can fill the groove 326 and the upper opening 328 at the same time, but its disadvantage is that the length of the window 323 of the circuit board 320 must be slightly longer than the length of the wafer 31 ′, which makes the mechanical strength of the circuit board 320 poor and easy to bend. It ca n’t even be applied to Chip Scale Package, that is, the size of the circuit board 3 2 0 cannot be smaller than one third of the size of the chip 3 10. In addition, the use of the adhesive film 360 to attach the chip 310 is not only costly, but also the chip The thermal stress caused by the thermal expansion between the 31 and the circuit board 320 cannot be effectively eliminated. [Objective and Summary of the Invention] The main object of the present invention is to provide an integrated circuit packaging structure with a window BG A package type, and a plurality of spacers are used to form an integrated circuit forming surface of a die bonding surface of a circuit board and a chip. Provide a distance between the circuit board and the wafer for the flow of the uncured pre-sealing gel, so that the design of the window size of the circuit board is no longer limited by the size of the wafer, which leads to the effective reduction of the window of the circuit board. Mechanical strength can even be used for chip size packaging. It is a second object of the present invention to provide an integrated circuit packaging structure with a window BGA package type, which uses a plurality of low-cost spacers to stand on the surface of a die bond of a circuit board and the integrated circuit forming surface of a wafer. In order to reduce the cost, the thermal stress of the circuit board is used to prevent the pimple. ^ Another object of the present invention is to provide a packaging method of a chip integrated circuit with a window BGA packaging type. When a die is bonded, a plurality of spacers are used. ^ The chip integrated circuit formed on the die surface of the circuit board and the chip is formed. Between two sides to replace the conventional two-sided adhesive film to form a circuit board and chip

第6頁 480688Page 6 480688

供未固化前㈣體之流動，模具不需再設計具 依太於口與黏晶表面之通料槽道，以降低製造成本。 依本务明之積體電路封裝結構，其包含： 包路板’具有-黏晶表面、—焊球表面及至少一窗For the flow of the uncured front carcass, the mold does not need to be designed with a feed channel that is too close to the mouth and the surface of the sticky crystal to reduce the manufacturing cost. The integrated circuit package structure according to the present invention includes: a package board having a surface of a sticky crystal, a surface of a solder ball, and at least one window

中 ;L片i位於電路板之勘晶表面上，該晶片具有-積 $路2成面及在該積體電路形成面之複數個焊塾，其 該硬數個焊墊係對應於電路板之窗口； 一封膠體； ’ 體隔塾塊，位於電路板之黏晶表面與晶片之積 祉，路形成面之間，提供在電路板與晶片之—間距，以 供未固化前封膠體之流動； f數個焊球，接合於電路板之焊球表面；及 複數個金屬導線，連接該晶片之焊墊與該電路板。 【發明詳細說明】 叫參閱所附圖式，本發明將列舉以下之實施例說明： 第1圖係依本發明之第一具體實施例，一種積體電路 =裝結構100之局部剖視立體圖，第2圖為該積體電路封裝 結構100之截面圖，第仏至3(1圖為該積體電路封裝結構1〇〇 之封裝過程截面圖，第4圖則在該積體電路封裝結構1〇()内 晶片110與電路板120之頂面示意圖。 該積體電路封裝結構丨00係包含有一晶片11〇、一電路 板12G、複數個金屬導線13〇、複數個焊球14〇、一封膠體 150及複數個間隔墊塊16〇，其中該電路板ι2〇具有一窗口Medium; L piece i is located on the crystal surface of the circuit board. The wafer has a product surface of 2 and a plurality of solder pads on the surface of the integrated circuit. The hard pads correspond to the circuit board. A window; a colloid; a body block, located between the surface of the circuit board and the wafer, and the road-forming surface, providing a space between the circuit board and the wafer for the uncured pre-sealed colloid Flow; f several solder balls, which are bonded to the surface of the solder ball of the circuit board; and a plurality of metal wires, which connect the solder pads of the chip and the circuit board. [Detailed description of the invention] With reference to the attached drawings, the present invention will enumerate the following embodiments: FIG. 1 is a partial cross-sectional perspective view of an integrated circuit = assembly structure 100 according to a first specific embodiment of the present invention. Fig. 2 is a cross-sectional view of the integrated circuit packaging structure 100, and Figs. 1-3 to 3 (1 is a cross-sectional view of the packaging process of the integrated circuit packaging structure 100, and Fig. 4 is the integrated circuit packaging structure 1 〇 () A schematic diagram of the top surface of the inner chip 110 and the circuit board 120. The integrated circuit package structure 丨 00 includes a chip 11 〇, a circuit board 12G, a plurality of metal wires 13 〇, a plurality of solder balls 14 〇, a Sealing gel 150 and a plurality of spacers 160, wherein the circuit board ι20 has a window

480688 五、發明說明（4) ---- 1 2 3，而複數個焊球1 4 0係呈球格陣列方式形成於電路板 120之焊球表面122，故積體電路封裝結構1〇〇係為窗口 BGA 〔Bal 1 Grid Array，球格陣列〕封裝型態。 曰曰片11 0係為一記憶體晶片、微處理器、邏輯性晶片 或其他晶片，例如DRAM、SRAM、SDRAM、ROM、EPROM、 flash、Rambus或DDR等記憶體晶片，如第！圖所示，晶片 110具有一積體電路形成面〔integrated circuit forming surface〕以及在該積體電路形成面上之複數個 焊墊111〔 bonding pad〕，其係以積體電路形成面朝向電 路板120之方式形成於電路板丨2〇之黏晶表面12ι上。 如第1及2圖所示，電路板12〇係為由Fr —4、FR-5或BT — 樹脂等含玻璃纖維布強化樹脂材質製備之微型印刷電路板 或疋共燒陶瓷電路板，其具有單層或多層之電路圖案，甚 至是具單層電路圖案之聚醯亞胺膠膜，電路板12〇具有一 黏晶表面121、一焊球表面122及一窗口 123，其中黏晶表 面1 2 1係用以黏固晶片11 〇，焊球表面丨2 2係用以焊接如鉛 錫合金之焊球140〔solder ball〕，以供表面接合，而窗 口 1 2 3係用以黏晶時裸露晶片11 〇之焊墊丨丨1，以供如金 線、銅線或含銅合金線等之金屬導線13〇打線連接晶片丨1() 與電路板120〔晶片11〇與電路板120之内部電性連接〕。 複數個間隔墊塊1 6 〇位於電路板1 2 0之黏晶表面1 2 1與 曰曰片110之積體電路形成面兩者之間，用以提供電路板12〇 與晶片110之一間距，以供未固化前封膠體15〇之流動，其 中該封膠體150係密封窗口丨23及晶片110，通常該間隔墊480688 V. Description of the invention (4) ---- 1 2 3, and the plurality of solder balls 1 40 are formed in a ball grid array on the solder ball surface 122 of the circuit board 120, so the integrated circuit packaging structure 10 It is a window BGA [Bal 1 Grid Array] package type. The chip 110 is a memory chip, microprocessor, logic chip, or other chip, such as a DRAM, SRAM, SDRAM, ROM, EPROM, flash, Rambus, or DDR memory chip. As shown in the figure, the chip 110 has an integrated circuit forming surface and a plurality of bonding pads 111 on the integrated circuit forming surface. The integrated circuit forming surface faces the circuit board. The 120 method is formed on the sticky surface 12m of the circuit board 丨 20. As shown in Figs. 1 and 2, the circuit board 120 is a micro printed circuit board or a co-fired ceramic circuit board made of glass fiber cloth-reinforced resin materials such as Fr-4, FR-5, or BT-resin. With a single-layer or multi-layer circuit pattern, or even a polyimide film with a single-layer circuit pattern, the circuit board 120 has a sticky crystal surface 121, a solder ball surface 122, and a window 123, of which the sticky crystal surface 1 2 1 is used to bond the wafer 11 〇, the surface of the solder ball 2 2 is used to solder a solder ball 140 [solder ball] such as lead-tin alloy for surface bonding, and the window 1 2 3 is used for the bonding of crystal The exposed pad of the wafer 11 〇 丨 1 for metal wires such as gold wire, copper wire or copper-containing alloy wire, etc. to connect the chip 丨 1 () and the circuit board 120 [wafer 11 〇 and the circuit board 120 Internal electrical connection]. A plurality of spacers 16 are located between the sticky surface 1 2 1 of the circuit board 120 and the integrated circuit forming surface of the wafer 110 to provide a distance between the circuit board 12 and the wafer 110. For the flow of the uncured sealant 150, wherein the sealant 150 is a sealed window 23 and the wafer 110, usually the spacer

480688 五、發明說明（5) 塊1 6 0之高度係在〇 · 0 5 mm至0 · 3mm之間，而在本實施例中， 間隔墊塊1 6 0係為一種具彈性之熱固性環氧化合物，如矽 膠〔s i 1 i ca ge 1〕，以液態網版印刷或固態黏附方式形成 該複數個呈圓柱體、橢圓體、圓球或其它形狀之間隔墊塊 1 6 0，此外，在間隔墊塊丨6 〇與晶片丨丨〇之間具有如銀膠之 黏膠161 ’以黏合晶片。 因此’該積體電路封裝結構1 〇 〇利用間隔塾塊1 6 〇具有 多重的功效，第一、間隔墊塊丨60所提供在晶片11()與電路 板120之間距，可以供未固化前封膠體15〇之流動，不再需 要特殊的電路板設計〔稍後詳述〕或模具變更；第二、間 隔塾塊1 6 0〔包含黏膠1 6 1〕遠比習知之兩面黏性膠膜具有 較低的成本；第三、克服晶片11()與電路板12〇之熱應力作 用’以防止翹曲〔warpage〕。 由於間隔墊塊1 6 0可供未固化前封膠體1 5 〇之流通於電 路板120之窗口123與黏晶表面121之上方，因此，如第4圖 所示，電路板120之窗口123長度L2不需要如習用的設計般 長於晶片之同一邊長度，即電路板12〇之窗口 123長度L2可 以小於晶片11 〇較長邊的長度L1，不再局限窗口丨2 3之設 冲 ^固口123長度L2小於晶片11〇較長邊的長度li時，電 路板120之機械強度能有效提昇，甚至使得可適用於晶片 尺寸封裝結構〔Chip Scale Package，CSP〕，也就是電 路板1 2 0〔黏晶表面1 2 1〕係不大於該晶片11 〇〔積體電路 形成面〕之一點三倍。在第5圖中則為電路板之窗口設計 變化’由於間隔墊塊1 6 0已克服封膠體1 5 〇在窗口與黏晶表480688 V. Description of the invention (5) The height of the block 160 is between 0.05 mm and 0.3 mm, and in this embodiment, the spacer block 160 is an elastic thermosetting epoxy. Compounds, such as silicone [si 1 i ca ge 1], are formed by liquid screen printing or solid-state adhesion to form a plurality of spacers 160, which are cylindrical, ellipsoidal, spherical, or other shapes. There is an adhesive 161 ′ such as silver glue between the pad 丨 6 〇 and the wafer 丨 丨 0 to adhere the wafer. Therefore, the integrated circuit package structure 100 has multiple functions using the spacers 160. First, the spacers 60 provided between the wafer 11 () and the circuit board 120 can be used before curing. The flow of the sealant 150 is no longer required for special circuit board design [more details later] or mold changes; second, the spacer block 160 (including the adhesive 1 6 1) is far more than the conventional two-sided adhesive The film has a lower cost; third, to overcome the thermal stress effect of the wafer 11 () and the circuit board 12 ′ to prevent warpage. Since the spacer 160 can be used for the uncured front sealing gel 1 50 to circulate above the window 123 and the die-attach surface 121 of the circuit board 120, as shown in FIG. 4, the length of the window 123 of the circuit board 120 L2 does not need to be longer than the length of the same side of the chip as in the conventional design, that is, the length L2 of the window 123 of the circuit board 12 can be smaller than the length L1 of the longer side of the chip 11 〇, no longer limited to the window. When the length L2 of 123 is less than the length li of the longer side of the wafer 110, the mechanical strength of the circuit board 120 can be effectively improved, and even it can be applied to the chip scale package structure (Chip Scale Package, CSP), that is, the circuit board 1 2 0 [ The sticky crystal surface 1 2 1] is not more than three times larger than one point of the wafer 11 0 [integrated circuit formation surface]. In Figure 5, the design of the window of the circuit board is changed. 'Since the spacer 160 has overcome the sealing compound 1 5 〇

480688 五、發明說明（6) 面流，之問題，故電路板120 /可包含一個以上且任意形 狀之窗口 1 23 '，不再受制於晶片丨丨〇 -尺寸之影響。 關於該積體電路封裝結構1 〇 〇之封裝過程，如第3 a圖 所示’提供一電路板，包含有多個上述每一封裝單元之電 $板120，其具有一黏晶表面κι、一焊球表面122及複數 窗口 123 ;之後，如第3b圖所示，形成複數個間隔墊塊16〇 於該電路板120之黏晶表面121，其中該間隔墊塊16〇之高 度，在0· 05mm至0· 3mm之間，例如以網版印刷方式先形成 液態或膠態之間隔墊塊丨6 〇再烘烤之，或是直接黏附固態 顆粒狀之間隔墊塊160，在本實施例中，並在間隔墊塊16() ^沾附黏膠161，以供黏結晶片110 ;接著，如第3c圖所 示’黏接複數個晶片1 1 〇於間隔墊塊1 6 〇上，其中晶片Η 〇 具有一積體電路形成面及在該積體電路形成面之複數個焊 墊111 ’當黏接後，晶片11 〇之複數個焊墊丨丨1係裸露雷 路板120之窗口123 ;如第3d圖所示，在打線電性連接晶片 11 0與電路板1 2 0，以形成複數個金屬導線i 3 〇號，將該晶 片110與電路板120之組合構造放入上模具與下模具2〇之 中’以壓模〔molding〕方式由注膠孔4〇灌入一具流動性 之封膠體150，經由間隔墊塊160所提供之間距流動於晶片 11〇與電路板120之間，以密封窗口123與晶片110 ;在=化 該封膠體150以及接植複數個焊球140於電路板12〇之焊球 表面122後並經適當切割即可構成如第1及2圖所示之積體 電路封裝結構100。 、 在本發明之第二具體實施例中，第6圖為該積體電路 480688480688 V. Description of the invention (6) The problem of surface flow, so the circuit board 120 / can include more than one and any shape of the window 1 23 ', which is no longer subject to the influence of the size of the wafer. Regarding the packaging process of the integrated circuit packaging structure 1000, as shown in FIG. 3a, 'a circuit board is provided, which includes a plurality of electrical boards 120 of each of the above packaging units, which has a sticky crystal surface κι, A solder ball surface 122 and a plurality of windows 123; after that, as shown in FIG. 3b, a plurality of spacers 160 are formed on the die-bonding surface 121 of the circuit board 120. The height of the spacers 16 is 0. · Between 05mm and 0 · 3mm, for example, the liquid or gel spacers are formed by screen printing, and then baked, or the solid spacer spacers 160 are directly adhered. In this embodiment, And attach the adhesive 161 to the spacer 16 () to adhere the crystal sheet 110; then, as shown in FIG. 3c, 'a plurality of wafers 1 1 10 are adhered to the spacer 16, of which The wafer 〇 〇 has an integrated circuit formation surface and a plurality of solder pads 111 ′ on the integrated circuit formation surface 111 ′. After bonding, the wafer 11 〇 multiple pads 丨 丨 1 is a window 123 of the exposed thunder board 120 As shown in Figure 3d, the chip 110 and the circuit board 120 are electrically connected to form a plurality of wires. Metal wire i 3 〇, put the combined structure of the wafer 110 and the circuit board 120 into the upper mold and the lower mold 20 ′ and inject a fluidity from the injection hole 40 by a molding method. The sealing compound 150 flows between the wafer 110 and the circuit board 120 through the distance provided by the spacer 160 to seal the window 123 and the wafer 110; the sealing compound 150 and a plurality of solder balls 140 are implanted in the circuit After the solder ball surface 122 of the board 120 is appropriately cut, the integrated circuit package structure 100 shown in FIGS. 1 and 2 can be formed. In the second specific embodiment of the present invention, FIG. 6 is the integrated circuit 480688

封裝結構200之形成封膠體步驟之截面圖，第7圖為該積體 電路封裝結構200之截面圖。A cross-sectional view of the step of forming the encapsulation structure of the package structure 200. FIG. 7 is a cross-sectional view of the integrated circuit package structure 200.

積體電路封裝結構20 0係包含有一晶片210、一電路板 220 複數個金屬導線230、複數個焊球240、一封膠體250 及複數個間隔墊塊260，其中電路板220係為一種多層印刷 電路板’具有一黏晶表面221、一焊球表面222及一窗口 2 23/窗口 223係為一階梯狀之狹長開口，對應於晶片21〇 之焊墊211，以供打線之金屬導線23〇連接晶片21〇之焊墊 211至電路板220之内層階梯表面，在電路板220之黏晶表 面221上形成有複數個呈橢圓體或圓球狀之絕緣性間隔墊 塊260，以黏固晶片21〇並提供一可供封膠體25〇流動之間 距在電路板220之焊球表面222則形成有複數個焊球 240 ’在本實施例中，係在黏晶〔黏接晶片210〕、打線 〔形成金屬導線230〕及接植焊球240後方形成一封膠體 2 50、’如第6圖所示，封膠體25〇係以點注塗施〔叩忖丨叫〕 方式由一點注針嘴3〇導出，直接塗施於電路板22〇焊球表 面2之囪口 223處，液態的封膠體250因毛細管及重力作 用流入=間隔墊塊26 0形成在晶片21〇與電路板22〇之間 =，以密封窗口223及圍繞晶片21〇之積體電路形成面之周 '以降低封裝製造成本、提高生產效率及提高製造良 =本發明之保護範圍當視後附之申請專利範圍所界定 r η肉糾ΐ何熟知此項技藝者，在不脫離本發明之精神和 巳 之任何變化與修改，均屬於本發明之保護範The integrated circuit package structure 200 series includes a chip 210, a circuit board 220, a plurality of metal wires 230, a plurality of solder balls 240, a gel 250, and a plurality of spacers 260. The circuit board 220 is a multilayer printing The circuit board 'has a sticky crystal surface 221, a solder ball surface 222, and a window 2 23 / window 223 is a step-shaped narrow opening corresponding to the pad 211 of the wafer 21, for the metal wire 23 to be wired. The pads 211 connecting the wafer 21 and the inner stepped surface of the circuit board 220 are formed on the die-bonding surface 221 of the circuit board 220 with a plurality of ellipsoidal or spherical insulating spacers 260 to adhere the wafer. 21 ° and providing a sealable body 25 ° space between the solder ball surface 222 of the circuit board 220 is formed with a plurality of solder balls 240 ′ In this embodiment, it is bonded to the die [adhesive wafer 210], wire [Forming the metal wire 230] and forming a piece of colloid 2 50 behind the implanted solder ball 240. As shown in FIG. 6, the sealing compound 25 is formed by a point injection method [叩 忖 丨] 3〇Export, apply directly to the circuit board 22〇 solder balls At the entrance 223 of the face 2, the liquid sealing compound 250 flows in due to the action of capillary and gravity = the spacer block 26 0 is formed between the wafer 21 and the circuit board 22 to seal the window 223 and the product surrounding the wafer 21 To reduce the cost of package manufacturing, increase production efficiency and improve manufacturing quality = the scope of protection of the present invention should be determined by the scope of the attached patent application. Any changes and modifications that deviate from the spirit and the invention of the present invention belong to the protection scope of the present invention.

第11頁 480688Page 11 480688

第12頁 480688Page 12 480688

圖式簡單說明Schematic illustration

式說明】 第 第3a 圖·依本發明之第一具體實施例，一積體電路封裝 結構之局部剖視立體圖； 圖·依本發明之第一具體實施例，一積體電路封裝 結構之截面圖； 第3b 第3c 第3d 第4 第5 第6[Explanation] Fig. 3a · According to a first embodiment of the present invention, a partial cross-sectional perspective view of a package structure of an integrated circuit; Figure · According to a first embodiment of the present invention, a section of a package circuit package structure Figure; 3b, 3c, 3d, 4th, 5th, 6th

圖： 圖： 圖： 圖： 圖： 圖· 圖： 圖： 在本發明之第一具體實施例中，其積體電路封 裝方法之提供電路板步驟之截面圖； 在本發明之第一具體實施例中，其積體電路封 裝方法之形成間隔墊塊步驟之截面圖； 在本發明之第一具體實施例中，其積體電路封 裝方法之黏接晶片步驟之截面圖； 、 在本發明之第一具體實施例 裝方法之電性連接步驟後置 依本發明之第一具體實施例 裝結構中電路板與晶片之頂 依本發明之積體電路封裝方 封裝結構中電路板之窗口變 依本發明之第二具體實施例 結構之形成封膠體步驟之戴 依本發明之第二具體實施例 結構之截面圖； 中，其積體電路封 入模具之截面圖·, ’在該積體電路封 面示意圖； 法，另一積體電路 化之頂面示意圖； ，一積體電路封裝 面圖； ，一積體電路封裝 t idci 麵Figures: Figures: Figures: Figures: Figures: Figures: Figures: Figures: In the first embodiment of the present invention, a cross-sectional view of the steps of providing a circuit board in a integrated circuit packaging method; in the first embodiment of the present invention In the example, a cross-sectional view of the step of forming a spacer in the integrated circuit packaging method; in a first specific embodiment of the present invention, a cross-sectional view of the step of bonding wafers in the integrated circuit packaging method; The electrical connection step of the mounting method of the first specific embodiment is followed by placing the top of the circuit board and the chip in the first specific mounting structure of the present invention according to the window of the circuit board in the integrated circuit packaging square packaging structure of the present invention. A cross-sectional view of the structure of the second specific embodiment of the present invention for forming a gel-sealing step, according to the second specific embodiment of the present invention. In the cross-sectional view of the integrated circuit sealed in the mold, "On the cover of the integrated circuit Schematic diagram; Method, another schematic diagram of the top surface of an integrated circuit;, an integrated circuit package side view;, an integrated circuit package t idci surface

第 在美國專利第6，1 77,723號「積體電路封裝及复 平板壓杈過程」中，其積體電路封裝結構之截、 面圖；及 和No. 6,77,723 in the "Integrated Circuit Packaging and Flat Panel Pressing Process" section, sectional view of the integrated circuit packaging structure; and

第13頁 480688Page 13 480688

第First

【圖號說明】 10 上模具 40 注膠孔 1 0 0積體電路封裝結構 11 〇晶片 111焊墊 11〇 晶片 12 0 2 〇 〇積體電路封裝結構 210晶片 211 黏晶表面 222 金屬導線 240 間隔墊塊 積體電路封裝結構 晶片 第二層板 121黏晶表面 130金屬導線 16 〇間隔墊塊 221 230 260 300 310 321 324引接線 3 2 7間距 330金屬導線 360膠膜 2〇 下模J 1 2 2焊球表面 14 0焊球 1 6 1黏膠 電路 焊墊 焊球表 焊球 311 焊塾 322第三層板 32 5巴士條 328上開口 340焊球 30 點注針嘴 12〇 電路板 1 2 3 窗口 1 5 〇 封膠體 123 ^ 窗口 M0電路板 2 2 3 窗口 M0 封膠體 3 2 0電路板 3 2 3 窗口 326凹槽 3 5 0 封膠體[Illustration of drawing number] 10 Upper mold 40 Plastic injection hole 1 0 0 Integrated circuit packaging structure 11 〇 Wafer 111 solder pads 11 〇 Wafer 12 0 2 〇 Integral circuit packaging structure 210 Wafer 211 Sticky crystal surface 222 Metal wire 240 Space Pad block integrated circuit package structure wafer second layer plate 121 sticky crystal surface 130 metal wire 16 〇 spacer pad 221 230 260 300 310 321 324 lead wire 3 2 7 pitch 330 metal wire 360 adhesive film 2 bottom die J 1 2 2 Solder ball surface 14 0 Solder ball 1 6 1 Adhesive circuit pad Pad solder ball Table solder ball 311 Welding pad 322 Third layer board 32 5 Opening on bus bar 328 340 Solder ball 30 Point injection nozzle 12 Circuit board 1 2 3 window 1 5 〇 sealant 123 ^ window M0 circuit board 2 2 3 window M0 sealant 3 2 0 circuit board 3 2 3 window 326 groove 3 5 0 sealant

480688 圖式簡單說明 L 1 晶片較長邊的長度 L2 電路板之窗口長度480688 Simple illustration of the length of the longer side of the L 1 chip L2 The window length of the circuit board

Claims (1)

480688480688 【申請專利範圍】 1、一種積體電路封裝結構，其包含有·· 一電路板，具有一黏晶表面、一焊球表面及至少一窗 曰曰片位於電路板之黏晶表面上，該晶片具有一穑 體電路形成面及在該積體電路形成面之複數個焊墊，盆 中該複數個焊墊係對應於電路板之窗口； 、 一封膠體； 複數個間隔塾塊，在電路板之黏晶表面與晶片之積體 電路形成面兩者之間，用以提供電路板與晶片之一間 複數個 複數個 2、 如申請 中該窗口 3、 如申請 中該間隔 4、 如申請 中該間隔 5、 如申請 中該間隔 6、 如申請 中該間隔 7、 如申請 接合於電 線，連接 圍第1項 長度係小 圍第1項 呈圓柱體 圍第1項 呈橢圓體 圍第1項 具有彈性 圍第1項 為熱固性 圍第1項 焊球， 金屬導 專利範 之最大 專利範 墊塊係 專利範 墊塊係 專利範 墊塊係 專利範 墊塊係 專利範 路板之焊球表面；及 該晶片之焊墊與該電路板。 所述之積體電路封裝結構，其 於該晶片之較長邊之長度。 所述之積體電路封裝結構，其 〇 所述之積體電路封裝結構，豆 或圓球狀。 / 所述之積體電路封裝結構，其 0 所述之積體電路封裝結構，其 之環氧化合物。 ' 所述之積體電路封裝結構，其 480688 六、申請專利範圍 中該間隔墊塊係為矽膠。 8、 如申請專利範圍第1項所述之積體電路封穿纟士禮， 中該間隔墊塊之高度係在〇· 〇5mm至〇· 3mm之間。 八 9、 如申請專利範圍第1項所述之積體電路封3 °社 中該封膠體係密封該窗口及該晶片。 、、·Ό稱’ /、 範圍第1 ,所述之積體電路封裝結構， 八中該電路板之黏晶表面係不大於該晶片之 形成面之一點三倍，而呈晶片尺寸封裝型態。、_ 11、 如申請專利範圍第丨項所述之積體電路y 其中該晶片係為一種記憶體晶片,-路封裝結構， 12、 如申請專利範圍第U項所述之積體電路 其中該晶片係為DDR記憶體晶片。 構 13、 一種積體電路之封裝方法： 面及複 數窗 提供一電路板，具有一黏晶表面、一 個間隔塾境於該電路板之點晶表面 該間隔墊塊之高度係在0.05mm至〇3_之 八 黏接複數個晶片於間隔墊塊上， s ’ 體電路形成面及在兮并雜+ A /、^日日片具有一積 -黏接德電路形成面之複數個焊墊， :黏接後’ W之複數個焊㈣裸露於電路板之窗 電性連接晶片與電路板； 形成一具流動性之封膠泣 之間，以密封窗口； 其机動於晶片與電路板 $ 17頁 480688 六、申請專利範圍 固化該封膠體；及 接植複數個焊球於電路板之焊球表面。 1 4、如申請專利範圍第1 3 項所述之積體電路之封裝方 法，其中在「形成複數個間隔墊塊」之步驟中，係以 網版印刷方式形成間隔墊塊。 15、如申請專利範圍第13項所述之積體電路之封裝方 法，其中在「黏接複數個晶片於間隔墊塊」之步驟[Scope of patent application] 1. An integrated circuit packaging structure comprising: a circuit board having a die-bond surface, a solder ball surface and at least one window on a die-bond surface of the circuit board, the The chip has a body circuit forming surface and a plurality of pads on the integrated circuit forming surface. The plurality of pads in the basin correspond to the window of the circuit board; a piece of gel; a plurality of spaced-apart blocks in the circuit Between the sticky crystal surface of the board and the integrated circuit forming surface of the wafer, to provide a plurality of multiples between the circuit board and one of the wafers 2. If the window is in the application 3, if the interval is in the application 4, if the application In the interval 5, if the application is in the interval 6, if the application is in the interval 7, if the application is connected to the electric wire, the length of the connection item 1 is a small enclosure, the first is a cylindrical enclosure, the first is an elliptical enclosure, the first Item 1 with elastic enclosure is the first solder ball of thermosetting enclosure. The largest patented pad of the metal guide patent is the patented pad. The patented pad is the patented pad. It is the solder ball surface of the patented road board. and The pads of the wafer and the circuit board. The integrated circuit package structure is the length of the longer side of the chip. The integrated circuit packaging structure, wherein the integrated circuit packaging structure is a bean or a sphere. / The integrated circuit package structure described in 0, the integrated circuit package structure described in 0, and an epoxy compound thereof. '' The integrated circuit package structure described above, which is 480688 VI. In the scope of the patent application, the spacer is silicon. 8. According to the integrated circuit sealing and sealing ceremony described in item 1 of the scope of patent application, the height of the spacer block is between 0.05 mm and 0.3 mm. 8. The sealant system seals the window and the wafer as described in the integrated circuit seal 3 ° described in item 1 of the patent application scope. The name of the integrated circuit packaging structure described in the first paragraph of the first and the second, the surface of the die bonding surface of the circuit board in the eighth is not more than three times that of the forming surface of the wafer, and it is a wafer-size package. state. _11. The integrated circuit y described in item 丨 of the scope of patent application, wherein the chip is a memory chip, a package structure, 12. The integrated circuit described in item U of the scope of patent application, where The chip is a DDR memory chip. Structure 13. An integrated circuit packaging method: a surface and a plurality of windows provide a circuit board with a sticky crystal surface and a spacing environment on the crystalline surface of the circuit board. The height of the spacer is between 0.05mm and 〇. 3_ / 8 Adhering a plurality of wafers to the spacer, the s' body circuit forming surface and the singular and mixed + A /, ^ Japanese film have a product-bonding Germany circuit forming surface with a plurality of pads, : After bonding, a plurality of solder pads are exposed on the window of the circuit board to electrically connect the chip and the circuit board; forming a fluid sealant to seal the window; it is motorized on the chip and the circuit board $ 17 Page 480688 6. Apply for a patent to cure the sealing gel; and implant a plurality of solder balls on the surface of the solder balls of the circuit board. 14. The packaging method of an integrated circuit as described in item 13 of the scope of patent application, wherein in the step of "forming a plurality of spacer blocks", the spacer blocks are formed by screen printing. 15. The packaging method of an integrated circuit as described in item 13 of the scope of patent application, wherein in the step of "adhering a plurality of wafers to a spacer block" 第18頁Page 18
TW090113424A 2001-05-28 2001-05-28 Window BGA package structure TW480688B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113658923A (en) * 2020-05-12 2021-11-16 宇瞻科技股份有限公司 Packaging structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113658923A (en) * 2020-05-12 2021-11-16 宇瞻科技股份有限公司 Packaging structure

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