1324361 (1) 玖、發明說明 【發明所屬之技術領域】 本發明係關於電漿處理方法及電漿處理裝置，特別是 有關於對半導體晶圓或L C D用基板等之被處理基板施以 電漿蝕刻處理等之電漿處理方法及電漿處理裝置。 【先前技術】 以往，電漿多用於進行半導體晶圓或LCD用基板等 被處理基板之電漿處理方法。例如，在半導體裝置之製造 工程中，用以在被處理基板，例如半導體晶圓，形成微細 之電氣電路之技術方面，多採用將被形成於半導體晶圓上 之薄膜等用電漿蝕刻除去之電漿蝕刻處理。 進行該電漿蝕刻處理之蝕刻裝置方面，例如，在內部 被構成可氣密閉鎖之處理室（蝕刻室）內製作成產生電漿 之方式。接著，在設置於該蝕刻室內之基座（suscepter ) 上載置半導體晶圓，進行蝕刻。 此外，就使產生上述電漿之手段方面已知有種種之型 態。其中，對被設成上下相對方向之方式之一對平行平板 電極供給高頻電力以產生電漿之型態之裝置方面，平行平 板電極之中的一方，例如下部電極則兼作基座。接著，在 該下部電極上配置半導體晶圓，對平行平板電極間施加高 頻電壓產生電漿，且進行蝕刻。 然而，該型態之蝕刻裝置方面，在蝕刻中，於半導體 晶圓之表面，會產生閃電之異常放電之所謂表面弧光現 -5- (2) (2)1324361 象。 上述表面弧光，大多例如在導體層之上形成絕緣體 層’且在蝕刻之場合下產生該絕緣體層之情況。例如.在 蝕刻由矽氧化膜形成之絕緣體層，並在下層之由金屬層形 成之導體層形成貫通之接觸孔之場合等，大多會產生破壞 藉由蝕刻讓膜厚減少之矽氧化膜之情況。 接著，如該異常放電產生，因爲半導體晶圓中之矽氧 化膜的大部分會遭到破壞，故而造成該半導體晶圓之大部 分元件之不良。此外，同時在蝕刻室內產生金屬污染，常 此下來便無法進行蝕刻處理，導致必須進行蝕刻室內之淸 理。因此，造成生產性顯著降低之問題。 【發明內容】 於是，本發明之目的在於提供一種能夠防止被處理基 板所產生之表面弧光之發生，且相較於以往能謀求生產性 之提升之電漿處理方法及電漿處理裝置。 本發明之電漿處理方法之特徵係：在使電漿作用於被 處理基板進行電漿處理之際，在進行前述電漿處理之前， 以弱於使用在電漿處理之電漿作用於前述被處理基板，使 該被處理基板之電荷狀態成爲一定之狀態，之後，進行前 述電漿處理。 此外，本發明之電漿處理方法之特徵係：於上述電漿 處理方法中，使前述弱的電漿以指定時間作用於前述被處 理基板，之後，對靜電夾盤施加用以吸著保持前述被處理 -6- (3) (3)1324361 基板之直流電壓。 此外，本發明之電漿處理方法之特徵係：於上述電漿 處理方法中，在前述弱的電漿消失前，開始對前述靜電夾 盤施加直流電壓t 此外，本發明之電漿處理方法之特徵係：於上述電漿 處理方法中，前述弱的電漿是由 Ar、〇2、CF4、或者N2 所形成之電漿。 此外’本發明之電漿處理方法之特徵係：於上述電漿 處理方法中，前述弱的電漿係由0. 1 5〜1 .OW/ cm2之高頻 電力所形成。 此外，本發明之電漿處理方法之特徵係：於上述電漿 處理方法中，前述弱的電漿係作用於前述被處理基板時間 長達5〜2 0秒。 此外，本發明之電漿處理方法之特徵係：於上述電漿 處理方法中，在前述電漿處理開始時，在開始施加用以產 生電漿之高頻電力後，開始對前述靜電夾盤施加直流電 壓’且在前述電漿處理終了時，在停止對前述靜電夾盤施 加直流電壓後，停止施加前述高頻電力。 此外，本發明之電漿處理方法之特徵係：於上述電漿 處理方法中，在利用在前述靜電夾盤之上方藉導體接地之 支撐棒以支撐前述被處理基板之狀態下，開始對前述靜電 夾盤施加直流電壓，之後，使前述被處理基板下降並載置 於前述靜電夾盤上。 此外’本發明之電漿處理方法之特徵係：於上述電漿 (4) (4)1324361 處理方法中，則述電獎處理係融刻處理，在進行該射j刻處 理之處理室內’使前述弱的電漿作用於前述被處理基板t 此外’本發明之電發處理裝置’係具備對被處理基板 施以電獎處理之電發處理機構’其特徵爲：具備控制前述 電漿處理機構，且進行上述電漿處理方法之控制部。 【實施方式】 以下’就本發明之實施型態方面，參照圖面並加以說 明。 第1圖係顯示本發明之實施型態所使用之電漿處理裝 置（蝕刻裝置）全體之槪略構成的模式圖。同圖中，圖號 1係表不，材質由例如鋁等所形成’內部被構成可氣密閉 鎖，且構成處理室之圓筒狀的真空室。 上述真空室〗係被接續至接地電位。於真空室]內 部’由導電性材料例如鋁等製作成區塊狀，且設置兼作下 部電極之載置台2。 該載置台2係中介著陶瓷等絕緣板3而被支撐於真空 室1內。於載置台2之半導體晶圓W載置面設置靜電夾 盤4。該靜電夾盤4係被製作成使靜電夾盤用電極4a中 介於由絕緣性材料形成之絕緣膜4b中，且於靜電夾盤用 電極4a接續直流電源5。靜電夾盤用電極4a係由例如銅 等所構成’絕緣膜4b則由聚醯胺等所構成。 此外’於載置台2內部設置：用以使控制溫度用之熱 媒體進行絕緣性流體循環之熱媒體流路6，與用以將氦等 -8 - (5) (5)1324361 控制溫度用氣體供給至半導體晶圓W之背面之氣體流路 7 = 於是’形成藉由在熱媒體流路6內使被控制成指定溫 度之絕緣性流體循環，能將載置台2控制成指定溫度，而 且’對該載置台2與半導體晶圓w之背面之間透過氣體 流路7供給控制溫度用之氣體促進其間之熱交換’並精確 度良好地且有效率地控制半導體晶圓W於指定溫度。 此外’於載置台2上方之外周設置以導電性材料或者 絕緣性材料形成之聚焦環8，再者，於載置台2之大致中 央接續著用以供給高頻電力之給電線9。製作成在該給電 線9透過整合器10接續高頻電源（RF電源）11’且由高 頻電源1 1供給指定頻率之高頻電力之型態。 此外，在上述之聚焦環8外側被製作成環狀’且設置 形成多數排氣孔之排氣環1 2，透過該排氣環1 2，利用被 接續至排氣通道1 3之排氣系1 4之真空泵浦等’進行真空 室1內之處理空間之真空排氣。 另一方面，於載置台2上方之真空室1之頂部’蓮蓬 頭（shower head) 15被設置成與載置台2平行地相對 向，而該蓮蓬頭15被接地。因此’該蓮蓬頭15與載置台 2之功能便構成一對電極（上部電極與下部電極）。 上述蓮蓬頭15 ’在其下面設置多數個氣體吐出孔 16，而且在其上部具有氣體導入部17。然後’在蓮蓬頭 15內部形成氣體擴散用空隙〗8。於氣體導入部17接續氣 體供給管1 9，於該氣體供給管1 9之另一端則接續氣體供 -9- (6) 1324361 給系2 0。該氣體供給系2 0係由用以控制氣體流量之氣體 流量控制器（M F C ) 2 1 ’與用以供給例如蝕刻用之處理氣 體等之處理氣體供給源22 ’以及用以供給Ar之Ar供給 源2 3等所構成。1324361 (1) Field of the Invention The present invention relates to a plasma processing method and a plasma processing apparatus, and more particularly to a plasma for a substrate to be processed such as a semiconductor wafer or a substrate for LCD. A plasma processing method such as an etching treatment and a plasma processing apparatus. [Prior Art] Conventionally, plasma is often used for a plasma processing method of a substrate to be processed such as a semiconductor wafer or an LCD substrate. For example, in the manufacturing process of a semiconductor device, in order to form a fine electric circuit on a substrate to be processed, for example, a semiconductor wafer, a film or the like formed on a semiconductor wafer is often removed by plasma etching. Plasma etching treatment. The etching apparatus for performing the plasma etching treatment is, for example, a method in which a plasma is generated in a processing chamber (etching chamber) which is hermetically sealed. Next, a semiconductor wafer is placed on a susceptor provided in the etching chamber, and etching is performed. Further, various types of means for producing the above plasma are known. Among them, one of the parallel plate electrodes, for example, the lower electrode, also serves as a susceptor for the device in which the high-frequency electric power is supplied to the parallel plate electrode in one of the upper and lower opposite directions to generate a plasma. Next, a semiconductor wafer is placed on the lower electrode, and a high frequency voltage is applied between the parallel plate electrodes to generate plasma, which is etched. However, in the etching apparatus of this type, in the etching, on the surface of the semiconductor wafer, a so-called surface arc which generates an abnormal discharge of lightning is present -5-(2) (2) 1323661. The surface arc is mostly formed by, for example, forming an insulator layer on the conductor layer and generating the insulator layer in the case of etching. For example, when an insulator layer formed of a tantalum oxide film is etched and a contact hole penetrating through a conductor layer formed of a metal layer is formed in the lower layer, an oxide film which is reduced in thickness by etching is often generated. . Then, if the abnormal discharge occurs, most of the germanium oxide film in the semiconductor wafer is destroyed, resulting in a defect in most of the semiconductor wafer. In addition, at the same time, metal contamination occurs in the etching chamber, and the etching process is often impossible, resulting in the necessity of performing etching in the etching chamber. Therefore, there is a problem that the productivity is significantly lowered. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a plasma processing method and a plasma processing apparatus which are capable of preventing the occurrence of surface arc generated by a substrate to be processed and which is capable of improving productivity in comparison with the prior art. The plasma processing method of the present invention is characterized in that, when the plasma is applied to the substrate to be processed for plasma treatment, before the plasma treatment, the plasma is weaker than the plasma used for the plasma treatment. The substrate is processed so that the state of charge of the substrate to be processed is in a constant state, and then the plasma treatment is performed. Further, in the plasma processing method of the present invention, in the plasma processing method, the weak plasma is applied to the substrate to be processed for a predetermined period of time, and then the electrostatic chuck is applied to occlude and hold the foregoing DC voltage of the substrate being processed - 6 - (3) (3) 13243361. Furthermore, the plasma processing method of the present invention is characterized in that, in the plasma processing method, a DC voltage is applied to the electrostatic chuck before the weak plasma disappears. Further, the plasma processing method of the present invention Characteristic system: In the above plasma processing method, the weak plasma is a plasma formed of Ar, 〇2, CF4, or N2. Further, the plasma processing method of the present invention is characterized in that, in the above plasma processing method, the weak plasma is formed by a high frequency power of 0.15 to 1. OW/cm2. Further, the plasma processing method of the present invention is characterized in that, in the plasma processing method, the weak plasma acts on the substrate to be processed for a time of 5 to 20 seconds. Further, in the plasma processing method of the present invention, in the plasma processing method, at the start of the plasma processing, application of the electrostatic chuck is started after the application of the high frequency power for generating the plasma is started. The DC voltage 'and at the end of the plasma treatment, the application of the high frequency power is stopped after the application of the DC voltage to the electrostatic chuck is stopped. Further, in the plasma processing method of the present invention, in the plasma processing method, the static electricity is started in a state in which the support substrate is supported by a support rod that is grounded by a conductor above the electrostatic chuck to support the substrate to be processed. A DC voltage is applied to the chuck, and then the substrate to be processed is lowered and placed on the electrostatic chuck. Further, the characteristics of the plasma processing method of the present invention are as follows: in the above-mentioned plasma (4) (4) 13236361 processing method, the electric prize processing is performed in a processing chamber in which the processing is performed. The weak plasma acts on the substrate to be processed t. Further, the "electric hair processing device of the present invention" includes an electric hair processing device that performs a credit award process on a substrate to be processed, and is characterized in that the plasma processing mechanism is controlled. And performing the control unit of the above plasma processing method. [Embodiment] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Fig. 1 is a schematic view showing a schematic configuration of the entire plasma processing apparatus (etching apparatus) used in the embodiment of the present invention. In the same figure, the reference numeral 1 is not shown, and the material is formed of, for example, aluminum or the like. The inside is configured to be airtightly closed, and a cylindrical vacuum chamber constituting the processing chamber. The vacuum chamber described above is connected to the ground potential. The inside of the vacuum chamber is made of a conductive material such as aluminum or the like, and a mounting table 2 serving as a lower electrode is provided. The mounting table 2 is supported in the vacuum chamber 1 by interposing an insulating plate 3 such as ceramic. An electrostatic chuck 4 is provided on the mounting surface of the semiconductor wafer W of the mounting table 2. The electrostatic chuck 4 is formed such that the electrostatic chuck electrode 4a is interposed between the insulating film 4b made of an insulating material, and the electrostatic chuck electrode 4a is connected to the DC power source 5. The electrode 4a for electrostatic chuck is made of, for example, copper. The insulating film 4b is made of polyimide or the like. Further, 'the inside of the mounting table 2 is provided: a heat medium flow path 6 for circulating an insulating fluid for controlling the temperature of the heat medium, and a gas for controlling the temperature of the -8-8 - (5) (5) 1324361 The gas flow path 7 supplied to the back surface of the semiconductor wafer W is then formed to circulate the insulating fluid controlled to a predetermined temperature in the heat medium flow path 6, so that the mounting table 2 can be controlled to a specified temperature, and The gas for controlling the temperature is supplied between the mounting table 2 and the back surface of the semiconductor wafer w through the gas flow path 7 to promote heat exchange therebetween. The semiconductor wafer W is accurately and efficiently controlled at a predetermined temperature. Further, a focus ring 8 made of a conductive material or an insulating material is provided on the outer periphery of the mounting table 2, and a power supply line 9 for supplying high-frequency power is connected to the center of the mounting table 2 in a substantially central portion. The high frequency power supply (RF power supply) 11' is connected to the power supply line 9 through the integrator 10, and the high frequency power supply 11 supplies a high frequency power of a predetermined frequency. Further, an exhaust ring 1 2 is formed in a ring shape outside the focus ring 8 and a plurality of exhaust holes are formed, and the exhaust ring 1 2 is passed through the exhaust system connected to the exhaust passage 13 The vacuum pumping of 1 4 performs vacuum evacuation of the processing space in the vacuum chamber 1. On the other hand, the top of the vacuum chamber 1 above the mounting table 2, the shower head 15, is disposed to face the mounting table 2 in parallel, and the shower head 15 is grounded. Therefore, the function of the shower head 15 and the mounting table 2 constitutes a pair of electrodes (upper electrode and lower electrode). The shower head 15' is provided with a plurality of gas discharge holes 16 on the lower surface thereof and a gas introduction portion 17 at the upper portion thereof. Then, a gas diffusion gap 8 is formed inside the shower head 15. At the gas introduction portion 17, the gas supply pipe 1 is connected, and at the other end of the gas supply pipe 19, a gas supply -9-(6) 1324361 is supplied to the system 20. The gas supply system 20 is a gas flow controller (MFC) 2 1 ' for controlling a gas flow rate, a processing gas supply source 22' for supplying a processing gas such as etching, and an Ar supply for supplying Ar. Source 2 3 and so on.
一方面’在真空室1外側周圍，以與真空室1同心狀 地配置環狀之磁場形成機構（環狀磁石）2 4，製作成在載 置台2與蓮蓬頭1 5間之處理空間形成磁場。該磁場形成 機構2 4係利用旋轉機構2 5 ’讓其全體能以指定之旋轉速 度繞行真空室1 一週。 此外，用以對半導體晶圓W施以電漿處理之上述直 流電源5、高頻電源1 1、氣體供給系2 0等之電漿處理機 構係被構成由控制部4 0所控制的型態。 其次，就依照如上述方式構成之蝕刻裝置依其蝕刻處 理順序加以說明。 (第1實施例） 首先，開放被設於真空室1之未圖示之閘閥（gate valve )，透過被配置於鄰接該閘閥之載入閉鎖真空室 (load· lock chamber)(未圖示），利用搬送機構（未圖 示）將半導體晶圓W搬入真空室1內，載置於載置台2 上。接著，在使搬送機構向真空室1外退避後，關閉閘 閥。又，該時點，並未由直流電源5對靜電夾盤4之靜電 夾盤用電極4a施加直流電壓（HV)。 之後，首先，一面利用排氣系14之真空泵浦通過排 -10- (7) 1324361 氣通道將真空室1內排氣成指定之真空度，一面從Ar 給源23將Ar供給至真空室1內。接著，在該狀態下， 第2圖所示，先由高頻電源】1對作爲下部電極之載置 2供給例如 300W等電力較低之高頻電力（頻率例 13.56MHz )，產生弱的電漿’使該弱的電漿作用於半 體晶圓W。 如此，使弱的電漿作用於半導體晶圓W，係根據如 之理由。 亦即，進行處理之半導體晶圓W方面，係根據前 程（例如CVD等之成膜工程）中之處理的狀態等，該 態並非相同，例如，有在半導體晶圓 W之內部蓄積電 之場合。於是，在如此於半導體晶圓 W內部蓄積電荷 狀態下，若使強的電漿作用，因爲產生表面弧光等之可 性高，所以在使該強的電漿作用之前，使弱的電漿作用 以使被蓄積於半導體晶圓W內部之電荷狀態等調整成 同（初期化）。 接著，在調整如此被蓄積於半導體晶圓W內部之 荷狀態時，由於半導體晶圓 w內部電何易於移動’所 在未進行對靜電夾盤4之靜電夾盤用電極4 a施加直流 壓（HV )之狀態下’利用該弱的電漿進行半導體晶圓 調整（初期化）。 又，用以產生該弱的電漿之高頻施加電力係大 〇15W/cm2 〜1.0 W/cm2，例如 100 〜500W 左右，使 的電獎作用於半導髏晶圓 W之時間則例如5〜2 0秒 供 如 台 如 導 下 工 狀 荷 之 能 ， 相 電 以 電 之 約 弱 左 -11 - (8) (8)1324361 右。 此外，上述中，係就採用A r，使a r之電漿作用之場 合加以說明，然氣體種類並不侷限於此，亦能使用例如 02、CF4 ' N2等氣體。但是，針對該氣體種類之選擇方 面’必須選擇使產生之電漿，對於半導體晶圓W，以及對 於真空室1之內壁，引起蝕刻等非期待之作用之程度小的 氣體，而且必須選擇讓電漿易於點火之氣體。再者，進行 處理之半導體晶圓W，亦根據在前工程是否被施以何種處 理，而有最適之氣體種類改變之場合，最好是考慮該場合 後適當選擇。 接著，在如上述使弱的電漿作用於半導體晶圓 W 後，如第2圖所示，進行對靜電夾盤用電極4 a施加來自 直流電源5之直流電壓（Η V )。之後，由處理氣體供給 源2 2對真空室】內供給指定之處理氣體（蝕刻氣體）’ 由高頻電源1 1對作爲下部電極之載置台 2供給例如 2000W等通常處理用之電力之高的高頻電力（頻率例如 13.56MHz )，產生強的電漿，進行通常之電漿處理（蝕 刻處理）。又，第2圖中，橫軸表示時間，縱軸表示在靜 電夾盤HV之場合爲電壓値，在RF輸出之場合爲電力 値。 此時，藉由對下部電極之載置台2施加高頻電力’於 上部電極之蓮蓬頭15與下部電極之載置台2間的處理空 間形成高頻電場，而且依照磁場形成機構24形成磁場’ 在該狀態下由電漿進行蝕刻。 -12- 1324361 Ο) 接著，一旦實行指定之蝕刻處理，便藉由停止由 電源1 1供給高頻電力以停止蝕刻處理，且以與上述 相反之順序，將半導體晶圓w搬出至真空室丨外t 如上述方式，首先’使弱的電漿作用於半導體晶 之後，進行半導體晶圓 w之蝕刻處理，便能使半導 圓w所產生表面弧光之比例成爲接近零（1 %以下） 因生產批次而有所不同。另一方面，在未使如上述之 電漿發揮作用便開始處理之場合，半導體晶圓w所 表面弧光之比例則隨著批次不同而有成爲80 %左右 合。原因是在比蝕刻更前面的工程中造成半導體晶 帶電，該種表面弧光，特別是在前工程藉由CVD形 謂Low— K膜之工程的場合下，發生之機率高。 因而能確認：在開始通常之處理前，藉由如上述 的電漿作用於半導體晶圓W，便能大幅地降低半導體 W所產生表面弧光之比例。 可是，上述實施型態方面，如第1圖所示，係就 僅對下部電極之載置台2施加高頻電力之構成之裝置 合加以說明，但亦能適用於例如第3圖所示之，被構 對作爲上部電極之蓮蓬頭15透過整合器由高頻電源 加高頻電力之方式之所謂上下部施加型的電漿處理裝 該場合，例如第4圖所示，首先，對下部電極之 台2開始施加低電力之高頻電力，之後對上部電極之 頭15開始施加低電力之高頻電力，在此，暫時停止 部電極之載置台2施加高頻電力。接著，在該狀態下 高頻 順序 圓， 體晶 ，不 弱的 產生 之場 B w 成所 使弱 晶圓 使用 的場 成亦 31施 置。 載置 蓮蓬 對下 以指 -13- (10) (10)1324361 定期間使弱的電漿作用於半導體晶圓w之後，亦停止對 上部電極之蓮蓬頭I 5施加高頻電力’且暫時讓電漿消 失。 然後，依序開始：對靜電夾盤4之靜電夾盤用窀極 4 a施加直流電壓（Η V ) ’對下部電極之載置台2施加處 理用之通常之高頻電力（高電力之高頻電力）’對上部電 極之蓮蓬頭】5施加處理用之通常之高頻電力（高電力之 高頻電力），開始半導體晶圓W之通常之處理。 如此一來，即使是上下部施加型之電漿處理裝置，本 發明亦能適用。 又，最好是除了如上述使弱的電漿發揮作用，或者， 單獨地，在開始處理之前，使例如離子化機作用於半導體 晶圓W，以減低其內部之電荷。藉由該離子化機之作用， 可抑制表面弧光之發生。該離子化機可以設置於真空室 內，或者亦能設置於真空室外之其他場所。 可是，第2圖所示之電漿處理方法方面，係在對下部 電極之載置台2施加弱的高頻電力並在使弱的電漿發揮作 用後不施加高頻電力之狀態下，開始對靜電夾盤4之靜電 夾盤用電極4a施加直流電壓（HV )。如此，在施加弱的 高頻電力並在使弱的電漿發揮作用後不施加高頻電力之狀 態下’開始對靜電夾盤用電極4 a施加直流電壓（Η V )， 則在開始施加直流電壓（HV )之際，就可能產生閃電狀 放電且對基板造成損傷。該種場合如第5圖所示，在對載 置台2施加高頻電力之狀態（使弱的電漿發生之狀態） -14- (11) 1324361 下，便開始對靜電夾盤用電極4a施加直流電壓（HV ) · 就能抑制放電的發生。 以上，對於第1實施例，係就：在蝕刻等電漿處理前 用 Ar使弱的電漿發揮作用之方法，以及此時之對靜電夾 盤用電極4a施加直流電壓之時機加以說明。 (第2實施例） 其次，針對進行蝕刻處理等之電漿處理之際施加高頻 電力之時機與對靜電夾盤用電極4a施加直流電壓之時機 之關係，以適當例子予以說明。 又，在上述靜電夾盤4有雙極型與單極型，另外這些 型態方面亦分別有庫命（c〇ul〇mb)型與 Johnson-Laveik 型。其中，使用單極型且庫侖型之靜電夾盤4之場合，最 好是按照如下之程序進行吸著半導體晶圓W。於第6圖表 示該程序。橫軸表示時間，縱軸方面虛線表示施加高頻電 力値（W )、實線則表示施加直流電壓値（V )。 亦即，在將半導體晶圓W載置於載置台2 (靜電夾盤 4 )上之後，開始朝真空室1內導入氣體。接著，之後如 第6圖以虛線所示，首先，開始朝載置台2施加高頻電力 產生電漿，之後，如同圖以實線所示，進行對靜電夾盤用 電極4a施加直流電壓（HV )。 又，因爲在開始對靜電夾盤用電極4a施加直流電壓 (HV )前，半導體晶圓W並未被吸著於靜電夾盤4，所 以溫度控制並未充分進行。因此，在最初產生電漿之際對On the other hand, an annular magnetic field forming mechanism (annular magnet) 24 is disposed concentrically with the vacuum chamber 1 around the outside of the vacuum chamber 1, and a magnetic field is formed in the processing space between the mounting table 2 and the shower head 15. The magnetic field forming mechanism 24 allows the entire vacuum chamber 1 to be wound around the vacuum chamber 1 at a predetermined rotational speed by the rotating mechanism 2 5 '. Further, the plasma processing mechanism such as the DC power source 5, the high-frequency power source 1 1 and the gas supply system 20 for performing plasma treatment on the semiconductor wafer W is configured to be controlled by the control unit 40. . Next, the etching apparatus constructed as described above will be described in accordance with the etching process sequence. (First Embodiment) First, a gate valve (not shown) provided in the vacuum chamber 1 is opened, and a load lock chamber (not shown) disposed adjacent to the gate valve is transmitted. The semiconductor wafer W is carried into the vacuum chamber 1 by a transfer mechanism (not shown) and placed on the mounting table 2. Next, after the transport mechanism is retracted outside the vacuum chamber 1, the gate valve is closed. Further, at this time, the direct current voltage (HV) is not applied to the electrostatic chuck electrode 4a of the electrostatic chuck 4 by the direct current power source 5. Thereafter, first, while evacuating the inside of the vacuum chamber 1 to a prescribed degree of vacuum by the vacuum pumping of the exhaust system 14 through the discharge channel -10 (7) 1324361 gas passage, Ar is supplied from the Ar to the source 23 to the vacuum chamber 1 . Next, in this state, as shown in FIG. 2, the high-frequency power source 1 first supplies the low-frequency high-frequency power (frequency example 13.56 MHz) such as 300 W to the mounting 2 as the lower electrode, and generates weak electricity. The slurry 'acts the weak plasma on the half wafer W. Thus, a weak plasma is applied to the semiconductor wafer W for the same reason. In other words, the semiconductor wafer W to be processed is not the same in the state of processing in the future (for example, a film formation process such as CVD), and for example, in the case where electricity is accumulated inside the semiconductor wafer W. . Therefore, in the state in which the electric charge is accumulated inside the semiconductor wafer W, if strong plasma is applied, since the surface arc or the like is highly high, the weak plasma action is performed before the strong plasma is applied. The state of charge or the like accumulated in the inside of the semiconductor wafer W is adjusted to be the same (initialization). Then, when the state of being stored in the inside of the semiconductor wafer W is adjusted, the internal voltage of the semiconductor wafer w is easily moved, and DC voltage is applied to the electrode 4 a for the electrostatic chuck of the electrostatic chuck 4 (HV). In the state of 'the semiconductor wafer adjustment (initialization) using the weak plasma. Further, the high-frequency application power for generating the weak plasma is about 15 W/cm 2 to 1.0 W/cm 2 , for example, about 100 to 500 W, and the time when the electric prize is applied to the semiconductor wafer W is, for example, 5 ~ 2 0 seconds for the power of the work such as the guide, the power is weak to the left -11 - (8) (8) 1323461 right. Further, in the above, A r is used to explain the action of the plasma of a, but the type of gas is not limited thereto, and gases such as 02 and CF4 'N2 can also be used. However, in terms of the selection of the gas type, it is necessary to select a plasma to be generated, a semiconductor wafer W, and a gas which is less likely to cause an undesired effect such as etching on the inner wall of the vacuum chamber 1, and must be selected. A plasma that is easy to ignite. Further, in the case where the semiconductor wafer W to be processed is also subjected to the treatment of the prior art and the optimum gas type is changed, it is preferable to appropriately select the case. Next, after the weak plasma is applied to the semiconductor wafer W as described above, a DC voltage (?V) from the DC power source 5 is applied to the electrostatic chuck electrode 4a as shown in Fig. 2 . After that, the processing gas supply source 2 supplies a predetermined processing gas (etching gas) to the inside of the vacuum chamber. The high-frequency power source 11 supplies the mounting stage 2 as the lower electrode with a high power for normal processing such as 2000 W. High-frequency power (frequency, for example, 13.56 MHz) generates strong plasma and is subjected to usual plasma processing (etching treatment). Further, in Fig. 2, the horizontal axis represents time, the vertical axis represents voltage 値 in the case of the electrostatic chuck HV, and the power 値 in the case of RF output. At this time, high-frequency electric power is applied to the mounting table 2 of the lower electrode to form a high-frequency electric field in the processing space between the shower head 15 of the upper electrode and the mounting table 2 of the lower electrode, and a magnetic field is formed in accordance with the magnetic field forming mechanism 24 The state is etched by plasma. -12- 1324361 Ο) Next, once the specified etching process is performed, the high-frequency power is stopped by the power source 1 1 to stop the etching process, and the semiconductor wafer w is carried out to the vacuum chamber in the reverse order to the above. As described above, first, after the weak plasma is applied to the semiconductor crystal, the semiconductor wafer w is etched, so that the ratio of the surface arc generated by the semiconducting circle w becomes close to zero (1% or less). Production batches vary. On the other hand, when the treatment is started without causing the plasma as described above, the ratio of the surface arc of the semiconductor wafer w is about 80% depending on the batch. The reason is that the semiconductor crystal is charged in a project earlier than etching, and this kind of surface arcing, especially in the case where the former project is operated by CVD to form a Low-K film, has a high probability of occurrence. Therefore, it can be confirmed that the ratio of the surface arc generated by the semiconductor W can be greatly reduced by the action of the plasma as described above on the semiconductor wafer W before the usual processing is started. However, in the above-described embodiment, as shown in FIG. 1, a device for applying high-frequency power only to the mounting table 2 of the lower electrode will be described. However, the present embodiment can be applied to, for example, FIG. In the case of a so-called upper and lower application type plasma processing apparatus in which the shower head 15 as the upper electrode is applied by a high-frequency power source and high-frequency power through an integrator, for example, as shown in FIG. 4, first, the lower electrode is placed. (2) High-frequency power of low-power is applied, and then low-frequency high-frequency power is applied to the head 15 of the upper electrode, and the high-frequency power is applied to the mounting table 2 of the temporary stop portion electrode. Then, in this state, the high-frequency sequential circle, the body crystal, and the weakly generated field B w are applied to the field used for the weak wafer. After the shower is placed on the semiconductor wafer w with a weak plasma during the period of the finger -13-(10) (10)1324361, the application of the high-frequency power to the shower head I 5 of the upper electrode is also stopped. The pulp disappeared. Then, sequentially, the DC voltage (Η V ) is applied to the electrostatic chuck of the electrostatic chuck 4 by the drain 4 a. The normal high-frequency power for processing the high-voltage power is applied to the mounting table 2 of the lower electrode. The power supply 'the upper electrode's shower head' 5 applies the usual high-frequency power (high-frequency high-frequency power) for processing, and starts the normal processing of the semiconductor wafer W. As a result, the present invention can be applied even to the upper and lower application type plasma processing apparatus. Further, it is preferable to apply an ionizer to the semiconductor wafer W in addition to the weak plasma as described above, or separately, before starting the treatment, to reduce the internal charge. By the action of the ionizer, the occurrence of surface arc light can be suppressed. The ionizer can be placed in a vacuum chamber or can be placed elsewhere in the vacuum chamber. However, in the plasma processing method shown in Fig. 2, the weak high-frequency power is applied to the mounting table 2 of the lower electrode, and after the weak plasma is applied, the high-frequency power is not applied, and the pair is started. The electrostatic chuck of the electrostatic chuck 4 applies a direct current voltage (HV) to the electrode 4a. In this way, when a weak DC power is applied and a DC voltage (Η V ) is applied to the electrostatic chuck electrode 4 a without applying high frequency power after the weak plasma is applied, the DC is applied. At the voltage (HV), a lightning discharge may occur and damage to the substrate may occur. In this case, as shown in Fig. 5, when the high-frequency power is applied to the mounting table 2 (the state in which the weak plasma is generated) -14-(11) 1324361, the application to the electrostatic chuck electrode 4a is started. DC voltage (HV) · can suppress the occurrence of discharge. As described above, the first embodiment is a method in which a weak plasma is applied by Ar before plasma treatment such as etching, and a timing at which a DC voltage is applied to the electrostatic chuck electrode 4a at this time. (Second Embodiment) Next, the relationship between the timing of applying high-frequency power during plasma processing such as etching treatment and the timing of applying a DC voltage to the electrostatic chuck electrode 4a will be described with a suitable example. Further, the above-mentioned electrostatic chuck 4 has a bipolar type and a unipolar type, and these types also have a c〇ul〇mb type and a Johnson-Laveik type. In the case where a unipolar type Coulomb type electrostatic chuck 4 is used, it is preferable to suck the semiconductor wafer W in accordance with the following procedure. The program is shown in the sixth chart. The horizontal axis represents time, the vertical axis represents the application of the high-frequency electric power 値 (W), and the solid line represents the application of the DC voltage 値 (V). That is, after the semiconductor wafer W is placed on the mounting table 2 (electrostatic chuck 4), the introduction of gas into the vacuum chamber 1 is started. Then, as shown by a broken line in Fig. 6, first, high-frequency power generation plasma is applied to the mounting table 2, and then a DC voltage is applied to the electrostatic chuck electrode 4a as shown by a solid line in the figure (HV). ). Further, since the semiconductor wafer W is not attracted to the electrostatic chuck 4 until the DC voltage (HV) is applied to the electrostatic chuck electrode 4a, the temperature control is not sufficiently performed. Therefore, at the time of the initial generation of plasma
-15- (12) (12)1324361 載置台2所施加之高頻電力，該電力會設定成低於進行處 理時所施加之高頻電力（例如5 0 0W左右），且最好是形 成藉由電漿之作用，讓半導體晶圓 W之溫度不會上昇之 方式。 接著，在將半導體晶圓w從靜電夾盤4取下之際， 亦如同圖所示，於電漿處理結束之後，首先，將施加高頻 電力値降低至低於進行處理時所施加之高頻電力之電力値 (並非0W )。之後，停止對靜電夾盤用電極4a施加直流 電壓（HV)，然後，停止施加高頻電力讓電漿消失。 又，在停止對靜電夾盤用電極4a施加直流電壓（HV)之 際，暫時對靜電夾盤用電極4a施加，極性與吸著時之極 性相反之電壓（例如負2000V左右），以除去電荷，且 易於取下半導體晶圓W。施加該種極性相反之電壓方面須 因應需要而進行，至於不進行施加極性相反之電壓亦能將 半導體晶圓W從靜電夾盤4輕易地取下之場合，便不進 行極性相反之電壓之施加。 第7圖顯示’如上述由靜電夾盤4吸著半導體晶圓W 之程序進行時，靜電夾盤（ESC)之銅製電極部（Cu)及 聚醯胺製絕緣膜部（PI )，與多層半導體晶圓（Multi Layer Wafer)之背面氧化膜部（B.S.0x)及矽基板部（si sub )及氧化膜部（0x )，與真空室內之處理空間部 (Space )及上部電極部（wal丨）等各部的電位變化。 如同圖所示，首先，使被設於載置台2之晶圓支撐用 之栓下降以將半導體晶圓W載置於載置台2上，如圖中 -16 - (13) (13)1324361 ①所示’各部之電位爲零的狀態’之後’對真空室1內開 始導入氣體時亦如圖中②所示’各部之電位爲零的狀態r 之後，當開始施加高頻電力產生電漿’如圖中③所 示，半導體晶圓 W之電位成爲決定於電漿之狀態之；ft 1 0 0 V左右之電位。 接著，於該狀態下’當開始對靜電夾盤用電極4 a施 加直流電壓（Η V ) ’如圖中④所示’靜電夾盤用電極4 a 之電位成爲施加之直流電壓（HV )之電位（例如1 .5KV 左右），且於絕緣膜部（PI )產生電位差而進行吸著半導 體晶圓W。 如此，若依照上述由靜電夾盤4吸著半導體晶圓W 之程序，因爲在半導體晶圓W表面不會伴隨對靜電夾盤 用電極4 a施加直流電壓（Η V )而施加高的電壓，故能防 止在半導體晶圓W表面產生非期待之異常放電。 又，第2實施例說明至此，就施加高頻電力後施加直 流電壓之程序方面，具有如以下所說明之效果。 第9圖所示之程序，亦即若進行在電漿處理開始時朝 靜電夾盤用電極4a施加直流電壓後朝下部電極（或者上 部電極）施加高頻電力，及在電漿處理結束後，高頻電力 OFF後之直流電壓OFF，則在使半導體晶圓W吸著或者 離脫時，如第10圖所示，會對半導體晶圓W施加大的電 壓。因此，在半導體晶圓 W可能發生損傷，具體而言可 能發生直徑數十左右的缺陷，該缺陷發生場所會在蝕 刻中引起弧光，造成製品不良。此外，缺陷會形成顆粒， -17- (14) (14)1324361 也會造成附著於半導體晶圓W之情況。 但是，本實施例說明至此，所謂在處理開始時 R F ON— HV ON，在處理結束時 HV OFF— RF OFF之 程序之場合，因爲不會對半導體晶圓施加高電壓，.所以不 會對半導體晶圓W造成損傷，而且能防止半導體晶圓W 表面弧光。 此外，依第9圖之程序，即使在半導體晶圓W表面 不會造成損傷之場合，因爲隨著對靜電夾盤用電極4a施 加直流電壓導致半導體晶圓W帶電，故可能造成該靜電 力所導致在處理室內通常浮遊之帶電顆粒會附著於半導體 晶圓W。 但是，所謂在處理開始時RF 0Ν-> Η V ON，在處 理結束時HV OFF— RF OFF之程序之場合，因爲在對 靜電夾盤施加直流電壓前會持續高頻放電，所以浮遊之帶 電顆粒會被捕捉至離子層中，結果能使附著於半導體晶圓 W之顆粒減少。亦有該種效果。 以下，顯示檢證離子層之捕捉效果。 第1 1圖顯示根據用以吸著半導體晶圓W之靜電夾盤 之直流施加電壓的大小不同所導致附著顆粒數不同之調查 結果。 亦即顯示，首先，使成爲顆粒發生源之CF系之反應 物附著（護套處理（sheathing))於電漿處理裝置之處理 室內，之後，將半導體晶圓W搬入處理室內載置於靜電 夾盤上並使處理氣體流通一定時間，然後，進行半導體晶 -18- (15) (15)1324361 圓W之除電後搬出處理室內，將附著於半導體晶圓W之 顆粒數，依顆粒大小分成3種類，計算該3種大小顆粒之 顆粒數’將靜電夾盤之直流電壓設定成 〇 V、1 . 5 k V、 2.0kV、2.5kV，就種種場合調查後之結果。 如同圖所示可知，若提高靜電夾盤之直流施加電壓， 則附著於半導體晶圓 W之顆粒數會增加。亦即可知，朝 靜電夾盤施加之直流電壓會對半導體晶圓 W之顆粒的附 著造成影響。 又，上述護套處理工程之處理條件爲：壓力： 6.65Pa、高頻電力：3 500W、使用氣體：C4F8/ Ar/ CH2F2 = 13 / 600 / 5sccm、晶圓背面壓力（中央/周 緣）：1 3 3 0 / 3 990Pa、溫度（頂部/側壁/底部）：60/ 6 0 / 6 0 °C、高頻施加時間：3分鐘。 此外’將半導體晶圓w配置於靜電夾盤上使氣體流 通之際的壓力、使用氣體、晶圓背面壓力、溫度的條件係 與上述相同’而高頻電力=〇、氣體流通時間爲60秒。 再者，上述除電工程方面，係於壓力：26_6Pa、施加 電壓：一 1 _5kV、電壓施加時間：1秒、以及壓力： 5 3 · 2 P a、N 2 : 1 〇 0 0 s c c m、時間：1 5秒之條件下進行半導 體晶圓W之除電，並於施加電壓：一 2. OkV、電壓施加時 間：1秒之條件下進行靜電夾盤之除電。又，因爲以該方 式進行除電係在製程結束後之搬送半導體W之際若半導 體晶圓W跳脫則有招致無益之顆粒再附著之虞，換言 之，藉由除電’使不發生該種半導體晶圓 W彈起之情 -19- (16) (16)1324361 形。 此外’第1 2圖係顯示：在上述護套處理工程之後. 將半導體晶圓W配置於處理室內，在該狀態下進行〇 2乾 式淸洗後使護套處理工程中附著之反應物發生多數之顆 粒，針對所謂在處理開始時R F Ο N — Η V 〇 Ν、在處理 結束時HV OFF— RF OFF之程序之場合，與所謂在處 理開始時HV ON— RF ON'在處理結束時RF OFF 〜Η V 〇 F F之程序之場合，測定附著於半導體晶圓w之 顆粒數之結果。又，關於測定方面，護套處理工程及除電 工程係與前述之場合相同，而0 2乾式淸洗工程之處理條 件爲：壓力：13.3Pa、高頻電力：1000W'使用氣體： 〇2= 1000sccm、晶圓背面壓力（中央/周緣）：1330/ 3 990Pa '溫度（頂部/側壁/底部）：60/ 60/ 60°C、高 頻施加時間：3 0秒。 如同圖所示，藉由採用所謂在處理開始時RF ON — HV ON、在處理結束時HV OFF— RF OFF之程序， 能使附著之顆粒數大幅減少。 又，如第8圖所示之程序，在將半導體晶圓以被設於 載置台2之晶圓支撐用之栓（支撐棒）支撐之狀態（①） 下開始對靜電夾盤用電極4a施加直流電壓（HV ) (②），之後，使晶圚支撐用之栓下降以將半導體晶圓W 載置於載置台2上（③、④），即使在吸著半導體晶圓W 之場合，亦不會使半導體晶圓 W之表面成爲施加之直流 電壓（HV )之電位。因此，即使藉由該方式之吸著程 -20- (17) (17)1324361 序，亦能防止在半導體晶圓 W之表面產生非預期之異常 放電。但是，該方式之程序方面，晶圓支撐用之栓爲導電 性，而非得形成從該栓供給電荷至半導體晶圓 W之構成 才能進行。 此外，上述方式之利用靜電夾盤吸著之際所產生之異 常放電方面，同樣地，即使是庫侖型之靜電夾盤，如使用 雙極型之靜電夾盤，亦能防止異常放電。 又，以上之例中，針對使用平行平板型蝕刻裝置之蝕 刻處理的實施型態加以說明，然本發明並不侷限於該實施 型態，而當然可以使用於所謂的電漿處理。此外，上述實 施型態中，針對在進行蝕刻處理之蝕刻裝置之真空室內使 弱的電漿發揮作用之場合加以說明，然亦能在進行處理之 裝置之其他場所使弱的電漿發揮作用，並初期化半導體晶 圓W。 如以上詳細說明，根據本發明，能防止被處理基板所 產生之表面弧光之發生，且相較於以往能謀求生產性之提 升。 產業上之利用可能性 關於本發明之電漿處理方法及電漿處理裝置係能使用 於進行半導體裝置之製造之半導體製造產業等。所以，具 有產業上之利用可能性。 【圖式簡單說明】 -21 - (18) (18)1324361 第1圖係使用於本發明之一實施型態之裝置之槪略構 成的模式圖。 第2圖係用以說明關於本發明之一實施型態之電漿處 理方法之圖。 第3圖係使用於本發明之其他實施型態之裝置之槪略 構成的模式圖。 第4圖係用以說明關於本發明之其他實施型態之電漿 處理方法之圖。 第5圖係用以說明關於第2圖所示之實施型態之變形 例之電漿處理方法之圖。 第6圖係用以說明依照靜電夾盤之夾盤方法之圖。 第7圖係用以說明第6圖之夾盤方法之各部的電位變 化之圖。 第8圖係用以說明其他之夾盤方法之各部的電位變化 之圖。 第9圖係用以說明依照靜電夾盤之夾盤方法之比較例 之圖。 第10圖係用以說明第9圖之夾盤方法之各部的電位 變化之圖。 第1】圖係顯示靜電夾盤之施加電壓與顆粒數之關係 圖。 第12圖係顯示程序不同造成顆粒數不同之圖。 圖號說明 -22- (19)1324361 w 半導體晶圓 1 真空室 2 載置台 絕緣板 4 靜電夾盤 5 直流電源 6 熱媒體流路 7 氣體流路 8 聚焦環 9 給電線 10 整合器 11 高頻電源-15- (12) (12) 13243361 The high-frequency power applied to the stage 2 is set to be lower than the high-frequency power (for example, about 500 W) applied during processing, and it is preferable to form a loan. The effect of the plasma is such that the temperature of the semiconductor wafer W does not rise. Next, when the semiconductor wafer w is removed from the electrostatic chuck 4, as shown in the figure, after the plasma processing is completed, first, the application of the high-frequency power 値 is lowered to be lower than that applied when the processing is performed. The power of the frequency power is not (0W). Thereafter, the application of the DC voltage (HV) to the electrostatic chuck electrode 4a is stopped, and then the application of the high frequency power is stopped to allow the plasma to disappear. When the application of the DC voltage (HV) to the electrostatic chuck electrode 4a is stopped, the electrostatic chuck electrode 4a is temporarily applied with a voltage having a polarity opposite to that at the time of absorbing (for example, about 2000 V minus) to remove the electric charge. And it is easy to remove the semiconductor wafer W. The application of such a voltage of opposite polarity should be carried out as needed. As long as the semiconductor wafer W can be easily removed from the electrostatic chuck 4 without applying a voltage of opposite polarity, the application of the opposite polarity voltage is not performed. . Fig. 7 shows a copper electrode portion (Cu) of an electrostatic chuck (ESC) and an insulating film portion (PI) made of a polyimide, as described above, when the semiconductor wafer W is sucked by the electrostatic chuck 4, and a plurality of layers. a back surface oxide film portion (BS0x), a germanium substrate portion (si sub ), and an oxide film portion (0x ) of a semiconductor wafer (Multi Layer Wafer), and a processing space portion (Space) and an upper electrode portion (wal丨 in a vacuum chamber) ) The potential changes of each part. As shown in the figure, first, the plug for supporting the wafer provided on the mounting table 2 is lowered to mount the semiconductor wafer W on the mounting table 2, as shown in Fig. 16 - (13) (13) 1324361 1 When the state in which the potential of each part is zero is shown, the state in which the gas is introduced into the vacuum chamber 1 is also shown in Fig. 2, and the state in which the potential of each part is zero is zero, when the application of the high frequency power is started to generate the plasma. As shown in Fig. 3, the potential of the semiconductor wafer W is determined by the state of the plasma; the potential of about ft 1 0 0 V. Then, in this state, 'the DC voltage (Η V ) is applied to the electrode 4 a for electrostatic chucks. ' As shown in Fig. 4, the potential of the electrode 4 a for the electrostatic chuck becomes the applied DC voltage (HV). The semiconductor wafer W is sorbed by a potential difference (for example, about 1.5 KV) and a potential difference is generated in the insulating film portion (PI). As described above, according to the above procedure for absorbing the semiconductor wafer W by the electrostatic chuck 4, a high voltage is applied to the surface of the semiconductor wafer W without applying a DC voltage (Η V ) to the electrostatic chuck electrode 4 a. Therefore, it is possible to prevent an unexpected abnormal discharge from occurring on the surface of the semiconductor wafer W. Further, the second embodiment has been described so far, and has an effect as described below in terms of a procedure for applying a DC voltage after applying high-frequency power. In the procedure shown in FIG. 9, when a DC voltage is applied to the electrostatic chuck electrode 4a at the start of the plasma treatment, high-frequency power is applied to the lower electrode (or the upper electrode), and after the plasma treatment is completed, When the DC voltage after the high-frequency power is turned off is OFF, when the semiconductor wafer W is sucked or removed, as shown in FIG. 10, a large voltage is applied to the semiconductor wafer W. Therefore, damage may occur in the semiconductor wafer W, and specifically, defects having a diameter of several tens or more may occur, and the place where the defect occurs may cause arcing in the etching, resulting in defective products. In addition, defects can form particles, and -17-(14)(14)1324361 can also cause adhesion to the semiconductor wafer W. However, this embodiment has been described so far, in the case where RF ON-HV ON at the start of processing and HV OFF-RF OFF at the end of processing, since no high voltage is applied to the semiconductor wafer, the semiconductor is not applied. The wafer W causes damage and prevents arcing of the surface of the semiconductor wafer W. Further, according to the procedure of Fig. 9, even when the surface of the semiconductor wafer W is not damaged, the semiconductor wafer W is charged as a direct current voltage is applied to the electrode 4a for the electrostatic chuck, so that the electrostatic force may be caused. The charged particles that normally float in the processing chamber will adhere to the semiconductor wafer W. However, in the case where RF 0Ν-> Η V ON at the start of processing, in the case of HV OFF-RF OFF at the end of processing, since high-frequency discharge is continued before DC voltage is applied to the electrostatic chuck, floating is charged. The particles are trapped in the ion layer, with the result that the particles attached to the semiconductor wafer W are reduced. There is also this effect. The capture effect of the verification ion layer is shown below. Fig. 1 shows a result of a survey of the number of attached particles depending on the magnitude of the DC applied voltage of the electrostatic chuck for absorbing the semiconductor wafer W. That is, first, the CF-based reactant which is the source of the particle generation is attached (sheathing) to the processing chamber of the plasma processing apparatus, and then the semiconductor wafer W is carried into the processing chamber and placed on the electrostatic chuck. The processing gas is circulated for a certain period of time on the disk, and then the semiconductor crystal 18-(15)(15)1324361 is removed and discharged into the processing chamber, and the number of particles adhering to the semiconductor wafer W is divided into three according to the particle size. Type, calculate the number of particles of the three sizes of particles 'Set the DC voltage of the electrostatic chuck to 〇V, 1.5 kV, 2.0kV, 2.5kV, and investigate the results of various occasions. As shown in the figure, if the DC applied voltage of the electrostatic chuck is increased, the number of particles adhering to the semiconductor wafer W increases. It can also be seen that the DC voltage applied to the electrostatic chuck affects the adhesion of the particles of the semiconductor wafer W. Further, the processing conditions of the above sheath treatment process are: pressure: 6.65 Pa, high frequency power: 3 500 W, use gas: C4F8/Ar/CH2F2 = 13 / 600 / 5 sccm, wafer back pressure (center/circumference): 1 3 3 0 / 3 990Pa, temperature (top/side/bottom): 60/ 6 0 / 60 °C, high frequency application time: 3 minutes. In addition, the conditions for the pressure, the gas used, the back pressure of the wafer, and the temperature when the semiconductor wafer w is placed on the electrostatic chuck are the same as described above, and the high-frequency power = 〇, gas circulation time is 60 seconds. . Furthermore, the above-mentioned static elimination engineering is based on pressure: 26_6 Pa, applied voltage: -1 _5 kV, voltage application time: 1 second, and pressure: 5 3 · 2 P a, N 2 : 1 〇 0 0 sccm, time: 1 The semiconductor wafer W was de-energized under a condition of 5 seconds, and the electrostatic chuck was removed under the application of a voltage of 2. OkV and a voltage application time of 1 second. Further, since the semiconductor wafer W is tripped when the semiconductor system W is transferred after the process is completed, the semiconductor wafer W is reattached. In other words, the semiconductor crystal is not generated by the charge elimination. Round W bounces -19- (16) (16) 1323661 shape. Further, the '12th figure shows that after the sheath treatment process, the semiconductor wafer W is placed in the processing chamber, and in this state, after the dry cleaning of the crucible 2, the reactants adhering to the sheath treatment process are mostly generated. The particle is for the so-called RF Ο N - Η V 〇Ν at the start of processing, HV OFF - RF OFF at the end of processing, and the so-called HV ON - RF ON' at the end of processing RF OFF at the end of processing In the case of the procedure of ~ Η V 〇 FF, the result of measuring the number of particles attached to the semiconductor wafer w is measured. Moreover, regarding the measurement, the sheath treatment engineering and the static elimination engineering are the same as those described above, and the processing conditions of the 0 2 dry rinsing project are: pressure: 13.3 Pa, high frequency power: 1000 W' use gas: 〇 2 = 1000 sccm Wafer back pressure (center/perimeter): 1330/ 3 990Pa 'Temperature (top/sidewall/bottom): 60/ 60/60°C, high frequency application time: 30 seconds. As shown in the figure, by using a program called RF ON - HV ON at the start of processing and HV OFF - RF OFF at the end of processing, the number of attached particles can be greatly reduced. Further, as shown in FIG. 8, the semiconductor wafer is applied to the electrostatic chuck electrode 4a in a state (1) in which the semiconductor wafer is supported by a plug (support rod) for supporting the wafer on the mounting table 2. DC voltage (HV) (2), after which the plug for supporting the wafer is lowered to mount the semiconductor wafer W on the mounting table 2 (3, 4), even when the semiconductor wafer W is sucked The surface of the semiconductor wafer W is not caused to be the potential of the applied direct current voltage (HV). Therefore, even if the absorbing range -20-(17)(17)1324361 is used in this manner, it is possible to prevent an unexpected abnormal discharge from occurring on the surface of the semiconductor wafer W. However, in terms of the procedural aspects of the method, the plug for wafer support is electrically conductive, rather than forming a structure for supplying charge from the plug to the semiconductor wafer W. Further, in the case of the abnormal discharge generated by the electrostatic chuck suction in the above manner, even in the case of the Coulomb type electrostatic chuck, the abnormal discharge can be prevented by using the bipolar electrostatic chuck. Further, in the above examples, the embodiment of the etching treatment using the parallel plate type etching apparatus will be described, but the present invention is not limited to this embodiment, and can of course be used for so-called plasma processing. Further, in the above embodiment, the case where the weak plasma acts in the vacuum chamber of the etching apparatus that performs the etching treatment will be described, but the weak plasma can be made to function in other places of the apparatus to be processed. The semiconductor wafer W is initialized. As described in detail above, according to the present invention, it is possible to prevent the occurrence of surface arc generated by the substrate to be processed, and it is possible to improve the productivity as compared with the prior art. Industrial Applicability The plasma processing method and the plasma processing apparatus of the present invention can be used in a semiconductor manufacturing industry or the like for manufacturing semiconductor devices. Therefore, there is an industrial use possibility. BRIEF DESCRIPTION OF THE DRAWINGS -21 - (18) (18) 13243261 Fig. 1 is a schematic view showing a schematic configuration of a device used in an embodiment of the present invention. Fig. 2 is a view for explaining a plasma treatment method relating to an embodiment of the present invention. Fig. 3 is a schematic view showing a schematic configuration of a device used in another embodiment of the present invention. Fig. 4 is a view for explaining a plasma processing method according to another embodiment of the present invention. Fig. 5 is a view for explaining a plasma processing method according to a modification of the embodiment shown in Fig. 2. Fig. 6 is a view for explaining a chucking method in accordance with an electrostatic chuck. Fig. 7 is a view for explaining the potential change of each portion of the chuck method of Fig. 6. Fig. 8 is a view for explaining changes in potential of respective portions of other chuck methods. Fig. 9 is a view for explaining a comparative example of the chucking method according to the electrostatic chuck. Fig. 10 is a view for explaining the change in potential of each portion of the chuck method of Fig. 9. The first diagram shows the relationship between the applied voltage of the electrostatic chuck and the number of particles. Fig. 12 is a diagram showing the difference in the number of particles caused by the difference in the program. Figure No. -22- (19)1324361 w Semiconductor wafer 1 Vacuum chamber 2 Mounting table insulation board 4 Electrostatic chuck 5 DC power supply 6 Thermal media flow path 7 Gas flow path 8 Focus ring 9 Feed wire 10 Integrator 11 High frequency power supply
-23 --twenty three -