!310840 九、發明說明： 【發明所屬之技術領域】 減算器，即可以電路=器;並且關於不須採用偏移 解析度、尚精度之測定的積體電路測試器。 【先前技術】 動液多階段(多階層)電壓，以驅 於例如曰本公開二置的積體電路測試器 加以說明之。 ㈣2GG2·98738 m，町參照圖i 於圖1中，受測試對象(以 ===峨接鳴 偏電移偏移 之多階段電壓與賴產生部2 ^ 的輸出’並將DUT1 後，再輸出之。開關4盘偏移者間的電壓差加以放大 將偏移減算器3 ^開關4之輸^^列而裝置。A/D轉換器5 器5 DUT1之輸出在A/D轉換 之信號產生部崎人的輪人模式、卜依未圖示 4，輸入到A/D轉換器5。趟;再經由開關 :資料，未㈣幽鴨數 圖示之信餘生，*誦依未 5。辦換w的電 5 1310840 种數位㈣與偏移電壓值，以判斷DUT1是否良好。 使用Ϊ移減有以下的問題點。前述之裝置中， 入範圍之力i使⑽11的輸出電壓納入㈣轉換器5的私 哭3㈣壯#而貫現高解析度、高精度的設定。為此，偏移減^ G ί ΐί ί於A/D轉換器5之輸人段的前段，並且 咸异益3之精度或漸趨穩定期間的影響。 偏移 【發明内容】 於 【實施方式】 例圖°圖2顯示本發明之第1實施 說明。 /、圖1相同部份則標上同一符號，並省略其 將t i ί置多數個A/D轉換器6以取代A/D轉換器5， 電壓供庠到輸出加以輸入。D/A轉換器7將下限基準 的二2=個=^+器6。驗轉換器w轉換器t 供應到多數個A/D轉加上賴’㈣上限基準電壓 生部。在此，上限=二此外，DA轉換器7、8成為電壓產 之輸入範圍的t壓：亦即1下限J準電壓係規定A/D轉換器6 電麼與下限基準電壓』：於一般的趟轉換器中，依上限基準 進行比較而形成㈣成比較電壓，並制内部之比較器 出加以輸人，^行言H。計算部9將多數個A/D轉換器6的輸 部的控制(數位置^^ D/Af奐器7、8依未圖示之控制 、丁十）以分別將下限基準電壓VL、上限基準電壓 6 1310840!310840 IX. Description of the invention: [Technical field to which the invention pertains] A subtractor, that is, a circuit = a device; and an integrated circuit tester that does not require measurement of offset resolution and accuracy. [Prior Art] A multi-stage (multi-level) voltage of a moving liquid is described in order to drive an integrated circuit tester such as the second disclosed in the present disclosure. (4) 2GG2·98738 m, the town refers to Figure i in Figure 1, the object to be tested (with ===峨, the multi-stage voltage of the partial offset shift and the output of the Lai generation unit 2 ^) and then the DUT1 is output The voltage difference between the shifts of the switch 4 discs is amplified and the output of the offset subtractor 3^switch 4 is arranged. The output of the A/D converter 5 and the output of the DUT1 is generated in the A/D conversion signal. The part of the people of the Ministry of the People's Republic of China, Buyi is not shown in Figure 4, and is input to the A/D converter 5. 趟; and then via the switch: data, not (four) the number of the number of the ducks, the rest of the letter, * 诵 depends on 5. Change the power of 5 1310840 kinds of digits (4) and offset voltage value to judge whether DUT1 is good. The following problem is solved by using Ϊ shifting. In the above device, the force i of the range is included to make the output voltage of (10)11 into the (four) converter. 5 private cry 3 (four) Zhuang # and high-resolution, high-precision settings. For this reason, the offset is reduced to the front segment of the input segment of the A/D converter 5, and the salty benefit 3 The influence of the accuracy or the period of the gradual stabilization period. [Description] [Embodiment] FIG. 2 shows a first embodiment of the present invention. Some parts are marked with the same symbol, and are omitted, and ti ί is placed in a plurality of A/D converters 6 to replace the A/D converter 5, and the voltage is supplied to the output for input. The D/A converter 7 sets the lower limit reference. Two 2 = one = ^ + device 6. The converter w converter t is supplied to a plurality of A/D turn plus Lai's (four) upper limit reference voltage generation. Here, the upper limit = two in addition, the DA converters 7, 8 The t-voltage that becomes the input range of the voltage production: that is, the 1st lower limit J-precision voltage defines the A/D converter 6 and the lower limit reference voltage: in a general 趟 converter, it is formed by comparison with the upper limit reference (4) Comparing the voltage, and making the internal comparator to input, ^I. H. The calculation unit 9 controls the input sections of the plurality of A/D converters 6 (number position ^^ D/Af奂7, 8 Control not shown, D) to lower the lower limit reference voltage VL and the upper limit reference voltage 6 1310840
VH供應到A/D轉換哭6如，A . ^>ν^νί nT VL=VS-VH/2(VS ： DUTl 輪入的輸入模辅出1侑、，JT1依未圖示之信號產生部所 換器並輸入到A/D轉 等輪出疋否在敎之_值細⑽躺或接_之^的判斷 換器靖形時德轉 慶；再供應到趟ίί^，更下限基準電壓、上限基準電 如則述，由於D/A轉換器7、8將 Α 7 屋可變動地供應到A/D轉換$ 6，基丰賴、上限基準電 仍可進行高解析度、高精b T不姻偏移減算器’ 广上裝置偏移減算器，因此能夠氏=二每 輪入範圍可容易地進行變換。 綠自)从構成。此外， 其次’本發明並不限定於此；關於DUT1 j 行電壓輸出之液晶驅練置，㈣f ’雖提示進 有姐=電流輪出之 轉換器設置於DUT1的輸出段，以脾私^圖3所不，將I/V 出到A/D轉換器6。 ；輸出電&轉換成電壓，再輪 又’所提示的構成雖於DUT1的每去接聯卜壯罢A & 6 ;但亦可裝置多工器等之選擇部二她轉，器 支接腳裝置一個A/D轉換器6。 、 的接腳，而每數 至於計算部9 ’可裝置位準移位電路於 換器6間取得位準之整合；或裝置位準移位/電二1和A/D轉 後段之數位電路(未圖示）間取得位準之整合。”、内和以和 又，可將範圍電路裝置於A/D轉換器6。 限基準電換器7、8將下限基準電壓、上 平㈣、應到職1的母支接腳之⑽轉換器6 ;但亦可每 1310840 多數個A/D轉換器6裝置D/A轉換器7、8。 此外，可藉由電壓測定部(未圖示），以測定DUT1之輸出電壓 的概略值，而設定D/A轉換器7、8的電塵值。 【圖式簡單說明】 圖1係顯示習用之積體電路測試器的構成圖。 圖2係顯示本發明之實施例的構成圖。 圖3係顯示本發明之其他實施例的構成圖。 【主要元件符號說明】 1〜受測試對象 2〜電壓產生部 3〜偏移減算器 4〜開關 5,6〜A/D轉換器 VH〜上限基準電壓 VL〜下限基準電壓 7,8〜D/A轉換器 9〜計算部 10〜I/V轉換器VH supply to A/D conversion cry 6 as, A. ^>ν^νί nT VL=VS-VH/2 (VS: DUTl wheeled input mode is supplemented by 1侑, JT1 is generated according to the signal not shown The converter is input and input to the A/D turn, etc., whether it is in the _ value of the _ value of the fine (10) lying or connected _ ^ ^ the judgment of the change of the shape of the Jingde dynasty; then supply to 趟 ί ί, lower limit datum The voltage and the upper limit reference voltage are as described above. Since the D/A converters 7 and 8 can be variably supplied to the A/D conversion $6, the base Fenglai and the upper limit reference power can still be high-resolution and high-precision. b T does not match the offset reducer's wide-range device offset reducer, so it can be easily converted every two rounds of the range. Green from). In addition, the second embodiment of the present invention is not limited to this; for the liquid crystal drive of the DUT1 j voltage output, (4) f 'there is a converter that is set to the output of the DUT1, and the spleen private map 3 No, the I/V is output to the A/D converter 6. The output power & converts into voltage, and then the round and 'presented composition, although the DUT1 is connected to each other, A &6; but can also be installed in the multiplexer, etc. The pin device is an A/D converter 6. , the pin of each, and the calculation unit 9 ' can be the device level shift circuit to obtain the level integration between the converters 6; or the device level shift / electric two 1 and A / D turn rear digital circuit (Unillustrated) the integration of the level is achieved. , and the range circuit can be installed in the A/D converter 6. The limit reference converters 7 and 8 convert the lower limit reference voltage, the upper level (four), and the parent support pin of the job 1 (10). 6; however, a plurality of A/D converters 6 may be provided for D/A converters 7 and 8 per 1310840. Further, a voltage measuring unit (not shown) may be used to measure the approximate value of the output voltage of the DUT 1. The electric dust value of the D/A converters 7 and 8 is set. [Brief Description of the Drawings] Fig. 1 is a view showing the configuration of a conventional integrated circuit tester. Fig. 2 is a view showing the configuration of an embodiment of the present invention. 3 shows a configuration diagram of another embodiment of the present invention. [Description of Main Element Symbols] 1 to Test Subject 2 to Voltage Generation Unit 3 to Offset Reducer 4 to Switch 5, 6 to A/D Converter VH to Upper Limit Reference voltage VL to lower limit reference voltage 7, 8 to D/A converter 9 to calculation unit 10 to I/V converter