1310202 九、發明說明： 【發明所屬之技術領域】 . 本發明涉及一種場發射陰極裝置之製造方法，尤其涉 及一種採用碳奈米管作發射體的三極型場發射陰極裝置之 製造方法。 、 【先前技術】 咖奴奈米管作爲場發射電子源的研究是碳奈米管應用研 九中最爲深入的研究領域之一。由於碳奈米管具有極優異 的導電性能’及幾乎接近理論極限之尖端表面積（尖端表面 積越小，其局部電場越集中）’同時還具有化學性質穩定、 機械強度高以及導熱性能料❹優異H 破太 管是目前最理想之場發射材料之一。 不〃 ::来管場發射陰極裝置至少包括一陰極支樓體及作 丄發=的3米管層，該碳奈米管層形成於陰極支揮體 米管形成於陰極支禮體上的方式主要有機 合成好的法。其山中’機械方法是通過機械手操縱 上t卜磁反不只官’將碳奈米管用化學膠固定到支撐體 縱直徑…右的碳奈;費時’特別是操 方法較複雜，不易操作。+ 4子疋不可能的，因此這種 過化上錄上金屬催化劑，然後通 碳奈米管，此種方法摔 方律趙上直接生長出 為早，妷奈米管與支撐體的電接 7 1310202 觸良好i_疋，對於三極型場發射陰極裝置，其是利用閑 極孔3鍍开/成金屬催化劑層’並在該金屬催化劑層上直接 生長出U s。由於閘極孔内蒸鑛的金屬催化劑區域面 積與閘極孔大小相-致，因此若生長出的碳奈”高度過 向，則邊緣處之碳奈米管會與閘極相接觸，從而造成陰極 與閘極間短路。且邊緣處的碳奈米管發射的電子有相當一 部分直接打到閘極之下表面，造成漏電，降低了發光效率。 爲了克服上述缺陷，一種現有技術提出了在間極上小 角f蒸鍍犧牲層從而減小金屬催化劑蒸鍍的面積的技術。 ^疋’該技術蒸鑛卫藝較爲複雜，而且蒸鍍金屬催化劑後 還南要完全除去犧牲層材料而不損害其他結構，卫蔽要東 較高’製造方法較爲複雜且若犧牲層不能除♦，有^能站 π發射體，影響整個場發射裝置的性能。 有鑑於此，有必要提供一種製造簡單且性能良好的三 極型場發射陰極裝置之製造方法。 【發明内容】 、以下將以實施例說明一種場發射陰極裝置之製造方 法0 -種場發射陰極裝置之製造方法，其包括以下步驟. ，供-個襯底；在襯底上依次形成—層閘極絕緣介質層， :層閘極金屬層及一層光刻膠層；微影光刻膠層形成一預 疋之圖案；分別蝕刻閘極金屬層及閘極絕緣介質層以形成 閘極’閘極絕緣介質間隔體及閘極孔；對光刻膠層加熱並 加壓使其面積增大；利用面積增大的光刻膠層作爲掩模， 1310202 1310202 出碳 於閘 蒸鑛金屬催化劑層；在金屬催化劑層上生長 奈未官陣列以形成場於 野知射源，該％發射源之橫截面小 極孔。 、 所述的％發射陰極裝置之製造方 將金屬催化劑的尺寸.¾ f山e , ^ ^ 寸減小，生長出的碳奈米管陣列的橫截 面小於閘極孔的橫截面，從而有效的避免了碳奈米管^ 極接觸’減小了短路的幾率。同時由於不再有碳奈米管位 於閘極的正下方’減小了場發射電子打到閘極上的幾率， 減小了漏電電流。而且’本方法僅需要將光刻滕層加熱壓 扁，其製程較爲簡單，對工藝要求較低，無需利用其他材 料’成本較低。 【實施方式】 下面結合附圖對本發明作進一步詳細說明。 本發明第一實施例的三極型場發射陰極裝置之製造方 法包括以下步驟： 步驟1 :提供一概底11〇。 明參閱圖1，該襯底110包括一普通玻璃基板111，以 及依次形成在玻璃基板111上的絕緣介質層112和金屬層 113。該金屬層113作爲陰極。該襯底110還可以僅採用一 導電玻璃基板作爲襯底’例如氧化銦錫（IT0，lndium Tin Oxide)或氧化姻辞（IZO，Indium Zinc Oxide)等，其可以直 接作爲陰極。 步驟2:在襯底110上依次形成一層閘極絕緣介質層 120 ’ 一閘極金屬層130和一光刻膠層140。 1310202 請參閱圖2，該閘極絕緣介質層12〇可以用鍍獏、印 刷等方法沈積在襯底110之上。該間極絕緣介質層u〇用 於間隔陰極113及閘極’使其電絕緣。該閘極絕緣介質層 12〇的厚度範圍在1微求〜1000微米，優選厚度範圍約爲 H)微米〜200微米。該閘極絕緣介質層12〇應當可光刻加 工，且能夠承受700°C左右的碳奈米管生長時的溫度，其 材料可選擇高溫玻璃、矽、氧化矽、陶瓷或雲母等。/、 該閘極金屬層13G是用於製造閘極的，其形成於問極 絕緣介質層120之上，與陰極113電絕緣。 步驟3 :微影該光刻膠層14〇形成一預定之圖案。 請參閱圖3 ’對塗覆在閘極金屬層13〇上的光刻膠層 140曝光顯影，使該光刻膠層14〇形成一定的圖案 圖案141對應于所要形成的閘極。 Α 步驟4 .分別蝕刻閘極金屬層13〇及閘極絕緣介声 120。 曰 • 請參閲® 4，形成-定圖案的光刻膠層141作爲 掩模’分別利用乾姓刻法银刻閘極金屬们3〇以形成問極 131利用濕蝕刻法蝕刻閘極絕緣介質層120以形成閘極 131與陰極113之間的間隔體121。通過兩次蝕刻，形成了 間極孔150。 步驟5.對光刻膠層141加熱並加壓使其面積增大。 °月參閱圖5,通過加熱使形成了一定圖案的光刻膠層141 軟化’同時在光娜層141的上方施加>1力，在壓力作用下， 光xi膠層141的厚度減小同時其面積增大，兩相鄰光刻膠層⑷ 1310202 間的間隔孔160之橫截面相應的減小，小於其下的閘極孔15〇。 步驟6 :蒸鑛金屬催化劑層。 請參閱圖6 ’利用壓扁的光刻膠層141作爲掩模，在 襯底110上蒸鍍金屬催化劑層17〇。該金屬催化劑層17〇 一般採用Fe、Co、Ni或其合金。該金屬催化劑層厚 度爲1〜10奈米，優選爲3〜5奈米。該金屬催化劑層17〇 可在300 C ~400 C溫度下進行退火，以利於催化劑奈来顆 粒的形成。而且，由於光刻膠層141間的間隔孔ι6〇小於 .閘極孔150，因此，蒸鍍的金屬催化劑層ι7〇的橫截面小 於閘極孔150。 步驟7 :在金屬催化劑層170上生長出碳奈米管陣列 180 ° 請參閱圖7 ’在金屬催化劑層17〇上用化學氣相沈積 的方法生長出垂直向上的碳奈米管陣列180。該碳奈米管 陣列180的發射面即上表面的面積相當於催化劑圖案的面 鲁積’因此其小於閘極孔150。 步驟8 :剝離光刻膠層141。 凊參閱圖8，將光刻膠層141從閘極131上剝離，形 成如圖所示的場發射陰極裝置。 ^ 與先前技術相比，該場發射陰極裝置的製造方法將金 屬催化劑170的尺寸減小，生長出的碳奈米管陣列18〇的 橫截面小於閘極孔150的橫截面，從而有效的避免了碳奈 米管180與閘極131接觸，減小了短路的幾率。同時由= 不再有碳奈米管180位於閘極131的正下方，減小了場發 11 -1310202 f電子打到閘極m上的幾率’減小了漏電電流。而且， 。。方法僅需要將光刻膠層141加熱㈣，其製程較爲簡 早’對工藝要求較低’無需利用其他材料，成本較低。 該步驟8也可以在步驟6蒸鏡金屬催化劑層後執行， 步驟7。即先剝離光刻膠層141然後再生長出碳奈 木官陣列180。 =參閱圖9,是本發明第二實施例的三極型場發射陰 極裝置的製造方法，該方法與第一實施例中的方法 ==比’其不同僅在於在閘極131與閘極絕緣介質間隔 間還形成一層第二絕緣介質間隔體190,該第二絕 緣介質間隔體190與間極絕緣介質間隔體ΐ2ι的材料不 =哲=第二絕緣介質間隔體⑽對步驟4中㈣閘極絕緣 n a 12G所用的腐#液具有好的耐㈣性，因此在對開 =邑=質層12G進行濕法_時，第二絕緣介質間隔體 間的問極孔直徑不會因腐姓而減小，從而與閘極131 =同，其可進一步有效的阻止碳奈米管18〇與閉極i3i 間接觸，減少短路發生的# I η k ^的4♦。同時阻擔了從下方發射到 體;9 =的電子，減少漏電電流。㈣二絕緣介質間隔 體190採用氮化矽材料。 ^上所述、，本發明符合發明專利要件，爰依法提出專 '明准以上所述者僅為本發明之較佳實施例，舉凡 :習本案技藝之人士’在援依本案發明之精神所作之等效 ，飾或變化，皆應包含於以下之申請專利範圍内。 【圖式簡單說明】 12 .1310202 圖1係本發明鏡片製程之流程示意圖。 圖1是本發明第一實施例所提供一片待加工的襯底的 截面示意圖。 圖2是在圖χ所示的襯底上形成閘極絕緣介質層、閘 極金屬層及光刻膠層的截面示意圖。 圖3是對圖2中的光刻膠層曝光顯影後的截面示意圖。 圖4是蝕刻圖3中的閘極金屬層及閘極絕緣介質層後 的截面示意圖。 圖5疋對圖4中的光刻膠層加熱加壓處理後的截面示 意圖。 圖6疋在圖5的基礎上蒸鍍金屬催化劑後的截面示意 意圖 圖7是在圖6的基礎上生長碳奈米管陣列後的戴面示 圖8是本發明第一實施例所製成的場發射陰 截面示意圖。 圖:是本發明第二實施例所製成的場發射陰極 戳面不意圖。 【主要元件符號說明】 110 玻璃基板 111 112 金屬層 113 121 閘極 131 120 閘極金屬層 130 140 、 141 閘極孔 150 襯底 絕緣介質層 閘極絕緣介質間隔體 閘極絕緣介質層 光刻膠層 13 170 1310202 光刻膠層間之間隔孔 160 催化劑層 180 第二絕緣介質間隔體 190 碳奈米管IX. Description of the Invention: [Technical Field] The present invention relates to a method of manufacturing a field emission cathode device, and more particularly to a method of manufacturing a three-pole field emission cathode device using a carbon nanotube as an emitter. [Prior Art] The study of the coffee-nanotube as a field emission electron source is one of the most in-depth research fields in the application of carbon nanotubes. Since the carbon nanotubes have excellent electrical conductivity' and a tip surface area that is close to the theoretical limit (the smaller the tip surface area, the local electric field is concentrated), it also has chemical stability, high mechanical strength, and excellent thermal conductivity. The broken Taiguan tube is one of the most ideal field launch materials. The following: The tube emission cathode device includes at least a cathode support body and a 3 m tube layer for bursting, and the carbon nanotube layer is formed on the cathode support tube formed on the cathode support body. The way is mainly organic synthesis of good methods. In the mountain, the mechanical method is to fix the carbon nanotubes with chemical glue to the carbon nanotubes on the right side of the support by the manipulator. The time-consuming method is especially complicated and difficult to operate. + 4 sub-疋 is impossible, so this kind of over-chemical recording of the metal catalyst, and then through the carbon nanotubes, this method directly grows out of the square law Zhao, the electrical connection between the tantalum tube and the support 7 1310202 is in good contact with i_疋. For a three-pole field emission cathode device, it is used to plate/form the metal catalyst layer 'with the idle hole 3' and directly grow U s on the metal catalyst layer. Since the area of the metal catalyst in the gate hole is the same as the size of the gate hole, if the carbon to be grown is highly over-oriented, the carbon nanotube at the edge will contact the gate, thereby causing A short circuit between the cathode and the gate, and a considerable portion of the electrons emitted by the carbon nanotube at the edge directly hit the lower surface of the gate, causing leakage and reducing luminous efficiency. To overcome the above drawbacks, a prior art is proposed The technique of vapor-depositing the sacrificial layer on the top small angle f to reduce the area of vapor deposition of the metal catalyst. ^疋' This technology is more complicated in steaming and polishing, and after the metallization catalyst is evaporated, the sacrificial layer material is completely removed without damaging the other. The structure is more complicated than the east. The manufacturing method is more complicated and if the sacrificial layer cannot be removed, there is a π emitter that can affect the performance of the entire field emission device. In view of this, it is necessary to provide a simple manufacturing and performance. A manufacturing method of a good three-pole field emission cathode device. [Description of the Invention] Hereinafter, a manufacturing method of a field emission cathode device will be described by way of example. A method for manufacturing a pole device, comprising the steps of: providing a substrate; sequentially forming a layer of a gate insulating dielectric layer on the substrate, : a gate gate metal layer and a photoresist layer; lithography photoresist Forming a pre-turned pattern; etching the gate metal layer and the gate insulating dielectric layer respectively to form a gate-gate insulating dielectric spacer and a gate hole; heating and pressing the photoresist layer to increase the area thereof Using an increased area of the photoresist layer as a mask, 1310202 1310202 carbon is deposited on the gated metallization catalyst layer; a Naiwei official array is grown on the metal catalyst layer to form a field source, the % of the emission source The small-pore hole of the section, the manufacturer of the %-emission cathode device reduces the size of the metal catalyst by 3⁄4 f mountain e, ^ ^ inch, and the cross section of the grown carbon nanotube array is smaller than the horizontal of the gate hole. The cross-section, thus effectively avoiding the carbon nanotubes' contact, reduces the probability of short-circuiting. At the same time, since there is no longer a carbon nanotube located directly below the gate, the probability of field-emitting electrons hitting the gate is reduced. , reducing the leakage current. The method only needs to heat and flatten the lithographic layer, the process is relatively simple, the process requirement is low, and the use of other materials is not required, and the cost is low. [Embodiment] The present invention will be further described in detail below with reference to the accompanying drawings. The manufacturing method of the three-pole field emission cathode device of the first embodiment of the present invention comprises the following steps: Step 1: providing a basic substrate. Referring to FIG. 1, the substrate 110 includes a common glass substrate 111, and is sequentially formed in the glass. An insulating dielectric layer 112 and a metal layer 113 on the substrate 111. The metal layer 113 serves as a cathode. The substrate 110 may also use only a conductive glass substrate as a substrate, such as indium tin oxide (IT0) or oxidized marriage. (IZO, Indium Zinc Oxide), etc., which can be used directly as a cathode. Step 2: sequentially forming a gate insulating dielectric layer 120' a gate metal layer 130 and a photoresist layer 140 on the substrate 110. Referring to FIG. 2, the gate insulating dielectric layer 12 can be deposited on the substrate 110 by plating, printing, or the like. The inter-electrode dielectric layer u is used to electrically insulate the cathode 113 and the gate. The gate insulating dielectric layer 12 has a thickness ranging from 1 μm to 1000 μm, preferably in a thickness ranging from about H) to 200 μm. The gate insulating dielectric layer 12〇 should be photolithographically processed and capable of withstanding the temperature at which the carbon nanotubes are grown at about 700 ° C, and the material may be selected from high temperature glass, tantalum, yttria, ceramic or mica. The gate metal layer 13G is used to fabricate a gate which is formed over the interrogation dielectric layer 120 and is electrically insulated from the cathode 113. Step 3: lithography the photoresist layer 14 to form a predetermined pattern. Referring to FIG. 3', the photoresist layer 140 coated on the gate metal layer 13 is exposed and developed such that the photoresist layer 14 is formed into a pattern 141 corresponding to the gate to be formed. Α Step 4. Separate the gate metal layer 13 and the gate insulating dielectric 120, respectively.曰• Refer to о 4, forming a patterned photoresist layer 141 as a mask's etched gate metal by dry etching, respectively, to form a gate 131. The gate insulating dielectric is etched by wet etching. The layer 120 is formed to form a spacer 121 between the gate 131 and the cathode 113. An interpole hole 150 is formed by two etchings. Step 5. The photoresist layer 141 is heated and pressurized to increase its area. Referring to Fig. 5, the photoresist layer 141 having a certain pattern is softened by heating while applying a force of >1 above the gamma layer 141, and the thickness of the light xi glue layer 141 is reduced under pressure. The area thereof is increased, and the cross-section of the spacing holes 160 between the two adjacent photoresist layers (4) 1310202 is correspondingly reduced, which is smaller than the lower gate holes 15〇. Step 6: steaming the metal catalyst layer. Referring to Fig. 6', a metal catalyst layer 17 is vapor-deposited on the substrate 110 by using the flattened photoresist layer 141 as a mask. The metal catalyst layer 17 is generally made of Fe, Co, Ni or an alloy thereof. The metal catalyst layer has a thickness of from 1 to 10 nm, preferably from 3 to 5 nm. The metal catalyst layer 17〇 can be annealed at a temperature of 300 C to 400 C to facilitate the formation of the catalyst. Further, since the spacer hole ι6 间 between the photoresist layers 141 is smaller than the gate hole 150, the vapor-deposited metal catalyst layer ι7 〇 has a smaller cross section than the gate hole 150. Step 7: Growth of a carbon nanotube array on the metal catalyst layer 170 180 ° A vertical upward carbon nanotube array 180 was grown by chemical vapor deposition on the metal catalyst layer 17A. The area of the upper surface of the emitting surface of the carbon nanotube array 180 corresponds to the surface area of the catalyst pattern so that it is smaller than the gate hole 150. Step 8: The photoresist layer 141 is peeled off. Referring to Figure 8, the photoresist layer 141 is stripped from the gate 131 to form a field emission cathode device as shown. ^ Compared with the prior art, the method of manufacturing the field emission cathode device reduces the size of the metal catalyst 170, and the cross section of the grown carbon nanotube array 18 is smaller than the cross section of the gate hole 150, thereby effectively avoiding The carbon nanotube 180 is in contact with the gate 131, reducing the probability of a short circuit. At the same time, by = no more carbon nanotubes 180 are located directly below the gate 131, reducing the probability that the field 11 - 1310202 f electrons hit the gate m 'reduces the leakage current. And,. . The method only needs to heat the photoresist layer 141 (IV), and the process is relatively simple, 'the process requirement is low', no need to use other materials, and the cost is low. This step 8 can also be performed after the metal catalyst layer is vaporized in step 6, step 7. That is, the photoresist layer 141 is first stripped and then the carbon nanostructure array 180 is regenerated. Referring to Fig. 9, there is shown a manufacturing method of a three-pole field emission cathode device according to a second embodiment of the present invention, which is different from the method of the first embodiment in the ratio of == in the gate electrode 131 and the gate. A second insulating dielectric spacer 190 is further formed between the dielectric spacers, and the material of the second insulating dielectric spacer 190 and the inter-polar insulating dielectric spacer 不2ι=================================================================== The rot #liquid used for insulating na 12G has good resistance to (four), so when the wet _ is performed on the open layer 邑 = 质 layer 12G, the diameter of the hole between the second insulating medium spacers is not reduced by the rot number. Therefore, it is the same as the gate 131 =, which can further effectively prevent the contact between the carbon nanotube 18 〇 and the closed pole i3i, and reduce the 4 ♦ of the # I η k ^ of the short circuit. At the same time, it blocks the emission from below to the body; 9 = electrons, reducing leakage current. (4) The two insulating dielectric spacers 190 are made of tantalum nitride material. According to the above description, the present invention complies with the requirements of the invention patent, and the above-mentioned ones are specifically described in the above, which are only the preferred embodiments of the present invention, and the persons skilled in the art of the present invention are made in the spirit of the invention of the present invention. Equivalent, decorative or variation should be included in the scope of the following patent application. BRIEF DESCRIPTION OF THE DRAWINGS 12.1310202 FIG. 1 is a schematic flow chart of a lens process of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic cross-sectional view showing a substrate to be processed according to a first embodiment of the present invention. Figure 2 is a schematic cross-sectional view showing the formation of a gate insulating dielectric layer, a gate metal layer and a photoresist layer on the substrate shown in Figure 。. 3 is a schematic cross-sectional view showing the photoresist layer of FIG. 2 after exposure and development. Fig. 4 is a schematic cross-sectional view showing the gate metal layer and the gate insulating dielectric layer of Fig. 3 being etched. Fig. 5 is a cross-sectional view showing the photoresist layer in Fig. 4 after heat and pressure treatment. Figure 6 is a schematic cross-sectional view of the metal catalyst after vapor deposition on the basis of Figure 5; Figure 7 is a front view of the carbon nanotube array grown on the basis of Figure 6; Figure 8 is a first embodiment of the present invention. A schematic diagram of the field emission of the field. Figure: is a schematic view of a field emission cathode stamp made in accordance with a second embodiment of the present invention. [Main component symbol description] 110 Glass substrate 111 112 Metal layer 113 121 Gate 131 120 Gate metal layer 130 140, 141 Gate hole 150 Substrate insulating dielectric layer Gate insulating dielectric spacer Gate insulating dielectric layer photoresist Layer 13 170 1310202 Interstitial holes between photoresist layers 160 Catalyst layer 180 Second dielectric spacer 190 Carbon nanotube
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