TWI295833B - Recycling a wafer comprising a buffer layer, after having taken off a thin layer therefrom - Google Patents

Recycling a wafer comprising a buffer layer, after having taken off a thin layer therefrom Download PDF

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Publication number
TWI295833B
TWI295833B TW092123247A TW92123247A TWI295833B TW I295833 B TWI295833 B TW I295833B TW 092123247 A TW092123247 A TW 092123247A TW 92123247 A TW92123247 A TW 92123247A TW I295833 B TWI295833 B TW I295833B
Authority
TW
Taiwan
Prior art keywords
layer
donor wafer
buffer structure
protective layer
removal
Prior art date
Application number
TW092123247A
Other languages
English (en)
Chinese (zh)
Other versions
TW200414417A (en
Inventor
Ghyselen Bruno
Aulnette Cecile
Osternaud Benedicte
Le Vaillant Yves-Mathieu
Akatsu Takeshi
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of TW200414417A publication Critical patent/TW200414417A/zh
Application granted granted Critical
Publication of TWI295833B publication Critical patent/TWI295833B/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02032—Preparing bulk and homogeneous wafers by reclaiming or re-processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Laminated Bodies (AREA)
TW092123247A 2002-08-26 2003-08-25 Recycling a wafer comprising a buffer layer, after having taken off a thin layer therefrom TWI295833B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0210587A FR2843826B1 (fr) 2002-08-26 2002-08-26 Recyclage d'une plaquette comprenant une couche tampon, apres y avoir preleve une couche mince
US43192802P 2002-12-09 2002-12-09

Publications (2)

Publication Number Publication Date
TW200414417A TW200414417A (en) 2004-08-01
TWI295833B true TWI295833B (en) 2008-04-11

Family

ID=31198315

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092123247A TWI295833B (en) 2002-08-26 2003-08-25 Recycling a wafer comprising a buffer layer, after having taken off a thin layer therefrom

Country Status (4)

Country Link
JP (1) JP4846363B2 (ja)
AT (1) ATE519222T1 (ja)
FR (1) FR2843826B1 (ja)
TW (1) TWI295833B (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI761587B (zh) * 2018-01-31 2022-04-21 台灣積體電路製造股份有限公司 晶圓加工方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2905799B1 (fr) * 2006-09-12 2008-12-26 Soitec Silicon On Insulator Realisation d'un substrat en gan
US8946054B2 (en) 2013-04-19 2015-02-03 International Business Machines Corporation Crack control for substrate separation

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0926709A3 (en) * 1997-12-26 2000-08-30 Canon Kabushiki Kaisha Method of manufacturing an SOI structure
JP2000349264A (ja) * 1998-12-04 2000-12-15 Canon Inc 半導体ウエハの製造方法、使用方法および利用方法
JP2000349266A (ja) * 1999-03-26 2000-12-15 Canon Inc 半導体部材の製造方法、半導体基体の利用方法、半導体部材の製造システム、半導体部材の生産管理方法及び堆積膜形成装置の利用方法
US6326279B1 (en) * 1999-03-26 2001-12-04 Canon Kabushiki Kaisha Process for producing semiconductor article
US6375738B1 (en) * 1999-03-26 2002-04-23 Canon Kabushiki Kaisha Process of producing semiconductor article
JP3453544B2 (ja) * 1999-03-26 2003-10-06 キヤノン株式会社 半導体部材の作製方法
JP2003506883A (ja) * 1999-08-10 2003-02-18 シリコン ジェネシス コーポレイション 低打ち込みドーズ量を用いて多層基板を製造するための劈開プロセス
JP3607194B2 (ja) * 1999-11-26 2005-01-05 株式会社東芝 半導体装置、半導体装置の製造方法、及び半導体基板
JP2004507084A (ja) * 2000-08-16 2004-03-04 マサチューセッツ　インスティテュート　オブ　テクノロジー グレーデッドエピタキシャル成長を用いた半導体品の製造プロセス
JP4296726B2 (ja) * 2001-06-29 2009-07-15 株式会社Ｓｕｍｃｏ 半導体基板の製造方法及び電界効果型トランジスタの製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI761587B (zh) * 2018-01-31 2022-04-21 台灣積體電路製造股份有限公司 晶圓加工方法

Also Published As

Publication number Publication date
FR2843826B1 (fr) 2006-12-22
JP4846363B2 (ja) 2011-12-28
JP2005537686A (ja) 2005-12-08
TW200414417A (en) 2004-08-01
ATE519222T1 (de) 2011-08-15
FR2843826A1 (fr) 2004-02-27

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