TWI286456B

TWI286456B - Multi-layer circuit board integrated with electronic elements and method for fabricating the same

Info

Publication number: TWI286456B
Application number: TW93118746A
Authority: TW
Inventors: Chu-Chin Hu; Lin-Yin Wong; Zao-Kuo Lai
Original assignee: Phoenix Prec Technology Corp
Priority date: 2004-06-28
Filing date: 2004-06-28
Publication date: 2007-09-01
Also published as: TW200601923A

Abstract

A multi-layer circuit board integrated with electronic elements and a method for fabricating the same are proposed, wherein an inner circuit board formed with a patterned circuit structure and a metal pad on at least a surface thereof is provided. An electronic element formed with electrical connections is mounted on the metal pad by an adhesive, and a build-up circuit structure is formed on the inner circuit board for electrically connecting to the electrical connections of the electronic element, so as to form a base circuit board integrated with an electronic element. Then, at least a stacked circuit unit integrated with an electronic element is laminated on the base circuit board, so as to integrate electronic elements, such as semiconductor chip or chip type passive component in a circuit board to improve electrical function of electronic device.

Description

1286456 五、發明說明α) 【發明所屬之技術領域】制本發明係有關於一種整合電子元件之多層電路板及其製法’尤指一種可嵌埋有主動元件甚或被動元件並提供其 ”圖案化線路結構相互電性導接之電路板結構及其製作方法。【先前技術】隨著半導體封裝技術的演進，半導體裝置（ Semiconductor device)已開發出不同的封裝型態，其中球，陣列式（Bal 1 grid array, BGA)為一種先進的半導體封裝技術，其特點在於採用一電路板來安置半導體晶片，亚利用自動對位（Self-alignment)技術以於該電路板背面植置複數個成柵狀陣列排列之錫球（s〇lder baU)，使相同單位面積之半導體晶片承栽件上可以容納更多輸 /輸出連接端（I/O connection)以符合高度集積化（ Integration)之半導體晶片所需，以藉由此些錫球將敕個封裝單元銲結並電性連接至外部之印刷電路板。正惟無論是採用打線式封裝製程亦或覆晶式封裝製該電路板之製程與半導體晶片之封農形式，均需 ^ 之製程機具與製程步驟，且其製程繁肖，製造不：一方面，對於打線式封裝製程而言，設置於半導片= ^之線狐密度極高，極易造成金線不㈣接產生片周 Sh〇rt)，增加打線作業困難度；再者，☆進行 ( 製程時，係將完成佈設晶片與導線 n^ 楔用、、果之電路板置於一封壯具中，俾供一環氧樹脂（Epoxy )材粗、衣 Μ枓注入模具中而形成1286456 V. INSTRUCTION DESCRIPTION α) [Technical Field of the Invention] The present invention relates to a multilayer circuit board incorporating electronic components and a method of manufacturing the same, in particular, an embedded active component or even a passive component can be embedded and provided with a "patterning" A circuit board structure in which a line structure is electrically connected to each other and a manufacturing method thereof. [Prior Art] With the evolution of semiconductor packaging technology, semiconductor devices have developed different package types, in which balls and arrays (Bal) 1 grid array, BGA) is an advanced semiconductor packaging technology featuring a circuit board for mounting semiconductor wafers, and a self-alignment technique for implanting a plurality of grids on the back side of the board. The array of solder balls (s〇lder baU) enables semiconductor wafer carriers of the same unit area to accommodate more I/O connections to conform to highly integrated semiconductor wafers. It is necessary to solder and electrically connect one package unit to the external printed circuit board by using the solder balls. The process of manufacturing the circuit board and the sealing form of the semiconductor wafer by using the wire-wound packaging process or the flip-chip package require the process tools and process steps, and the manufacturing process is complicated, and the manufacturing process is not: On the one hand, for the wire type In terms of the packaging process, the density of the foxes placed on the semi-guided film = ^ is extremely high, which is very likely to cause the gold wire not to be connected (4) to produce the film circumference Sh〇rt), which increases the difficulty of the wire-laying operation; The system will complete the laying of the wafer and the wire n^ wedge, and the circuit board of the fruit is placed in a cultivator, and an epoxy resin (Epoxy) material is thickened, and the plaque is injected into the mold to form.

17707全懲.ptd 第17707 full punishment. ptd

1286456 五、發明說明（2) ---- 以包覆該晶片與銲線之封裝膠體，然而，於實，制。該模具由於受限於半導體封裝件之設計，故其^ =程中，夾壓位置勢必有所差異而造成無法緊密夾固等^尺寸與入樹脂材料時，容易導致封裝膠體溢膠至該電路^丄俟注 ::但降低該半導體封裝件之表面平整度與美觀二：’ 月匕巧染該電路板上後續欲植置錫球之銲墊位置，=:更可半導體封裝件之電性連接品質，嚴重影響該之生產品質及產品信賴度。J +導體封裝件 f迭ΐ Ϊ : Γι Γ ΐ導體裝置之製程，係、首先由晶片承葡祙衣4業者（例如電路板片承載件晶片承載#，之後5屋適用於+導體裝置之業者進行置晶、模壓再載件交由半導體封裳客戶端所需之電子ς能：呈’最後，方可完成業者（即包含有晶片承 ^衣置。其間涉及不同製程因此於實際製造過牛製&業者與半導體封裝業者），且，若客戶：欲二：：！步驟煩續且界面整合不易，況層面更是複雜，亦不：土以计時，其牵涉變更與整合況且，隨著電子：：需ΐ變更彈性與經濟效益。入多功能、高性能的^的蓬勃t展，電子產品亦逐漸邁集度（IntegratiooW方/V為滿足半導體封裝件高積封裝需求，提供多數主&及被型化（Mlniaturizati〇n)的漸由雙層板演變成多線路，之電… 限的空間下，藉d(MUltl: b〇ard)，俾於有 )擴大電路板上可^ ^接技術（erUyer C〇nnection 用的電路面積而配合高電子密度之積1286456 V. Description of the Invention (2) ---- The encapsulation gel covering the wafer and the bonding wire, however, is practical. Due to the limitation of the design of the semiconductor package, the mold may have a different clamping position, which may result in inability to be tightly clamped. When the size is entered into the resin material, the package gel may easily overflow into the circuit. ^Note:: But reduce the surface flatness and aesthetics of the semiconductor package. 2: 'The location of the solder pads on the board that will be used to implant the solder balls on the board. =: The electrical properties of the semiconductor package. The quality of the connection seriously affects the production quality and product reliability. J + conductor package f ΐ Γ : Γ Γ ΐ ΐ ΐ ΐ ΐ ΐ 之 , ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ Performing the crystallization, molding, and reloading of the electronic components required by the semiconductor package client: in the end, the manufacturer can be completed (that is, the wafer is contained), and the process involves different processes. System & industry and semiconductor packaging industry), and, if the customer: want two::! Steps are troublesome and interface integration is not easy, the situation is more complex, nor: the earth is timing, it involves changes and integration, and Electronic:: Need to change flexibility and economic benefits. Into the multi-functional, high-performance ^ boom, electronic products are gradually gaining degrees (IntegratiooW side / V to meet the high-package requirements of semiconductor packages, provide the majority & and the typed (Mlniaturizati〇n) gradually evolved into a multi-line, the power of the ... limited space, by d (MUltl: b〇ard), 俾有) can expand the board can ^ ^接技术(erUyer C〇nn The area of the circuit used for ection and the product of high electron density

17707全懋.ptd 第9頁 1286456 五、發明說明（3) 體電路（Integrated circuit)需求。再者，因半導體裝置之集積化，封裝構造之接腳數目亦隨著增加，而由於接腳數目之增多，導致雜訊亦隨之增大，因此，一般為消除雜訊，係於半導體封裝構造中加入被動元件，如:電阻元件、電容元件與電感元件等，藉以消除雜訊及穩定電路，使得所封裝之半導體晶片具有特定之電流特性。因此，如何在電路板有限的空間下，提供有效數量之被動元件與半導體晶片等電子元件於該電路板中，藉以提昇電子產品之電性功能，亦為目前亟待解決之課題。【發明内容】鑒於以上所述習知技術之缺點，本發明之主要目的係提供一種整合電子元件之多層電路板及其製法，俾形成一内嵌有半導體晶片甚或被動元件之電路板結構，藉以提昇電子產品之電性功能。本發明之又一目的係提供一種整合電子元件之多層電路板及其製法，俾同時整合晶片承載件之製造與半導體封裝技術之製程，以提供客戶端較大需求弹性，同時得以簡化半導體業者製程步驟、成本及界面整合問題。本發明之另一目的係提供一種整合電子元件之多層電路板及其製法，俾有效避免半導體封裝製程所導致之問題〇本發明之再一目的係提供一種整合電子元件之多層電路板及其製法，俾有效增加用以承載主動元件與被動元件之電路板空間利用率。17707 全懋.ptd Page 9 1286456 V. Invention Description (3) Integrated circuit requirements. Furthermore, due to the accumulation of semiconductor devices, the number of pins of the package structure also increases, and the number of pins increases, so that the noise is also increased. Therefore, generally, the noise is eliminated in the semiconductor package. Passive components, such as resistive components, capacitive components, and inductive components, are added to the structure to eliminate noise and stabilize the circuit, so that the packaged semiconductor wafer has specific current characteristics. Therefore, how to provide an effective number of electronic components such as passive components and semiconductor chips in the circuit board in a limited space of the circuit board, thereby improving the electrical function of the electronic product, is also an urgent problem to be solved. SUMMARY OF THE INVENTION In view of the above disadvantages of the prior art, the main object of the present invention is to provide a multilayer circuit board incorporating electronic components and a method of manufacturing the same, which form a circuit board structure in which a semiconductor wafer or even a passive component is embedded. Improve the electrical function of electronic products. Another object of the present invention is to provide a multilayer circuit board integrating electronic components and a method for manufacturing the same, which simultaneously integrates the manufacturing process of the wafer carrier and the manufacturing process of the semiconductor packaging technology to provide greater flexibility of the client and simplify the process of the semiconductor industry. Steps, costs and interface integration issues. Another object of the present invention is to provide a multilayer circuit board incorporating electronic components and a method of manufacturing the same, which effectively avoids the problems caused by the semiconductor packaging process. A further object of the present invention is to provide a multilayer circuit board integrating electronic components and a method of manufacturing the same , 俾 effectively increase the board space utilization for carrying active components and passive components.

17707 全懋.ptd 第10頁 1286456 五、發明說明（4) 本發明之又另一目的係提供一種整合電子元件之多層電路板及其製法，俾得形成一整合有複數個主、被動元件之半導體裝置之多晶片模組（Multi chip module, MCM)，藉以延伸線路佈局空間，進而符合現今電子產品之多功能、高電性及高速運作之發展。為達上揭及其它目的，本發明之整合電子元件之多層電路板製法，主要係包括下列步驟：提供一内層電路板，該内層電路板至少一表面形成有圖案化線路結構與金屬墊 ;將表面具有電性連接端之電子元件透過一膠黏劑接置於該金屬墊上；於該接置有電子元件之内層電路板上形成增層線路結構，並使該增層線路結構得以電性導接至該電子元件之電性連接端，藉以形成一整合電子元件之基層電路板；以及於該整合電子元件之基層電路板上壓合至少一具電子元件之堆疊線路單元。其中，該具電子元件之堆疊線路單元之製程係包括：提供一側具有金屬層之絕緣板；於該絕緣板未具有金屬層之一側形成複數開口，藉以顯露出該絕緣板另一側之金屬層；於該絕緣板開孔中形成有金屬凸塊；於該絕緣板具金屬凸塊之一側形成一膠黏層；圖案化該絕緣板之金屬層以形成有圖案化線路結構與金屬墊，俾提供電子元件透過一膠黏劑接置於該金屬墊上；以及於該安置有電子元件之線路結構上形成一增層線路結構，並使該增層線路結構得以電性導接至該電子元件，藉此形成整合有電子元件之堆疊線路單元，俾供後續得以將該堆疊線路單元以其具膠黏層之一側壓合至該整合有電子元件之17707 全懋.ptd Page 10 1286456 V. Inventive Description (4) Still another object of the present invention is to provide a multilayer circuit board incorporating electronic components and a method of manufacturing the same, which form an integrated plurality of active and passive components. The multi-chip module (MCM) of the semiconductor device is used to extend the layout space of the circuit, thereby conforming to the development of the versatility, high-power and high-speed operation of today's electronic products. For the purpose of achieving the above and other objects, the method for manufacturing a multi-layer circuit board for integrating electronic components of the present invention mainly comprises the steps of: providing an inner layer circuit board having at least one surface formed with a patterned circuit structure and a metal pad; An electronic component having an electrical connection end is disposed on the metal pad through an adhesive; a build-up line structure is formed on the inner circuit board on which the electronic component is connected, and the build-up line structure is electrically conductive Connecting to the electrical connection end of the electronic component, thereby forming a base circuit board of the integrated electronic component; and pressing the stacked circuit unit of the at least one electronic component on the base circuit board of the integrated electronic component. The process of the stacked circuit unit with an electronic component includes: providing an insulating plate having a metal layer on one side; forming a plurality of openings on a side of the insulating plate not having a metal layer, thereby exposing the other side of the insulating plate a metal layer; a metal bump is formed in the opening of the insulating plate; an adhesive layer is formed on one side of the insulating plate with the metal bump; and the metal layer of the insulating plate is patterned to form a patterned circuit structure and metal a pad, the electronic component is placed on the metal pad through an adhesive; and a build-up line structure is formed on the circuit structure on which the electronic component is disposed, and the build-up line structure is electrically connected to the An electronic component, thereby forming a stacked wiring unit integrated with the electronic component, for subsequent bonding of the stacked wiring unit to one side of the adhesive layer to the integrated electronic component

17707 全懋.ptd 第11頁 1286456 五、發明說明（5) 基層電路板上。當然，亦可持續在該基層電路板上壓合複數堆疊線路單元，並使該堆疊線路單元之膠黏層側之金屬凸塊得以電性導接至另一堆疊線路單元相對應之增層線路結構」，俾形成一整合電子元件之多層電路板。- 經由上述製程，本發明之整合電子元件之多層電路板，主要係包括一基層電路板，以及至少一壓合於該基層電路板上之堆疊線路單元。該基層電路板包括一内層電路板，該内層電路板至少一表面形成有圖案化線路結構與金屬墊；至少一具電性連接端之電子元件，係透過膠黏劑以接置於該金屬墊上；以及至少一增層線路結構，係形成於該内層電路板上，並得以電性導接至該電子元件之電性連接端。該堆疊線路單元係包括一絕緣板，該絕緣板之一表面形成有圖案化線路結構與金屬墊，另一表面形面形成膠黏層，且該絕緣板中形成有金屬凸塊以電性連接至該圖案化線路結構；至少一電子元件，係接置於該金屬墊上；以及至少一增層線路結構，係形成於該接置有電子元件之圖案化線路結構上，並使該增層線路結構得以電性連接至該電子元件。其中，該堆疊線路單元與基層電路板之電性導接，係可藉由將該堆疊線路單元之膠黏層壓合至該基層電路板之增層線路結構上，並使該膠黏層側之金屬凸塊得以電性導接至其相對應之增層線路結構。再者，於該多層電路板表面之線路結構上復可形成有圖案化絕緣層，並透過表面黏著方式（SMT)以提供複數之被動元件接置於該絕緣層上並得以電性導接至該增層線路結構，藉以進一步提供17707 Full 懋.ptd Page 11 1286456 V. Description of invention (5) Basic circuit board. Of course, the plurality of stacked line units can be continuously pressed on the base layer circuit board, and the metal bumps on the adhesive layer side of the stacked line unit can be electrically connected to the corresponding layered line of another stacked line unit. Structure", which forms a multilayer circuit board with integrated electronic components. - Through the above process, the multi-layer circuit board of the integrated electronic component of the present invention mainly comprises a base circuit board and at least one stacked circuit unit press-bonded to the base circuit board. The base layer circuit board includes an inner circuit board, at least one surface of which is formed with a patterned circuit structure and a metal pad; at least one electronic component having an electrical connection end is adhered to the metal pad through an adhesive And at least one build-up line structure formed on the inner circuit board and electrically connected to the electrical connection end of the electronic component. The stacked circuit unit comprises an insulating plate, one surface of the insulating plate is formed with a patterned circuit structure and a metal pad, and the other surface forming an adhesive layer, and the metal plate is formed in the insulating plate to be electrically connected To the patterned circuit structure; at least one electronic component is attached to the metal pad; and at least one build-up circuit structure is formed on the patterned circuit structure on which the electronic component is connected, and the build-up circuit is The structure is electrically connected to the electronic component. The electrical connection between the stacked circuit unit and the base circuit board can be performed by adhesively laminating the stacked circuit unit to the build-up line structure of the base circuit board, and the adhesive layer side is The metal bumps are electrically connected to their corresponding build-up line structures. Furthermore, a patterned insulating layer is formed on the circuit structure on the surface of the multilayer circuit board, and a plurality of passive components are provided through the surface adhesion mode (SMT) to be connected to the insulating layer and electrically connected to The layered circuit structure is further provided

17707 全懋.ptd 第12頁 1286456 五、發明說明（6) 電子產品較佳之電性功能。因此，本發明之整合電子元件之多層電路板及其製法，主要係在線路結構中形成有至少一金屬墊，俾得以提供至少，一例如半導體晶片之主動元件甚或晶片型被動元件透過一例如銀膠之膠黏劑接置於該金屬墊上，之後，再於該接置有主動元件甚或被動元件之線路結構上，持續壓合有複數包括金屬墊之線路結構，藉以形成一整合有多數電子元件之具多層線路層之電路板結構，而符合現今電子產品之多功能、高電性及高速運作之發展。亦即，本發明係可在電路板中整合有例如半導體晶片之主動元件甚或例如電阻、電容、或電感之晶片型被動元件，藉以提昇電子產品之電性功能，同時本發明亦可整合晶片承載件之製造與半導體封裝技術之製程，以提供客戶端較大需求彈性，並得以簡化半導體業者製程步驟、成本及界面整合等問題。【實施方式】以下係藉由特定的具體實施例說明本發明之實施方式，熟習此技藝之人士可由本說明書所揭示之内容輕易地瞭解本發明之其他優點與功效。本發明亦可藉由其他不同的具體實施例加以施行或應用，本說明書中的各項細節亦可基於不同觀點與應用，在不悖離本發明之精神下進行各種修飾與變更。請參閱第1 A至第1 F圖，係為本發明之整合電子元件之多層電路板製法中形成基層電路板之剖面示意圖。如第1 A及1 B圖所示，首先，提供一内層電路板1 1，該17707 懋.ptd Page 12 1286456 V. Description of the invention (6) Electronic functions of electronic products. Therefore, the multi-layer circuit board of the integrated electronic component of the present invention and the method of manufacturing the same are mainly characterized in that at least one metal pad is formed in the circuit structure, and at least one active component such as a semiconductor wafer or even a chip passive component is transmitted through, for example, silver. The adhesive of the glue is placed on the metal pad, and then the circuit structure including the active component or the passive component is continuously pressed, and a plurality of circuit structures including the metal pad are continuously pressed to form an integrated electronic component. It has a multi-layer circuit board structure, which is in line with the development of multi-function, high-power and high-speed operation of today's electronic products. That is, the present invention can integrate an active component such as a semiconductor wafer or even a chip-type passive component such as a resistor, a capacitor, or an inductor in a circuit board, thereby improving the electrical function of the electronic product, and the present invention can also integrate the wafer carrier. Manufacturing and semiconductor packaging technology processes to provide greater flexibility for the client's needs, and to simplify semiconductor process steps, cost and interface integration issues. [Embodiment] The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can readily understand other advantages and functions of the present invention from the disclosure of the present disclosure. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes may be made without departing from the spirit and scope of the invention. Referring to Figures 1A through 1F, there is shown a cross-sectional view of a substrate circuit board formed in a multilayer circuit board manufacturing method for integrated electronic components of the present invention. As shown in Figures 1A and 1B, first, an inner layer circuit board 1 1 is provided.

17707 全懋.ptd 第13頁 1286456 五、發明說明（7) 内層電路板11係可藉由提供一表面形成有金屬層1 〇 1之芯層板1 0，利用線路圖案化製程以在該芯層板1 0之表面金屬層1 0 1中形成有圖案化線路結構1 2與至少一金屬墊1 3，並於該芯層板1 0中形成有複數導電通孔H以供該芯層板1〇表面之圖案化線路結構1 2得以相互電性導接。其中，該芯層板1 0亦可為一完成前段製程之多層電路板。於本實施例之圖式中，該芯層板1 0係由一絶緣層及形成於該絕緣層表面之金屬層所構成，該絕緣層可為環氧樹脂（Ε ρ ο X y r e s i η )、聚乙醯胺（Polyimide)、氰酯（Cyanate Ester)、破璃纖維、雙順丁烯二酸醯亞胺/三氮阱（Bismaleimide Tri az i ne，BT)或混合環氧樹脂與玻璃纖維之FR5材質所製成，該金屬層一般係以導電性較佳之銅（C u)為主，以作為乱號傳遞的導線材料’且該金屬層可先壓合或沉積於該、、巴緣層上’或使用樹脂壓合銅( r e s i n c 〇 a t e d c 〇 p p e r， RCC)予以製作，由於為有效提供後續電鑛金屬層之密著性’較佳之具體實施例係於該金屬層沉積以前，須預先將絕緣層表面施以粗面化，同時，本實施例採用一樹脂壓合鋼洎（RCC)為例進行說明。另本圖式中該内層電路板1 1 之導電通孔1 4係以電性導通孔（PTH)作為說明，然其亦可為例如導電盲孔等層間導電結構。而由於該内層電路板 1 1之圖案化線路製程係為半導體業界熟知之製程，亦非本案技術特徵所在，故於此不在贅述。如第1 C及1 D圖所示，然後於該内層電路板11之金屬墊 1 3上塗佈例如銀膠之膠黏劑1 5，俾供至少一電子元件丨6得17707 懋.ptd Page 13 1286456 V. Description of the Invention (7) The inner layer circuit board 11 can be formed by a line patterning process by providing a core layer 10 having a metal layer 1 〇1 on the surface. A patterned wiring structure 12 and at least one metal pad 13 are formed in the surface metal layer 110 of the layer 10, and a plurality of conductive vias H are formed in the core layer 10 for the core layer The patterned circuit structure 12 of the 1〇 surface is electrically connected to each other. The core board 10 can also be a multi-layer circuit board that completes the front-end process. In the embodiment of the present embodiment, the core layer 10 is composed of an insulating layer and a metal layer formed on the surface of the insulating layer, and the insulating layer may be an epoxy resin (Ε ρ ο X yresi η ). Polyimide, Cyanate Ester, glass fiber, Bismaleimide Tri az i ne (BT) or mixed epoxy resin and glass fiber Made of FR5 material, the metal layer is generally made of copper (C u) with better conductivity, which is used as a wire material transmitted by the chaotic number, and the metal layer can be pressed or deposited on the edge layer. Made 'on or with resin 〇 c c per per per R R R R , , , , , , , , , , , , ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' The surface of the insulating layer is roughened. At the same time, a resin laminated steel crucible (RCC) is used as an example for description. In the figure, the conductive vias 14 of the inner layer circuit board 1 are electrically conductive vias (PTH). Alternatively, they may be interlayer conductive structures such as conductive vias. Since the patterned circuit process of the inner circuit board 1 is a well-known process in the semiconductor industry, it is not a technical feature of the present invention, so it will not be described here. As shown in FIGS. 1C and 1D, an adhesive such as silver paste 15 is applied to the metal pad 13 of the inner circuit board 11 to supply at least one electronic component 丨6.

17707全戀.ptd 第14頁 1286456 五、發明說明（8) — -- 以透過該金屬墊1 3與膠黏劑丨5而有效接置於該内層電路板 11上，其中，#電子it件16之上表面具有複數個電性連接端160,並以其下表面接置於該内層電路板n之金屬墊13 上，.且該電子元件1 6可例如半導體晶片之主動元件甚或晶片型被動元件。即如第2圖所示，係為該内層電路板以之金屬塾1 3上透過一膠黏劑1 5以接置有電子元件1 6之部分示意圖。如第1 E及1 F圖所示，接著在該接置有電子元件丨6之内層電路板1 1上形成一絕緣層1 7 〇或一覆有金屬層之絕緣層 (未圖不）’然後利用例如雷射鑽孔等技術以在該絕緣層 1 7 〇 (亦或覆有金屬層之絕緣層）中鑽設有複數盲孔1 7 i，藉以顯露出該内層電路板1 1之部分圖案化線路結構丨2與該電子元件1 6之電性連接端1 6 〇，當然，該絕緣層1 7 〇亦可為光顯性材質形式，並可藉由顯影技術形成複數開孔，藉以顯露出該電子元件1 6之電性連接端1 6 〇 ;其後利用增層技術以在該絕緣層1 7 0上形成線路層1 7 2與導電盲孔1 7 3，以形成一線路結構1 7 a，並使該線路層1 7 2可透過複數貫穿該系巴緣層1 7 0之導電盲孔1 7 3以電性導接至該電子元件1 6之電性連接端1 6 0以及該内層電路板丨丨之圖案化線路結構1 2，以形成整合電子元件丨6之基層電路板Ua。其中，本實施例之圖不’雖僅在該内層電路板丨丨具電子元件丨6之一側形成有增層線路結構，但非以此為限，亦可在内層電路板i i 另一側形成有增層線路結構。另外’該線路增層製程主要係先在該絕緣層1 7 0 (或17707全恋.ptd Page 14 1286456 V. Invention Description (8) — -- Effectively attached to the inner circuit board 11 through the metal pad 13 and the adhesive 丨 5, wherein #电子特件The upper surface of the 16 has a plurality of electrical connecting ends 160, and the lower surface thereof is attached to the metal pad 13 of the inner layer circuit board n. The electronic component 16 can be, for example, an active component of a semiconductor wafer or even a passive chip type. element. That is, as shown in Fig. 2, it is a schematic view of the inner layer board on which the metal element 13 is passed through an adhesive 15 to which the electronic component 16 is attached. As shown in FIGS. 1E and 1F, an insulating layer 17 or an insulating layer covered with a metal layer (not shown) is formed on the inner circuit board 1 1 on which the electronic component 丨6 is attached. Then, using a technique such as laser drilling, a plurality of blind vias 1 7 i are drilled in the insulating layer 17 (or an insulating layer covered with a metal layer) to expose portions of the inner circuit board 1 1 . The patterned circuit structure 丨2 and the electrical connection end of the electronic component 16 are 16 〇. Of course, the insulating layer 17 〇 can also be in the form of a light-sensitive material, and a plurality of openings can be formed by a developing technique. The electrical connection end 16 6 of the electronic component 16 is exposed; thereafter, a build-up technique is used to form a wiring layer 172 and a conductive blind via 173 on the insulating layer 170 to form a line structure. 1 7 a, and the circuit layer 172 can be electrically connected to the electrical connection terminal 1 6 0 of the electronic component 16 through a plurality of conductive blind holes 173 through the barrier layer 170 And the patterned circuit structure 12 of the inner circuit board 以 to form the base circuit board Ua of the integrated electronic component 丨6. The figure of this embodiment does not form a build-up line structure only on one side of the inner circuit board cookware electronic device ,6, but not limited thereto, and may also be on the other side of the inner layer circuit board ii. A build-up line structure is formed. In addition, the line build-up process is mainly in the insulation layer 170 (or

I、發明說〜-- 圖示層之絕，f)及盲孔171表面形成導電金屬層（未進行電^制t該導電金屬層上形成一圖案化電鍵阻層’復 17 3，之二^程以形成有圖案化線路層172與複數導電盲孔以完成如唆再移除該-電錢阻層及其所覆蓋之金孱層部分’ 在覆有八L 1 E圖所示之線路結構1 7 a之製程。當然’亦可 (未圖S) 3之層及盲孔171表面形成有導電金屬層錄金屬^^進行電錢製程’以在該導電金屬層上形成電移除夫I»彳又於该電錢金屬層上形成圖案化蝕刻阻層，以随層，同 ^復盘之金屬層部分’其後再移除該#刻導電盲孔iV、可-形、成如第1 ?圖所示之圖案化線路層172與本發明> ,3° $述該線路增層製程係為習用技術，並非限制本於，術，ί所在，且僅係用以例示說明，而非用以可力a r, I明之可實施範鳴’其餘任何等效線路增層製程皆刀口从應用於本發明十。件=時請參閱第3A至第3 ;圖，係為本發明之整合電子元夕層電路板製法中形成於基層電路板上堆疊線路單元 < 4面示意圖。I, the invention says ~-- the picture layer is absolutely, f) and the surface of the blind hole 171 is formed with a conductive metal layer (not formed by electro-electricity, a patterned electro-bonding layer is formed on the conductive metal layer). The process is performed to form a patterned circuit layer 172 and a plurality of conductive blind vias to complete the removal of the --electric barrier layer and the portion of the metal layer covered by it, in the line covered by the eight L 1 E diagram. Structure 1 7 a process. Of course 'can also (not shown S) 3 layers and blind holes 171 surface formed with a conductive metal layer recording metal ^ ^ to carry out the electricity process 'to form an electrical removal on the conductive metal layer I»彳 forms a patterned etch stop layer on the metal layer of the electric money, so as to follow the layer, the metal layer portion of the same type of disk, and then remove the #-conductive conductive hole iV, can be shaped, formed into The patterned circuit layer 172 shown in FIG. 1 is in accordance with the present invention, and the circuit-adding process is a conventional technique, and is not limited to the present invention, and is merely for illustration. Rather than using force ar, I can implement Fan Ming's any other equivalent line build-up process from the application of the blade to the present invention. 3A through 3; FIG., Department of the present invention to integrate an electronic element Xi-layer board manufacturing method in the base layer is formed on the circuit board are stacked in line unit < 4 schematic side.

在形成如第1 F圖所示之整合電子元件丨6之基層電路板 a ’後續復得以在該基層電路板u a上壓合有至少一整合有電子元件之堆疊線路單元，藉以形成一整合有電子元件之多層電路板。該基層電路板113主要係包括有一内層電路板11，該内層電路板11至少一表面形成有圖案化線路結構12與金屬墊13;至少一具電性連接端16〇之電子元件16 ，係透過膠黏劑1 5以接置於該金屬墊丨3上；至少一辦層The base circuit board a' forming the integrated electronic component 丨6 as shown in FIG. 1F is subsequently laminated on the base circuit board ua with at least one stacked circuit unit integrated with electronic components, thereby forming an integrated Multi-layer circuit board for electronic components. The base layer circuit board 113 mainly includes an inner circuit board 11 having at least one surface formed with a patterned circuit structure 12 and a metal pad 13; at least one electronic component 16 having an electrical connection end 16 is transmitted through Adhesive 15 is attached to the metal pad 3; at least one layer

17707 全懋.ptd17707 full 懋.ptd

1286456 五、發明說明（ίο) 路結構1 7 a，係形成於該内層電路板1 1上，並得以電性導接至該電子元件1 6之電性連接端1 6 0。而該堆疊線路單元與多層電路板之製程係如下所述。如第3 A圖所示，提供一絕緣板2 1，該絕緣板2 1之一側具有可例如銅層之金屬層2 2。如第3 B圖所示，於該絕緣板2 1未具有金屬層2 2之一側形成複數開口 2 1 0，藉以顯露出該絕緣板2 1另一側之金屬層2 2。如第3 C圖所示，於該絕緣板開口 2 1 0中形成有金屬凸塊2 3，該金屬凸塊2 3可利用例如電鍍等方式可先形成有一金屬銅層231後，再形成有一銲錫層232。如第3 D圖所示，於該絕緣板具金屬凸塊2 3之一側形成一膠黏層2 4。如第3 E圖所示，圖案化該絕緣板之金屬層2 2以形成有圖案化線路結構2 2 1與金屬墊2 2 2，俾提供表面形成有電性連接端2 5 0之電子元件2 5透過一膠黏劑2 6接置於該金屬墊 2 22上（如第3F圖所示）。如第3G圖所示，於該安置有電子元件2 5之線路結構上形成一增層線路結構2 8 a。其係可透過形成一絕緣層2 7或一覆有金屬層之絕緣層（未圖示），然後利用例如雷射鑽孔等技術以在該絕緣層2 7 (亦或覆有金屬層之絕緣層）中鑽設有複數盲孔2 7 0，藉以顯露出部分圖案化線路結構2 2 1 與該電子元件2 5之電性連接端2 5 0，當然，該絕緣層1 7 0亦可為光顯性材質形式，並可藉由顯影技術形成複數開孔，1286456 V. DESCRIPTION OF THE INVENTION (L) The circuit structure 17a is formed on the inner circuit board 1 1 and electrically connected to the electrical connection end 160 of the electronic component 16. The process of the stacked wiring unit and the multilayer circuit board is as follows. As shown in Fig. 3A, an insulating plate 2 1 is provided, and one side of the insulating plate 21 has a metal layer 2 2 which can be, for example, a copper layer. As shown in Fig. 3B, a plurality of openings 2 1 0 are formed on one side of the insulating plate 21 without the metal layer 2 2, thereby exposing the metal layer 2 2 on the other side of the insulating plate 2 1 . As shown in FIG. 3C, metal bumps 2 3 are formed in the insulating plate opening 210, and the metal bumps 2 can be formed by first forming a metal copper layer 231 by, for example, electroplating. Solder layer 232. As shown in Fig. 3D, an adhesive layer 24 is formed on one side of the insulating plate with metal bumps 2 3 . As shown in FIG. 3E, the metal layer 2 2 of the insulating plate is patterned to form a patterned wiring structure 2 2 1 and a metal pad 2 2 2, and the electronic component having the surface formed with the electrical connection end 250 is provided. 2 5 is placed on the metal pad 22 by an adhesive 2 6 (as shown in Fig. 3F). As shown in Fig. 3G, a build-up line structure 28 8a is formed on the line structure in which the electronic component 25 is placed. It can be formed by forming an insulating layer 27 or an insulating layer (not shown) covered with a metal layer, and then using a technique such as laser drilling to insulate the insulating layer 27 (or with a metal layer). a plurality of blind holes 270 are formed in the middle of the layer, thereby exposing a portion of the patterned circuit structure 2 2 1 and the electrical connection end 2 5 0 of the electronic component 25, of course, the insulating layer 170 can also be In the form of a light-sensitive material, a plurality of openings can be formed by a developing technique.

17707 全懋.ptd 第17頁 1286456 發明說明（11) 藉以顯露出該電子元件1 6之電性連接端i 6 〇 · 俾使該線路層2 8可透過複數貫穿該絕緣層2 厂tL 2 8 〇， 2 8 0以電性·導接至該電子元件2 5之·電性連曰接/導電盲孔案化線路結構221，藉此形成整合有電子元=25〇以及該單元2 0 (如篦η Ηϋΐ斛杀、，备处士人也一牛之堆4 Α ^圏層技術以在該絕緣層2 7上形成線路層2 8與導♦其^後利用増俾使該線路層28可透過複數貫穿該絕緣芦' 免盲孔28〇f 線略，元20(如第3H圖所示），當然於實際應用干之▲堆疊姜單元2 0之增層線路結構並非僅侷限於單—展時叇堆叠如第3 I圖所示，之後即可將至少一=。 24之一側壓合至該基層電c單冗線路早兀20之金屬凸塊23得以電性導接 a，並使該應之增層線路結構17a，俾形成—敕Ϊ基層電路柄 m板。當然亦得持續在該基層電路。t子元件j 稷數隹豎線路單元20，以使—堆疊線路 1 U上壓合之 T層24之-側接合至另一堆疊線路單元：2〇得以其Q夏有 a之—側，並使該膠黏層24—側之金屬几、増層線略^膠至相對應之增層線路結構2 8 a。 *鬼2 3電性、、.、、、°構如第3 J圖所示，後續可於該導接緣層29 ’俾使該絕緣層29形成^ ^形成有圖娈線路結構2 8 a之電性連接端部分複數開口以外露出二=絕面利用表面黏著技術接置有；遠電路板之9層件或電感元件之被動元件3。，；進!^、電容表元電性功能。 “，提供電子裝置較：復請參閱第3丨圖所示，經電子元件之多層電路板，主二=，本發明之整合匕括基層電路板lla，以17707 全懋.ptd Page 17 1286456 DESCRIPTION OF THE INVENTION (11) By showing the electrical connection end of the electronic component 16 6 〇 · 俾该该线路该线路线路线路该该该该该该该该该该该该该该该该该该该该该该该〇, 280 is electrically connected to the electronic component 2 5 electrically connected/conductive blind via circuit structure 221, thereby forming an integrated electronic element = 25 〇 and the unit 20 ( For example, 篦η Ηϋΐ斛 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Through the plural through the insulated reed 'free blind hole 28〇f line slightly, element 20 (as shown in Figure 3H), of course, in the practical application of dry ▲ stacked ginger unit 20 0 layered line structure is not limited to single - The stacking time of the stack is as shown in FIG. 3I, and then at least one of the sides of the 24 can be electrically connected to the metal bumps of the base layer. The layered circuit structure 17a is formed, and the base layer is formed into a circuit board of the base layer circuit. Of course, it must continue in the base layer circuit. t sub-element j 稷 number vertical line The unit 20 is configured to join the side of the T layer 24 which is press-bonded on the stacking line 1 U to another stacking line unit: 2 〇 has its Q-sum side a side, and the adhesive layer 24 side The metal and bismuth lines are slightly glued to the corresponding build-up line structure 2 8 a. * Ghost 2 3 electrical, , , , , and ° are as shown in Figure 3 J, and the subsequent connection can be made The layer 29' is formed such that the insulating layer 29 is formed with a pattern of the wiring structure. The electrical connection end portion of the terminal is formed by a plurality of openings. The second surface is formed by surface adhesion technology; the 9-layer member of the remote circuit board is formed. Or the passive component of the inductive component 3,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, The integration of the present invention includes the base layer circuit board 11a to

1286456 五、發明說明（12) 及至少一壓合於該基層電路板11 a上之堆疊線路單元2 〇。 ϋ亥基層電路板11 a包括一内層電路板11，該内層電路板η 至少一表面形成有圖案化線路結構1 2與金屬塾！ 3 ;至少一具尾性連接.端、1 β 〇之電子元件1 6，係透過膠黏劑1 5以接置於該金屬急1 3上；以及至少一增層線路結構丨7a，係形成於該内層電路板1 1上，並得以電性導接至該電子元件25之電性連接端2 5 0。該堆疊線路單元2 0係包括一絕緣板2卜 5亥絕緣板2 1之一表面形成有圖案化線路結構2 2 1與金屬塾 2 2 2 ’另一表面形面形成膠黏層2 4，且該絕緣板2 1中形成有金屬凸塊2 3以電性連接至該圖案化線路結構；至少一電子元件2 5，係接置於該金屬墊2 2 2上；以及至少一增層線路結構28a，係形成於該接置有電子元件25之圖案化線路結構2 2 1上，並使該增層線路結構2 8a得以電性連接至該電子元件2 5。其中，該堆疊線路單元2 0與基層電路板1 1 a之電性導接，係可藉由將該堆疊線路單元2 0之膠黏層2 4壓合至該基層電路板11 a之增層線路結構1 7 a上，以使該堆疊線路單元2 0之金屬凸塊2 3得以電性導接至其相對應之基層電路板1 1 a之增層線路結構1 7 a。因此，本發明之整合電子元件之多層電路板及其製法 ’主要係在線路結構十形成有至少一金屬塾，俾得以提供至少一例如半導體晶片之主動元件甚或晶片型被動元件透過一例如銀膠之膠黏劑接置於該金屬墊上，之後，再於該接置有主動元件甚或被動元件之線路結構上，增層或壓合有複數包括有金屬墊之線路結構，並持續在該線路結構之1286456 V. Inventive Description (12) and at least one stacked wiring unit 2 压 press-fitted to the base circuit board 11a. The base layer circuit board 11a includes an inner circuit board 11, and at least one surface of the inner circuit board n is formed with a patterned circuit structure 12 and a metal 塾! 3; at least one tail connection, the end, 1 β 〇 electronic component 16 is attached to the metal emergency 13 through the adhesive 15; and at least one build-up line structure 丨7a, is formed The inner circuit board 11 is electrically connected to the electrical connection end 250 of the electronic component 25. The stacked circuit unit 20 includes an insulating plate 2, and a surface of the insulating plate 2 is formed with a patterned circuit structure 2 2 1 and a metal 塾 2 2 2 'the other surface forming surface forms an adhesive layer 24, And the metal plate 2 is formed in the insulating plate 21 to be electrically connected to the patterned circuit structure; at least one electronic component 25 is electrically connected to the metal pad 22; and at least one build-up circuit The structure 28a is formed on the patterned circuit structure 2 2 1 with the electronic component 25 disposed thereon, and the build-up wiring structure 28 8a is electrically connected to the electronic component 25 . The electrical connection between the stacked circuit unit 20 and the base circuit board 11a can be performed by bonding the adhesive layer 24 of the stacked circuit unit 20 to the layer of the base circuit board 11a. The wiring structure 17a is such that the metal bumps 2 of the stacked wiring unit 20 are electrically connected to the corresponding layered circuit structure 1 7 a of the corresponding base circuit board 1 1 a. Therefore, the multi-layer circuit board of the integrated electronic component of the present invention and the method of manufacturing the same are mainly characterized in that at least one metal germanium is formed in the wiring structure, and at least one active component such as a semiconductor wafer or even a passive passive component is transmitted through a silver paste, for example. The adhesive is placed on the metal pad, and then the circuit structure including the active component or the passive component is layered or laminated with a plurality of circuit structures including metal pads, and continues in the circuit structure. It

17707 全懋.ptd 第19頁 1286456 五、發明說明（13) 金屬墊上接置電子元件，藉以形成一整合有多數電子元件之具多層線路層之電路板結構，而符合現今電子產品之多功能、高電性及高速運作之發展。亦即，本發明係可在電路板中整合有例如半導體晶片之·主動元件甚或例如電阻、電容、或電感之晶片，型被動元件，藉以提昇電子產品之電性功能，同時本發明亦可整合晶片承載件之製造與半導體封裝技術之製程，以提供客戶端較大需求彈性，並得以簡化半導體業者製程步驟、成本及界面整合等問題。以上所述僅為本發明之較佳實施例而已，並非用以限定本發明之實質技術内容範圍，本發明之實質技術内容係廣義地定義於下述之申請專利範圍中，任何他人完成之技術實體或方法，若是與下述之申請專利範圍所定義者係完全相同，亦或為同一等效變更，均將被視為涵蓋於此申請專利範圍中。17707 懋.ptd Page 19 1286456 V. Description of the invention (13) The electronic component is connected to the metal pad to form a circuit board structure with a plurality of circuit layers integrated with most electronic components, which is in line with the versatility of today's electronic products. The development of high power and high speed operation. That is, the present invention can integrate, for example, an active component of a semiconductor wafer or even a chip such as a resistor, a capacitor, or an inductor, or a passive component, in the circuit board, thereby improving the electrical function of the electronic product, and the present invention can also be integrated. The fabrication of wafer carriers and the process of semiconductor packaging technology to provide greater flexibility for the client, and to simplify semiconductor process steps, cost and interface integration issues. The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the technical scope of the present invention. The technical content of the present invention is broadly defined in the following patent application, any other technology completed by others. Entities or methods that are identical or equivalent to those defined in the claims below are considered to be covered by the scope of this application.

17707 全懋.ptd 第20頁 1286456 圖式簡單說明【圖式簡單說明】第1 A至第1 F圖，係為本發明之整合電子元件之多層電路板製法中形成基層電路板之剖面示意圖。第2圖係在本發明之内層電路板之金屬塾吐接置有電子元件之部分示意圖；以及第3 A至第3 J圖，係為本發明之整合電子元件之多層電路板製法中形成於基層電路板上堆疊線路單元之剖面示意圖。 (元件符號說明） 10 芯層板 100 電路板 101 金屬層 11 内層電路板 11a 基層電路板 12 圖案化線路結構 13 金屬墊 14 導電通孔 15 膠黏劑 16 電子元件 160 電性連接端 17a 增層線路結構 170 絕緣層 171 盲孔 172 線路層 173 導電盲孔 20 堆疊線路 XJ0 一早兀 21 絕緣板 210 開口 22 金屬層 221 線路結構 222 金屬墊 23 金屬凸塊 231 金屬銅層 232 銲錫層 24 膠黏層 25 電子元件 250 電性連接端 26 膠黏劑 27 絕緣層17707 全懋.ptd Page 20 1286456 Brief Description of the Drawings [Simplified Schematic] The first to the fifteenth F are schematic cross-sectional views showing the formation of a base circuit board in the method of manufacturing a multi-layer circuit board incorporating integrated electronic components of the present invention. 2 is a schematic view showing a portion of a metal circuit board in which an inner layer of the present invention is mounted with electronic components; and FIGS. 3A to 3J are formed in the method of manufacturing a multilayer circuit board of the integrated electronic component of the present invention. A schematic cross-sectional view of a stacked circuit unit on a base layer circuit board. (Component symbol description) 10 core board 100 circuit board 101 metal layer 11 inner layer circuit board 11a base layer circuit board 12 patterned circuit structure 13 metal pad 14 conductive via 15 adhesive 16 electronic component 160 electrical connection end 17a buildup Line structure 170 Insulation 171 Blind hole 172 Line layer 173 Conductive blind hole 20 Stack line XJ0 Early 兀 21 Insulation board 210 Opening 22 Metal layer 221 Line structure 222 Metal pad 23 Metal bump 231 Metal copper layer 232 Solder layer 24 Adhesive layer 25 Electronic components 250 Electrical connection 26 Adhesive 27 Insulation

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17707 全想.ptd 第22頁17707 全想.ptd第22页

Claims

Ι2864ί客年^炉曰修⑽正替換頁 _Ί 莹骑年孓月 > 曰修正_ 六、申請專利範圍 1 . 一種整合電子元件之多層電路板製法，係包括：提供一内層電路板，該内層電路板至少一表面形成有圖案化線路結構與金屬墊；將表面具有電性連接端之電子元件於其未具有電性連接墊之表面透過一膠黏劑接置於該金屬墊上；於該接置有電子元件之内層電路板上形成增層線路結構，並使該增層線路結構得以電性導接至該電子元件之電性連接端，藉以形成一整合電子元件之基層電路板；提供一具電子元件之堆疊線路單元，其係具有一絕緣板，該絕緣板之一表面形成有圖案化線路結構與金屬墊，另一表面形面形成一膠黏層，且該絕緣板中形成有複數金屬凸塊電性連接至該圖案化線路結構；以及疊置該堆疊線路單元於該基層電路板上，並將該膠黏層之一側壓合至該基層電路板上，俾使該金屬凸塊電性導接至該基層電路板上相對應之增層線路結構。 2.如申請專利範圍第1項之整合電子元件之多層電路板製法，其中，該具電子元件之堆疊線路單元之製程係包括：提供一絕緣板，該絕緣板之一侧具有金屬層；於該絕緣板未具有金屬層之一側形成複數開口’ 藉以顯露出該絕緣板另一側之金屬層；Ι2864ί客年^炉曰修(10)正换页_Ί 莹骑年孓月> 曰修正_6. Patent application scope 1. A multi-layer circuit board method for integrating electronic components, comprising: providing an inner circuit board, The at least one surface of the inner circuit board is formed with a patterned circuit structure and a metal pad; the electronic component having the electrical connection end on the surface is placed on the metal pad through an adhesive on the surface thereof without the electrical connection pad; Forming a build-up line structure on the inner circuit board on which the electronic component is connected, and electrically connecting the build-up line structure to the electrical connection end of the electronic component, thereby forming a base circuit board of the integrated electronic component; a stacked circuit unit of an electronic component having an insulating plate, a surface of one of the insulating plates is formed with a patterned circuit structure and a metal pad, and another surface forming an adhesive layer, and the insulating plate is formed with Multiple metal bumps are electrically connected to the patterned circuit structure; and the stacked circuit unit is stacked on the base circuit board, and one side of the adhesive layer is pressed And bonding to the base circuit board, the metal bumps are electrically connected to the corresponding build-up line structure on the base circuit board. 2. The method of manufacturing a multi-layer circuit board for integrating electronic components according to claim 1, wherein the process of the stacked circuit unit with the electronic component comprises: providing an insulating plate having a metal layer on one side thereof; The insulating plate does not have a metal opening on one side of the metal layer to expose the metal layer on the other side of the insulating plate;

17707修正本.ptc 第23頁 1286456 ㈣，月L日—》士17707 Amendment to this .ptc Page 23 1286456 (D), Month L-Day

六、申請專利範園 ^ φ - . 於該絕緣板開 7成有金屬凸塊；於該絕緣板：：：：：之-側形成一膠黏層；圖案化該：ΪΪ電Ϊ層以形成有圖案化線路社構與金屬* : 、電子疋件透過一膠黏劑接置於二金屬些上·，以及 Z 於該安置有電子元件之線路結構上形成一择路結構，姐使該增層線路結構得以電 ^ ^友 3 元件，藉此f成Ϊ合有電子元件之：疊電子如申請專利範圍弟1或2項之整人雷 _ ' 板製法，復包括持續在該基層;敗70件之多層電路線路單元，並使該堆疊線路單 2上壓合複數堆疊塊得以電性導接至另一堆疊 > 黏層側之金屬凸路結構。且線路早元相對應之增層線 4 ·如申請專利範圍第1項之整合 ― 法，復包括： 70件之多層電路极製在該完成線路製程之電路層；以及仅上覆盖一圖案化絕緣在該形成有圖案化絕緣層面黏著技術接置有複數被動元電路板上表面利用表如申請專利範圍第〗項人。法，其中，該電子元件係為3主電/元件之多層電路板製 6. 如申請專利範圍帛5項之整合電動兀件。法’其中’該主動元件為半 70件之多層電路板製 7. 如申請專利範圍第择人題曰曰片。項之正合電子元件之多層電路板製 mm, 128645私年月乂日修(名正每，，匕 _I—衆號9311.8,7/Ιβ 年5月 > 曰修正_ 六、申請專利範圍法，其中，該電子元件係為晶片型被動元件。 8 .如申請專利範圍第1項之整合電子元件之多層電路板製法，其中，該膠黏劑為銀膠。 9. 一種整合電子元件之多層電路板，係包括：一基層電路板，該基層電路板包括有一内層電路板，該内層電路板至少一表面形成有圖案化線路結構與金屬墊；至少一具電性連接端之電子元件，係透過膠黏劑以接置於該金屬墊上；以及至少一增層線路結構，係形成於該内層電路板上，並得以電性導接至該電子元件之電性連接端；以及至少一壓合於該基層電路板上之堆疊線路單元，該堆疊線路單元包括有一絕緣板，該絕緣板之一表面形成有圖案化線路結構與金屬墊，另一表面形面形成一膠黏層，且該絕緣板中形成有複數金屬凸塊電性連接至該圖案化線路結構；至少一電子元件，係接置於該金屬墊上；以及至少一增層線路結構，係形成於該接置有電子元件之圖案化線路結構上，並使該增層線路結構得以電性連接至該電子元件；其中該堆疊線路單元係以該膠黏層黏結至該基層電路板之增層線路結構上，並藉由該膠黏層側之金屬凸塊電性導接至其相對應之增層線路結構，俾使該堆疊線路單元電性導接該基層電路板。 1 0 .如申請專利範圍第9項之整合電子元件之多層電路板，復包括·Sixth, apply for a patent garden ^ φ - . The insulating plate is opened with 70 metal bumps; an adhesive layer is formed on the side of the insulating plate:::::; the pattern is: the electric layer is formed to form There is a patterned circuit structure and metal*: the electronic components are placed on the two metals through an adhesive, and Z forms a routing structure on the circuit structure in which the electronic components are placed. The layer circuit structure can be used to make the electronic components: the stacking electrons such as the patent application scope 1 or 2 of the whole person mine _ 'plate method, the complex includes continuing at the grassroots; A multi-layer circuit circuit unit of 70 pieces, and the laminated plurality of stacked blocks on the stacking circuit unit 2 are electrically connected to the metal stacking structure of the other stack> adhesive layer side. And the addition line of the line corresponding to the early element 4 · The integration of the first item of the patent application scope - the method includes: 70 pieces of multi-layer circuit is formed in the circuit layer of the completed line process; and only a pattern is covered Insulation is formed by a patterned insulating layer adhesion technique with a plurality of passive element boards on the surface of the surface using a table such as the scope of the patent application. The method, wherein the electronic component is a multi-layer circuit board of 3 main power/components. 6. The integrated electric component is as claimed in claim 5. The method 'in which the active element is a half-layered multi-layer circuit board 7. As claimed in the patent application. The multi-layer circuit board of the electronic component of the item is mm, 128645 is the year of the private year. (Name is every,, 匕 _I - public number 9311.8, 7 / Ι β May] 曰 Amendment _ VI. Patent application scope The method, wherein the electronic component is a chip type passive component. 8. The multilayer circuit board manufacturing method of the integrated electronic component according to claim 1, wherein the adhesive is silver paste. 9. An integrated electronic component The multi-layer circuit board includes: a base circuit board, the base circuit board includes an inner circuit board, the inner circuit board has at least one surface formed with a patterned circuit structure and a metal pad; and at least one electronic component having an electrical connection end, Attached to the metal pad through an adhesive; and at least one build-up line structure formed on the inner circuit board and electrically connected to the electrical connection end of the electronic component; and at least one pressure And a stacked circuit unit on the base circuit board, the stacked circuit unit includes an insulating plate, and one surface of the insulating plate is formed with a patterned circuit structure and a metal pad, and the other surface is shaped An adhesive layer, wherein the plurality of metal bumps are electrically connected to the patterned circuit structure; at least one electronic component is attached to the metal pad; and at least one build-up circuit structure is formed on Connecting the patterned circuit structure of the electronic component and electrically connecting the build-up wiring structure to the electronic component; wherein the stacked circuit unit is bonded to the build-up circuit of the base circuit board by the adhesive layer Structurally, the metal bumps on the adhesive layer side are electrically connected to the corresponding build-up wiring structure, so that the stacked circuit unit is electrically connected to the base circuit board. The multilayer circuit board of the integrated electronic component of the ninth item, including

17707修正本.ptc 第25頁 12861批月2曰修(影正替队i __案號9311游6 9<〇年7月 > 曰_iMi_ 六、申請專利範圍一圖案化絕緣層，係形成在該完成線路增層製程之電路板表面；以及複數被動元件，係利用表面黏著技術以接置在該形成有圖案化絕緣層之電路板上表面。 1 1.如申請專利範圍第9項之整合電子元件之多層電路板，其中，該電子元件係為主動元件。 12.如申請專利範圍第11項之整合電子元件之多層電路板’其中，該主動元件為半導體晶片。 1 3.如申請專利範圍第9項之整合電子元件之多層電路板，其中，該電子元件係為晶片型被動元件。 1 4.如申請專利範圍第9項之整合電子元件之多層電路板，其中，該膠黏劑為銀膠。17707 Amendment to .ptc Page 25 12861 Approved 2曰修(影正队 i __案号9311游6 9<July July> 曰_iMi_ VI. Patent application area 1 patterned insulation layer, Forming a surface of the circuit board on the completed line build-up process; and a plurality of passive components are attached to the surface of the circuit board on which the patterned insulating layer is formed by using a surface adhesion technique. 1 1. As claimed in claim 9 The multi-layer circuit board of the integrated electronic component, wherein the electronic component is an active component. 12. The multi-layer circuit board of the integrated electronic component of claim 11 wherein the active component is a semiconductor wafer. The multi-layer circuit board of the integrated electronic component of the ninth aspect of the patent application, wherein the electronic component is a chip type passive component. 1 4. The multilayer circuit board of the integrated electronic component according to claim 9 of the patent scope, wherein the glue The adhesive is silver glue.

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