TWI246750B - A carrier for stacked chips and a method for fabricating the same and a semiconductor package with the chip carrier - Google Patents
A carrier for stacked chips and a method for fabricating the same and a semiconductor package with the chip carrier Download PDFInfo
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- TWI246750B TWI246750B TW092137574A TW92137574A TWI246750B TW I246750 B TWI246750 B TW I246750B TW 092137574 A TW092137574 A TW 092137574A TW 92137574 A TW92137574 A TW 92137574A TW I246750 B TWI246750 B TW I246750B
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- Prior art keywords
- substrate
- build
- wafer carrier
- opening
- semiconductor package
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 154
- 229910000679 solder Inorganic materials 0.000 claims abstract description 58
- 238000004519 manufacturing process Methods 0.000 claims description 16
- 239000000853 adhesive Substances 0.000 claims description 5
- 230000001070 adhesive effect Effects 0.000 claims description 4
- 239000008393 encapsulating agent Substances 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 230000003292 diminished effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 66
- 235000012431 wafers Nutrition 0.000 description 62
- 238000010586 diagram Methods 0.000 description 5
- 238000000059 patterning Methods 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 239000000084 colloidal system Substances 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229920000297 Rayon Polymers 0.000 description 1
- 239000002313 adhesive film Substances 0.000 description 1
- 239000011324 bead Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000012050 conventional carrier Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical group [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000007731 hot pressing Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000011120 plywood Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Wire Bonding (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
12467501246750
五、發明說明（1) 【發明所屬之技術領域】 一種晶片承載件（chlpcarrler)，尤指一種在 式基板至少一側上疊接一增層基板，以縮減銲球墊間距。 (Finger Pitch)而於相同基板單位面積下設置更多 的輸入/輸出連接端之晶片承載件，及具有該晶片承里 之半導體封裝件。 X + 【先前技術】 隨著電子產業的蓬勃發展，電子產品亦逐漸邁入多功 能、高性能的研發方向，為滿足半導體封裝件高積集度 (Integration )以及微型化（Mini aturizati〇n)的封裝 ^ 求，提供多數主被動元件及線路載接之基板（b〇ard)亦逐 漸由雙層板演變成多層板，以在有限的空間下藉由層間連 接技術（Interlayer Connection)擴大基板上可利用的電 路面積，俾以配合高電子密度之積體電路（Integrated C i rcu i t)的需求。 傳統的多層電路板種類，以目前來說計有壓合式電路 板（Laminated，board)及增層式電路板（Build-up board) 兩種，其中以壓合法製成之多層板如第8 A圖及第8 B圖所 示，係於絕緣基材兩面的銅箔上各形成一内層線路層 10 1’’，俾以構成一核心基板1 0 0 π，之後，在不同核心基板 100”，100an，100b”之間分另U夾置一黏著層5”，經過疊層 (Laminated)及熱壓(Heat Press)等步驟，將不同核心基 板100”， 100a”，100bn上下壓合即形成一多層基板結構。 惟以壓合法製造多層基板時，在層數及孔數的製造上V. INSTRUCTION DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention A wafer carrier, in particular, a layered substrate is laminated on at least one side of a substrate to reduce the pitch of the solder ball pads. (Finger Pitch) A wafer carrier having more input/output terminals at the same substrate unit area, and a semiconductor package having the wafer carrier. X + [Prior Art] With the rapid development of the electronics industry, electronic products are gradually entering the direction of multi-functional, high-performance research and development, in order to meet the high integration and miniaturization of semiconductor packages (Mini aturizati〇n) The package is provided, and most of the active and passive components and the substrate (b〇ard) which are connected to the line are gradually evolved into a multi-layer board from the double-layer board to expand the substrate by the interlayer connection technology (Interlayer Connection) in a limited space. The available circuit area is designed to meet the needs of integrated circuits with high electron density. The traditional multi-layer circuit board type is currently composed of a laminated circuit board (Laminated, board) and a build-up board (Build-up board), in which a multi-layer board made by pressing, such as 8A As shown in FIG. 8B, an inner wiring layer 10 1 ′′ is formed on each of the copper foils on both sides of the insulating substrate to form a core substrate 1 0 0 π, and then, on different core substrates 100 ”, 100A, 100b" is placed between the other U sandwiches an adhesive layer 5", through lamination and hot pressing (Heat Press) and other steps, the different core substrates 100", 100a", 100bn are pressed up and down to form a Multi-layer substrate structure. When manufacturing a multilayer substrate by pressing, the number of layers and the number of holes are manufactured.
17508 矽品.ptd 第8頁 1246750 五、發明說明（2) 有明顯限制’同時，由於其圖案化製程中係以壓合銅箔經 暴光、Μ於、姓刻專減層方式（$ u b s ^ r a c ^丨v e )所形成，使 其銲球墊寬度及相鄰銲球墊間距（Finger Pi tch)因受製 程限制最小均只能縮小到50// m，既難以適用高密度電性 連接端（I/O Connect ions)之封裝產品，也無法作為多晶 片模組（Mul tipi e Chip Module，MCM)或晶片規格封裝 (Chip Scale Package， CSP)等半導體封裝件之基板來 源。 再者，受到傳統蝕刻製程之限制，基板上每一個銲球 墊最小寬度約為5 0// m，加上相鄰銲球墊間最短距離約為 5 0// m，此表示每多設一個銲球墊至基板上即須佔據約i 〇 〇 β in寬的距離，若進一步將該等銲球墊圓形環列在晶片周 圍外’並以半導體晶片之幾何中心作為圓心時，如第9圖 所不，各銲球墊61,距離圓心的半徑_丨0(^/2^ # m (其中 η為銲球墊數量），因此基板1 ”上如佈有2 〇 〇個銲球墊時， 受到相鄰銲球墊間距5()// m及銲球墊寬m共1〇〇// m寬度 的限制’銲球墊6 ”排列的圓周長約為1 〇 〇 ( # m) χ ( 2 〇 〇 - 1 Υ ’換异其圓周直徑相當於6mm ;顯示基板輸入/輸出連接 *而（未圖不）鉅量增加而導致銲球墊佈設量提高時，相對 地銲球墊形成的圓周區域也會擴大而增加基板及封裝件的 成品面積。 ^ 又增層電路板必須由内至外逐層堆疊方能完成，而其 電鍍製程極為精密與缓慢，因此在量產（Mass17508 .品.ptd Page 8 1246750 V. Description of invention (2) There are obvious limitations 'At the same time, because of its patterning process, the copper foil is pressed, exposed, and surnamed ($ ubs ^ Rac ^丨ve ) is formed so that the width of the solder ball pad and the spacing of the adjacent solder ball pads (Finger Pi tch) can only be reduced to 50 / / m due to the minimum process limit, which is difficult to apply to the high-density electrical connection. (I/O Connect ions) package products cannot be used as substrate sources for semiconductor packages such as Mul tipi Chip Modules (MCMs) or Chip Scale Packages (CSPs). Furthermore, due to the limitation of the conventional etching process, the minimum width of each solder ball pad on the substrate is about 50/m, and the shortest distance between adjacent solder ball pads is about 50/m. A solder ball pad to the substrate must occupy a distance of about i 〇〇 β in, if the solder ball pad is further arranged around the wafer and is centered on the geometric center of the semiconductor wafer, such as 9 Figure No, each solder ball pad 61, the radius from the center of the circle _ 丨 0 (^ / 2 ^ # m (where η is the number of solder ball pads), so the substrate 1 "" is covered with 2 solder ball pads When the adjacent solder ball pad pitch is 5 () / / m and the solder ball pad width m is 1 〇〇 / / m width limit "Ball ball pad 6" arranged in a circumference of about 1 〇〇 ( # m) χ ( 2 〇〇 - 1 Υ 'Variation of the circumference of the diameter is equivalent to 6mm; display substrate input / output connection * and (not shown) a large increase in the amount of solder ball mats increased, the relative solder ball mat formation The circumferential area will also be enlarged to increase the finished area of the substrate and the package. ^ The additional circuit board must be stacked from the inside to the outside, and its electricity can be completed. The process is very slow and precise, so mass production (Mass
Product ion)上極為耗時、複雜而且成本極高，售價約為Product ion) is extremely time consuming, complicated and costly, and the price is about
17508矽品.ptd 第9頁 1246750 五、發明說明（3) 至五倍，因此不利於大量生產與普及使 一般壓合板的 用。 咏為達’專小封裳及降低成本之目的，因而有如美國專利 第8 7 0，2 8 9號，其係揭露一種得縮小封裝面積之結構， 如第1 0A圖所示，係於一單面電路板9〇的底面設有電路 9 〇 1 ’再以一霉占膠片9 1將積體電路晶片9 2黏結於單面電路 f 9 〇的頂面’且該單面電路板9 0及黏膠片9 1上設有複數個 二^ 10 2、911 ’於該穿孔9 0 2、9 1 1内穿設有導電柱9 3，而 Λ: ^ 9 3底端電性連接在單面電路板9 0的電路9 0 1上’ ^ ϋ亥&包柱9 3的頂端則電性連接積體電路晶片9 2底面的銲 塾9^，/卩成為一單層之單元結構9。 …明蒼閱第1 0 Β圖，前述之單元結構9上的單面電路板9 〇 2擴f成一大面積的基板9 0 a，且在該基板9 0 a上得電性連 一 2 ^们和肢電路晶片9 2，而在積體電路晶片9 2上再套裝 右一欣9 4 ’亚以膠體9 5進行封裝，且在基板9 0 a之一側設 抖继!t Ϊ輸入/輪出的連接器9 6，即可完成一單層多個的 封裝結構。 缝® 閱第1oc圖，若要多層封裝，則將單元結構9與絕 柱9曰8办、尚:f ?疊裝在一多夕電路板90让，再以長導電 牙k σ固單兀結構9的單面電路板9 0及多層電路板 9〇b，使各個單元結構9的單面電路板9〇電性連接在多層電 路板9 0 b的上方，接著在豐裝的單元結構9外面包覆一外殼 99，且該外殼99的底面結合在多層電路板90b的上方，以 將疊裝的單元結構9封裝在多層電路板9〇tUl，然後再於多17508矽品.ptd Page 9 1246750 V. Invention description (3) Up to five times, it is not conducive to mass production and popularization for general plywood. For the purpose of reducing the cost and reducing the cost, it is similar to the US Patent No. 780, 289, which discloses a structure for reducing the package area, as shown in Figure 10A. The bottom surface of the single-sided circuit board 9 is provided with a circuit 9 〇 1 ' and then the integrated circuit film 9 2 is bonded to the top surface of the single-sided circuit f 9 以 and the single-sided circuit board 9 0 And the adhesive film 9 1 is provided with a plurality of two 2, 2, 911 '. The conductive pillars 9 3 are disposed in the perforations 9 0 2, 9 1 1 , and the bottom end is electrically connected to the single side. The top end of the circuit 9 0 of the circuit board 90 is electrically connected to the bottom surface of the integrated circuit chip 92, and becomes a single-layer unit structure 9. ...the Ming Cang reading the 10th map, the single-sided circuit board 9 〇2 on the unit structure 9 described above is expanded into a large-area substrate 90a, and electrically connected to the substrate 90a. And the limb circuit chip 92, and on the integrated circuit chip 92, and then set the right one 9 4' sub-package with the colloid 9 5, and set the jitter on one side of the substrate 90 a! The rounded connector 96 can complete a single layer and multiple package structures. Slit® Read the 1oc diagram. If you want to package in multiple layers, then the unit structure 9 and the column 9曰8, still: f? stacked on a multi-day circuit board 90, and then a long conductive tooth k σ solid single 兀The single-sided circuit board 90 of the structure 9 and the multi-layer circuit board 9〇b are electrically connected to the single-sided circuit board 9 of each unit structure 9 above the multi-layer circuit board 90b, and then in the bulky unit structure 9. The outer casing is covered with a casing 99, and the bottom surface of the casing 99 is bonded over the multi-layer circuit board 90b to package the stacked unit structure 9 on the multi-layer circuit board 9〇tUl, and then more
1246750 五、發明說明（4) 9 〇 c，即成為 層電路板9 0 b底面連接作為輸出/輪入的產曰 一多層封裝的結構。 ^ 、、干球 而由於積體電路晶片9 2係藉由長導恭 多層電路板9 0 b上，雖可降低封穿面積 ^挺98直接連接在 輸入接點的使用數目，則因單元結構、9之，若要增加輸出/ 能提供的接點有限，因此無法直接在w 舉面電路板9 0所 接點，僅能藉由向外擴張電路基板的路板9 0上增加 數量，如此一來即無法減少面積以達薄f以增加接點的 右僅能維持電路基板之面積，則盔^衣之目的。 接點的使用數目，a & 十θ ^、丄、土…宏w加輸出/輸入 與多I/0接點之封裝目的。 、、伯小體積、高密度 f者’該積體電路晶片9 2連接在多 必須先經過一今私壯 。β 曰寬路板9 Ob後， 進行外形的第：：：壯之後的单層3多層封裝，則必須再 增加製造成本Γ人封裝’因而增加製造程序的複雜性，故 為]i匕，士口 ^可奸至 佈設之餘仍能進—^ 2裝方式，使基板在容納大量銲球墊 業界急切之務。ν縮減BGA封裝件之整體體積，已成為 【發明内容】1246750 V. INSTRUCTION DESCRIPTION (4) 9 〇 c, that is, the structure of the multi-layer package which is connected to the bottom of the layer circuit board 90b as an output/wheel. ^,, dry ball and because the integrated circuit chip 9 2 is made by the long-conducting multilayer circuit board 90 b, although the sealing area can be reduced to directly connect the number of input contacts in the input contact, the unit structure 9, if you want to increase the output / can provide a limited number of contacts, so you can not directly connect to the w-plane board 90, can only increase the number of the board 90 by outward expansion of the circuit board, so In one case, the area cannot be reduced to achieve a thin f to increase the right side of the contact only to maintain the area of the circuit substrate. The number of contacts used, a & ten θ ^, 丄, earth... macro w plus output / input and multi-I / 0 contact packaging purposes. , the small volume, the high density of the 'the integrated circuit chip 9 2 connected more must first pass through today's private. After the β 曰 wide slab 9 Ob, the single-layer 3-layer package after the shape of the ::: strong, must increase the manufacturing cost of the package, thus increasing the complexity of the manufacturing process, so it is] The mouth ^ can be raped until the layout is still able to enter - ^ 2 installation, so that the substrate in the industry to accommodate a large number of solder ball mats urgently. νReducing the overall volume of the BGA package has become [invention]
本發明之主I 積，橫向縮減半導嘴的’係在提供一種可降低基板使用面 製法，以及具有a収封袭件尺寸之堆豎式晶片承載件及其 本發明^又f堆4式晶片承載件之半導體封裝件。 板之植4面積兼二1的，則在提供一種不會限制壓合式基 ' 大破既有製程限制，以縮減銲球墊寬度及The invention provides a method for reducing the thickness of a substrate, and a stacked vertical wafer carrier having a size of a sealed member and the present invention. A semiconductor package of a wafer carrier. The 4th area of the board and the 2nd of the board provide a kind of process limit that does not limit the press-fit base 'large breaks, to reduce the width of the solder ball pad and
1246750 五、發明說明（5) 相鄰銲球墊間距至5 0/z m以下之堆疊式曰 ^ ^ 八曰曰片承載件及其製 法’以及具有該堆疊式晶片承載件之半導體封穿件。 、本發明之再-目的，係在提供一種僅;;進‘一次封裝 以降低製造成本之堆疊式晶片承載件之半導體封裝件。 為達成上述及其他目的，本發明传 _ ^ , 义θ你徒供一種將增層式 （ BU1d-up Substrate)及壓合式基板（Laminated u strate)合而為一，亚能進—步形成晶片朝上型或晶 ΐ 裝結構，以減少封裝成品之整體尺寸之組合式 日日片承載件及其製法，以及具有該組 導體封裝件。 D式曰曰片承載件之丰 ^其中，本發明之組合式晶片承載件係包括：-壓合式 基板（Laminated Substrate)，其包含至少一電路層及 二敷設於該電路層外之第一絕緣層，該第一絕緣層上^係形 成複數個供該電路層外露之第一開口；至少一接置於該壓 合式基板上之增層式基板，該增層式基板具有複數層增層 線路層及一覆蓋在該增層線路層表面而與該壓合式基板第 一絕緣層相對之第二絕緣層，該第二絕緣層係形成有複數 個提供該增層線路層曝露之第二開口；以及複數個導電元 件，係形成於該第一開口及第二開口之間，俾接合該壓合 式基板電路層及該增層線路層而使該壓合式基板與該增層 式基板之間電性連接。 而上述組合式晶片承載件之製法，則包括以下步驟： 預備一壓合式基板（Laminated Substrate)，該壓合式 基板包括有至少一電路層及一敷設於該電路層外之第一絕1246750 V. INSTRUCTIONS (5) Stacked 曰 ^ ^ octagonal sheet carrier and its manufacturing method with adjacent solder ball pads spaced below 5 0 / z m and a semiconductor sealing member having the stacked wafer carrier. A further object of the present invention is to provide a semiconductor package that is only a one-package to reduce the manufacturing cost of the stacked wafer carrier. In order to achieve the above and other objects, the present invention provides a method for combining a BU1d-up Substrate and a laminated substrate (Laminated u strate) into a sub-energy step-forming wafer. A modular day-to-day carrier and a method of manufacturing the same, to reduce the overall size of the packaged product, and to have the set of conductor packages. The composite wafer carrier of the present invention comprises: a laminated substrate comprising at least one circuit layer and two first insulation disposed outside the circuit layer a first insulating layer on the first insulating layer to form a plurality of first openings for exposing the circuit layer; at least one build-up substrate disposed on the laminated substrate, the build-up substrate having a plurality of build-up lines And a second insulating layer covering the surface of the build-up wiring layer opposite to the first insulating layer of the laminated substrate, the second insulating layer is formed with a plurality of second openings for providing exposure of the build-up circuit layer; And a plurality of conductive elements formed between the first opening and the second opening, and bonding the laminated substrate circuit layer and the build-up wiring layer to electrically connect the laminated substrate and the build-up substrate connection. The method for manufacturing the combined wafer carrier comprises the following steps: preparing a laminated substrate, the laminated substrate comprising at least one circuit layer and a first one disposed outside the circuit layer
17508石夕品.pt；d 第12頁 1246750 五、發明說明（6) 緣 層，該第一絕緣層上係形成複數個供該電路層外露之第 一開口；製備至少一與該壓合式基板接置之增層式基板， 該增層式基板具有複數層增層線路層及一覆蓋在該增層線 路層表面而與該壓合式基板第一絕緣層相對之第二絕緣 層’且δ亥第一絕緣層係形成有複數個提供該增層線路層曝 露之第二開口；以及，設置複數個導電元件至該第一開口 及第二開口之間，俾接合該壓合式基板電路層及該增層線 路層而使該壓合式基板與該增層式基板之間電性連接。曰" 另外，本發明亦包含以上述堆疊式晶片承載件載接晶 片之球栅陣列式半導體封裝件。該半導體封裝件係包括： 一組合式晶片承載件，其包含一壓合式基板，至少一增層 式基板及提供該壓合式基板與增層式基板接合並且ϋ 元件，*中，該增層式基板中央部係設有 Μ#至少一半導體晶片，係接置於該組合式晶 導接·封=二=載區上，並與該堆疊式晶片承載件電性 ίί: 用以包覆該半導…：以及複數個 1干球係植接於該組合式晶片承載件上。 製程：Πΐί 相鄰二球塾間距及銲球塾寬在現有 片周圍時，若按昭目2 7之銲球墊亚以®形環繞於晶 球墊寬U⑼乘以(r'於（相曰鄰銲球塾間距（#ra) +銲 所佔據的圓周直徑將可干^塾數里—υ、计异，排列銲球墊 低基板使用面積，以户2 減至2.5龍而明顯降 、 h向縮減該基板及半導體封裝件的尺17508石夕品.pt;d Page 12 1246750 V. Description of the invention (6) The edge layer, the first insulating layer is formed with a plurality of first openings for exposing the circuit layer; preparing at least one and the pressed substrate a build-up substrate, the build-up substrate having a plurality of build-up wiring layers and a second insulating layer covering the surface of the build-up wiring layer opposite to the first insulating layer of the laminated substrate The first insulating layer is formed with a plurality of second openings for providing exposure of the build-up wiring layer; and a plurality of conductive elements are disposed between the first opening and the second opening to bond the laminated substrate circuit layer and the The circuit layer is layered to electrically connect the laminated substrate to the build-up substrate. Further, the present invention also encompasses a ball grid array type semiconductor package in which a wafer is carried by the above stacked wafer carrier. The semiconductor package includes: a combined wafer carrier comprising a laminated substrate, at least one build-up substrate, and a bonded substrate and a build-up substrate bonded to the germanium element, wherein the build-up layer The central portion of the substrate is provided with at least one semiconductor wafer, and is connected to the combined crystal conduction joint seal = two = load region, and is electrically connected to the stacked wafer carrier: Guided by: and a plurality of dry bulbs are implanted on the combined wafer carrier. Process: Πΐί When the spacing between the adjacent two balls and the width of the solder ball are around the existing piece, if the ball pad is in the shape of a beam, the shape is wrapped around the width of the crystal ball U(9) and multiplied by (r' Neighboring solder ball spacing (#ra) + The diameter of the circumference occupied by the welding will be able to dry, the number of holes, the difference, the arrangement of the solder ball mat, the low substrate area, and the reduction of the household 2 to 2.5 dragons. To reduce the size of the substrate and the semiconductor package
17508矽品.ptd 11 llil17508 products.ptd 11 llil
第13頁 1246750 五、發明說明（7) 寸。 另一方面，本發明之組合 板與壓合式基板，利用增# ㈤7載件整合增層式基 合式基板，在有限的基板以=，精？度上高出壓 而壓合式基板在結構強度與夕數1之銲球墊， 特點’使壓合式基板可以提 ::層式基板之 ，增層式基板來說可降低整 =太以及相對 【實施方式】 才干您衣作成本。 以下係藉由特定的具體實施例說明本 式，熟習此技藝之人+ π山士 兀月尽毛明之貫施方 瞭解本發明之；說：書所揭示…輕易地 的具體實施例加：由其他不同 可基於不同觀…用二：：書中的各項細節亦 種修飾與變更。 不#離本發明之精神下進行各 以下之κ知例係進一步詳細說明本發明之觀點，但並 非以任何觀點限制本發明之範脅。 本發明係提供一種將增層式基板（Bui ld-upPage 13 1246750 V. Description of invention (7) Inch. On the other hand, the composite board of the present invention and the press-fitted substrate are integrated with a layered base substrate by using a #(五)7 carrier, in a limited substrate to =, fine? The pressure is high and the pressure of the laminated substrate is in the structural strength and the number 1 of the solder ball pad. The characteristics of the laminated substrate can be raised: the layered substrate, the layered substrate can reduce the overall = too and relative Implementation method] The cost of your clothing. The following is a description of the present invention by a specific embodiment, and the person skilled in the art + π 兀 兀 尽 尽 尽 尽 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 轻易 轻易 轻易 轻易 轻易 轻易 轻易 轻易 轻易Other differences can be based on different views... Use the second:: The details in the book are also modified and changed. The present invention is not limited by the scope of the present invention, and the present invention is not limited by any point of view. The present invention provides a build-up substrate (Bui ld-up
Substrate)及壓合式基板（Laminated Substrate)合而 為一 ’並且進一步形成晶片朝下型之覆晶方式 (Fi lp-chip) ’如第丨A圖及第1B圖所示之封裝結構，或晶 片朝上型之焊線式（wi re bond)，如第2A圖及第2B圖所示 之封裝、结構’以減少封裝成品尺寸之組合式晶片承載件及 其製法，以及具有該組合式晶片承載件之半導體封裝件， 而藉由下述實施例分別予以詳細說明。Substrate) and laminated substrate (Laminated Substrate) are combined into one's and further formed into a wafer-facing type of flip-chip type (Fi lp-chip) 'package structure as shown in FIG. 1A and FIG. 1B, or a wafer Wi-bond, a package, structure as shown in FIGS. 2A and 2B, a combined wafer carrier for reducing the size of the package, and a method for manufacturing the same, and having the combined wafer carrier The semiconductor package of the device is described in detail by the following embodiments.
17508 矽品.ptd 第14頁 1246750 五、發明說明（8) •本發^具有組合式晶片承載件之半導體封裝件係包 括·一.堆豐式晶片承載件1 ;至少一半導體晶片2係以覆晶 式（F1 Chlp)電性連接組合在該堆疊式晶片承載件1頂 面:如第1 A圖及第1 B圖所示，或該半導體晶片2以銲線式 (Wire fond)電性連接組合在該堆疊式晶片承載件1頂 面:如第2A圖及第2B圖所示；一封裝膠體3係用以包覆該 半導體晶片2，以及複數個植接於該堆疊式晶片承載件1底 部之銲球4。 ，上述堆疊式晶片承載件1及其製法進一步包括：預 備一壓合式基板1〇( Laminated Substrate)，該壓合式 基板1 0之一側係提供該等銲球4植接，以供半導體晶片2與 外部裝置（未圖示）電性連結；製備至少一增層式基板i丄 (Build-up Substrate)，係接置於該壓合式基板ι〇未植 球之一側，該增層式基板丨丨上設有至少一供半導體晶片2 安置之晶片承載區1 1 〇 ;以及，提供至少一導電元件1 2， 係用以接合並提供該壓合式基板1 〇與該增層式基板丨丨導電 連接。 如第3 A圖及第3 B圖所示，該壓合式基板1 〇 (Lam i nated Substrate)係包含多數如銅结與例如bt樹 脂、聚亞醯胺（Poly imide) 、FR-5樹脂或環氧樹脂等絕 緣材料所製成之核心基板1 〇 〇，以及形成於該核心基板i 〇 〇 表面之一或多層内層線路層1〇1，其中，該壓合式基板1〇 之一側係形成有多數銲球墊1 〇 3提供銲球（未圖示）植 接’且為阻隔外界電性干擾，壓合式基板1 〇最外側的内層17508 .品.ptd Page 14 1246750 V. INSTRUCTION DESCRIPTION (8) • The present invention has a semiconductor package having a combined wafer carrier comprising a stack of wafer carriers 1; at least one semiconductor wafer 2 A flip-chip (F1 Chlp) electrical connection is combined on the top surface of the stacked wafer carrier 1 as shown in FIGS. 1A and 1B, or the semiconductor wafer 2 is wire-wired. The connection is assembled on the top surface of the stacked wafer carrier 1 as shown in FIGS. 2A and 2B; an encapsulant 3 is used to coat the semiconductor wafer 2, and a plurality of implants are attached to the stacked wafer carrier 1 solder ball 4 at the bottom. The stacked wafer carrier 1 and the method of fabricating the same further include: preparing a laminated substrate 1 La (Laminated Substrate), the side of the laminated substrate 10 is provided to the solder balls 4 for the semiconductor wafer 2 Electrically connecting with an external device (not shown); preparing at least one build-up substrate, Build-up Substrate, attached to one side of the unbonded substrate of the press-fit substrate, the build-up substrate At least one wafer carrying area 1 1 for the semiconductor wafer 2 is disposed on the crucible; and at least one conductive element 12 is provided for bonding and providing the laminated substrate 1 and the build-up substrate Conductive connection. As shown in FIGS. 3A and 3B, the laminated substrate 1 includes a plurality of such as copper bonds and, for example, bt resin, poly imide, FR-5 resin or a core substrate 1 made of an insulating material such as an epoxy resin, and one or more inner wiring layers 1〇1 formed on the surface of the core substrate i, wherein one side of the laminated substrate is formed There are many solder ball pads 1 〇3 to provide solder balls (not shown) to be implanted' and to block external electrical interference, the innermost layer of the laminated substrate 1 〇
17508石夕品.ptd 第15頁 1246750 五、發明說明（9) 線路層1 (Π經過圖案化後，於該内層線路層i 〇丨上外覆一層 /、有夕數第開口 1 〇 2 a之弟一拒銲劑層i〇2( Solder Mask )，以，該内層線路層101透過各第一開口1〇以而外露。 如第4A圖所示，該增層式基板u ( BuUd —up17508石夕品.ptd Page 15 1246750 V. Description of invention (9) Circuit layer 1 (Π After patterning, the inner layer of the inner layer is covered with a layer/, with a number of openings 1 〇 2 a a solder resist layer i 〇 2 ( Solder Mask), so that the inner wiring layer 101 is exposed through the first openings 1 。. As shown in FIG. 4A, the build-up substrate u (BuUd — up
Substrate)係利用增層技術交互堆疊多層絕緣層及導電 層，並於該絕緣層中開設多數導電貫孔113( c〇nductive V 1 a)，經過包鍍以及圖案化等製程後形成複數層上下電 性導通之增層線路層丨丨4。惟如第4β圖所示，本發明之堆 疊式晶片> 承載件，係在增層式基板【丨中央形成一晶片承载 區1 1 0 亥曰曰片承載區i i 0藉以電性連接半導體晶片2。 而為阻隔外界電性干擾，增層式基板11外側的增層線 二層1 1 4經過圖案化後，亦會和壓合式基板i 〇一樣於基板 最外側覆+蓋一一層具複數個第二開口丄丨2&之第二拒銲劑層 1 1 2 ’该第一開口 1 1 2 a之位置係與該壓合式基板丨〇之第—Substrate) alternately stacks a plurality of insulating layers and conductive layers by using a build-up technique, and a plurality of conductive vias 113 (c〇nductive V 1 a) are formed in the insulating layer, and a plurality of layers are formed after plating and patterning. Electrically conductive layered layer 丨丨4. However, as shown in FIG. 4β, the stacked wafer of the present invention is formed on the build-up substrate [the center of the wafer is formed with a wafer carrying area 1 1 0 曰曰 承载 carrying area ii 0 for electrically connecting the semiconductor wafer 2. In order to block the external electrical interference, the layer 2 of the build-up layer outside the layered substrate 11 is patterned, and the same as the laminated substrate i 覆 is covered on the outermost side of the substrate. The second opening 丄丨2& the second solder resist layer 1 1 2 'the first opening 1 1 2 a is located at the same position as the pressed substrate —
開口 1 0 2a位置彼此對應，以形成如第4β圖底視圖示 板結構。 I 本發明之堆®式晶片承載件丨不同於習知承載件之 處，係利用至少-導電元件12將該壓合式基板1()及增 基板11合而為一，1亥導電元件12如導電性膠黏劑、銲錫： (SolderPaste)^?冷里 句 义鮮錫凸塊（Solder Bump)等，俾蕤 由勝黏或迴銲等㈣令該壓合式基板1〇與增層式基板二 電性連接。以本貫施例為例，如第5A圖及第⑽圖所示， 壓合式基板1 0之第一拒銲劑層i 〇2的第一開口 i 〇2a處、 網印或點膠等方式塗佈—銲錫m將該增層式基板uThe openings 1 0 2a are positioned to correspond to each other to form a bottom view panel structure as in the 4th. I The stack of the wafer carrier of the present invention is different from the conventional carrier, and the laminated substrate 1 and the substrate 11 are combined by at least the conductive member 12, and the conductive element 12 is Conductive Adhesive, Solder: (SolderPaste)^?Solid Bump, etc., such as wink or reflow, etc. (4) The laminated substrate 1〇 and the build-up substrate 2 Electrical connection. Taking the present embodiment as an example, as shown in FIGS. 5A and (10), the first opening i 〇 2a of the first solder resist layer i 〇 2 of the laminated substrate 10 is coated by screen printing or dispensing. Cloth-solder m, the build-up substrate u
1246750 五、發明說明（ΙΟ) 覆蓋到壓合式基板U上，以使該第一開口 i 02a與該第二開 1 口 1 1 2a對應接觸而讓該銲錫膏〗2溢流入該第二開口 1 1 , 經過迴嬋aefiow)等程序，使得該内層線路層i〇i及增層 線路層114之間能透過該銲錫膏接合並且電性連接。惟 |該導電元件^除於增層式基板u接合前預先佈設於該慶合 式基板1 0之弟一開口；1023外，亦可反過來預先形成於該第 一拒銲劑層Π2表面之第二開口 112a，然本實施例之導電 = 電膠或銲錫膏夕卜，凡不影響增層式基板 π與屋合式基板10電性接合之接合技術或元 I本發明之可實施範疇。 各 由於增層式基板i丨之相鄰銲球墊間距及銲球墊寬在現 ί = 2〇“，相較於傳統屢合式基板 卜；曰王片：n t基板上佈設相同數量之銲球墊並以圓形環 ΓΛ曰曰，若按照圓周等於（相鄰辉球墊間距（# 、干；足m乃乘以（銲球墊數量）計算，排列r ί降：：：：圓周直徑:可，原本的6mm縮減至2· 5襲而明 |尺寸。土用面積，橫向縮減該基板及半導體封裝件的 I其你=面，、本發明之堆疊式晶片承載件1整合增層式 h x έ合式基板1 〇，利用該增層式基板11在味路 數量之鮮式基板1〇,以在有限的基板面積下佈設更多 U “2,而該壓合式基板10在結構強度上佳於增ί 壓合式基板10可提供良好的結“ | 子於增層式基板11來說可降低整體封裳件之制1246750 V. The invention description (ΙΟ) covers the press-fit substrate U such that the first opening i 02a is in contact with the second opening 1 1 2a to allow the solder paste to overflow into the second opening 1 1. After a procedure such as returning aefiow), the inner wiring layer i〇i and the build-up wiring layer 114 can be bonded and electrically connected through the solder paste. However, the conductive element is pre-disposed on the opening of the rendezvous substrate 10 before being joined to the build-up substrate u; and 1023 may be reversely formed in advance on the surface of the first solder resist layer 2 The opening 112a, in the present embodiment, is conductive=electro-adhesive or solder paste, and does not affect the bonding technique of the build-up substrate π and the electrically-bonded substrate 10 or the practical implementation of the invention. The spacing of the adjacent solder ball pads and the width of the solder ball pads of the layered substrate i在 are now ί = 2〇", compared with the conventional multi-chip substrate; the same number of solder balls are disposed on the nt substrate. The pad is a circular ring, if the circumference is equal to (the adjacent glow pad spacing (#, dry; foot m is multiplied by (the number of solder ball pads), the arrangement r ί falls :::: circumference diameter: Yes, the original 6mm is reduced to 5.2. The size of the soil area is laterally reduced by the substrate and the semiconductor package. The stacked wafer carrier 1 of the present invention is integrated with the layered hx. The laminated substrate 1 利用, using the build-up substrate 11 in the fresh substrate 1 味 of the number of taste channels, to lay more U "2" under a limited substrate area, and the laminated substrate 10 is better in structural strength than增 压 压 压 压 压 压 压 压 压 压 压 压 压 压 压 压 压 压 压 压 压 压 压 压 压 压 压 压 压 压 压
第17頁 1246750 五、發明說明（11) 作成本。 請參閱第6圖，該封裝膠體3係為一散熱片3 a，而該散 熱片3 a係為一罩體，其四周邊固定在堆疊式晶片承載件1 之壓合式基板1 0上面，俾可藉由該散熱片3 a進行散熱，以 避免半導體晶片2過熱而損壞，因而可以更佳的使用效 果，此為本發明封裝之另一實施。 請參閱第7圖，該壓合式基板1 0上方得排開疊裝複數 個相同或不同尺寸規格的增層式基板1 1，且在各個增層式 基板1 1上方分別疊裝同功能或不同功能的半導體晶片2， 接著再以封裝膠體3封裝，使其可在壓合式基板1 0上多重 封裝複數個半導體晶片2，因而得以達到縮小封裝面積之 目的，且僅須一次進行封裝，而得簡化封裝製程，俾以節 省製造成本。 上述實施例僅為例示性說明本發明之原理及其功效， 而非用於限制本發明。任何熟習此技藝之人士均可在不違 背本發明之精神及範疇下，對上述實施例進行修飾與變 化。因此，本發明之權利保護範圍，應如後述之申請專利 範圍所列。Page 17 1246750 V. Description of invention (11) Cost. Referring to FIG. 6, the encapsulant 3 is a heat sink 3 a, and the heat sink 3 a is a cover, and the four periphery thereof is fixed on the laminated substrate 10 of the stacked wafer carrier 1 . The heat sink 3 a can be used for heat dissipation to prevent the semiconductor wafer 2 from being overheated and damaged, so that the effect can be better, which is another implementation of the package of the present invention. Referring to FIG. 7 , a plurality of stacked substrates 1 1 of the same or different sizes are stacked on top of the laminated substrate 10 , and the same function or different is stacked on each of the build-up substrates 1 1 . The functional semiconductor wafer 2 is then packaged by the encapsulant 3 so that a plurality of semiconductor wafers 2 can be multi-packaged on the laminated substrate 10, thereby achieving the purpose of reducing the package area and only requiring one package at a time. Simplify the packaging process to save manufacturing costs. The above-described embodiments are merely illustrative of the principles of the invention and its advantages, and are not intended to limit the invention. Modifications and variations of the above-described embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the scope of the patent application to be described later.
]7508石夕品.ptd 第18頁 1246750 圖式簡單說明 【圖式簡單說明】 第1 A圖係為本發明具有該堆疊式晶片承載件之半導體 封裝件的晶片朝下型的分解組合示意圖； 第1 B圖係為本發明具有該堆疊式晶片承載件之半導體 封裝件的晶片朝下型的組合示意圖； 第2A圖係為本發明具有該堆疊式晶片承載件之半導體 封裝件的晶片朝上型的分解組合示意圖； 第2 B圖係為本發明具有該堆疊式晶片承載件之半導體 封裝件的晶片朝上型的組合示意圖； 第3A圖係本發明堆疊式晶片承載件之壓合式基板之局 部剖視圖； 第3 B圖係本發明堆疊式晶片承載件之壓合式基板之底 視圖， 第4A圖係本發明堆疊式晶片承載件之增層式基板之局 部剖視圖； 第4B圖係本發明堆疊式晶片承載件之增層式基板之上 視圖； 第5 A圖係本發明之堆疊式晶片承載件中，該增層式基 板與壓合式基板接合前之示意圖； 第5 B圖係本發明之堆疊式晶片承載件中，該增層式基 板與壓合式基板接合後之示意圖； 第6圖係本發明具有堆疊式晶片承載件之半導體封裝 件另一封裝實施之剖面示意圖； 第7圖係本發明具有堆疊式晶片承載件之半導體封裝7508石夕品.ptd Page 18 1246750 Brief description of the drawing [Simplified illustration of the drawing] FIG. 1A is a schematic exploded view of the wafer-down type of the semiconductor package having the stacked wafer carrier of the present invention; 1B is a schematic view showing a combination of a wafer facing downward type of a semiconductor package having the stacked wafer carrier; FIG. 2A is a wafer facing of the semiconductor package having the stacked wafer carrier of the present invention; FIG. 2B is a schematic diagram of a combination of a wafer facing up type of a semiconductor package having the stacked wafer carrier; FIG. 3A is a laminated substrate of the stacked wafer carrier of the present invention; 3B is a bottom view of a laminated substrate of the stacked wafer carrier of the present invention, and FIG. 4A is a partial cross-sectional view of the stacked substrate of the stacked wafer carrier of the present invention; FIG. 4B is a stacked view of the present invention Above view of the layered substrate of the wafer carrier; FIG. 5A is a stacked wafer carrier of the present invention, before the bonded substrate is bonded to the laminated substrate 5B is a schematic view of the stacked wafer carrier of the present invention after bonding the laminated substrate to the laminated substrate; FIG. 6 is a semiconductor package having a stacked wafer carrier of the present invention and another package Schematic diagram of the implementation; Figure 7 is a semiconductor package having a stacked wafer carrier of the present invention
17508石夕品.ptd 第19頁 1246750 圖式簡單說明 件又一封裝實施之剖面示意圖； 第8 A圖及第8 B圖係習知以壓合法製作多層基板之剖視 圖； 第9圖係習知銲球墊環設於晶片周圍之基板區域之假 想示意圖；以及 第10A圖、第10B圖及第10C圖係為美國專利第 5，8 7 0，2 8 9號半導體封裝之剖視示意圖。 1 堆 疊 式 晶 片 承 載 件 100” 核 心 基 板 100a ’丨核 心 基 板 1 0 0 b 丨， 核 心 基 板 Γ、 90a 基 板 10卜 101M 内 層 線路層 102a 第 — 開 α 102 拒 銲 劑 層 103 銲 球 墊 10 壓 合 式 基 板 110 晶 片 承 載 區 112a 第 二 開 a 112 第 二 拒 銲 劑 層 113 導 電 貫 孔 114 增 層 線 路 層 11 增 層 式 基 板 12 銲 錫 膏 、 導 電 元 件 2 半 導 體 晶 片 3 a 散 孰 4 片 3 封 裝 膠 體 4 銲 球 5M 黏 著 層 6丨’ 銲 球 墊 9 單 元 結 構 90 單 面 電 路 板 90b 多 層 電 路 板 90c 銲 球 901 電 路 9 0 2〜 91 ] L穿孔 91 黏 膠 片 92 積 體 電 路 晶 片 921 銲 墊17508石夕品.ptd Page 19 1246750 Schematic diagram of a simplified illustration of another package implementation; Figures 8A and 8B are conventional cross-sectional views of a multilayer substrate fabricated by compression; Figure 9 is a conventional view An imaginary schematic diagram of a solder ball bead ring disposed on a substrate area around the wafer; and FIGS. 10A, 10B, and 10C are schematic cross-sectional views of a semiconductor package of U.S. Patent No. 5,870,289. 1 stacked wafer carrier 100" core substrate 100a '丨 core substrate 1 0 0 b 丨, core substrate Γ, 90a substrate 10 卜 101M inner layer circuit layer 102a - open α 102 solder resist layer 103 solder ball pad 10 press-type substrate 110 wafer carrying area 112a second opening a 112 second solder resist layer 113 conductive through hole 114 build-up wiring layer 11 build-up substrate 12 solder paste, conductive element 2 semiconductor wafer 3 a divergent 4 piece 3 package colloid 4 solder ball 5M Adhesive layer 6丨' Solder ball pad 9 Unit structure 90 Single-sided circuit board 90b Multi-layer circuit board 90c Solder ball 901 Circuit 9 0 2~ 91 ] L-perforated 91 Viscose film 92 Integrated circuit chip 921 Solder pad
17508石夕品.ptd 第20頁 124675017508石夕品.ptd Page 20 1246750
17508石夕品.ptd 第21頁17508 Shi Xipin.ptd Page 21
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7551455B2 (en) | 2006-05-04 | 2009-06-23 | Cyntec Co., Ltd. | Package structure |
| TWI426588B (en) * | 2010-10-12 | 2014-02-11 | Advanced Semiconductor Eng | Package structure and package process |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI508239B (en) * | 2009-08-20 | 2015-11-11 | Xintec Inc | Chip package and manufacturing method thereof |
| TWI768552B (en) * | 2020-11-20 | 2022-06-21 | 力成科技股份有限公司 | Stacked semiconductor package and packaging method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7551455B2 (en) | 2006-05-04 | 2009-06-23 | Cyntec Co., Ltd. | Package structure |
| TWI426588B (en) * | 2010-10-12 | 2014-02-11 | Advanced Semiconductor Eng | Package structure and package process |
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