JP5097006B2 - Printed wiring board and manufacturing method thereof - Google Patents

Printed wiring board and manufacturing method thereof Download PDF

Info

Publication number
JP5097006B2
JP5097006B2 JP2008126998A JP2008126998A JP5097006B2 JP 5097006 B2 JP5097006 B2 JP 5097006B2 JP 2008126998 A JP2008126998 A JP 2008126998A JP 2008126998 A JP2008126998 A JP 2008126998A JP 5097006 B2 JP5097006 B2 JP 5097006B2
Authority
JP
Japan
Prior art keywords
wiring
insulating resin
substrate
semiconductor
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2008126998A
Other languages
Japanese (ja)
Other versions
JP2009277846A (en
Inventor
誠裕 岡本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujikura Ltd
Original Assignee
Fujikura Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujikura Ltd filed Critical Fujikura Ltd
Priority to JP2008126998A priority Critical patent/JP5097006B2/en
Publication of JP2009277846A publication Critical patent/JP2009277846A/en
Application granted granted Critical
Publication of JP5097006B2 publication Critical patent/JP5097006B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

本発明は、プリント配線基板及びその製造方法に係り、特に、複数の半導体素子が埋め込まれたプリント配線基板及びその製造方法に関する。   The present invention relates to a printed wiring board and a manufacturing method thereof, and more particularly to a printed wiring board in which a plurality of semiconductor elements are embedded and a manufacturing method thereof.

近年、携帯電話やデジタルカメラ等に代表される携帯電子機器において、製品の小型化、高機能化が急速に進んでいる。それにともない、それらの電子機器に搭載される部品にも、小型化、高機能化、大容量化等が要求されている。半導体パッケージにおいても、上記の流れから、１つのパッケージにＩＣ（Ｉｎｔｅｇｒａｔｅｄ Ｃｉｒｃｕｉｔ）チップ等の半導体素子を複数個内包してシステム化するシステムインパッケージ技術が注目を浴びている。   2. Description of the Related Art In recent years, in portable electronic devices typified by mobile phones and digital cameras, products have been rapidly reduced in size and functionality. Along with this, parts mounted on these electronic devices are also required to be downsized, highly functional, large capacity, and the like. Also in the semiconductor package, from the above-mentioned flow, a system-in-package technique for systematizing a plurality of semiconductor elements such as an IC (Integrated Circuit) chip in one package has been attracting attention.

また、パッケージの薄型化という点からは、Ｓｉウエハ薄型加工技術が発達してきた。最近では、ＩＣを１００μｍ厚程度まで薄肉化することが可能となったことを受け、プリント配線基板の内部にＩＣチップ等を埋め込む部品内蔵基板技術が注目されている。この部品内蔵基板は、プリント配線基板内部にＩＣチップ等を埋め込むことにより、従来に比べて、相対的に実装面積を増やすことができる。   In addition, Si wafer thinning technology has been developed from the viewpoint of thinning the package. Recently, in response to the fact that an IC can be thinned to a thickness of about 100 μm, a component-embedded substrate technology in which an IC chip or the like is embedded in a printed wiring board has attracted attention. The component-embedded substrate can have a relatively increased mounting area as compared with the prior art by embedding an IC chip or the like in the printed wiring board.

特許文献１には、複数の半導体装置に対応するサイズのベース板上の接着層上に格子状の埋込材を接着し、埋込材の開口部内における接着層上に、シリコン基板上に再配線、柱状電極及び封止膜を設けてなる半導体構成体を接着し、半導体構成体とその外側の方形枠上の埋込材との間に封止膜を形成し、第１の上層絶縁膜、第２の上層再配線、第３の上層絶縁膜を順次、積層状に形成し、半田ボールを形成し、互いに隣接する半導体構成体間において切断することにより半田ボールを備えた半導体装置が複数個得られることが示されている。
特開２００４−９５８３６号公報 In Patent Document 1, a grid-like embedding material is adhered onto an adhesive layer on a base plate having a size corresponding to a plurality of semiconductor devices, and the adhesive layer in the opening of the embedding material is re-applied on a silicon substrate. A semiconductor structure including a wiring, a columnar electrode, and a sealing film is bonded, and a sealing film is formed between the semiconductor structure and an embedding material on a rectangular frame outside the first structure. A plurality of semiconductor devices including solder balls by sequentially forming a second upper layer rewiring and a third upper layer insulating film in a laminated form, forming solder balls, and cutting between adjacent semiconductor structures; It is shown that it can be obtained.
JP 2004-95836 A

ところで、プリント配線基板の中に複数個のＩＣチップ等の半導体素子を埋め込んで製造する場合には、半導体素子の入出力（Ｉ／Ｏ）パッドピッチを拡大するため再配線層等が素子回路面側に多数積層される。これに対して、半導体素子の素子回路面と反対側である裏面の素子基板面では、再配線層等はほとんど設けられていない。そのため、複数の半導体素子が素子回路面を同じ方向に向けて埋め込まれて多層化される場合には、プリント配線基板の層構成に異方性が生じるためプリント配線基板に反りが生じる可能性がある。   By the way, when a semiconductor element such as a plurality of IC chips is embedded in a printed wiring board, a rewiring layer is provided on the element circuit surface in order to increase the input / output (I / O) pad pitch of the semiconductor element. Many are stacked on the side. On the other hand, a rewiring layer or the like is scarcely provided on the element substrate surface on the back side opposite to the element circuit surface of the semiconductor element. For this reason, when a plurality of semiconductor elements are embedded with their element circuit surfaces oriented in the same direction, the printed wiring board may be warped due to anisotropy in the layer structure of the printed wiring board. is there.

そこで、本発明の目的は、反りを抑制したプリント配線基板及びその製造方法を提供することである。   Then, the objective of this invention is providing the printed wiring board which suppressed curvature, and its manufacturing method.

本発明に係るプリント配線基板は、複数の半導体素子が埋め込まれたプリント配線基板であって、第１絶縁樹脂板と、前記第１絶縁樹脂板の一方の面に設けられる第１導体回路と、前記第１絶縁樹脂板の他方の面から突出して形成され、前記第１絶縁樹脂板を貫通し、前記第１導体回路と接触させた複数の第１貫通電極と、を有する第１配線部材と、第１半導体素子と、前記第１半導体素子の素子回路面に設けられ、素子回路電極と前記第１貫通電極とを接続する第１再配線層と、を有する第１半導体部材と、前記第１半導体部材が埋め込まれ、前記第１配線部材と前記第１半導体部材とを一体化する第１絶縁樹脂基材と、を含む第１配線部と、
第２絶縁樹脂板と、前記第２絶縁樹脂板の一方の面に設けられる第２導体回路と、前記第２絶縁樹脂板の他方の面から突出して形成され、前記第２絶縁樹脂板を貫通し、前記第２導体回路と接触させた複数の第２貫通電極と、を有する第２配線部材と、第２半導体素子と、前記第２半導体素子の素子回路面に設けられ、素子回路電極と前記第２貫通電極とを接続する第２再配線層と、を有する第２半導体部材と、前記第２半導体部材が埋め込まれ、前記第２配線部材と前記第２半導体部材とを一体化する第２絶縁樹脂基材と、を含む第２配線部と、
を備え、
絶縁樹脂シートと、前記絶縁樹脂シートの一方の面に設けられ、前記第１貫通電極と前記第２貫通電極とに接続される導電層と、を有し、一端が前記第１絶縁樹脂基材に埋め込まれ、他端が前記第２絶縁樹脂基材に埋め込まれ、前記一端と前記他端との間の部位を前記第１絶縁樹脂基材及び前記第２絶縁樹脂基材から突出させた接続部材を含み、前記第１配線部と前記第２配線部とは、前記第１半導体素子と前記第２半導体素子との前記素子回路面と反対側の素子基板面を各々対向させて略対称に配置され、前記第１配線部と前記第２配線部との間に、支持部材が接着剤で加熱圧着されて設けられ、前記接続部材は、前記第１配線部と前記第２配線部と前記支持部材との間に中空状の隙間を設けて配置され、前記接続部材の内周面への前記接着剤の流れ込みによる固着を抑えるため、前記中空状の隙間の大きさが前記支持部材の厚みを変えることにより調整されていることを特徴とする。 A printed wiring board according to the present invention is a printed wiring board in which a plurality of semiconductor elements are embedded, and a first insulating resin plate, a first conductor circuit provided on one surface of the first insulating resin plate, A first wiring member having a plurality of first through electrodes formed protruding from the other surface of the first insulating resin plate, penetrating through the first insulating resin plate, and in contact with the first conductor circuit; A first semiconductor member comprising: a first semiconductor element; and a first redistribution layer provided on an element circuit surface of the first semiconductor element and connecting the element circuit electrode and the first through electrode; A first wiring portion including a first insulating resin base material in which one semiconductor member is embedded and the first wiring member and the first semiconductor member are integrated;
A second insulating resin plate, a second conductor circuit provided on one surface of the second insulating resin plate, and formed to protrude from the other surface of the second insulating resin plate and penetrate through the second insulating resin plate A second wiring member having a plurality of second through electrodes in contact with the second conductor circuit, a second semiconductor element, and an element circuit electrode provided on the element circuit surface of the second semiconductor element; A second semiconductor member having a second redistribution layer connecting to the second through electrode; and a second semiconductor member embedded in the second semiconductor member and integrating the second wiring member and the second semiconductor member. A second wiring portion including two insulating resin substrates;
With
An insulating resin sheet; and a conductive layer provided on one surface of the insulating resin sheet and connected to the first through electrode and the second through electrode, one end of the first insulating resin substrate The other end is embedded in the second insulating resin base material, and a portion between the one end and the other end is protruded from the first insulating resin base material and the second insulating resin base material. The first wiring portion and the second wiring portion are substantially symmetrical with each other facing the element substrate surface of the first semiconductor element and the second semiconductor element opposite to the element circuit surface. Disposed between the first wiring portion and the second wiring portion, and a support member is provided by being heat-pressed with an adhesive, and the connection member includes the first wiring portion, the second wiring portion, and the second wiring portion. A hollow gap is provided between the support member and the connection member to the inner peripheral surface of the connection member. To suppress the sticking by inflow of agents, the size of the hollow gap is characterized that you have been adjusted by changing the thickness of the support member.

本発明に係るプリント配線基板において、前記支持部材は、ポリイミド樹脂で成形された樹脂シート、繊維強化樹脂複合材料で成形された複合材料シート、無機材料で成形されたセラミックシート、またはモリブデンやインバー合金を銅で挟持した金属板で形成されていることを特徴とする。 In the printed wiring board according to the present invention, the support member is a resin sheet molded from a polyimide resin, a composite material sheet molded from a fiber reinforced resin composite material, a ceramic sheet molded from an inorganic material, or molybdenum or an Invar alloy. the features that you have been formed of a metal plate which sandwiches with copper.

本発明に係るプリント配線基板は、前記第１絶縁樹脂基材に埋め込まれ、前記第１半導体素子と略同じ厚みを有する第１スペーサまたは前記第２絶縁樹脂基材に埋め込まれ、前記第２半導体素子と略同じ厚みを有する第２スペーサを備えることを特徴とする。   The printed wiring board according to the present invention is embedded in the first insulating resin base material, embedded in the first spacer having the same thickness as the first semiconductor element or the second insulating resin base material, and the second semiconductor. A second spacer having substantially the same thickness as the element is provided.

本発明に係るプリント配線基板の製造方法は、複数の半導体素子が埋め込まれたプリント配線基板の製造方法であって、絶縁樹脂板と、前記絶縁樹脂板の一方の面に形成される導体回路と、前記絶縁樹脂板の他方の面に設けられる第１接着層と、前記絶縁樹脂板と前記第１接着層とを貫通し、前記導体回路と導通する複数の導電性ペースト電極と、を含む複数の配線基材を成形する配線基材成形工程と、半導体素子と、前記半導体素子の素子回路面に設けられ、素子回路電極と前記導電性ペースト電極とを接続する再配線層と、を含む複数の半導体部材とを成形する半導体部材成形工程と、絶縁樹脂ベース板と、前記絶縁樹脂ベース板の一方の面に設けられる第２接着層と、を含む複数の配線ベース基材とを成形する配線ベース基材成形工程と、絶縁樹脂シートと、前記絶縁樹脂シートの一方の面に形成される導電層と、を有する接続部材を成形する接続部材成形工程と、
を備え、
前記複数の配線ベース基材の第１配線ベース基材と第２配線ベース基材とは、前記接続部材の長さより短い間隔を設けて、前記第２接着層を同じ向きにして配置され、前記接続部材は、一端を前記第１配線ベース基材の第２接着層に、他端を前記第２配線ベース基材の第２接着層に、前記絶縁樹脂シートを向けて積層され、前記複数の半導体部材の第１半導体部材と第２半導体部材とは、前記第１配線ベース基材と前記第２配線ベース基材との第２接着層に、前記素子回路面と反対側の素子基板面を向けて各々積層され、前記複数の配線基材の第１配線基材と第２配線基材とは、各々一端の導電性ペースト電極を前記接続部材の導電層と接触させ、各々所定の導電性ペースト電極を前記再配線層と接触させて、前記第１半導体部材と前記第２半導体部材と前記接続部材とに積層されて配線基材積層体を形成する配線基材積層体形成工程と、
前記配線基材積層体に含まれる第１接着層と第２接着層とを硬化させて、前記第１配線基材と前記第１半導体部材と前記第１配線ベース基材を一体化させた第１配線予備基体と、前記第２配線基材と前記第２半導体部材と前記第２配線ベース基材を一体化させた第２配線予備基体と、前記第１配線予備基体と前記第２配線予備基体とに接続された接続部材と、を含む配線予備成形体を予備成形する配線予備成形体成形工程と、
前記第１配線予備基体と前記第２配線予備基体とに埋め込まれた各々半導体素子の素子基板面を対向させるように前記接続部材を曲げて前記第１配線予備基体と前記第２配線予備基体とを略対称に配置し、前記第１配線予備基体と前記第２配線予備基体との各々絶縁樹脂ベース板を接合する接合工程と、
を有し、
前記接合工程は、前記第１配線予備基体と前記第２配線予備基体との間に支持部材が挟持されて接着剤で加熱圧着され、前記接続部材は、前記第１配線部と前記第２配線部と前記支持部材との間に中空状の隙間を設けて配置され、前記接続部材の内周面への前記接着剤の流れ込みによる固着を抑えるため、前記中空状の隙間の大きさが前記支持部材の厚みを変えることにより調整されることを特徴とする。 A printed wiring board manufacturing method according to the present invention is a printed wiring board manufacturing method in which a plurality of semiconductor elements are embedded, and an insulating resin plate and a conductor circuit formed on one surface of the insulating resin plate A plurality of conductive paste electrodes that pass through the insulating resin plate and the first adhesive layer and are electrically connected to the conductor circuit; and a first adhesive layer provided on the other surface of the insulating resin plate. A wiring substrate molding step for molding the wiring substrate, a semiconductor element, and a rewiring layer provided on the element circuit surface of the semiconductor element and connecting the element circuit electrode and the conductive paste electrode Wiring for forming a plurality of wiring base substrates including a semiconductor member molding step for molding the semiconductor member, an insulating resin base plate, and a second adhesive layer provided on one surface of the insulating resin base plate Base substrate molding process , The insulating resin sheet, and the connecting member forming step of forming a connecting member having a conductive layer formed on one surface of the insulating resin sheet,
With
The first wiring base substrate and the second wiring base substrate of the plurality of wiring base substrates are arranged with the second adhesive layer in the same direction, with an interval shorter than the length of the connection member, The connection member is laminated with one end facing the second adhesive layer of the first wiring base substrate and the other end facing the second adhesive layer of the second wiring base substrate with the insulating resin sheet facing the plurality of the connection members. The first semiconductor member and the second semiconductor member of the semiconductor member have an element substrate surface opposite to the element circuit surface on the second adhesive layer of the first wiring base substrate and the second wiring base substrate. The first wiring substrate and the second wiring substrate of the plurality of wiring substrates are respectively brought into contact with the conductive layer of the connection member, and each of the plurality of wiring substrates has a predetermined conductivity. A paste electrode is brought into contact with the rewiring layer, and the first semiconductor member and the second semiconductor member A wiring substrate stacked body forming step of forming a wiring base material laminate are laminated and the connection member to the conductor member,
The first adhesive layer and the second adhesive layer included in the wiring substrate laminate are cured, and the first wiring substrate, the first semiconductor member, and the first wiring base substrate are integrated. 1 wiring preliminary substrate, second wiring substrate, second semiconductor member and second wiring base substrate integrated with the second wiring base substrate, first wiring preliminary substrate and second wiring preliminary A wiring preform forming step for preforming a wiring preform including a connection member connected to the base body;
The connection member is bent so that the element substrate surfaces of the respective semiconductor elements embedded in the first wiring preliminary substrate and the second wiring preliminary substrate are opposed to each other, and the first wiring preliminary substrate, the second wiring preliminary substrate, Are disposed substantially symmetrically, and a bonding step of bonding the insulating resin base plates to the first wiring preliminary substrate and the second wiring preliminary substrate,
I have a,
In the joining step, a supporting member is sandwiched between the first wiring preliminary base and the second wiring preliminary base and heat-pressed with an adhesive, and the connection member includes the first wiring portion and the second wiring. In order to suppress sticking due to the flow of the adhesive into the inner peripheral surface of the connection member, the size of the hollow gap is set to the support. is adjusted by varying the thickness of the member, characterized in Rukoto.

本発明に係るプリント配線基板の製造方法において、前記支持部材は、ポリイミド樹脂で成形された樹脂シート、繊維強化樹脂複合材料で成形された複合材料シート、無機材料で成形されたセラミックシート、またはモリブデンやインバー合金を銅で挟持した金属板で形成されていることを特徴とする。 In the method for manufacturing a printed wiring board according to the present invention, the support member is a resin sheet molded from a polyimide resin, a composite material sheet molded from a fiber-reinforced resin composite material, a ceramic sheet molded from an inorganic material, or molybdenum. And Invar alloy is formed of a metal plate sandwiched between copper .

本発明に係るプリント配線基板の製造方法において、前記配線基材成形工程は、一方の面に銅層が設けられた絶縁樹脂板の前記銅層をエッチングして前記導体回路を形成し、前記絶縁樹脂板の他方の面に、前記第１接着層を形成し、前記第１接着層にマスキング層を形成し、前記絶縁樹脂板と前記第１接着層と前記マスキング層とに貫通して、前記導体回路と接続させる接続穴を形成し、前記接続穴に導電性ペーストを充填した後、前記マスキング層を除去して導電性ペースト電極を形成することを特徴とする。   In the method for manufacturing a printed wiring board according to the present invention, the wiring base material forming step forms the conductor circuit by etching the copper layer of an insulating resin plate having a copper layer provided on one surface, and forming the conductive circuit. Forming the first adhesive layer on the other surface of the resin plate, forming a masking layer on the first adhesive layer, penetrating the insulating resin plate, the first adhesive layer, and the masking layer; A connection hole to be connected to a conductor circuit is formed, and after filling the connection hole with a conductive paste, the masking layer is removed to form a conductive paste electrode.

本発明に係るプリント配線基板の製造方法において、前記半導体部材成形工程は、前記半導体素子の素子回路電極位置に第１開口を設けて第１絶縁層を形成し、前記第１開口に導電性材料で前記再配線層を形成し、前記再配線層の所定位置に第２開口を設けて第２絶縁層を形成することを特徴とする。   In the method for manufacturing a printed wiring board according to the present invention, in the semiconductor member forming step, a first insulating layer is formed by providing a first opening at a position of an element circuit electrode of the semiconductor element, and a conductive material is formed in the first opening. The rewiring layer is formed, and a second opening is provided at a predetermined position of the rewiring layer to form a second insulating layer.

上記構成におけるプリント配線基板及びその製造方法によれば、配線基板の層構成を略対称にすることができるのでプリント配線基板の反りが抑制される。   According to the printed wiring board and the method for manufacturing the same in the above configuration, the layer configuration of the wiring board can be made substantially symmetrical, so that warpage of the printed wiring board is suppressed.

以下に、本発明の実施の形態について図面を用いて詳細に説明する。図１は、プリント配線基板１０の構成を示す断面図である。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a cross-sectional view showing the configuration of the printed wiring board 10.

プリント配線基板１０は、第１配線部材１２ａと第１半導体部材１４ａと第１絶縁樹脂基材１６ａとを有する第１配線部１８ａと、第２配線部材１２ｂと第２半導体部材１４ｂと第２絶縁樹脂基材１６ｂとを有する第２配線部１８ｂと、を備えている。   The printed wiring board 10 includes a first wiring member 18a having a first wiring member 12a, a first semiconductor member 14a, and a first insulating resin base material 16a, a second wiring member 12b, a second semiconductor member 14b, and a second insulation. And a second wiring portion 18b having a resin base material 16b.

第１配線部１２ａは、第１絶縁樹脂板２０ａと、第１絶縁樹脂板２０ａの一方の面に設けられる第１導体回路２２ａと、第１絶縁樹脂板２０ａの他方の面から突出して形成され、第１絶縁樹脂板２０ａを貫通し、第１導体回路２２ａと接触させて設けられる複数の第１貫通電極２３ａ、２４ａと、を有している。   The first wiring portion 12a is formed to protrude from the first insulating resin plate 20a, the first conductor circuit 22a provided on one surface of the first insulating resin plate 20a, and the other surface of the first insulating resin plate 20a. And a plurality of first through electrodes 23a, 24a provided through the first insulating resin plate 20a and in contact with the first conductor circuit 22a.

第１絶縁樹脂板２０ａは、ポリイミド樹脂等の絶縁樹脂材料で成形される。第１絶縁樹脂板２０ａの一方の面に設けられる第１導体回路２２ａは、例えば、銅材料や銀材料で形成されたリード配線層で形成される。第１貫通電極２３ａ、２４ａは、例えば、銅材料や銀材料等の導電性材料で形成される。また、第１配線部材１２ａの第１導体回路２２ａ側に、更に、他の配線部材２６ａを積層してもよい。   The first insulating resin plate 20a is formed of an insulating resin material such as polyimide resin. The first conductor circuit 22a provided on one surface of the first insulating resin plate 20a is formed of, for example, a lead wiring layer formed of a copper material or a silver material. The first through electrodes 23a and 24a are formed of a conductive material such as a copper material or a silver material, for example. Further, another wiring member 26a may be further laminated on the first conductor circuit 22a side of the first wiring member 12a.

第１半導体部材１４ａは、第１半導体素子３０ａと、第１半導体素子３０ａの素子回路面に設けられ、素子回路電極３１ａと第１貫通電極２３ａとを接続する第１再配線層３２ａと、各々の第１再配線層３２ａを絶縁する第１絶縁体３４ａと、を有している。第１半導体素子３０ａには、例えば、ＩＣチップ等が用いられる。   The first semiconductor member 14a is provided on the element circuit surface of the first semiconductor element 30a, the first semiconductor element 30a, and the first redistribution layer 32a connecting the element circuit electrode 31a and the first through electrode 23a, respectively. And a first insulator 34a that insulates the first redistribution layer 32a. For example, an IC chip or the like is used for the first semiconductor element 30a.

第１再配線層３２ａは、第１半導体素子３０ａの素子回路面に設けられ、第１半導体素子３０ａの素子回路電極３１ａと第１貫通電極２３ａとに接続される。第１再配線層３２ａは、第１半導体素子３０ａと第１配線部材１２ａとを、端子を再配列して接続するために設けられる。第１再配線層３２ａは、例えば、銅材料や銀材料等の導電性材料で形成される。   The first redistribution layer 32a is provided on the element circuit surface of the first semiconductor element 30a, and is connected to the element circuit electrode 31a and the first through electrode 23a of the first semiconductor element 30a. The first rewiring layer 32a is provided to connect the first semiconductor element 30a and the first wiring member 12a by rearranging the terminals. The first redistribution layer 32a is formed of a conductive material such as a copper material or a silver material, for example.

また、第１半導体素子３０ａの外周を囲むようにして、第１半導体素子３０ａの厚みと略同じ厚みを有する第１スペーサ３６ａを配置してもよい。第１スペーサ３６ａは、例えば、樹脂シートや、一方の面に導体層が設けられた樹脂シート等で形成される。   Further, a first spacer 36a having substantially the same thickness as that of the first semiconductor element 30a may be disposed so as to surround the outer periphery of the first semiconductor element 30a. The first spacer 36a is formed of, for example, a resin sheet or a resin sheet provided with a conductor layer on one surface.

第１絶縁樹脂基材１６ａは、第１半導体部材１４ａが埋め込まれ、第１配線部材１２ａと第１半導体部材１４ａとを一体化する機能を有している。また、第１絶縁樹脂基材１６ａは、第１貫通電極２３ａ、２４ａの間を絶縁する機能を有している。第１絶縁樹脂基材１６ａは、例えば、エポキシ樹脂等の絶縁樹脂材料で形成される。また、第１スペーサ３６ａが用いられる場合には、第１スペーサ３６ａも第１絶縁樹脂基材１６ａに埋め込まれる。   The first insulating resin base material 16a has a function of embedding the first semiconductor member 14a and integrating the first wiring member 12a and the first semiconductor member 14a. Further, the first insulating resin base material 16a has a function of insulating between the first through electrodes 23a and 24a. The first insulating resin base material 16a is formed of an insulating resin material such as an epoxy resin, for example. When the first spacer 36a is used, the first spacer 36a is also embedded in the first insulating resin base material 16a.

第２配線部材１２ｂは、第２絶縁樹脂板２０ｂと、第２絶縁樹脂板２０ｂの一方の面に設けられる第２導体回路２２ｂと、第２絶縁樹脂板２０ｂの他方の面から突出して形成され、第２絶縁樹脂板２０ｂを貫通し、第２導体回路２２ｂと接触させて設けられる複数の第２貫通電極２３ｂ、２４ｂと、を有している。第２配線部材１２ｂは、第１配線部材１２ａと同様にして形成される。また、第２配線部材１２ｂの第２導体回路２２ｂ側に、更に、他の配線部材２６ｂを積層してもよい。   The second wiring member 12b is formed to protrude from the second insulating resin plate 20b, the second conductor circuit 22b provided on one surface of the second insulating resin plate 20b, and the other surface of the second insulating resin plate 20b. And a plurality of second through electrodes 23b and 24b provided so as to penetrate the second insulating resin plate 20b and to be in contact with the second conductor circuit 22b. The second wiring member 12b is formed in the same manner as the first wiring member 12a. Further, another wiring member 26b may be further laminated on the second conductor circuit 22b side of the second wiring member 12b.

第２半導体部材１４ｂは、第２半導体素子３０ｂと、第２半導体素子３０ｂの素子回路面に設けられ、素子回路電極３１ｂと第２貫通電極２３ｂとを接続する第２再配線層３２ｂと、各々の第２再配線層３２ｂを絶縁する第２絶縁体３４ｂと、を有している。第２半導体部材１４ｂは、第１半導体部材１４ａと同様にして形成される。また、第２半導体素子３０ｂの外周を囲むようにして、第２半導体素子３０ｂの厚みと略同じ厚みを有する第２スペーサ３６ｂを配置してもよい。なお、第２スペーサ３６ｂは、第１スペーサ３６ａと同様にして形成される。   The second semiconductor member 14b includes a second semiconductor element 30b, a second redistribution layer 32b provided on the element circuit surface of the second semiconductor element 30b, and connecting the element circuit electrode 31b and the second through electrode 23b. And a second insulator 34b for insulating the second redistribution layer 32b. The second semiconductor member 14b is formed in the same manner as the first semiconductor member 14a. Further, a second spacer 36b having a thickness substantially the same as the thickness of the second semiconductor element 30b may be disposed so as to surround the outer periphery of the second semiconductor element 30b. The second spacer 36b is formed in the same manner as the first spacer 36a.

第２絶縁樹脂基材１６ｂは、第２半導体部材１４ｂが埋め込まれ、第２配線部材１２ｂと第２半導体部材１４ｂとを一体化する機能を有している。また、第２絶縁樹脂基材１６ｂは、第２貫通電極２３ｂ、２４ｂの間を絶縁する機能を有している。第２絶縁樹脂基材１６ｂは、第１絶縁樹脂基材１６ａと同様にしで形成される。   The second insulating resin base material 16b has a function of embedding the second semiconductor member 14b and integrating the second wiring member 12b and the second semiconductor member 14b. Further, the second insulating resin base material 16b has a function of insulating between the second through electrodes 23b and 24b. The second insulating resin base material 16b is formed in the same manner as the first insulating resin base material 16a.

また、第１配線部１８ａは、第１配線ベース部材３８ａを有し、第２配線部１８ｂは、第２配線ベース部材３８ｂを有していてもよい。第１配線ベース部材３８ａと第２配線ベース部材３８ｂとは、例えば、ポリイミド樹脂等の絶縁樹脂材料で成形される。   The first wiring portion 18a may have a first wiring base member 38a, and the second wiring portion 18b may have a second wiring base member 38b. The first wiring base member 38a and the second wiring base member 38b are formed of an insulating resin material such as polyimide resin, for example.

更に、第１配線ベース部材３８ａと第２配線ベース部材３８ｂとの間には、支持部材３９を設けることができる。支持部材３９には、ポリイミド樹脂等の合成樹脂で成形された樹脂シート、繊維強化樹脂複合材料（ＦＲＰ）で成形された複合材料シート、無機材料等で成形されたセラミックシート、放熱特性に優れた金属材料で成形された金属シート等を用いることができる。また、支持部材３９は、半導体素子の主構成物であるシリコンと熱膨張係数が近く、放熱特性に優れる材料で成形されることが好ましく、このような材料には、例えば、モリブデンやインバー合金を銅で挟持した金属板等を用いることができる。   Furthermore, a support member 39 can be provided between the first wiring base member 38a and the second wiring base member 38b. The support member 39 has a resin sheet molded from a synthetic resin such as a polyimide resin, a composite material sheet molded from a fiber reinforced resin composite material (FRP), a ceramic sheet molded from an inorganic material, etc., and excellent heat dissipation characteristics. A metal sheet or the like formed from a metal material can be used. The support member 39 is preferably formed of a material having a thermal expansion coefficient close to that of silicon, which is a main component of the semiconductor element, and excellent in heat dissipation characteristics. Examples of such a material include molybdenum and Invar alloy. A metal plate sandwiched between copper and the like can be used.

接続部材４０は、絶縁樹脂シート４２と、絶縁樹脂シート４２の一方の面に設けられ、第１配線部材１２ａの一端に置かれる第１貫通電極２４ａと、第２配線部材１２ｂの一端に置かれる第２貫通電極２４ｂとに接続される導電層４４と、を有している。   The connecting member 40 is provided on one surface of the insulating resin sheet 42 and the insulating resin sheet 42, and is disposed on one end of the first wiring member 12a and one end of the second wiring member 12b. And a conductive layer 44 connected to the second through electrode 24b.

絶縁樹脂シート４２には、ポリイミド樹脂等の絶縁樹脂材料で形成された可撓性を有する合成樹脂フィルム等が用いられる。そのため、絶縁樹脂シート４２は、柔軟性を有しており、例えば、容易に折り曲げられる。導電層４４は、例えば、銅材料や銀材料等の導電性材料で形成される。導電層４４が、第１配線部材１２ａの一端に置かれる第１貫通電極２４ａと、第２配線部材１２ｂの一端に置かれる第２貫通電極２４ｂとに接続されることにより、第１配線部１８ａと第２配線部１８ｂとが電気的に接続される。   As the insulating resin sheet 42, a flexible synthetic resin film formed of an insulating resin material such as polyimide resin is used. Therefore, the insulating resin sheet 42 has flexibility, and can be easily bent, for example. The conductive layer 44 is formed of a conductive material such as a copper material or a silver material, for example. The conductive layer 44 is connected to the first through electrode 24a placed at one end of the first wiring member 12a and the second through electrode 24b placed at one end of the second wiring member 12b, whereby the first wiring portion 18a. Are electrically connected to the second wiring portion 18b.

接続部材４０は、その一端が第１絶縁樹脂基材１６ａに埋め込まれて第１配線部１８ａに連結され、他端が第２絶縁樹脂基材１６ｂに埋め込まれて第２配線部１８ｂに連結される。また、接続部材４０は、一端と他端との間の部位を、第１絶縁樹脂基材１６ａ及び第２絶縁樹脂基材１６ｂから突出させて設けられる。また、接続部材４０は、例えば、環状に折り曲げられることにより、第１絶縁樹脂基材１６ａ及び第２絶縁樹脂基材１６ｂとの間に中空状の隙間４６を空けて設けられる。接続部材４０の一端と他端との間の部位は、第１絶縁樹脂基材１６ａ及び第２絶縁樹脂基材１６ｂに埋め込まれて固定されていないので、プリント配線基板１０の積層方向である厚み方向の熱膨張等の膨張に対して変形して追従できる。そのため、プリント配線基板１０の厚さ方向に生じる熱応力を緩和して、電気的接続の信頼性が向上する。   One end of the connection member 40 is embedded in the first insulating resin base material 16a and connected to the first wiring portion 18a, and the other end is embedded in the second insulating resin base material 16b and connected to the second wiring portion 18b. The Further, the connecting member 40 is provided by projecting a portion between one end and the other end from the first insulating resin base material 16a and the second insulating resin base material 16b. Further, the connecting member 40 is provided, for example, by being bent in an annular shape, with a hollow gap 46 between the first insulating resin base material 16a and the second insulating resin base material 16b. Since the portion between one end and the other end of the connection member 40 is not embedded and fixed in the first insulating resin base material 16a and the second insulating resin base material 16b, the thickness in the stacking direction of the printed wiring board 10 It can deform and follow expansion such as thermal expansion in the direction. Therefore, the thermal stress generated in the thickness direction of the printed wiring board 10 is relaxed, and the reliability of electrical connection is improved.

第１配線部１８ａと第２配線部１８ｂとは、第１半導体素子３０ａの素子回路面と反対側の素子基板面と、第２半導体素子３０ｂの素子回路面と反対側の素子基板面とを対向させて設けられる。図１では、第１半導体素子３０ａは、再配線層３２ａが設けられた素子回路面を上側に向けて配置され、第２半導体素子３０ｂは、再配線層３２ｂが設けられた素子回路面を下側に向けて配置されており、第１半導体部材１６ａと第２半導体部材１６ｂとは上下逆向きに埋め込まれている。そのため、第１配線部１８ａと第２配線部１８ｂとは、支持部材３９に対して略対称に配置されるので、プリント配線基板１０の反りが抑えられる。   The first wiring portion 18a and the second wiring portion 18b include an element substrate surface opposite to the element circuit surface of the first semiconductor element 30a and an element substrate surface opposite to the element circuit surface of the second semiconductor element 30b. It is provided to face each other. In FIG. 1, the first semiconductor element 30a is disposed with the element circuit surface provided with the rewiring layer 32a facing upward, and the second semiconductor element 30b is disposed below the element circuit surface provided with the rewiring layer 32b. The first semiconductor member 16a and the second semiconductor member 16b are embedded upside down. Therefore, since the first wiring portion 18a and the second wiring portion 18b are disposed substantially symmetrically with respect to the support member 39, the warp of the printed wiring board 10 can be suppressed.

次に、複数の半導体素子が埋め込まれたプリント配線基板１０の製造方法について説明する。   Next, a method for manufacturing the printed wiring board 10 in which a plurality of semiconductor elements are embedded will be described.

図２は、プリント配線基板１０の製造方法を示すフローチャートである。プリント配線基板１０の製造方法は、配線基材成形工程（Ｓ１０）と、半導体部材成形工程（Ｓ１２）と、配線ベース基材成形工程（Ｓ１４）と、接続部材成形工程（Ｓ１６）と、配線基材積層体形成工程（Ｓ１８）と、配線予備成形体成形工程（Ｓ２０）と、接合工程（Ｓ２２）と、を備えている。このうち、配線基材成形工程（Ｓ１０）と、半導体部材成形工程（Ｓ１２）と、配線ベース基材成形工程（Ｓ１４）と、接続部材成形工程（Ｓ１６）とは、特に、順序はなく、例えば、複数の工程を同時に行ってもよい。   FIG. 2 is a flowchart showing a method for manufacturing the printed wiring board 10. The manufacturing method of the printed wiring board 10 includes a wiring base material forming step (S10), a semiconductor member forming step (S12), a wiring base base material forming step (S14), a connecting member forming step (S16), a wiring base A material laminate forming step (S18), a wiring preform forming step (S20), and a joining step (S22) are provided. Among these, the wiring substrate forming step (S10), the semiconductor member forming step (S12), the wiring base substrate forming step (S14), and the connecting member forming step (S16) are not particularly in order, for example, A plurality of steps may be performed simultaneously.

配線基材成形工程（Ｓ１０）は、絶縁樹脂板と、絶縁樹脂板の一方の面に形成される導体回路と、絶縁樹脂板の他方の面に設けられる第１接着層と、絶縁樹脂板と第１接着層とを貫通し、導体回路と導通する複数の導電性ペースト電極と、を含む複数の配線基材を成形する工程である。   The wiring substrate forming step (S10) includes an insulating resin plate, a conductor circuit formed on one surface of the insulating resin plate, a first adhesive layer provided on the other surface of the insulating resin plate, an insulating resin plate, It is a step of forming a plurality of wiring base materials including a plurality of conductive paste electrodes that penetrate through the first adhesive layer and are electrically connected to the conductor circuit.

配線基材成形工程（Ｓ１０）は、一方の面に銅層が設けられた絶縁樹脂板をエッチングして導体回路を形成する工程と、絶縁樹脂板の他方の面に第１接着層を形成する工程と、第１接着層にマスキング層を形成する工程と、絶縁樹脂板とマスキング層とを貫通し、導体回路と導通させる接続穴を形成する工程と、接続穴に導電性ペーストを充填した後、マスキング層を除去して導電性ペースト電極を形成する工程と、を有している。   In the wiring substrate forming step (S10), a conductive circuit is formed by etching an insulating resin plate provided with a copper layer on one surface, and a first adhesive layer is formed on the other surface of the insulating resin plate. A process, a process of forming a masking layer on the first adhesive layer, a process of forming a connection hole penetrating the insulating resin plate and the masking layer and conducting with the conductor circuit, and after filling the connection hole with the conductive paste And removing the masking layer to form a conductive paste electrode.

導体回路は、一方の面に銅層が設けられた絶縁樹脂板の銅層をエッチングして形成される。図３は、一方の面に銅層５０が設けられた絶縁樹脂板５２の構成を示す断面図である。銅層５０が設けられた絶縁樹脂板５２には、例えば、片面銅張板（ＣＣＬ：Ｃｏｐｐｅｒ Ｃｌａｄ Ｌａｍｉｎａｔｅ）が用いられる。   The conductor circuit is formed by etching a copper layer of an insulating resin plate having a copper layer provided on one surface. FIG. 3 is a cross-sectional view showing a configuration of an insulating resin plate 52 provided with a copper layer 50 on one surface. For the insulating resin plate 52 provided with the copper layer 50, for example, a single-sided copper clad plate (CCL: Copper Clad Laminate) is used.

絶縁樹脂板５２には、例えば、ポリイミド樹脂で成形されたポリイミド樹脂フィルムが用いられる。ポリイミド樹脂フィルムには、例えば、厚みが２５μｍのフィルム材が用いられる。絶縁樹脂板５２を成形する合成樹脂は、ポリイミド樹脂に限定されることなく、ポリエチレンテレフタレート樹脂、ビスマレイミドトリアジン（ＢＴ）樹脂、エポキシ樹脂、フッ素樹脂、フェノール樹脂等の熱可塑性樹脂や熱硬化性樹脂を用いることができる。また、絶縁樹脂板５２を成形する合成樹脂には、液晶ポリマー（ＬＣＰ）等を用いてもよい。また、銅層５０は、絶縁樹脂板５２の一方の面に、例えば、９μｍの厚みで形成される。   For the insulating resin plate 52, for example, a polyimide resin film molded from a polyimide resin is used. For example, a film material having a thickness of 25 μm is used for the polyimide resin film. The synthetic resin for forming the insulating resin plate 52 is not limited to polyimide resin, but is thermoplastic resin such as polyethylene terephthalate resin, bismaleimide triazine (BT) resin, epoxy resin, fluorine resin, phenol resin, or thermosetting resin. Can be used. Further, a liquid crystal polymer (LCP) or the like may be used as a synthetic resin for forming the insulating resin plate 52. The copper layer 50 is formed on one surface of the insulating resin plate 52 with a thickness of 9 μm, for example.

片面銅張板には、銅箔にポリイミドワニスを塗布してワニスを硬化させる、いわゆるキャスティング法により成形された片面銅張板を用いてもよいし、ポリイミド樹脂フィルムに導電性シード層をスパッタリング法で形成し、導電性シード層に電解銅めっき法等で銅層を形成して成形した片面銅張板を用いてもよいし、圧延銅箔または電解銅箔と、ポリイミド樹脂フィルムとを接着剤で貼り合わせて成形した片面銅張板を用いてもよい。   For a single-sided copper-clad plate, a single-sided copper-clad plate formed by a so-called casting method, in which a polyimide varnish is applied to a copper foil and the varnish is cured, or a conductive seed layer is sputtered onto a polyimide resin film A single-sided copper-clad plate formed by forming a copper layer on the conductive seed layer by electrolytic copper plating or the like may be used, or a rolled copper foil or electrolytic copper foil and a polyimide resin film may be used as an adhesive You may use the single-sided copper clad board bonded together and shape | molded.

導体回路５４は、絶縁樹脂板５２に設けられた銅層５０をエッチングすることにより形成される。図４は、絶縁樹脂板５２に形成された導体回路５４の構成を示す断面図である。エッチングは、銅層５０の表面にフォトリソグラフィ技術によりエッチングレジストを形成した後、塩化第二鉄を主成分とするエッチャントを用いて化学エッチングして行われる。エッチャントは、塩化第二鉄を主成分とするエッチャントに限定されることなく、塩化第二銅を主成分とするエッチャントを用いてもよい。   The conductor circuit 54 is formed by etching the copper layer 50 provided on the insulating resin plate 52. FIG. 4 is a cross-sectional view showing the configuration of the conductor circuit 54 formed on the insulating resin plate 52. Etching is performed by forming an etching resist on the surface of the copper layer 50 by photolithography and then chemically etching it using an etchant containing ferric chloride as a main component. The etchant is not limited to an etchant mainly composed of ferric chloride, and an etchant mainly composed of cupric chloride may be used.

第１接着層は、絶縁樹脂板５２の導体回路面と反対側の他方の面に設けられる。図５は、第１接着層５６を設けた状態を示す断面図である。第１接着層５６は、例えば、厚みが２５μｍのエポキシ樹脂系熱硬化性フィルム等の熱硬化性フィルム接着剤で形成される。勿論、第１接着層５６は、エポキシ樹脂系熱硬化性フィルム接着剤に限定されることなく、アクリル樹脂系フィルム接着剤や、熱可塑性ポリイミド樹脂系フィルム接着剤等の熱可塑性フィルム接着剤を用いてもよい。また、第１接着層５６は、樹脂フィルム接着剤で形成されることに限定されることなく、絶縁樹脂板５２の表面にワニス状の樹脂液を塗布して形成されてもよい。   The first adhesive layer is provided on the other surface of the insulating resin plate 52 opposite to the conductor circuit surface. FIG. 5 is a cross-sectional view showing a state in which the first adhesive layer 56 is provided. The first adhesive layer 56 is formed of a thermosetting film adhesive such as an epoxy resin thermosetting film having a thickness of 25 μm, for example. Of course, the first adhesive layer 56 is not limited to the epoxy resin thermosetting film adhesive, and uses a thermoplastic film adhesive such as an acrylic resin film adhesive or a thermoplastic polyimide resin film adhesive. May be. The first adhesive layer 56 is not limited to being formed of a resin film adhesive, and may be formed by applying a varnish-like resin liquid to the surface of the insulating resin plate 52.

マスキング層は、第１接着層５６に設けられる。図６は、マスキング層５８を設けた状態を示す断面図である。マスキング層５８には、例えば、合成樹脂フィルムが用いられる。合成樹脂フィルムには、例えば、厚みが２５μｍのポリイミド樹脂フィルムを用いることが好ましい。勿論、合成樹脂フィルムには、ポリイミド樹脂フィルムに限定されることなく、ポリエチレンテレフタレート（ＰＥＴ）樹脂フィルムやポリエチレンナフタレート（ＰＥＮ）樹脂フィルム等を用いることができる。また、マスキング樹脂フィルムには、ＵＶ照射によって接着や剥離が可能な樹脂フィルムを用いてもよい。   The masking layer is provided on the first adhesive layer 56. FIG. 6 is a cross-sectional view showing a state in which the masking layer 58 is provided. For the masking layer 58, for example, a synthetic resin film is used. For the synthetic resin film, for example, a polyimide resin film having a thickness of 25 μm is preferably used. Of course, the synthetic resin film is not limited to a polyimide resin film, and a polyethylene terephthalate (PET) resin film, a polyethylene naphthalate (PEN) resin film, or the like can be used. The masking resin film may be a resin film that can be bonded or peeled off by UV irradiation.

ここで、導体回路５４が形成された絶縁樹脂板５２と、第１接着層５６と、マスキング層５８とは、加熱圧着されて積層される。加熱圧着には、例えば、真空ラミネータ等を用いて、減圧下の雰囲気中にて、樹脂フィルム接着剤の硬化温度以下の加熱温度で、例えば、０．３ＭＰａの圧力でプレスして加熱圧着される。   Here, the insulating resin plate 52 on which the conductor circuit 54 is formed, the first adhesive layer 56, and the masking layer 58 are laminated by thermocompression bonding. For thermocompression bonding, for example, using a vacuum laminator or the like, pressing is performed at a heating temperature equal to or lower than the curing temperature of the resin film adhesive at a pressure of 0.3 MPa, for example, in an atmosphere under reduced pressure. .

接続穴は、絶縁樹脂板５２と第１接着層５６とマスキング層５８とに貫通して、導体回路５４と接続させて形成される。図７は、接続穴６０を形成した状態を示す断面図である。接続穴６０は、絶縁樹脂板５２と第１接着層５６とマスキング層５８とを、例えば、ＹＡＧレーザ等でレーザ加工することにより形成される。レーザ加工に用いられるレーザには、ＹＡＧレーザに限定されることなく、炭酸ガスレーザやエキシマレーザ等を用いてもよい。また、レーザ加工だけでなく、ドリル加工や化学的エッチング加工により貫通穴を形成してもよい。   The connection hole is formed through the insulating resin plate 52, the first adhesive layer 56, and the masking layer 58 and connected to the conductor circuit 54. FIG. 7 is a cross-sectional view illustrating a state in which the connection hole 60 is formed. The connection hole 60 is formed by laser processing the insulating resin plate 52, the first adhesive layer 56, and the masking layer 58 with, for example, a YAG laser or the like. The laser used for laser processing is not limited to a YAG laser, and a carbon dioxide laser, an excimer laser, or the like may be used. Further, the through hole may be formed not only by laser processing but also by drilling or chemical etching.

次に、接続穴６０は、プラズマデスミア処理等でデスミア処理される。プラズマデスミア処理の使用ガスには、ＣＦ４及びＯ２混合ガス、Ａｒガス等の不活性ガス等を用いることができる。また、デスミア処理には、ドライ処理だけでなく、薬液を用いたウエットデスミア処理を用いてもよい。 Next, the connection hole 60 is subjected to a desmear process such as a plasma desmear process. As the gas used for the plasma desmear treatment, an inert gas such as CF 4 and O 2 mixed gas, Ar gas, or the like can be used. Further, in the desmear process, not only a dry process but also a wet desmear process using a chemical solution may be used.

導電性ペースト電極は、接続穴６０に導電性ペーストを充填した後、マスキング層５８を除去して形成される。図８は、接続穴６０に導電性ペースト６２を充填した状態を示す断面図である。導電性ペースト６２は、電気抵抗が小さい金属粒子と、低融点金属粒子と、バインダと、を含んで構成される。電気抵抗が小さい金属粒子には、ニッケル（Ｎｉ）、銀（Ａｇ）、銅（Ｃｕ）から選択される少なくとも１種類の金属粒子が用いられる。低融点金属粒子には、錫（Ｓｎ）、ビスマス（Ｂｉ）、インジウム（Ｉｎ）、鉛（Ｐｂ）から選択される少なくとも１種類の低融点金属粒子が用いられる。バインダには、エポキシ樹脂を主成分とする材料が用いられる。導電性ペースト６２は、例えば、スクリーン印刷法等により接続穴６０に充填される。   The conductive paste electrode is formed by removing the masking layer 58 after filling the connection hole 60 with the conductive paste. FIG. 8 is a cross-sectional view illustrating a state in which the connection hole 60 is filled with the conductive paste 62. The conductive paste 62 includes metal particles having low electrical resistance, low melting point metal particles, and a binder. As the metal particles having a small electric resistance, at least one kind of metal particles selected from nickel (Ni), silver (Ag), and copper (Cu) is used. As the low melting point metal particles, at least one kind of low melting point metal particles selected from tin (Sn), bismuth (Bi), indium (In), and lead (Pb) is used. For the binder, a material mainly composed of an epoxy resin is used. The conductive paste 62 is filled in the connection hole 60 by, for example, a screen printing method or the like.

マスキング層５８は、導電性ペースト６２を接続穴６０に充填した後、除去される。図９は、マスキング層５８を除去した状態を示す断面図である。マスキング層５８が第１接着層５６から除去されることにより、マスキング層５８の厚みを有する突起部を含む導電性ペースト電極６４が形成される。   The masking layer 58 is removed after filling the connection holes 60 with the conductive paste 62. FIG. 9 is a cross-sectional view showing a state where the masking layer 58 is removed. By removing the masking layer 58 from the first adhesive layer 56, the conductive paste electrode 64 including the protrusion having the thickness of the masking layer 58 is formed.

以上により配線基材が成形される。図１０は、成形された配線基材７０を示す断面図である。マスキング層５８を除去した後、例えば、所定箇所で切断して分割することにより、複数の配線基材７０が成形される。   The wiring substrate is formed as described above. FIG. 10 is a cross-sectional view showing the molded wiring substrate 70. After removing the masking layer 58, for example, by cutting and dividing at a predetermined location, a plurality of wiring base materials 70 are formed.

次に、半導体部材を成形する半導体部材成形工程について説明する。   Next, a semiconductor member molding process for molding a semiconductor member will be described.

半導体部材成形工程は、半導体素子の素子回路電極位置に第１開口を設けて第１絶縁層を形成する工程と、第１開口に導電性材料で再配線層を形成する工程と、再配線層の所定位置に第２開口を設けて第２絶縁層を形成する工程とを有している。   The semiconductor member forming step includes a step of forming a first insulating layer by providing a first opening at an element circuit electrode position of a semiconductor element, a step of forming a rewiring layer with a conductive material in the first opening, and a rewiring layer. Forming a second insulating layer by providing a second opening at a predetermined position.

図１１は、半導体部材の成形方法を示す断面図であり、図１１（ａ）は、ウエハ状半導体素子板７２を示す断面図であり、図１１（ｂ）は、第１絶縁層７４を形成した状態を示す断面図であり、図１１（ｃ）は、再配線層７６を形成した状態を示す断面図であり、図１１（ｄ）は、第２絶縁層７８を形成した状態を示す断面図であり、図１１（ｅ）は、個片化された半導体部材８０を示す断面図である。   FIG. 11 is a cross-sectional view showing a method for forming a semiconductor member, FIG. 11 (a) is a cross-sectional view showing a wafer-like semiconductor element plate 72, and FIG. 11 (b) shows the formation of a first insulating layer 74. 11C is a cross-sectional view showing a state where the rewiring layer 76 is formed, and FIG. 11D is a cross-sectional view showing a state where the second insulating layer 78 is formed. FIG. 11E is a cross-sectional view showing the semiconductor member 80 divided into pieces.

ダイジング前のウエハ状半導体素子板７２は、図１１（ａ）に示すように、素子回路面に、Ａｌパッド等の素子回路電極８２と、パッシベーション層８４とを有している。パッシベーション層８４は、酸化珪素や窒化珪素等の無機絶縁層で形成される。   As shown in FIG. 11A, the wafer-like semiconductor element plate 72 before dicing has an element circuit electrode 82 such as an Al pad and a passivation layer 84 on the element circuit surface. The passivation layer 84 is formed of an inorganic insulating layer such as silicon oxide or silicon nitride.

第１絶縁層７４は、図１１（ｂ）に示すように、ウエハ状半導体素子板７２の素子回路電極部位に第１開口８６を設けて形成される。第１絶縁層７４は、例えば、ポリイミド樹脂等の絶縁性樹脂で形成される。第１絶縁層７４は、ウエハ状半導体素子板７２の素子回路面に、液状の感光性ポリイミド前駆体をスピンコートし、フォトリソグラフィによってコンタクトホールである第１開口８６を形成した後、焼成して、例えば、１０μｍの厚みで形成される。   As shown in FIG. 11B, the first insulating layer 74 is formed by providing a first opening 86 in the element circuit electrode portion of the wafer-like semiconductor element plate 72. The first insulating layer 74 is formed of an insulating resin such as a polyimide resin, for example. The first insulating layer 74 is formed by spin-coating a liquid photosensitive polyimide precursor on the element circuit surface of the wafer-like semiconductor element plate 72 and forming a first opening 86 as a contact hole by photolithography, followed by baking. For example, it is formed with a thickness of 10 μm.

再配線層７６は、図１１（ｃ）に示すように、第１開口８６に導電性材料で形成される。導電性材料には、銅材料や銀材料等が用いられる。再配線層７６は、セミアディティブ法を用いて、素子回路電極８２の直上または素子回路電極８２の直上と第１絶縁層７４の直上とに、例えば、厚み５μｍで形成される。   The rewiring layer 76 is formed of a conductive material in the first opening 86 as shown in FIG. As the conductive material, a copper material, a silver material, or the like is used. The redistribution layer 76 is formed with a thickness of 5 μm, for example, immediately above the element circuit electrode 82 or directly above the element circuit electrode 82 and directly above the first insulating layer 74 using a semi-additive method.

第２絶縁層７８は、図１１（ｄ）に示すように、再配線層７６の所定位置に第２開口８８を設けて第２絶縁層７８を形成する工程である。第２絶縁層７８は、例えば、ポリイミド樹脂等の絶縁性樹脂で形成される。第２絶縁層７８は、液状の感光性ポリイミド前駆体をスピンコートし、フォトリソグラフィによってコンタクトホールである第２開口８８を形成した後、焼成して、例えば、厚み５μｍで形成される。   The second insulating layer 78 is a step of forming the second insulating layer 78 by providing a second opening 88 at a predetermined position of the rewiring layer 76 as shown in FIG. The second insulating layer 78 is formed of an insulating resin such as a polyimide resin, for example. The second insulating layer 78 is formed with a thickness of 5 μm, for example, by spin-coating a liquid photosensitive polyimide precursor, forming a second opening 88 as a contact hole by photolithography, and then baking.

ここで、第１絶縁層７４と第２絶縁層７８とにより、上述した第１絶縁体３４ａと第２絶縁体３４ｂとが形成される。なお、第１絶縁層７４と第２絶縁層７８とを形成する合成樹脂は、ポリイミド樹脂に限定されることなく、ベンゾシクロブテン（ＢＣＢ）樹脂、ポリベンゾビスオキサゾール（ＰＢＯ）樹脂等を用いることができる。また、感光性樹脂は、スピンコートに限定されることなく、カーテンコート、スクリーン印刷、スプレーコート等で塗布されてもよい。第１絶縁層７４と第２絶縁層７８とは、感光性樹脂フィルムを半導体素子にラミネートして形成してもよい。   Here, the first insulating layer 74 and the second insulating layer 78 form the first insulator 34 a and the second insulator 34 b described above. Note that the synthetic resin forming the first insulating layer 74 and the second insulating layer 78 is not limited to polyimide resin, and benzocyclobutene (BCB) resin, polybenzobisoxazole (PBO) resin, or the like is used. Can do. The photosensitive resin is not limited to spin coating, and may be applied by curtain coating, screen printing, spray coating, or the like. The first insulating layer 74 and the second insulating layer 78 may be formed by laminating a photosensitive resin film on a semiconductor element.

プロービングにより検査を行った後、第１絶縁層７４、第２絶縁層７８及び再配線層７６が設けられた素子回路面と反対側の素子基板面を、砥石による研削や、機械的または化学的なポリッシング等することにより、ウエハ状半導体素子板７２を、例えば、総厚８５μｍまで薄型加工する。その後、ダイジングによってウエハ状半導体素子板７２を個片化する。それにより、図１１（ｅ）に示すように、複数の半導体部材８０が成形される。なお、半導体素子の回路には、通常の導電用回路の他、インダクタ、キャパシタ、抵抗等の機能を付与させることができる。   After inspection by probing, the element substrate surface opposite to the element circuit surface provided with the first insulating layer 74, the second insulating layer 78, and the rewiring layer 76 is ground with a grindstone, mechanically or chemically. By performing polishing or the like, the wafer-shaped semiconductor element plate 72 is thinned to a total thickness of 85 μm, for example. Thereafter, the wafer-like semiconductor element plate 72 is separated into pieces by dicing. Thereby, as shown in FIG.11 (e), the several semiconductor member 80 is shape | molded. The semiconductor element circuit can be provided with functions such as an inductor, a capacitor, and a resistor in addition to a normal conductive circuit.

配線ベース基材成形工程（Ｓ１４）は、配線ベース基材を成形する工程である。図１２は、配線ベース基材９０の構成を示す断面図である。配線ベース基材９０は、絶縁樹脂ベース板９２と、絶縁樹脂ベース板９２に設けられる第２接着層９４とを有している。   The wiring base substrate forming step (S14) is a step of forming the wiring base substrate. FIG. 12 is a cross-sectional view showing the configuration of the wiring base substrate 90. The wiring base substrate 90 has an insulating resin base plate 92 and a second adhesive layer 94 provided on the insulating resin base plate 92.

絶縁樹脂ベース板９２には、絶縁樹脂板５２と同様にポリイミド樹脂フィルム等が用いられる。また、第２接着層９４には、第１接着層５６と同様にエポキシ樹脂系の熱硬化性フィルム接着剤等が用いられる。絶縁樹脂ベース板９２と第２接着層９４とは、例えば、真空ラミネータ等を用いて、減圧下の雰囲気中にて、樹脂フィルム接着剤の硬化温度以下の加熱温度で、例えば、０．３ＭＰａの圧力でプレスして加熱圧着される。以上により、複数の配線ベース基材９０が成形される。   A polyimide resin film or the like is used for the insulating resin base plate 92 as in the case of the insulating resin plate 52. In addition, an epoxy resin thermosetting film adhesive or the like is used for the second adhesive layer 94 similarly to the first adhesive layer 56. The insulating resin base plate 92 and the second adhesive layer 94 are, for example, a vacuum laminator or the like at a heating temperature equal to or lower than the curing temperature of the resin film adhesive in an atmosphere under reduced pressure, for example, 0.3 MPa. Pressed with pressure and heat-bonded. Thus, a plurality of wiring base substrates 90 are formed.

接続部材成形工程（Ｓ１６）は、接続部材４０を成形する工程である。図１３は、接続部材４０の構成を示す断面図である。接続部材４０は、絶縁樹脂シート４２と、絶縁樹脂シート４２の一方の面に形成される導電層４４と、を有している。接続部材４０には、銅箔にポリイミドワニスを塗布してワニスを硬化させる、いわゆるキャスティング法により成形された部材を用いてもよいし、ポリイミド樹脂フィルム等の絶縁樹脂シートに導電性シード層をスパッタリング法で形成し、導電性シード層に電解銅めっき法等で銅層を形成して成形した部材を用いてもよいし、圧延銅箔または電解銅箔と、ポリイミド樹脂フィルム等の絶縁樹脂シートと、を接着剤で貼り合わせて成形した部材を用いてもよい。以上により、接続部材４０が成形される。   The connecting member forming step (S16) is a step of forming the connecting member 40. FIG. 13 is a cross-sectional view showing the configuration of the connection member 40. The connecting member 40 includes an insulating resin sheet 42 and a conductive layer 44 formed on one surface of the insulating resin sheet 42. The connection member 40 may be a member formed by a so-called casting method in which a polyimide varnish is applied to a copper foil to cure the varnish, or a conductive seed layer is sputtered onto an insulating resin sheet such as a polyimide resin film. A member formed by forming a copper layer on the conductive seed layer by electrolytic copper plating or the like may be used, or a rolled copper foil or electrolytic copper foil, and an insulating resin sheet such as a polyimide resin film Alternatively, a member formed by bonding together with an adhesive may be used. Thus, the connection member 40 is formed.

配線基材積層体形成工程（Ｓ１８）は、配線基材７０と半導体部材８０と配線ベース基材９０と接続部材４０と、を積層して、配線基材積層体を形成する工程である。図１４は、配線基材積層体１００の積層構成を示す断面図である。   The wiring substrate laminate formation step (S18) is a step of forming the wiring substrate laminate by laminating the wiring substrate 70, the semiconductor member 80, the wiring base substrate 90, and the connection member 40. FIG. 14 is a cross-sectional view showing a laminated configuration of the wiring substrate laminate 100.

まず、第１配線ベース基材９０ａと第２配線ベース基材９０ｂとは、接続部材４０の長さより短い間隔を設けて配置される。また、第１配線ベース基材９０ａと第２配線ベース基材９０ｂとは、第２接着層９４を同じ方向である、例えば、上側に向けて配置される。   First, the first wiring base base material 90 a and the second wiring base base material 90 b are arranged with an interval shorter than the length of the connection member 40. The first wiring base substrate 90a and the second wiring base substrate 90b are arranged with the second adhesive layer 94 in the same direction, for example, upward.

接続部材４０は、第１配線ベース基材９０ａと第２配線ベース基材９０ｂとの間に積層される。接続部材４０は、その一端が第１配線ベース基材９０ａの第２接着層９４に置かれ、他端が第２配線ベース基材９０ｂの第２接着層９４に置かれて積層される。接続部材４０は、絶縁樹脂シート４２を第２接着層９４に接触させて積層される。   The connecting member 40 is laminated between the first wiring base substrate 90a and the second wiring base substrate 90b. One end of the connection member 40 is placed on the second adhesive layer 94 of the first wiring base substrate 90a, and the other end is placed on the second adhesive layer 94 of the second wiring base substrate 90b. The connecting member 40 is laminated by bringing the insulating resin sheet 42 into contact with the second adhesive layer 94.

次に、第１半導体部材８０ａが第１配線ベース基材９０ａに積層され、第２半導体部材８０ｂが第２配線ベース基材９０ｂに積層される。第１半導体部材８０ａと第２半導体部材８０ｂとは、第１配線ベース基材９０ａと第２配線ベース基材９０ｂとの第２接着層９４に、素子回路面と反対側である素子基板面を向けて積層される。また、第１半導体部材８０ａと第２半導体部材８０ｂとの周りには、スペーサ１０２ａ、１０２ｂを積層してもよい。   Next, the first semiconductor member 80a is laminated on the first wiring base substrate 90a, and the second semiconductor member 80b is laminated on the second wiring base substrate 90b. The first semiconductor member 80a and the second semiconductor member 80b have an element substrate surface opposite to the element circuit surface on the second adhesive layer 94 of the first wiring base substrate 90a and the second wiring base substrate 90b. Laminated. In addition, spacers 102a and 102b may be stacked around the first semiconductor member 80a and the second semiconductor member 80b.

次に、第１配線基材７０ａと第２配線基材７０ｂとが、第１半導体部材８０ａと第２半導体部材８０ｂと接続部材４０とに積層される。第１配線基材７０ａは、一端の導電性ペースト電極６４ａを接続部材４０の導電層４４と接触させ、所定の導電性ペースト電極６４ｂを第１半導体部材８０ａの再配線層７６と接触させて積層される。また、第２配線基材７０ｂは、一端の導電性ペーストビア６４ａを接続部材４０の導電層４４と接触させ、所定の導電性ペーストビア６４ｂを第２半導体部材８０ｂの再配線層７６と接触させて積層される。   Next, the first wiring substrate 70a and the second wiring substrate 70b are laminated on the first semiconductor member 80a, the second semiconductor member 80b, and the connection member 40. The first wiring substrate 70a is laminated by bringing the conductive paste electrode 64a at one end into contact with the conductive layer 44 of the connection member 40 and bringing the predetermined conductive paste electrode 64b into contact with the rewiring layer 76 of the first semiconductor member 80a. Is done. Further, the second wiring substrate 70b has the conductive paste via 64a at one end in contact with the conductive layer 44 of the connection member 40 and the predetermined conductive paste via 64b in contact with the rewiring layer 76 of the second semiconductor member 80b. Are stacked.

ここで、第１配線基材７０ａと第１半導体部材８０ａとは、半導体チップ用マウンタ等で位置合わせされ、第１接着層５６及び導電性ペースト電極６４ａ、６４ｂに含まれるバインダの硬化温度以下の温度で加熱して予め仮留めしておくことが好ましい。第１配線基材７０ａと第１半導体部材８０ａとの積層がより容易になるからである。また、第２配線基材７０ｂと第２半導体部材８０ｂについても、予め仮留めしておくことが好ましい。なお、第１配線基材７０ａと第２配線基材７０ｂとの上に、更に、他の配線基材１０４ａ、１０４ｂを積層してもよい。以上により配線基材積層体１００が形成される。   Here, the first wiring substrate 70a and the first semiconductor member 80a are aligned by a semiconductor chip mounter or the like, and are equal to or lower than the curing temperature of the binder contained in the first adhesive layer 56 and the conductive paste electrodes 64a and 64b. It is preferable to preliminarily preliminarily fasten by heating at a temperature. This is because it becomes easier to stack the first wiring substrate 70a and the first semiconductor member 80a. Further, it is preferable that the second wiring base material 70b and the second semiconductor member 80b are temporarily secured in advance. In addition, other wiring base materials 104a and 104b may be further laminated on the first wiring base material 70a and the second wiring base material 70b. Thus, the wiring substrate laminate 100 is formed.

配線予備成形体成形工程（Ｓ２０）は、配線基材積層体１００に含まれる第１接着層５６と第２接着層９４とを硬化させることにより一体化して配線予備成形体を成形する工程である。図１５は、配線予備成形体１１０の構成を示す断面図である。   The wiring preform body molding step (S20) is a step of molding the wiring preform body by integrating the first adhesive layer 56 and the second adhesive layer 94 included in the wiring substrate laminate 100 by curing. . FIG. 15 is a cross-sectional view showing the configuration of the wiring preform 110. As shown in FIG.

配線予備成形体１１０は、配線基材積層体１００を、例えば、真空キュアプレス機を用いて１ｋＰａ以下の減圧雰囲気中で加熱圧着し一体化して成形される。配線基材積層体１００を加熱圧着することにより、半硬化状態の第１接着層５６と第２接着層９４とを加熱硬化して配線予備成形体１１０が予備成形される。なお、第１接着層５６及び第２接着層９４である層間接着剤の硬化と同時に、導電性ペースト電極６４の硬化と合金化とを行って上述した貫通電極２３ａ、２４ａ、２３ｂ、２４ｂが形成される。なお、第１接着層５６と第２接着層９４とを加熱圧着によりフローさせて硬化させることにより、上述した第１絶縁樹脂基材１６ａと第２絶縁樹脂基材１６ｂとが形成される。   The wiring preform 110 is integrally formed by thermocompression bonding the wiring substrate laminate 100 using, for example, a vacuum curing press in a reduced pressure atmosphere of 1 kPa or less. By thermocompression bonding the wiring substrate laminate 100, the semi-cured first adhesive layer 56 and the second adhesive layer 94 are heat cured to preform the wiring preform 110. The above-described through electrodes 23a, 24a, 23b, and 24b are formed by curing and alloying the conductive paste electrode 64 simultaneously with the curing of the interlayer adhesive that is the first adhesive layer 56 and the second adhesive layer 94. Is done. In addition, the 1st insulating resin base material 16a and the 2nd insulating resin base material 16b mentioned above are formed by making the 1st contact bonding layer 56 and the 2nd contact bonding layer 94 flow and harden | cure by thermocompression bonding.

配線予備成形体１１０は、第１配線基材７０ａと第１半導体部材８０ａと第１配線ベース基材９０ａとを一体化した第１配線予備成形基体１１２ａと、第２配線基材７０ｂと第２半導体部材８０ｂと第２配線ベース基材９０ｂとを一体化した第２配線予備成形基体１１２ｂと、第１配線予備成形基体１１２ａと第２配線予備成形基体１１２ｂとを連結し、電気的に接続する接続部材４０とを含んで構成される。図１５に示されるように、配線予備成形体１１０は、接続部材４０の一端と他端との間の部位が第１配線予備成形基体１１２ａ及び第２配線予備成形基体１１２ｂに埋め込まれていないので、接続部材４０から折り曲げることができる。なお、図１５に示される配線予備成形体１１０では、接続部材４０に２個の配線予備成形基体１１２ａ、１１２ｂが連結されているが、３個以上の配線予備成形基体が連結されるようにしてもよい。   The wiring preform 110 includes a first wiring base body 112a in which the first wiring base material 70a, the first semiconductor member 80a, and the first wiring base base material 90a are integrated, a second wiring base material 70b, and a second wiring base material 70a. The second wiring preform base 112b in which the semiconductor member 80b and the second wiring base substrate 90b are integrated, and the first wiring preform base 112a and the second wiring preform base 112b are connected and electrically connected. And a connecting member 40. As shown in FIG. 15, in the wiring preform 110, the portion between one end and the other end of the connection member 40 is not embedded in the first wiring preform 112a and the second wiring preform 112b. The connecting member 40 can be bent. In the wiring preform 110 shown in FIG. 15, two wiring preforms 112a and 112b are connected to the connecting member 40, but three or more wiring preforms are connected. Also good.

接合工程（Ｓ２２）は、接続部材４０を曲げて、第１配線予備成形基体１１２ａと第２配線予備成形基体１１２ｂとを接合する工程である。図１６は、接続部材４０を曲げて接合前のセットアップした状態を示す断面図である。配線予備成形体１１０は、第１配線予備成形基体１１２ａに埋め込まれた第１半導体部材８０ａにおける第１半導体素子の素子基板面と、第２配線予備成形基体１１２ｂに埋め込まれた第２半導体部材８０ｂにおける第２半導体素子の素子基板面とが対向するように、接続部材４０を曲げてセットアップされる。したがって、接続部材４０は、絶縁樹脂シート４２が内周側となり、導電層４４が外周側となるように折り曲げられる。   The joining step (S22) is a step of bending the connection member 40 to join the first wiring preform base 112a and the second wiring preform 112b. FIG. 16 is a cross-sectional view showing a state where the connection member 40 is bent and set up before joining. The wiring preform 110 includes an element substrate surface of the first semiconductor element in the first semiconductor member 80a embedded in the first wiring preform 112a and a second semiconductor member 80b embedded in the second wiring preform 112b. The connection member 40 is bent and set up so that the element substrate surface of the second semiconductor element in FIG. Therefore, the connecting member 40 is bent so that the insulating resin sheet 42 is on the inner peripheral side and the conductive layer 44 is on the outer peripheral side.

第１配線予備成形基体１１２ａと第２配線予備成形基体１１２ｂとの間には、支持部材３９が設けられる。上述したように、支持部材３９は、絶縁樹脂板５２に用いられるポリイミド樹脂フィルム等で形成されることが好ましい。勿論、支持部材３９は、例えば、ガラス繊維クロスにエポキシ樹脂系の熱硬化性樹脂を含浸して硬化させたいわゆるガラス繊維強化エポキシ樹脂基板、焼成セラミックス等の硬質基材や、放熱特性に優れた金属材料等で形成されてもよい。また、支持部材３９の両面に設けられる接着層１１４は、例えば、エポキシ樹脂系の熱硬化性フィルム接着剤等で形成される。   A support member 39 is provided between the first wiring preform base 112a and the second wiring preform base 112b. As described above, the support member 39 is preferably formed of a polyimide resin film or the like used for the insulating resin plate 52. Of course, the support member 39 has excellent heat dissipation characteristics, for example, a so-called glass fiber reinforced epoxy resin substrate in which a glass fiber cloth is impregnated with an epoxy resin thermosetting resin and cured, or a fired ceramic. You may form with a metal material etc. The adhesive layers 114 provided on both surfaces of the support member 39 are formed of, for example, an epoxy resin thermosetting film adhesive.

ここで、接続部材４０は、その内周面への接着剤の流れ込みによる固着を抑えるため、第１配線予備成形基体１１２ａと第２配線予備成形基体１１２ｂと支持部材３９との間に中空状の隙間４６を設けて配置される。なお、中空状の隙間４６の大きさは、支持部材３９の厚みを変えることにより調整可能である。そして、第１配線予備成形基体１１２ａと第２配線予備成形基体１１２ｂと支持部材３９とは、例えば、真空キュアプレス機を用いて１ｋＰａ以下の減圧雰囲気中で加熱圧着して接合される。   Here, the connection member 40 has a hollow shape between the first wiring pre-formed base 112a, the second wiring pre-formed base 112b, and the support member 39 in order to suppress sticking due to the flow of the adhesive to the inner peripheral surface. A gap 46 is provided. Note that the size of the hollow gap 46 can be adjusted by changing the thickness of the support member 39. The first wiring preform base 112a, the second wiring preform 112b, and the support member 39 are bonded by thermocompression bonding in a reduced pressure atmosphere of 1 kPa or less using, for example, a vacuum curing press.

以上により複数の半導体素子が埋め込まれたプリント配線基板１０の製造が完了する。なお、上記構成では、第１配線予備成形基体１１２ａと第２配線予備成形基体１１２ｂとの間に支持部材３９を設けてプリント配線基板１０を製造したが、支持部材３９を設けないで、第１配線予備成形基体１１２ａと第２配線予備成形基体１１２ｂとを接着層１１４で直接接着して製造してもよい。図１７は、支持部材３９を設けないで製造したプリント配線基板１０を示す断面図である。第１配線予備成形基体１１２ａと第２配線予備成形基体１１２ｂとの間に、例えば、エポキシ樹脂系の熱硬化性フィルム接着剤等の接着層１１４を挟んで、上述した硬化条件で接着剤を硬化させることにより、第１配線予備成形基体１１２ａと第２配線予備成形基体１１２ｂとを接合してプリント配線基板を製造することができる。   Thus, the manufacture of the printed wiring board 10 in which a plurality of semiconductor elements are embedded is completed. In the above configuration, the printed wiring board 10 is manufactured by providing the support member 39 between the first wiring preform base 112a and the second wiring preform base 112b, but the first member without the support member 39 is provided. The wiring preform body 112a and the second wiring preform body 112b may be directly bonded by the adhesive layer 114 for manufacturing. FIG. 17 is a cross-sectional view showing the printed wiring board 10 manufactured without providing the support member 39. For example, an adhesive layer 114 such as an epoxy resin-based thermosetting film adhesive is sandwiched between the first wiring preform base 112a and the second wiring preform base 112b, and the adhesive is cured under the above-described curing conditions. By doing so, the printed wiring board can be manufactured by bonding the first wiring preform base 112a and the second wiring preform 112b.

上記構成によれば、第１配線部と第２配線部とは、第１半導体素子の素子回路面と反対側の素子基板面と、第２半導体素子の素子回路面と反対側の素子基板面とを対向させて配置されることにより、支持部材に対して略対称に配置されるため、多層化されたプリント配線基板の反りが抑えられる。   According to the above configuration, the first wiring portion and the second wiring portion are the element substrate surface opposite to the element circuit surface of the first semiconductor element and the element substrate surface opposite to the element circuit surface of the second semiconductor element. Are arranged substantially symmetrically with respect to the support member, so that warpage of the multilayered printed wiring board can be suppressed.

上記構成によれば、第１配線部と第２配線部とは、第１半導体素子の素子回路面と反対側の素子基板面と、第２半導体素子の素子回路面と反対側の素子基板面とを対向させて配置されることによりスタック段数が抑えられるので、ビアの直上にビアが配置される構造（いわゆるビアオンビア構造）よりも貫通電極であるビアの接続性が向上する。それにより、プリント配線基板の電気的な接続信頼性が向上する。   According to the above configuration, the first wiring portion and the second wiring portion are the element substrate surface opposite to the element circuit surface of the first semiconductor element and the element substrate surface opposite to the element circuit surface of the second semiconductor element. Since the number of stacks is reduced by arranging them so as to face each other, the connectivity of vias, which are through electrodes, is improved over a structure in which vias are arranged immediately above the vias (so-called via-on-via structure). Thereby, the electrical connection reliability of the printed wiring board is improved.

上記構成によれば、接続部材の導電層が、第１配線部材の一端に置かれる第１貫通電極と、第２配線部材の一端に置かれる第２貫通電極とに接続されることにより、第１配線部と第２配線部とが電気的に接続されるので、ビルドアップ多層配線板で使用されるめっきビアが不要になり、めっき工程中の煩雑なウエットプロセスを省略できるので生産性が向上する。   According to the above configuration, the conductive layer of the connection member is connected to the first through electrode placed at one end of the first wiring member and the second through electrode placed at one end of the second wiring member, so that the first Since the 1st wiring part and the 2nd wiring part are electrically connected, the plating via used in the build-up multilayer wiring board is unnecessary, and the complicated wet process during the plating process can be omitted, thus improving productivity. To do.

上記構成によれば、接続部材は、その一端と他端との間の部位を、第１絶縁樹脂基材及び第２絶縁樹脂基材から突出させて、例えば、環状に折り曲げられることにより、第１絶縁樹脂基材及び第２絶縁樹脂基材との間に中空状の隙間を空けて設けられる。そのため、接続部材の一端と他端との間の部位は、第１絶縁樹脂基材及び第２絶縁樹脂基材に埋め込まれていないので、プリント配線基板の積層方向の熱膨張等の膨張に対して変形して追従し、プリント配線基板の厚さ方向に生じる熱応力を緩和して、電気的接続の信頼性を向上させることができる。   According to the above configuration, the connecting member protrudes from the first insulating resin base material and the second insulating resin base material at a portion between one end and the other end, and is bent, for example, in an annular shape. A hollow gap is provided between the first insulating resin base material and the second insulating resin base material. Therefore, the part between the one end and the other end of the connecting member is not embedded in the first insulating resin base material and the second insulating resin base material, and therefore, against expansion such as thermal expansion in the stacking direction of the printed wiring board. Thus, the thermal stress generated in the thickness direction of the printed wiring board can be relaxed and the reliability of electrical connection can be improved.

上記構成によれば、配線基材に予め導体回路が形成された片面銅張板を用い、層間の電気接続に導電性ペーストを印刷充填して形成したビアである導電性ペーストビアを用いていることにより、従来のビルドアップ方式に比べてめっき工程をより削減できるので、プリント配線基板の生産時間をより短縮して生産性を向上させることができる。   According to the above configuration, the conductive paste via, which is a via formed by printing and filling the conductive paste for the interlayer electrical connection, is used using the single-sided copper-clad plate in which the conductor circuit is previously formed on the wiring substrate. As a result, the plating process can be further reduced as compared with the conventional build-up method, so that the production time of the printed wiring board can be further shortened and the productivity can be improved.

上記構成によれば、配線基材と半導体部材と配線ベース基材と接続部材とは別工程で作製されることにより、各工程で不良品が生じた場合でもその都度排除できるので、プリント配線基板の生産性を向上させることができる。   According to the above configuration, since the wiring base material, the semiconductor member, the wiring base base material, and the connection member are produced in separate processes, even if a defective product is generated in each process, it can be eliminated each time. Productivity can be improved.

上記構成によれば、貫通電極の形成に用いられる導電性ペーストに、第１接着層及び第２接着層に使用される層間接着剤の硬化温度程度の低温で合金化する組成を適用することにより、導電性ペースト内の金属粒子同士、また、導体回路を形成する銅の接続パッドと導電性ペースト内の金属粒子が拡散接合し、バルクの金属やめっきによる層間接続と同等の接続信頼性を確保することができる。   According to the above configuration, by applying a composition that is alloyed at a low temperature, such as the curing temperature of the interlayer adhesive used for the first adhesive layer and the second adhesive layer, to the conductive paste used for forming the through electrode. In addition, the metal particles in the conductive paste and the copper connection pads that form the conductor circuit and the metal particles in the conductive paste are diffusion bonded to ensure the same connection reliability as bulk metal or interlayer connection by plating. can do.

本発明の実施の形態において、プリント配線基板の構成を示す断面図である。In embodiment of this invention, it is sectional drawing which shows the structure of a printed wiring board. 本発明の実施の形態において、プリント配線基板の製造方法を示すフローチャートである。In embodiment of this invention, it is a flowchart which shows the manufacturing method of a printed wiring board. 本発明の実施の形態において、一方の面に銅層が設けられた絶縁樹脂板の構成を示す断面図である。In embodiment of this invention, it is sectional drawing which shows the structure of the insulating resin board in which the copper layer was provided in one surface. 本発明の実施の形態において、絶縁樹脂板に形成された導体回路の構成を示す断面図である。In embodiment of this invention, it is sectional drawing which shows the structure of the conductor circuit formed in the insulating resin board. 本発明の実施の形態において、第１接着層を設けた状態を示す断面図である。In embodiment of this invention, it is sectional drawing which shows the state which provided the 1st contact bonding layer. 本発明の実施の形態において、マスキング層を設けた状態を示す断面図である。In embodiment of this invention, it is sectional drawing which shows the state which provided the masking layer. 本発明の実施の形態において、接続穴を形成した状態を示す断面図である。In embodiment of this invention, it is sectional drawing which shows the state which formed the connection hole. 本発明の実施の形態において、接続穴に導電性ペーストを充填した状態を示す断面図である。In embodiment of this invention, it is sectional drawing which shows the state which filled the connection hole with the electrically conductive paste. 本発明の実施の形態において、マスキング層を除去した状態を示す断面図である。In embodiment of this invention, it is sectional drawing which shows the state which removed the masking layer. 本発明の実施の形態において、成形された配線基材を示す断面図である。In embodiment of this invention, it is sectional drawing which shows the shape | molded wiring base material. 本発明の実施の形態において、半導体部材の成形方法を示す断面図である。In embodiment of this invention, it is sectional drawing which shows the shaping | molding method of a semiconductor member. 本発明の実施の形態において、配線ベース基材の構成を示す断面図である。In embodiment of this invention, it is sectional drawing which shows the structure of a wiring base base material. 本発明の実施の形態において、接続部材の構成を示す断面図である。In embodiment of this invention, it is sectional drawing which shows the structure of a connection member. 本発明の実施の形態において、配線基材積層体の積層構成を示す断面図である。In embodiment of this invention, it is sectional drawing which shows the laminated structure of a wiring base-material laminated body. 本発明の実施の形態において、配線予備成形体の構成を示す断面図である。In embodiment of this invention, it is sectional drawing which shows the structure of a wiring preform. 本発明の実施の形態において、接続部材を曲げて接合前のセットアップした状態を示す断面図である。In embodiment of this invention, it is sectional drawing which shows the state set up before joining by bending a connection member. 本発明の実施の形態において、支持部材を設けないで製造したプリント配線基板を示す断面図である。In embodiment of this invention, it is sectional drawing which shows the printed wiring board manufactured without providing a supporting member.

符号の説明Explanation of symbols

１０ プリント配線基板
１２ａ 第１配線部材
１２ｂ 第２配線部材
１４ａ、８０ａ 第１半導体部材
１４ｂ、８０ｂ 第２半導体部材
１６ａ 第１絶縁樹脂基材
１６ｂ 第２絶縁樹脂基材
１８ａ 第１配線部
１８ｂ 第２配線部
２０ａ 第１絶縁樹脂板
２０ｂ 第２絶縁樹脂板
２２ａ 第１導体回路
２２ｂ 第２導体回路
２３ａ、２４ａ 第１貫通電極
２３ｂ、２４ｂ 第２貫通電極
２６ａ、２６ｂ 他の配線部材
３０ａ 第１半導体素子
３０ｂ 第２半導体素子
３２ａ 第１再配線層
３２ｂ 第２再配線層
３４ａ 第１絶縁体
３４ｂ 第２絶縁体
３６ａ 第１スペーサ
３６ｂ 第２スペーサ
３９ 支持部材
４０ 接続部材
４２ 絶縁樹脂シート
４４ 導電層
４６ 中空状の隙間
５０ 銅層
５２ 絶縁樹脂板
５４ 導体回路
５６ 第１接着層
５８ マスキング層
６０ 接続穴
６２ 導電性ペースト
６４ 導電性ペースト電極
７０ 配線基材
７０ａ 第１配線基材
７０ｂ 第２配線基材
７２ ウエハ状半導体素子板
７４ 第１絶縁層
７６ 再配線層
７８ 第２絶縁層
８０ 半導体部材
８２ 素子回路電極
８４ パッシベーション層
８６ 第１開口
８８ 第２開口
９０ 配線ベース基材
９０ａ 第１配線ベース基材
９０ｂ 第２配線ベース基材
９２ 絶縁樹脂ベース板
９４ 第２接着層
１００ 配線基材積層体
１０２ａ、１０２ｂ スペーサ部材
１０４ａ、１０４ｂ 他の配線基材
１１０ 配線予備成形体
１１２ａ 第１配線予備成形基体
１１２ｂ 第２配線予備成形基体
１１４ 接着層 DESCRIPTION OF SYMBOLS 10 Printed wiring board 12a 1st wiring member 12b 2nd wiring member 14a, 80a 1st semiconductor member 14b, 80b 2nd semiconductor member 16a 1st insulating resin base material 16b 2nd insulating resin base material 18a 1st wiring part 18b 2nd Wiring portion 20a First insulating resin plate 20b Second insulating resin plate 22a First conductor circuit 22b Second conductor circuit 23a, 24a First through electrode 23b, 24b Second through electrode 26a, 26b Other wiring member 30a First semiconductor element 30b Second semiconductor element 32a First redistribution layer 32b Second redistribution layer 34a First insulator 34b Second insulator 36a First spacer 36b Second spacer 39 Support member 40 Connection member 42 Insulating resin sheet 44 Conductive layer 46 Hollow Gap 50 50 Copper layer 52 Insulating resin plate 54 Conductor circuit 56 First adhesive layer 58 Masking layer 6 Connection hole 62 Conductive paste 64 Conductive paste electrode 70 Wiring substrate 70a First wiring substrate 70b Second wiring substrate 72 Wafer-like semiconductor element board 74 First insulating layer 76 Rewiring layer 78 Second insulating layer 80 Semiconductor member 82 Element Circuit Electrode 84 Passivation Layer 86 First Opening 88 Second Opening 90 Wiring Base Substrate 90a First Wiring Base Substrate 90b Second Wiring Base Substrate 92 Insulating Resin Base Plate 94 Second Adhesive Layer 100 Wiring Base Laminate 102a, 102b Spacer members 104a, 104b Other wiring base materials 110 Wiring preforms 112a First wiring preform bodies 112b Second wiring preform bodies 114 Adhesive layers

Claims (7)

複数の半導体素子が埋め込まれたプリント配線基板であって、
第１絶縁樹脂板と、前記第１絶縁樹脂板の一方の面に設けられる第１導体回路と、前記第１絶縁樹脂板の他方の面から突出して形成され、前記第１絶縁樹脂板を貫通し、前記第１導体回路と接触させた複数の第１貫通電極と、を有する第１配線部材と、
第１半導体素子と、前記第１半導体素子の素子回路面に設けられ、素子回路電極と前記第１貫通電極とを接続する第１再配線層と、を有する第１半導体部材と、
前記第１半導体部材が埋め込まれ、前記第１配線部材と前記第１半導体部材とを一体化する第１絶縁樹脂基材と、
を含む第１配線部と、
第２絶縁樹脂板と、前記第２絶縁樹脂板の一方の面に設けられる第２導体回路と、前記第２絶縁樹脂板の他方の面から突出して形成され、前記第２絶縁樹脂板を貫通し、前記第２導体回路と接触させた複数の第２貫通電極と、を有する第２配線部材と、
第２半導体素子と、前記第２半導体素子の素子回路面に設けられ、素子回路電極と前記第２貫通電極とを接続する第２再配線層と、を有する第２半導体部材と、
前記第２半導体部材が埋め込まれ、前記第２配線部材と前記第２半導体部材とを一体化する第２絶縁樹脂基材と、
を含む第２配線部と、
を備え、
絶縁樹脂シートと、前記絶縁樹脂シートの一方の面に設けられ、前記第１貫通電極と前記第２貫通電極とに接続される導電層と、を有し、一端が前記第１絶縁樹脂基材に埋め込まれ、他端が前記第２絶縁樹脂基材に埋め込まれ、前記一端と前記他端との間の部位を前記第１絶縁樹脂基材及び前記第２絶縁樹脂基材から突出させた接続部材を含み、
前記第１配線部と前記第２配線部とは、前記第１半導体素子と前記第２半導体素子との前記素子回路面と反対側の素子基板面を各々対向させて略対称に配置され、
前記第１配線部と前記第２配線部との間に、支持部材が接着剤で加熱圧着されて設けられ、
前記接続部材は、前記第１配線部と前記第２配線部と前記支持部材との間に中空状の隙間を設けて配置され、前記接続部材の内周面への前記接着剤の流れ込みによる固着を抑えるため、前記中空状の隙間の大きさが前記支持部材の厚みを変えることにより調整されていることを特徴とするプリント配線基板。 A printed wiring board in which a plurality of semiconductor elements are embedded,
A first insulating resin plate, a first conductor circuit provided on one surface of the first insulating resin plate, and formed to protrude from the other surface of the first insulating resin plate and penetrate through the first insulating resin plate A first wiring member having a plurality of first through electrodes in contact with the first conductor circuit;
A first semiconductor member having a first semiconductor element and a first redistribution layer provided on an element circuit surface of the first semiconductor element and connecting the element circuit electrode and the first through electrode;
A first insulating resin base material in which the first semiconductor member is embedded, and the first wiring member and the first semiconductor member are integrated;
A first wiring portion including:
A second insulating resin plate, a second conductor circuit provided on one surface of the second insulating resin plate, and formed to protrude from the other surface of the second insulating resin plate and penetrate through the second insulating resin plate And a second wiring member having a plurality of second through electrodes in contact with the second conductor circuit,
A second semiconductor member having a second semiconductor element and a second redistribution layer provided on the element circuit surface of the second semiconductor element and connecting the element circuit electrode and the second through electrode;
A second insulating resin base material in which the second semiconductor member is embedded, and the second wiring member and the second semiconductor member are integrated;
A second wiring portion including:
With
An insulating resin sheet; and a conductive layer provided on one surface of the insulating resin sheet and connected to the first through electrode and the second through electrode, one end of the first insulating resin substrate The other end is embedded in the second insulating resin base material, and a portion between the one end and the other end is protruded from the first insulating resin base material and the second insulating resin base material. Including members,
The first wiring portion and the second wiring portion are disposed substantially symmetrically with the element substrate surfaces opposite to the element circuit surfaces of the first semiconductor element and the second semiconductor element facing each other .
Between the first wiring part and the second wiring part, a support member is provided by being hot-pressed with an adhesive,
The connection member is disposed with a hollow gap between the first wiring portion, the second wiring portion, and the support member, and is fixed by the adhesive flowing into the inner peripheral surface of the connection member. to suppress the printed wiring board, wherein Rukoto size of the hollow gap is adjusted by changing the thickness of the support member. 請求項１に記載のプリント配線基板であって、
前記支持部材は、ポリイミド樹脂で成形された樹脂シート、繊維強化樹脂複合材料で成形された複合材料シート、無機材料で成形されたセラミックシート、またはモリブデンやインバー合金を銅で挟持した金属板で形成されていることを特徴とするプリント配線基板。 The printed wiring board according to claim 1,
The support member is formed of a resin sheet formed of polyimide resin, a composite material sheet formed of a fiber reinforced resin composite material, a ceramic sheet formed of an inorganic material, or a metal plate sandwiched between molybdenum or invar alloy with copper. printed circuit board, characterized that you have been. 請求項１または２に記載のプリント配線基板であって、
前記第１絶縁樹脂基材に埋め込まれ、前記第１半導体素子と略同じ厚みを有する第１スペーサまたは前記第２絶縁樹脂基材に埋め込まれ、前記第２半導体素子と略同じ厚みを有する第２スペーサを備えることを特徴とするプリント配線基板。 The printed wiring board according to claim 1 or 2,
A second spacer embedded in the first insulating resin substrate and embedded in the first spacer or the second insulating resin substrate having substantially the same thickness as the first semiconductor element, and having approximately the same thickness as the second semiconductor element. A printed wiring board comprising a spacer. 複数の半導体素子が埋め込まれたプリント配線基板の製造方法であって、
絶縁樹脂板と、前記絶縁樹脂板の一方の面に形成される導体回路と、前記絶縁樹脂板の他方の面に設けられる第１接着層と、前記絶縁樹脂板と前記第１接着層とを貫通し、前記導体回路と導通する複数の導電性ペースト電極と、を含む複数の配線基材を成形する配線基材成形工程と、
半導体素子と、前記半導体素子の素子回路面に設けられ、素子回路電極と前記導電性ペースト電極とを接続する再配線層と、を含む複数の半導体部材とを成形する半導体部材成形工程と、
絶縁樹脂ベース板と、前記絶縁樹脂ベース板の一方の面に設けられる第２接着層と、を含む複数の配線ベース基材とを成形する配線ベース基材成形工程と、
絶縁樹脂シートと、前記絶縁樹脂シートの一方の面に形成される導電層と、を有する接続部材を成形する接続部材成形工程と、
を備え、
前記複数の配線ベース基材の第１配線ベース基材と第２配線ベース基材とは、前記接続部材の長さより短い間隔を設けて、前記第２接着層を同じ向きにして配置され、
前記接続部材は、一端を前記第１配線ベース基材の第２接着層に、他端を前記第２配線ベース基材の第２接着層に、前記絶縁樹脂シートを向けて積層され、
前記複数の半導体部材の第１半導体部材と第２半導体部材とは、前記第１配線ベース基材と前記第２配線ベース基材との第２接着層に、前記素子回路面と反対側の素子基板面を向けて各々積層され、
前記複数の配線基材の第１配線基材と第２配線基材とは、各々一端の導電性ペースト電極を前記接続部材の導電層と接触させ、各々所定の導電性ペースト電極を前記再配線層と接触させて、前記第１半導体部材と前記第２半導体部材と前記接続部材とに積層されて配線基材積層体を形成する配線基材積層体形成工程と、
前記配線基材積層体に含まれる第１接着層と第２接着層とを硬化させて、前記第１配線基材と前記第１半導体部材と前記第１配線ベース基材を一体化させた第１配線予備基体と、前記第２配線基材と前記第２半導体部材と前記第２配線ベース基材を一体化させた第２配線予備基体と、前記第１配線予備基体と前記第２配線予備基体とに接続された接続部材と、を含む配線予備成形体を予備成形する配線予備成形体成形工程と、
前記第１配線予備基体と前記第２配線予備基体とに埋め込まれた各々半導体素子の素子基板面を対向させるように前記接続部材を曲げて前記第１配線予備基体と前記第２配線予備基体とを略対称に配置し、前記第１配線予備基体と前記第２配線予備基体との各々絶縁樹脂ベース板を接合する接合工程と、
を有し、
前記接合工程は、前記第１配線予備基体と前記第２配線予備基体との間に支持部材が挟持されて接着剤で加熱圧着され、
前記接続部材は、前記第１配線部と前記第２配線部と前記支持部材との間に中空状の隙間を設けて配置され、前記接続部材の内周面への前記接着剤の流れ込みによる固着を抑えるため、前記中空状の隙間の大きさが前記支持部材の厚みを変えることにより調整されることを特徴とするプリント配線基板の製造方法。 A method of manufacturing a printed wiring board in which a plurality of semiconductor elements are embedded,
An insulating resin plate, a conductor circuit formed on one surface of the insulating resin plate, a first adhesive layer provided on the other surface of the insulating resin plate, the insulating resin plate and the first adhesive layer A wiring base material forming step for forming a plurality of wiring base materials including a plurality of conductive paste electrodes that pass through and are electrically connected to the conductor circuit;
A semiconductor member forming step of forming a plurality of semiconductor members including a semiconductor element and a rewiring layer provided on the element circuit surface of the semiconductor element and connecting the element circuit electrode and the conductive paste electrode;
A wiring base substrate molding step for molding a plurality of wiring base substrates including an insulating resin base plate and a second adhesive layer provided on one surface of the insulating resin base plate;
A connecting member forming step of forming a connecting member having an insulating resin sheet and a conductive layer formed on one surface of the insulating resin sheet;
With
The first wiring base substrate and the second wiring base substrate of the plurality of wiring base substrates are arranged with an interval shorter than the length of the connection member, with the second adhesive layer in the same direction,
The connection member is laminated with one end facing the second adhesive layer of the first wiring base substrate and the other end facing the second adhesive layer of the second wiring base substrate with the insulating resin sheet facing.
The first semiconductor member and the second semiconductor member of the plurality of semiconductor members are formed on the second adhesive layer of the first wiring base base material and the second wiring base base material on the element opposite to the element circuit surface. Each is laminated with the substrate surface facing
The first wiring substrate and the second wiring substrate of the plurality of wiring substrates each have a conductive paste electrode at one end in contact with the conductive layer of the connecting member, and each predetermined conductive paste electrode is rewired. A wiring substrate laminate forming step in which a wiring substrate laminate is formed in contact with a layer and laminated on the first semiconductor member, the second semiconductor member, and the connection member;
The first adhesive layer and the second adhesive layer included in the wiring substrate laminate are cured, and the first wiring substrate, the first semiconductor member, and the first wiring base substrate are integrated. 1 wiring preliminary substrate, second wiring substrate, second semiconductor member and second wiring base substrate integrated with the second wiring base substrate, first wiring preliminary substrate and second wiring preliminary A wiring preform forming step for preforming a wiring preform including a connection member connected to the base body;
The connection member is bent so that the element substrate surfaces of the respective semiconductor elements embedded in the first wiring preliminary substrate and the second wiring preliminary substrate are opposed to each other, and the first wiring preliminary substrate, the second wiring preliminary substrate, Are disposed substantially symmetrically, and a bonding step of bonding the insulating resin base plates to the first wiring preliminary substrate and the second wiring preliminary substrate,
I have a,
In the bonding step, a support member is sandwiched between the first wiring preliminary base and the second wiring preliminary base and heat-pressed with an adhesive,
The connection member is disposed with a hollow gap between the first wiring portion, the second wiring portion, and the support member, and is fixed by the adhesive flowing into the inner peripheral surface of the connection member. to suppress the manufacturing method of the printed wiring board, wherein Rukoto be adjusted by the size of the hollow gap changing the thickness of the support member. 請求項４に記載のプリント配線基板の製造方法であって、
前記支持部材は、ポリイミド樹脂で成形された樹脂シート、繊維強化樹脂複合材料で成形された複合材料シート、無機材料で成形されたセラミックシート、またはモリブデンやインバー合金を銅で挟持した金属板で形成されていることを特徴とするプリント配線基板の製造方法。 It is a manufacturing method of the printed wiring board according to claim 4,
The support member is formed of a resin sheet formed of polyimide resin, a composite material sheet formed of a fiber reinforced resin composite material, a ceramic sheet formed of an inorganic material, or a metal plate sandwiched between molybdenum or invar alloy with copper. which do method for manufacturing a printed wiring board, wherein Rukoto. 請求項４または５に記載のプリント配線基板の製造方法であって、
前記配線基材成形工程は、
一方の面に銅層が設けられた絶縁樹脂板の前記銅層をエッチングして前記導体回路を形成し、前記絶縁樹脂板の他方の面に、前記第１接着層を形成し、前記第１接着層にマスキング層を形成し、前記絶縁樹脂板と前記第１接着層と前記マスキング層とに貫通して、前記導体回路と接続させる接続穴を形成し、前記接続穴に導電性ペーストを充填した後、前記マスキング層を除去して導電性ペースト電極を形成することを特徴とするプリント配線基板の製造方法。 It is a manufacturing method of the printed wiring board according to claim 4 or 5,
The wiring substrate molding step
The conductive layer is formed by etching the copper layer of the insulating resin plate provided with a copper layer on one surface, the first adhesive layer is formed on the other surface of the insulating resin plate, and the first A masking layer is formed on the adhesive layer, a connection hole is formed through the insulating resin plate, the first adhesive layer, and the masking layer to connect to the conductor circuit, and the connection hole is filled with a conductive paste. Thereafter, the masking layer is removed to form a conductive paste electrode. 請求項４から６のいずれか１つに記載のプリント配線基板の製造方法であって、
前記半導体部材成形工程は、
前記半導体素子の素子回路電極位置に第１開口を設けて第１絶縁層を形成し、前記第１開口に導電性材料で前記再配線層を形成し、前記再配線層の所定位置に第２開口を設けて第２絶縁層を形成することを特徴とするプリント配線基板の製造方法。 A printed wiring board manufacturing method according to any one of claims 4 to 6,
The semiconductor member molding step includes
A first insulating layer is formed by providing a first opening at an element circuit electrode position of the semiconductor element, the rewiring layer is formed of a conductive material in the first opening, and a second is formed at a predetermined position of the rewiring layer. A method for manufacturing a printed wiring board, wherein an opening is provided to form a second insulating layer.
JP2008126998A 2008-05-14 2008-05-14 Printed wiring board and manufacturing method thereof Active JP5097006B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008126998A JP5097006B2 (en) 2008-05-14 2008-05-14 Printed wiring board and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008126998A JP5097006B2 (en) 2008-05-14 2008-05-14 Printed wiring board and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2009277846A JP2009277846A (en) 2009-11-26
JP5097006B2 true JP5097006B2 (en) 2012-12-12

Family

ID=41443010

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008126998A Active JP5097006B2 (en) 2008-05-14 2008-05-14 Printed wiring board and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP5097006B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9257467B2 (en) 2009-12-16 2016-02-09 Samsung Electronics Co., Ltd. Image sensor modules, methods of manufacturing the same, and image processing systems including the image sensor modules
WO2013027795A1 (en) 2011-08-23 2013-02-28 株式会社フジクラ Substrate with built-in component and method of manufacturing same

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3224889B2 (en) * 1993-01-13 2001-11-05 イビデン株式会社 Printed wiring board and its manufacturing method
JP3892259B2 (en) * 2001-09-14 2007-03-14 カシオ計算機株式会社 Manufacturing method of semiconductor device
JP2003133518A (en) * 2001-10-29 2003-05-09 Mitsubishi Electric Corp Semiconductor module
JP2003158356A (en) * 2001-11-20 2003-05-30 Murata Mfg Co Ltd Electronic circuit device
JP3888267B2 (en) * 2002-08-30 2007-02-28 カシオ計算機株式会社 Semiconductor device and manufacturing method thereof
JP2004127970A (en) * 2002-09-30 2004-04-22 Denso Corp Method for producing elemental board of multilayer board and method for producing multilayer board using that elemental board

Also Published As

Publication number Publication date
JP2009277846A (en) 2009-11-26

Similar Documents

Publication Publication Date Title
JP4055717B2 (en) Semiconductor device and manufacturing method thereof
US8941016B2 (en) Laminated wiring board and manufacturing method for same
KR100778597B1 (en) Stackable Semiconductor Device and Method of Manufacturing the Same
US7705446B2 (en) Package structure having semiconductor chip embedded therein and method for fabricating the same
JP4073945B1 (en) Manufacturing method of multilayer wiring board
JPWO2007043639A1 (en) Printed wiring board and method for manufacturing printed wiring board
TW200531237A (en) Semiconductor device and method of fabricating the same
JP2006173232A (en) Semiconductor apparatus and its manufacturing method
JP2002170921A (en) Semiconductor device and its manufacturing method
JP4950743B2 (en) Multilayer wiring board and manufacturing method thereof
JP4157829B2 (en) Semiconductor device and manufacturing method thereof
JP5238182B2 (en) Manufacturing method of multilayer wiring board
KR100639737B1 (en) Method of manufacturing circuit device
JP4438389B2 (en) Manufacturing method of semiconductor device
JP2009146940A (en) Laminated wiring board and manufacturing method therefor
JP5097006B2 (en) Printed wiring board and manufacturing method thereof
JP2008182039A (en) Multilayer wiring board and its manufacturing method
JP5385699B2 (en) Manufacturing method of multilayer wiring board
JP4324732B2 (en) Manufacturing method of semiconductor device
JP5285385B2 (en) Manufacturing method of multilayer wiring board
JP4513302B2 (en) Semiconductor device
JP2012186270A (en) Manufacturing method of semiconductor package
JP4442181B2 (en) Semiconductor device and manufacturing method thereof
JP4461801B2 (en) Semiconductor device and manufacturing method thereof
JP4209341B2 (en) Semiconductor device and manufacturing method thereof

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20101125

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120229

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120306

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120426

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120911

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120921

R151 Written notification of patent or utility model registration

Ref document number: 5097006

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150928

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250