TWI242858B - Assembled chip carrier and method for fabricating the same and semiconductor package with the same - Google Patents
Assembled chip carrier and method for fabricating the same and semiconductor package with the same Download PDFInfo
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- TWI242858B TWI242858B TW092133129A TW92133129A TWI242858B TW I242858 B TWI242858 B TW I242858B TW 092133129 A TW092133129 A TW 092133129A TW 92133129 A TW92133129 A TW 92133129A TW I242858 B TWI242858 B TW I242858B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
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- Wire Bonding (AREA)
Abstract
Description
1242858 4五、發明說明（1) 【發明所屬之技術領域】 一種晶片承载件（Chlp Carrier)， 基板至少一側上疊接一栌# 尤拐種在核心 (Finger Pitch)而於相同基 f！間距 的於入/於屮；查拉从 j卷板早位面積下設置更多數晋 的輸入/輸出連接端之晶片承載件，及且歎里 之半導體封裝件。 有4日日片承載件 【先前技術】 逍者電子產業的蓬勃發展，電子產品亦逐漸邁入多 能、高性能的研發方向，為滿足半導體封裝件高積集度 (Integration)以及微型化（Mi n iaturizati 〇n)的封裝需 求，提供多數主被動元件及線路載接之基板（b〇ard)亦逐 漸由雙層板演變成多層板，以在有限的空間下藉由層間連 接技術（I n t e r 1 a y e r C ο η n e c t i ο η )擴大基板上可利用的電 路面積，俾以配合高電子密度之積體電路（Integrated C i rcu i t)的需求。· 傳統多層板之製造方法，一般是藉由壓合法 (Laminated)及增層法（Build-up)兩種方式。以壓合法製 成之多層板，如第8A圖及第8B圖所示，係於絕緣基材兩面 的銅箔上各形成一内層線路層1 0 1 ”，俾構成一核心基板 100π，之後，在不同核心基板100"，l〇〇an，100bn之間分別 夾置一黏著層5"，經過疊層（Laminated)及熱壓（Heat P r e s s )等步驟，將不同核心基板1 0 0 n， 1 0 0 a ’’，1 0 0 b ’’上下 壓合即形成一多層基板結構。 惟以壓合法製造多層基板時，在層數及孔數的製造上1242858 4 V. Description of the invention (1) [Technical field to which the invention belongs] A chip carrier (Chlp Carrier), at least one side of a substrate is superimposed with a stack of # Youguai in the core (Finger Pitch) and the same base f! The distance between the input and output of the chip; Chala sets the number of input / output terminals of the wafer carrier from the early area of the j-roll plate, and the semiconductor package. There are 4-day Japanese film carriers. [Prior technology] The electronics industry is booming, and electronic products are gradually moving into a multi-functional, high-performance research and development direction. In order to meet the high integration and miniaturization of semiconductor packages ( The packaging requirements of Mi n iaturizati 〇n), which provide the majority of active and passive components and circuit-carrying substrates (b〇ard), have gradually evolved from double-layer boards to multi-layer boards, in order to limit the use of inter-layer connection technology (I nter 1 ayer C ο η necti ο η) Expand the available circuit area on the substrate to meet the needs of Integrated Circuits with High Electron Density (Integrated Circuit). · Traditional multi-layer board manufacturing methods generally use two methods: Laminated and Build-up. As shown in FIG. 8A and FIG. 8B, the multi-layer board made by pressing is formed on the copper foil on both sides of the insulating substrate to form an inner layer circuit layer 1 0 1 ”, and then a core substrate 100π is formed. An adhesive layer 5 is sandwiched between the different core substrates 100, 100 and 100bn, and the different core substrates 1 0 0 n are passed through steps such as laminated and heat pressing. 1 0 0 a ”, 1 0 0 b” is pressed up and down to form a multilayer substrate structure. However, when manufacturing a multilayer substrate by pressing, the number of layers and the number of holes are manufactured.
1242858 五、發明說明（2) :明頒限制’㈤日守’由於其圖案化製程中係以壓合銅箔經 ，光、微影、蝕刻等減層方式（Substractive)所形成，使 其鮮線墊寬度及相鄰銲線塾間距（Finger pitch)因受製 ，限制最小均只能縮小到50// m，既難以適用高密度電性 連接端（I/O Connections)之封裝產品，也無法作為多晶 片模組（Multiple Chip M〇dule，MCM)或晶片規格封裝 (Chip Scale Package, CSP)等半導體封裝件之基板來 源。 再者，受到傳統蝕刻製程之限制，基板上每一個銲線 墊最小寬度約為5 0// m，加上相鄰銲線墊間最短距離約為 5 〇// m，此表示每多設一個銲線墊至基板上即須佔據約j 〇 〇 a m寬的距離，若進一步將該等銲線墊圓形環列在晶片周 圍外’並以半導體晶片之幾何中心作為圓心時，如第9圖 所示，各銲線墊6，，距離圓心的半徑尺為1〇〇n/2；r μ m (其中 n為銲線墊數量），因此基板1π上如佈有2 〇 〇個銲線墊時， 笑到相鄰銲線墊間距50// m及銲線墊寬5〇/z m共1 00// m寬度 的限制，銲線墊6 ’’排列的圓周長約為1 〇 〇 ( # m) X ( 2 0 0 - 1 )，換算其圓周直徑相當於6mm ;顯示基板輸入/輸出連接 端（未圖示）鉅量增加而導致銲線墊佈設量提高時，相對 地銲線墊形成的圓周區域也會擴大而增加基板及封裝件的 成品面積。 另一方面，半導體封裝件的微小化除須考量從橫向縮 減基板使用面積外，亦須縱向減低封裝件之整體高度。如 美國專利第6, 515, 356號案及第6, 486,53 7號案所述，基1242858 V. Description of the invention (2): The limitation of the Ming Dynasty was limited because the patterning process was formed by lamination of copper foil, light, lithography, etching and other substractive methods. Due to the limitation of the wire pad width and the adjacent finger pitch, the minimum limit can only be reduced to 50 // m. It is difficult to apply to high-density electrical connection (I / O Connections) packaging products. It cannot be used as a substrate source for semiconductor packages such as Multiple Chip Modules (MCM) or Chip Scale Package (CSP). Furthermore, due to the limitation of the traditional etching process, the minimum width of each bonding pad on the substrate is about 50 // m, and the shortest distance between adjacent bonding pads is about 50 // m, which means that each additional design A wire pad must occupy a distance of about 〇00am wide on the substrate. If the circular ring of these wire pads is further arranged around the wafer 'and the geometric center of the semiconductor wafer is used as the center, as in Section 9 As shown in the figure, the radius of each bonding pad 6 from the center of the circle is 100n / 2; r μm (where n is the number of bonding pads), so there are 200 bonding wires on the substrate 1π. When the pads are used, the width of the adjacent pads is 50 // m and the width of the pads is 50 / zm, which is a total of 100 // m. The width of the pads is about 100%. # m) X (2 0 0-1), equivalent to a circumference diameter of 6mm; when the input / output connection end (not shown) of the display substrate is increased significantly and the amount of wire pads is increased, the wire pads are relatively grounded The formed circumferential area will also expand and increase the finished product area of the substrate and package. On the other hand, in miniaturization of semiconductor packages, in addition to reducing the area of the substrate from the lateral direction, the overall height of the package must also be reduced vertically. As described in U.S. Patent Nos. 6,515,356 and 6,486,53 7,
Π507矽品.Ptd 第8頁 1242858 五、發明說明（3) 板上^供晶片接置之區域係開設有供曰曰片容納之至少—門 槽，該開槽深度須大於晶片厚度，以使晶片厚度可以包八 在基板厚度内而形成如第10 A圖及第10 B圖所示夕曰w 日日月朝上 型或晶片朝下型球柵陣列式半導體封裝件（cavi ty Up/Π507 silicon product. Ptd Page 8 1242858 V. Description of the invention (3) The area on the board ^ where the chip is placed is provided with at least a door slot for the chip to be accommodated. The depth of the slot must be greater than the thickness of the chip so that The thickness of the wafer can be formed within the thickness of the substrate to form a ball grid array semiconductor package as shown in FIG. 10A and FIG. 10B.
Cavity Down BGA Semiconductor Package) 〇 惟此種薄型BGA半導體封裝件雖然能利用基板丨,，開 1 1 〇深度包含晶片2 ”厚度的方式來降低封裴成品之整㉝言 度，但是在基板1 ”上挖洞必須變更線路佈局， :=阿 阳卫《亦會限 制住基板Γ植球區域而增大基板使用面積；爯_ 竹 万面，開 槽在封裝製程中必須先以膠片封抵開槽開口 ，待模壓作業 完成後才會脫除膠片，如此更會增加基板製程複雜性，^ 使基板成本顯著提高。 ” 此外’在基板上挖設開槽亦會損害基板的結構強度， 而減損基板對於機械應力的抵抗性，因此，封裝過程$晶 片與封裝膠體或封裝膠體與基板接合面間很容易發生脫層 或變形而影響到封裝產品之良率。 X 0 為此，如何運用現有壓合式基板（Laminated Substrate)及增層式基板（Build — up Substrate)來改 善封裳產品’使基板在容納大量銲線墊佈設之餘仍能進一 步縮減BGA封裝件之整體體積，已成為業界急切之務。 【發明内容】 本發明之主要目的，係在提供一種可降低基板使用面 積，以在未增加封裝件之整體高度下，橫向縮減半導體封 裝件尺寸之組合式晶片承載件及其製法，以及具有該組合Cavity Down BGA Semiconductor Package) 〇 Although this type of thin BGA semiconductor package can use the substrate 丨, the depth of 1 1 〇 to include the depth of the wafer 2 "thickness to reduce the integrity of the finished package, but on the substrate 1" The layout of the upper hole must be changed.: = A Yangwei 《It will also limit the substrate Γ ball planting area and increase the area of the substrate; 爯 _ Bamboo surface, the groove must be sealed with a film in the packaging process The opening will not be removed until the molding operation is completed. This will increase the complexity of the substrate manufacturing process and significantly increase the cost of the substrate. "In addition, digging a slot in the substrate will also damage the structural strength of the substrate and reduce the resistance of the substrate to mechanical stress. Therefore, delamination is easy to occur between the chip and the packaging gel or the bonding surface of the packaging gel and the substrate. Or deformation that affects the yield of the packaged product. X 0 For this reason, how to use the existing laminated substrate (Build-up Substrate) to improve the package products' make the substrate accommodate a large number of bonding wires Beyond the layout, the overall volume of the BGA package can be further reduced, which has become an urgent task in the industry. [Summary of the invention] The main purpose of the present invention is to provide a method that can reduce the use area of the substrate so as not to increase the overall package. Combined wafer carrier for reducing the size of a semiconductor package laterally at a height, a manufacturing method thereof, and the combination
1242858 五、發明說明（4) 式晶片承載件之半導體封裝件。 本發明之另一目的，係在提供一種不會限制壓合式基 板之植球面積兼突破既有製程限制，以縮減銲線墊寬度及 相鄰銲線墊間距至5 0// m以下之組合式晶片承載件及其製 法，以及具有該組合式晶片承載件之半導體封裝件。 本發明之再一目的，係在提供一種縱向縮減封裝成品 厚度同時，仍然保有足夠基板結構強度，以免封裝膠體與 基板接觸面間發生脫層之組合式晶片承載件及其製法，以 及具有該組合式晶片承載件之半導體封裝件。 本發明之又一目的，係在提供一種可簡化壓合式基板 製程，避免上膠片及去膠片等步驟之組合式晶片承載件及 其製法，以及具有該組合式晶片承載件之半導體封裝件。 為達成上述及其他目的，本發明係提供一種將增層式 基板（Build-up Substrate)及壓合式基板（Laminated Substrate)合而為一，並能進一步形成晶片朝上型或晶 片朝下型封裝結構，以減少封裝成品之整體厚度之組合式 晶片承載件及其製法，以及具有該組合式晶片承載件之半 導體封裝件。 其中，本發明之組合式晶片承載件係包括：一壓合式 基板（Laminated Substrate)，其包含至少一電路層及 一敷設於該電路層外之第一絕緣層，該第一絕緣層上係形 成複數個供該電路層外露之第一開口；至少一接置於該壓 合式基板上之增層式基板，該增層式基板具有複數層增層 線路層及一覆蓋在該增層線路層表面而與該第一絕緣層相1242858 V. Description of the invention (4) Semiconductor package for wafer carrier. Another object of the present invention is to provide a combination that does not limit the ball-planting area of the pressure-bonded substrate and breaks the existing process limit to reduce the width of the bonding pads and the spacing between adjacent bonding pads to less than 50 // m. Wafer carrier and manufacturing method thereof, and semiconductor package having the combined wafer carrier. Still another object of the present invention is to provide a combined wafer carrier and a method for manufacturing the same while reducing the thickness of the packaged product in the longitudinal direction, while still maintaining sufficient substrate structural strength to prevent delamination between the packaging colloid and the substrate contact surface, and the combination thereof Package of semiconductor wafer carrier. Yet another object of the present invention is to provide a combined wafer carrier and a manufacturing method thereof that can simplify the process of pressing a substrate, avoid the steps of laminating and removing a film, and a semiconductor package having the combined wafer carrier. To achieve the above and other objectives, the present invention provides a combination of a build-up substrate and a laminated substrate into one, and can further form a chip-up or chip-down package. A combined wafer carrier having a structure to reduce the overall thickness of a packaged finished product and a manufacturing method thereof, and a semiconductor package having the combined wafer carrier. Wherein, the combined wafer carrier of the present invention comprises: a laminated substrate (Laminated Substrate), which includes at least a circuit layer and a first insulating layer laid on the circuit layer, and the first insulating layer is formed on the first insulating layer. A plurality of first openings for exposing the circuit layer; at least one build-up substrate connected to the laminated substrate, the build-up substrate having a plurality of build-up circuit layers and a surface covering the build-up circuit layer And the first insulating layer
]7507石夕品.ptd 第10頁 1242858 五、發明說明（5) 對之第二絕緣 層線路層曝露 於該第一開口 線路層 而使該 上述組 壓合式 而 預備一 基板包括有至 緣層，該第一 一開口；製備該增層式基板 路層表面而與 絕緣層係形成 層， 之第 及第 壓合 合式 基板 少一 絕緣 至少 具有 該第 有複 該第二絕緣層 二開口；以及 二開口之間， 式基板與該增 晶片承載件之 (Laminated 電路層及一敷 層上係形成複 一與該壓合式 係形成有複數 複數個導電元 俾接合該電路 層式基板之間 製法，則包括 Substrate) 設於該電路層 數個供該電路 基板接置之增 複數層增層線路層及一覆蓋 個提供該增 件’係形成 層及該增層 電性連接。 以下步驟： 、該壓合式 外之第 絕 一絕緣層相對 數個提供該增 之第二絕緣層 層線路層曝露 層外露之第 層式基板， 在該增層線 ，且該第二 之第二開 口；以及，設置複數個導電元件至該第一開口及第二開口 之間，俾接合該電路層及该增層線路層而使該壓合式基板 與該增層式基板之間電性連接。 另外，本發明亦包含以上述組合式晶片承載件載接晶 片之球柵陣列式半導體封裝件。該半導體封裝件係包括： 一組合式晶片承載件，其包含一壓合式基板，至少一增層 式基板及提供該壓合式基板與增層式基板接合並且電性^ 接之複數個導電元件，其中，該增層式基板中央部係開設 有一開槽；至少一半導體晶片，係接置於該組合式晶片承 載件之開槽内，並與該組合式晶片承載件電性導接；一封 裝膠體，用以包覆該半導體晶片；以及複數個銲球，係植 接於該組合式晶月承載件上。] 7507 石 夕 品 .ptd Page 10 1242858 V. Description of the invention (5) The second insulating layer circuit layer is exposed to the first open circuit layer to make the above group of compression type and prepare a substrate including the edge layer The first and the first openings; preparing the layered substrate road surface and forming a layer with the insulating layer system, the first and the second compression-bonded substrates having at least one insulation having at least the first and second openings of the second insulating layer; and Between two openings, a method for forming a substrate between the substrate and the wafer carrier (Laminated circuit layer and a cladding layer), and a plurality of conductive elements formed on the lamination system, and bonding the circuit layer substrate, It includes Substrate), a plurality of multi-layered multi-layered circuit layers provided on the circuit layer for the circuit substrate to be connected, and a cover to provide the add-on's formation layer and the multi-layered electrical connection. The following steps: 1. The first insulating layer outside the press-fit type is provided to the first layer type substrate with the exposed layer of the second insulating layer layer, the exposed layer of the circuit layer, and the second, second, and second layers An opening; and a plurality of conductive elements are provided between the first opening and the second opening, and the circuit layer and the build-up circuit layer are bonded to electrically connect the compression-bonded substrate and the build-up substrate. In addition, the present invention also includes a ball grid array type semiconductor package in which a wafer is mounted on the combined wafer carrier. The semiconductor package includes: a combined wafer carrier including a laminated substrate, at least one build-up substrate, and a plurality of conductive elements for providing the laminate-type substrate and the build-up substrate to be electrically connected. A slot is provided in the central portion of the build-up substrate; at least one semiconductor wafer is connected to the slot of the combined wafer carrier and is electrically connected to the combined wafer carrier; a package A colloid is used to cover the semiconductor wafer; and a plurality of solder balls are implanted on the combined crystal moon carrier.
17507矽品.Ptd 第11頁 1242858 五、發明說明（6) 由於增層式基板之相鄰銲線墊間距及銲線墊寬在現有 製程上可以控制到2 0// m，相較於傳統壓合式基板5 0// m的 製程極限，當基板上佈設相同數量之銲線墊並以圓形環繞 於晶片周圍時，若按照圓周等於（相鄰銲線墊間距（// m) +銲線墊寬（// m))乘以（銲線墊數量-1)計算，排列銲 線塾所佔據的圓周直徑將可從原本的6mm縮減至2 . 5mm而明 顯降低基板使用面積，以橫向縮減該基板及半導體封裝件 的尺寸。 另一方面，本發明之組合式晶片承載件整合增層式基 板與壓合式基板，利用增層式基板在線路精密度上高出壓 合式基板，而壓合式基板在結構強度上優於增層式基板之 特點，在增層式基板上開設晶片收納開槽，使晶片厚度包 含在增層式基板深度内，以降低封裝成品之整體高度，並 在有限的基板面積下佈設更多數量之銲線墊；相對地，壓 合式基板上未開設開槽則可以提供良好的結構強度及足夠 的植球面積，避免為顧慮植球而擴大基板使用面積；同時 在封裝製程中，亦不需要先用膠片覆蓋開槽而省略上膠 片、去膠片等步驟，而達到降低製程複雜度的目的。 【實施方式】 以下係藉由特定的具體實施例說明本發明之實施方 式，熟習此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點與功效。本發明亦可藉由其他不同 的具體實施例加以施行或應用，本說明書中的各項細節亦 可基於不同觀點與應用，在不悖離本發明之精神下進行各17507 silicon product. Ptd Page 11 1242858 V. Description of the invention (6) Because the distance between the adjacent bonding pads and the bonding pad width of the build-up substrate can be controlled to 20 // m in the existing process, compared with the traditional The process limit of 50 // m for press-fit substrates. When the same number of wire pads are arranged on the substrate and surround the wafer in a circle, if the circumference is equal to (adjacent wire pad spacing (// m) + welding) Line pad width (// m)) multiplied by (number of wire pads -1), the diameter of the circle occupied by the arranged wire 塾 can be reduced from the original 6mm to 2.5mm, and the area of the substrate is significantly reduced. Reduce the size of the substrate and semiconductor package. On the other hand, the combined wafer carrier of the present invention integrates the build-up substrate and the press-type substrate, and the use of the build-up substrate is higher in circuit precision than the press-type substrate, and the press-type substrate is superior in structure strength to the build-up substrate. The characteristics of the type substrate, the wafer receiving slot is opened on the build-up substrate, so that the thickness of the wafer is included in the depth of the build-up substrate, in order to reduce the overall height of the packaged product, and a larger number of solders are arranged under the limited substrate area. Wire pads; in contrast, the absence of slots on the press-fit substrate can provide good structural strength and sufficient ball planting area to avoid expanding the area of the substrate for the sake of ball planting. At the same time, in the packaging process, there is no need to use The film covers the slot and omits the steps of film loading and film removing, so as to reduce the complexity of the process. [Embodiment] The following is a description of specific embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied by other different specific embodiments. The details in this specification can also be implemented based on different viewpoints and applications without departing from the spirit of the present invention.
]7507石夕品.ptd 第12頁 1242858 五、發明說明（7) 種 修飾與變更。 非 不只鈀例係進—步詳細說明本發明之觀點，但並 何硯點限制本發明之範疇。 本發明係提供一種將增層式基板（BuUd —叫 Substrate)及壓合夫甘，， 、， 飞基板（Laminated Substrate)合而 Γ ：，/ 進步形成晶片朝上型（Cav i ty Up)或晶片 ^ ( 一"。wn)封裝結構，以減少封裝成 曰r ϋί合式晶片*載件及其製*，以及具有該組合式 曰曰7之半導體封裝件，而藉由下述實施例分別予以 詳細說明。 凊芩閱第1 Α圖及第丨]5圖，本發明具有組合式晶片承載 件之^導體封裝件係包括：一組合式晶片承載件丨；至少 一半導體晶片2，係收納於該組合式晶片承載件1内並與之 電性連接；一封裝膠體3，係用以包覆該半導體晶片2 ;以 及複數個植接於該組合式晶片承載件1底部之銲球4。 而上述組合式晶片承載件1及其製法進一步包括：預 備一壓合式基板1〇( Laminated Substrate)，該壓合式 基板1 0之一側係提供該等銲球4植接，以供晶片2與外部裝 置（未圖示）電性連結；製備至少一增層式基板1 1 (Build-up Substrate)，係接置於該壓合式基板10未植 球之一側，該增層式基板1 1上開設有至少一開槽1 1 〇，且 該開槽1 1 0之口徑大於半導體晶片2，以供晶片2安置其 内；以及，提供至少一導電元件1 2，係用以接合並提供該 壓合式基板1 0與該增層式基板1 1導電連接。] 7507 石 夕 品 .ptd Page 12 1242858 5. Description of the invention (7) Modifications and changes. Not only are the examples of palladium detailed-the points of the present invention are explained in detail, but the points are not limited to the scope of the present invention. The present invention provides a method of combining a build-up substrate (BuUd — called Substrate) and a laminated substrate (Laminated Substrate) to form a wafer-up type (Cav i ty Up) or The chip ^ (一 " wn) package structure to reduce packaging into an integrated wafer * carrier and its manufacturing *, and a semiconductor package having the combined type of 7, and by the following embodiments, respectively Be detailed.凊 芩 See FIG. 1A and FIG. 5], the conductor package having a combined wafer carrier according to the present invention includes: a combined wafer carrier; and at least one semiconductor wafer 2 is housed in the combined The wafer carrier 1 is electrically connected to the wafer carrier 1; a packaging gel 3 is used to cover the semiconductor wafer 2; and a plurality of solder balls 4 implanted on the bottom of the combined wafer carrier 1. The above-mentioned combined wafer carrier 1 and its manufacturing method further include: preparing a laminated substrate 10 (Laminated Substrate), one side of the laminated substrate 10 is provided with the solder balls 4 implanted for the wafer 2 and An external device (not shown) is electrically connected; at least one build-up substrate 1 1 (Build-up Substrate) is prepared, and the build-up substrate 1 1 is connected to one side of an un-implanted ball of the laminated substrate 10, and the build-up substrate 1 1 There is at least one slot 1 10 formed on the top, and the diameter of the slot 1 10 is larger than the semiconductor wafer 2 for the wafer 2 to be placed therein; and, at least one conductive element 12 is provided for bonding and providing the The compression-bonded substrate 10 is electrically connected to the build-up substrate 11.
1242858 五、發明說明（8) 如第2圖及第3圖所示，該壓合式基板i〇( Laminated S u b s t r a t e)係包含多數如銅猪與例如b T樹脂、聚亞醯胺 (Polyimide) 、FR-5樹脂或環氧樹脂等絕緣材料所製成 之核心基板1 0 0，以及形成於該核心基板1 〇 〇表面之一或多 層内層線路層1 0 1，其中，該壓合式基板1 〇之一側係形成 有多數球墊1 0 3提供銲球（未圖示）植接，且為阻隔外界 電性干擾，壓合式基板1 〇最外側的内層線路層1 〇 1經過圖 案化後，於該内層線路層1 〇 1上外覆一層具有多數開口之 拒銲劑層（So 1 der Mask)(為以示區別，本實施例係以 第一開口 1 0 2 a及第一拒銲劑層1 0 2稱之），以使該内層線 路層1 0 1透過各第一開口 1 0 2 a而外露。 如第4圖所示，該增層式基板1 1 ( Bui ld-up Substrate)係利用增層技術交互堆疊多層絕緣層及導電 層，並於該絕緣層中開設多數導電貫孔1 1 3 ( C ο n d u c t i v e V i a)，經過電鍍以及圖案化等製程後形成複數層上下電 性導通之增層線路層1 1 4。惟如第5圖所示，本發明之組合 式晶片承載件不同於習知基板之一，係在該增層式基板1 1 中央形成一 口徑大於半導體晶片之開槽1 1 〇，該開槽1 1 〇可 以貫穿通孔（Through Hole)形式貫穿該增層式基板1 1或 為開槽1 1 0底部仍具增層式基板之單邊開口開槽等，藉以 收納半導體晶片2至開槽1 1 〇中而使該晶片厚度至少一部分 或全部包含在該開槽1 1 〇之深度中。 而為阻隔外界電性干擾，增層式基板11外側的增層線 路層1 1 4經過圖案化後，亦會和壓合式基板1 〇一樣於基板1242858 V. Description of the invention (8) As shown in FIG. 2 and FIG. 3, the laminated substrate i0 (Laminated S ubstrate) contains a large number of copper pigs and, for example, b T resin, polyimide, A core substrate 100 made of an insulating material such as FR-5 resin or epoxy resin, and one or more inner layer circuit layers 101 formed on the surface of the core substrate 1000, among which the compression-molded substrate 1 〇 One side is formed with a plurality of ball pads 103 to provide solder ball (not shown) planting, and to block external electrical interference, the outermost inner circuit layer 1 0 of the compression-bonded substrate 1 0 is patterned, A layer of solder resist (So 1 der Mask) with a plurality of openings is overlaid on the inner layer circuit layer 101 (for the purpose of illustration, this embodiment uses the first opening 1 0 2 a and the first solder resist layer 1 (Referred to as 0 2), so that the inner circuit layer 1 0 1 is exposed through each first opening 10 2 a. As shown in FIG. 4, the build-up substrate 1 1 (Bui ld-up Substrate) uses a build-up technology to alternately stack multiple insulating layers and conductive layers, and a plurality of conductive vias 1 1 3 ( C ο nductive V ia), after the processes of electroplating and patterning, etc., a plurality of layers of electrically conductive layered circuit layers 1 1 4 are formed. However, as shown in FIG. 5, the combined wafer carrier of the present invention is different from one of the conventional substrates. A slot 1 1 0 having a diameter larger than that of a semiconductor wafer is formed in the center of the layered substrate 1 1. 1 1 〇 Through the through hole (Through Hole) through the build-up substrate 11 or slot 1 1 0 single-sided opening slot with a build-up substrate at the bottom, etc., to accommodate the semiconductor wafer 2 to the slot 1 10 and at least a part or all of the thickness of the wafer is included in the depth of the slot 1 1 10. In order to block external electrical interference, the build-up circuit layer 1 1 4 on the outside of the build-up substrate 11 will also be the same as the laminated substrate 10 after patterning.
】7507矽品· ptd 第14頁 1242858 五、發明說明（9) 最外側覆蓋一層具多數開口之拒銲劑層（為與該第一開口 1 0 2 a及弟*^拒在干劑層1 0 2以不區別’本貫施例以鄰近於該 壓合式基板1 0之增層式基板11拒銲劑層稱為第二拒銲劑層 1 1 2，而第二拒銲劑層1 1 2上各開口則以第二開口 1 1 2 a稱之 )，該第二開口 1 1 2a之位置係與該壓合式基板1 〇之第一開 口 1 0 2 a位置彼此對應，以形成如第5圖底視圖所示之基板 結構。 本發明之組合式晶片承載件不同於習知基板之二，係 利用至少一導電元件1 2將該壓合式基板1 〇及增層式基板1 1 合而為一，該導電元件1 2係為例如導電性膠黏劑、銲錫膏 (Solder Paste)或銲錫凸塊（Solder Bump)等，俾藉 由膠黏或迴銲等技術令該壓合式基板1 〇與增層式基板丨！間 電性連接。以本實施例為例，如第6A圖及第6B圖所示，該 壓合式基板1 0之第一拒銲劑層開口 1 〇 2 a處利用網印或點膠 等方式塗佈一銲錫膏1 2後，將該增層式基板1 1覆蓋到壓合 式基板1 0上’以使該第一開口 1 〇 2 a與該第二開口 1 1 2 a對應 接觸而讓該銲錫膏1 2溢流入該第二開口 1 1 2 a，經過迴焊 (re flow)等程序，使得該内層線路層ι〇1及增層線路層n4 之間能透過該銲錫膏1 2接合並且電性連接。惟該導電元件 1 2除於增層式基板1 1接合前預先佈設於該壓合式基板丨〇之 第一開口 1 0 2 a外，亦可反過來預先形成於該第二拒銲劑層 1 1 2表面之第二開口 π 2 a，然本實施例之導電元件除上述 之導電膠或錄錫膏外，凡不影響增層式基板與壓合式基板 電性接合之接合技術或元件，均包含於本發明之可實施範] 7507 Silicone · ptd Page 14 1242858 V. Description of the Invention (9) The outermost layer is covered with a solder resist layer with many openings (for the first opening 1 0 2 a and younger brother * ^ refusing to be in the desiccant layer 1 0 2 In order to make no difference, in the present embodiment, the build-up substrate 11 adjacent to the press-type substrate 10 is referred to as a second solder resist layer 1 1 2, and each of the second solder resist layers 1 1 2 is open. The second opening 1 1 2 a is called), and the position of the second opening 1 1 2 a corresponds to the position of the first opening 1 0 2 a of the compression-type substrate 10 to form a bottom view as shown in FIG. 5. The substrate structure shown. The combined wafer carrier of the present invention is different from the second conventional substrate, which uses the at least one conductive element 12 to combine the pressure-bonded substrate 10 and the build-up substrate 1 1 into one. The conductive element 12 is For example, conductive adhesive, solder paste (Solder Paste), or solder bump (Solder Bump), etc., by bonding or re-soldering technology to make the press-type substrate 10 and build-up substrate 丨! Between electrical connections. Taking this embodiment as an example, as shown in FIG. 6A and FIG. 6B, the first solder resist layer opening 1 of the compression-type substrate 10 is coated with a solder paste 1 by screen printing or dispensing, etc. After that, the build-up substrate 11 is covered on the press-type substrate 10 so that the first opening 102a is in contact with the second opening 1 1a and the solder paste 12 overflows. The second opening 1 1 2 a undergoes procedures such as reflow, so that the inner circuit layer ι01 and the build-up circuit layer n4 can be connected and electrically connected through the solder paste 12. However, the conductive element 12 can be formed in advance on the second solder resist layer 1 1 in addition to the first opening 1 0 2 a which is arranged in advance on the press-type substrate 11 before bonding. 2 surface of the second opening π 2 a, except that the conductive element of this embodiment, in addition to the above-mentioned conductive glue or solder paste, any bonding technology or component that does not affect the electrical bonding of the build-up substrate and the press-bonded substrate includes Practicable
]7507石夕品.ptd 第15頁 1242858 ' —'___ 五、發明說明（10) 疇。 由於增層式基板1 1之相鄰銲線塾間距及輝線墊寬在現 有製程上可以控制到2 0// m，相較於傳統壓合式基板5 〇// m 的製程極限，當基板上佈設相同數量之銲線墊並以圓形環 繞於晶片周圍時，若按照圓周等於（相鄰銲線墊間距 m) +銲線墊寬（// m))乘以（銲線墊數量）計算，排列銲 線墊所佔據的圓周直徑將可從原本的6mm縮減至2. 5mm而明 顯降低基板使用面積，橫向縮減該基板及半導體封裝件的 尺寸。 另一方面，本發明之組合式晶片承載件1整合增層式 基板1 1與壓合式基板1 0，利用該增層式基板1 1在線路精密 度上優於壓合式基板1 〇而該壓合式基板1 〇在結構強度上佳 於增層式基板11之特點，在該增層式基板11上開設晶片收 納開槽1 1 0，使得晶片厚度包含在增層式基板深度内，而 降低封裝成品之整體高度，以在有限的基板面積下佈設更 多數量之銲線塾；相對地，麼合式基板1 〇不設開槽則可以 提供良好的結構強度及足夠的植球面積’避免為顧慮植球 而擴大基板範圍；同時，在封裝製程中’該壓合式基板亦 不需要先用膠片覆蓋開槽而省略上膠片、去膠片等步驟， 進而達到降低製程複雜度的目的。 第7圖係顯示本發明具組合式晶片承載件之半導體封 裝件之第二實施例。如圖所示，此實施例之半導體封裝件 與前述半導體封裝件之結構大致相似，其不同處在於該半 導體晶片2’係藉由覆晶形式（Flip Chip)電性連接在增 1] 7507 石 夕 品 .ptd Page 15 1242858 '—'___ 5. Description of the invention (10) Domain. Because the distance between adjacent bonding wires and the width of the glow wire pads of the build-up substrate 11 can be controlled to 20 // m in the existing process, compared to the process limit of 5 0 // m of the traditional laminated substrate, when the substrate is on the substrate, When the same number of wire pads are arranged and circled around the wafer, if the circumference is equal to (adjacent wire pad spacing m) + wire pad width (// m)) multiplied by (number of wire pads) , The circumferential diameter occupied by the bonding pads can be reduced from the original 6mm to 2.5mm, which significantly reduces the area of the substrate and reduces the size of the substrate and the semiconductor package laterally. On the other hand, the combined wafer carrier 1 of the present invention integrates the build-up substrate 11 and the press-bonded substrate 10, and uses the build-up substrate 11 to be superior to the press-fit substrate 10 in terms of circuit accuracy. The composite substrate 10 is better in structural strength than the build-up substrate 11, and a wafer receiving slot 1 10 is formed on the build-up substrate 11 so that the thickness of the wafer is included in the depth of the build-up substrate, thereby reducing packaging. The overall height of the finished product allows a larger number of bonding wires to be laid under a limited substrate area. In contrast, the Mohe type substrate 10 can provide good structural strength and sufficient ball planting area without slotting. At the same time, in the packaging process, the 'press-fit substrate' does not need to cover the slot with a film first, omitting steps such as film loading and film removing, thereby reducing the complexity of the process. Fig. 7 shows a second embodiment of a semiconductor package with a combined wafer carrier according to the present invention. As shown in the figure, the structure of the semiconductor package of this embodiment is similar to that of the aforementioned semiconductor package, except that the semiconductor wafer 2 'is electrically connected to the semiconductor chip 1 through a flip chip.
HI iHI i
Sf VLI) ΛSf VLI) Λ
17507 矽品.ptd 第]6頁 1242858 五、發明說明（11) 層式基板11’底面，且在壓合式基板10’上設有一得供半導 體晶片2 ’容置之開槽1 1 0 ’，使該半導體晶片2 ’隱藏在壓合 式基板1 0 ’的開槽1 1 0 ’内，而可有效縮減半導體封裝件之 整體高度。又，於增層式基板1 1 ’中央開設之開槽1 1 0 ’收 納晶片2 ’，且該增層式基板1 1 ’優於壓合式基板1 0 ’之線路 精密度能更進一步降低銲線墊間距（Finger Pi tch)及銲 球墊間距（Ba 1 1 Pad P i t ch)，以橫向縮減基板使用面 積，令封裝產品尺寸更趨微小化。另由於增層式基板1 1 ’ 上並未開設開槽，因此，提供增層式基板1 1 ’上方來安置 散熱片（未圖示），俾進一步提昇晶片2 ’之散熱效能。 上述實施例僅為例示性說明本發明之原理及其功效， 而非用於限制本發明。任何熟習此技藝之人士均可在不違 背本發明之精神及範疇下，對上述實施例進行修飾與變 化。因此，本發明之權利保護範圍，應如後述之申請專利 範圍所列。17507 Silicon Product.ptd Page 6 of 1242858 V. Description of the invention (11) The bottom surface of the layered substrate 11 ', and a laminated substrate 10' is provided with a slot 1 1 0 'for the semiconductor wafer 2', The semiconductor wafer 2 ′ is hidden in the slot 1 1 0 ′ of the press-type substrate 10 ′, and the overall height of the semiconductor package can be effectively reduced. In addition, the slot 1 1 0 opened in the center of the build-up substrate 1 1 'receives the wafer 2', and the line precision of the build-up substrate 1 1 'is better than that of the press-fit substrate 1 0', which can further reduce the soldering. The wire pad pitch (Finger Pi tch) and solder ball pad pitch (Ba 1 1 Pad P it ch) reduce the use area of the substrate laterally, and make the size of package products smaller. In addition, since the slot is not provided on the build-up substrate 1 1 ′, a heat sink (not shown) is provided above the build-up substrate 1 1 ′ to further improve the heat dissipation performance of the chip 2 ′. The above-mentioned embodiments are merely illustrative for explaining the principle of the present invention and its effects, and are not intended to limit the present invention. Anyone skilled in the art can modify and change the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of patent application mentioned later.
]7507石夕品.ptd 第17頁 1242858 圖式簡單說明 【圖式簡單說明】 第1 A圖係為本發明具有組合式晶片承載件之半導體封 裝件之拆解組合示意圖； 第1 B圖係為本發明具有組合式晶片承載件之半導體封 裝件之組合示意圖； 第2圖係本發明組合式晶片承載件之壓合式基板之局 部剖視圖； 第3圖係本發明組合式晶片承載件之壓合式基板之底 視圖， 第4圖係本發明組合式晶片承載件之增層式基板之局 部剖視圖； 第5圖係本發明組合式晶片承載件之增層式基板之上 視圖； 第6 A圖係本發明之組合式晶片承載件中，該增層式基 板與壓合式基板接合前之示意圖； 第6 B圖係本發明之組合式晶片承載件中，該增層式基 板與壓合式基板接合後之示意圖； 第7圖係本發明具有組合式晶片承載件之半導體封裝 件第二實施例之剖面示意圖； 第8A圖及第8B圖係習知以壓合法製作多層基板之剖視 圖， 第9圖係習知銲線墊環設於晶片周圍之基板區域之假 想示意圖； 第10A圖係習知晶片朝上型（Cavity Up)半導體封裝] 7507 石 夕 品 .ptd Page 17 1242858 Brief Description of Drawings [Simplified Description of Drawings] Figure 1A is a disassembly and assembly schematic diagram of a semiconductor package with a combined wafer carrier according to the present invention; Figure 1B It is a combined schematic diagram of a semiconductor package with a combined wafer carrier according to the present invention; FIG. 2 is a partial cross-sectional view of a laminated substrate of the combined wafer carrier of the present invention; FIG. 3 is a laminated type of the combined wafer carrier of the present invention The bottom view of the substrate, FIG. 4 is a partial cross-sectional view of the build-up substrate of the combined wafer carrier of the present invention; FIG. 5 is the top view of the build-up substrate of the combined wafer carrier of the present invention; In the combined wafer carrier of the present invention, a schematic diagram before the build-up substrate is bonded to the press-type substrate; FIG. 6B is a diagram of the combined wafer carrier of the present invention after the build-up substrate is bonded to the press-type substrate Schematic diagram; FIG. 7 is a cross-sectional diagram of a second embodiment of a semiconductor package with a combined wafer carrier according to the present invention; and FIGS. 8A and 8B are conventional methods for fabricating multiple layers by pressing. A cross-sectional view of the plate, FIG. 9 based conventional wire bonding pads disposed around the peripheral area of the dummy substrate wafer schematic like; FIG. 10A based on a conventional wafer-up type (Cavity Up) semiconductor package
]7507碎品.ptd 第18頁 1242858 圖式簡單說明 件之剖視圖；以及 第1 Ο B圖係習知晶片朝下型（C a v i t y D〇 wη)半導體封 裝件之剖視圖。 1 組 111 基 10, 10’ 壓 1 0 0, 1 0 0 n 核 1 0 1，1 0 1π 内 102 第 102a 第 11， 11’ 增 1 1 0，1 1 0 ’，1 1 0，， 開 112 第 112a 第 113 導 114 增 12 導 13’ 凸 合式晶片承載件 板 合式基板 心基板 層線路層 一拒鲜劑層 一開口 層式基板 槽 二拒銲劑層 二開口 電貫孔 層線路層 電元件（銲錫膏） 塊銲墊 2，2 ’，2 π 半導體晶片 3 封裝膠體 4，4 ’’ 銲球 5 ’’ 黏合層 6 ’’ 銲線墊] 7507 碎 品 .ptd Page 18 1242858 Schematic cross-sectional view of the component; and Figure 10B is a cross-sectional view of a conventional wafer-down (C av ty D0 wη) semiconductor package. 1 set of 111 base 10, 10 'pressure 1 0 0, 1 0 0 n core 1 0 1, 1 0 1π inner 102th 102a 11th, 11' increase 1 1 0, 1 1 0 ', 1 1 0 ,, open 112 Section 112a Section 113 Guide 114 Add 12 Guide 13 'Convex wafer carrier PCB laminated substrate core substrate layer circuit layer one antireflective layer one open layer substrate slot two solder resist layer two open electrical through hole layer circuit layer electrical components (Solder Paste) Bulk Pads 2, 2 ', 2 π Semiconductor Wafer 3 Packaging Gel 4, 4 ”Solder Ball 5” Adhesive Layer 6 ”Wire Pad
]7507石夕品.ptd 第]9頁] 7507 石 夕 品 .ptd Page] 9
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW092133129A TWI242858B (en) | 2003-11-26 | 2003-11-26 | Assembled chip carrier and method for fabricating the same and semiconductor package with the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW092133129A TWI242858B (en) | 2003-11-26 | 2003-11-26 | Assembled chip carrier and method for fabricating the same and semiconductor package with the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200518294A TW200518294A (en) | 2005-06-01 |
| TWI242858B true TWI242858B (en) | 2005-11-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW092133129A TWI242858B (en) | 2003-11-26 | 2003-11-26 | Assembled chip carrier and method for fabricating the same and semiconductor package with the same |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI242858B (en) |
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| Publication number | Publication date |
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| TW200518294A (en) | 2005-06-01 |
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| MM4A | Annulment or lapse of patent due to non-payment of fees |