TW200518294A - Assembled chip carrier and method for fabricating the same and semiconductor package with the same - Google Patents

Assembled chip carrier and method for fabricating the same and semiconductor package with the same

Info

Publication number
TW200518294A
TW200518294A TW092133129A TW92133129A TW200518294A TW 200518294 A TW200518294 A TW 200518294A TW 092133129 A TW092133129 A TW 092133129A TW 92133129 A TW92133129 A TW 92133129A TW 200518294 A TW200518294 A TW 200518294A
Authority
TW
Taiwan
Prior art keywords
substrate
build
same
chip carrier
assembled chip
Prior art date
Application number
TW092133129A
Other languages
Chinese (zh)
Other versions
TWI242858B (en
Inventor
Yu-Po Wang
Chien-Ping Huang
Chih-Ming Huang
Cheng-Hsu Hsiao
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Priority to TW092133129A priority Critical patent/TWI242858B/en
Publication of TW200518294A publication Critical patent/TW200518294A/en
Application granted granted Critical
Publication of TWI242858B publication Critical patent/TWI242858B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

Landscapes

  • Wire Bonding (AREA)

Abstract

An assembled chip carrier and a method for fabricating the same and a semiconductor package with the assembled chip carrier are proposed. The assembled chip carrier includes a laminated substrate and a build-up substrate formed on the laminated substrate, wherein the build-up substrate is formed with a recess to receive a chip therein. A solder mask formed on the laminated substrate and build-up substrate is formed with openings to expose an inner circuit layer of the laminated substrate and a build-up circuit layer of the build-up substrate. The laminated substrate and the build-up substrate can be electrically connected to each other with the openings filled with solder paste. By the arrangement, a pitch between the adjacent solder bumps and the width of the solder bump can be reduced under 20 μm, and the diameter of the solder bump can be reduced from 6 mm to 2.5 mm to reduce the using area of the substrate via the excellent precision layout of the circuit layer of the build-up substrate.
TW092133129A 2003-11-26 2003-11-26 Assembled chip carrier and method for fabricating the same and semiconductor package with the same TWI242858B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW092133129A TWI242858B (en) 2003-11-26 2003-11-26 Assembled chip carrier and method for fabricating the same and semiconductor package with the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW092133129A TWI242858B (en) 2003-11-26 2003-11-26 Assembled chip carrier and method for fabricating the same and semiconductor package with the same

Publications (2)

Publication Number Publication Date
TW200518294A true TW200518294A (en) 2005-06-01
TWI242858B TWI242858B (en) 2005-11-01

Family

ID=37022627

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092133129A TWI242858B (en) 2003-11-26 2003-11-26 Assembled chip carrier and method for fabricating the same and semiconductor package with the same

Country Status (1)

Country Link
TW (1) TWI242858B (en)

Also Published As

Publication number Publication date
TWI242858B (en) 2005-11-01

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees