1238506 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種高散熱性之直接導通式半導體 元件結構之製法，尤指一種同時整合有散熱件、半導體晶 片與線路結構之半導體元件結構之製作方法。 【先前技術】 隨著半導體封裝技術的演進，半導體裝置 (Semiconductor device)已開發出不同的封裝型態，其中球 栅陣列式（Ball grid array, BGA)為一種先進的半導體封裝 技術，其特點在於採用一基板來安置半導體晶片，並利用 自動對位（Self-alignment)技術以於該基板背面植置複數個 成柵狀陣列排列之銲球（Solder ball)，使相同單位面積之半 導體晶片承載件上可以容納更多輸入/輸出連接端（I/O connection)以符合高度集積化（Integration)之半導體晶片 所需，以藉由此些銲球將整個封裝單元銲結並電性連接至 外部之印刷電路板。 然而，上述封裝件實際執行卻會產生許多問題：首 先，因為半導體晶片上之電子元件及電子電路之密度高集 積化，其運作產生之熱量多，如不及時將半導體晶片產生 之熱量有效逸散，將嚴重縮短半導體晶片之性能及壽命； 再者，該封裝件缺乏有效遮蔽效果(Shielding)，容易受到 外界電磁及雜訊之干擾。 請參閱第1圖，為解決上述問題，一種習知之底穴置 晶型球柵陣型式封裝結構（Cavity-down ball grid array, 5 18039 1238506 cdbga)，係為—種特殊形^ ?:在Γ其中之基板形成有-開”：:二:導： :片以倒置方式安置於該底穴之 封裝結構1G至少包含：Μ 之球柵陣列式 半導體晶U、複數條料14 散熱件12、至少一 銲球16。 鐵‘線14、-封轉體15以及複數 该基板11具有一正面1丨 —北 少_門π 17 · 月面11 b ’且形成有至 開孔111，該散熱件〗2的 , 性；bl· Μ η/ > 诃貝為一例如為銅之高導勒 性材枓，且其係耦合至該基板 …， 苴k , 攸11的正面a上，以使得續 土板11的開孔111形成一開 " 13且古予^ 開朝下之底穴；該半導體晶月 八有一琶性作用面13a(Activesurf 面 13b(lnactive surface) 户电注作用 13 ^ 於，、且裊過私中，係將半導體晶片 &女置於基板11的開孔111巾，並將其非命 性作用13 b黏結至散敎件丨2，妒接、仓/ 八电 1V4lm 月又…件12然後，進行-銲線製程，藉 以利用銲線14將半導f曰H j 1 + 牛¥版日日片13電性連接至該基板11表面 一 U復干V版日日13片和銲線14，之後，進 =植球程序’藉此而於基板η的背面m上植置複數個 έ士。16此即兀成该底穴置晶型球柵陣列式（CDBGA)封裝 、、、口構 1 〇 〇 、 —上；4封裝單元耗得以利用該散熱件解決其散熱與 、黑^丈果（Shielding) ’但—般為能夠將該銲球順利銲結至 古卩P刷包路板，该銲球配置高度必須大於該銲線弧所佔 门度嚴重影響該基板之佈局性（Routabiiity)與銲球配置高 18039 6 1238506 :線二二之線弧密度極高，議 者，於進;r ^ ^ 01 )’增加打線作業困難度；再 基板置於佈&晶片與導線之 模具中而’彳供—核氧樹脂吻㈣材料注入 故其模穴尺L 於受限於半導體封裝件之設計， 固等問題，俟:主夾^位置勢必有所差異而造成無法緊密夾 該基板I ^人㈣㈣時，容《導闕m益膠至 口发吞板表面，非但降低該 觀’同時更可能污染該基板上後：==與美 脂材料於注二Π:之電性連接品質；況且，該樹 晶片與基板電性入該模穴⑼ 制不當時，二== 產，覆力，若注入速度控 生短路門題二舌Μ土力衝線，使導線產生碰觸而發 信賴度。'’厫重影響該半導體封褒件之生產品質及產品 制泛::二t半導體裝置之製程’係首先由晶片承載件 :==:=?:置之一，如= 者進行置晶、模壓、：::二刚交由半導體封褒業 戶端所需之電子:能程其= 者（即包含有晶片承载件製造業者與半導:t不=程業 1匕以=造過程中不僅步驟㈣且界二:業者）:因 且’右各戶端欲進行變更功能設計時，其牵涉變更與ί合 18039 7 1238506 層面更是複雜’亦不符合需求變更 一 m VL L j „ 性妗、纟里凊效益。 口此，如何猎由簡單製程、花 決半導體裝置之散熱、電磁干擾、封1乂=本即可同時解 合等問顆，者p A、、， 衣板壓與製程界面整 、 、貝已成目前亟欲解決的課題。 【發明内容】 ' 提#==上所述f知技術之缺點，本發明之主要目的係 r、：種馬放熱性之直接導通式半導體元件結構之梦法:、 冋％整合晶片承载件之製造與半 以提供客戶端較大雲、卡π k门士 衣孜術之衣私’ 田 求弹性，同時得以簡化半導體聿者制 程與界面整合問題。 卞今版系f衣 式丰ΪΓ 月之再一目的係提供-種高散熱性之直接導通 大半‘肢元件結構之製法值右 時所產生之¥ rnt 散切體晶片於運作 P冰置 提供半導體裝置電磁遮蔽效果，避 免又外界毛磁及雜訊之干擾。 、本么月之另目的係提供一種高散熱性之直接導通 元件結構之製法，係可提供半導體晶片直接電性 V通至外部，藉以提升電性品質。 、本么月之又一目的係提供一種高散熱性之直接導通 式半導體元件結構之製法，避免習知半導體晶片電性導接 至包路板日讀需複雜製程及S備等問題。 、 、 '本發明之又另一目的係提供一種高散熱性之直接導 式半‘ to元件結構之製法，避免習知封裝製程之模壓與 才求作業中所產生之溢膠與佈設等問題’俾有效提昇半 體裝置之生產品質及產品信賴度。 、 8 18039 1238506 2上揭及其它目的，本發明之高散熱性之直接導通 :接置：：：:吉構之製法，主要係包括：將複數半導體晶 、月文熱件上；於該表面接置有+導體晶片之散埶 件上形成至少一絕緣層；於該絕緣層上形成至少一圖幸： 層，並令該圖案化線路層電性導接至該半導體晶二 :後復可進㈣單作業，^彡成魏w 播的车n 4電性延伸出之線路結 70件結構，並可在最相之圖案化線路層上設 置稷數供電性導接至外界之導電元件。 一其中該半導體晶片具有一電性作用面及一相對之另 一表面’該晶片之電性作用面具有複數電 藉由導熱膠黏層而以其另-表面接置於該散敎; =卑：由該散熱件有效傳遞熱量，另該半導體晶片：可 性連接塾以及複數形成於絕緣層中之導 (例如導電凸塊或導電盲孔），而據以延伸出線路結構。 槿制、Γ1卜’本發明之高散熱性之直接導通式半導體元件结 =該、可藉由電鑛、無電鑛及沈積等 形成多層線路結構。 迷仃曰層衣私以 因此’本發明所揭露之高散熱性之 ::結構之製法，主要係提供至少-半導㈣透過：導 :则接置於一例如為金屬板之散熱件上，以有效利用 该金屬板來逸散該半導體晶片於運作時產生之 、，用 藉由該金屬板提供該半導體裝置電磁遮蔽效果：且該二 18039 9 1238506 體晶片係整合於其承载件中 薄短小目的；此外， 值'^正肢厚度，以達輕 構’並可在該線路結構上設置有多數之；出線路結 料導體元件結财接電㈣接料部，以提供 再者，本發明同時可藉由整合該 與線路結構，而同時結入 x月’七、"導體晶片 技術之製程，俾提#。=3^之製造與半導體封裝 卞促1、各戶力而較大需求 業者製程與界面H用卩卩θ 間化半導體 打線或置晶等方式電性導接利用 時所需複雜製程及設備等問題。 彳电子裝置 【實施方式】 為使本發明之目的、特徵及功效 :同:f配合詳細揭露及圖式詳加說明如二當步:瞭： t 了以夕種形式實施之，以τ所述係、為本發明之n者 而非心限制本發明之範圍，合先敛明。 铂麥閱第2A至2G圖，俜為太扒的 一 道福十主谱口係為本發明之咼散熱性之直接 ，^ 肢兀件結構之製法剖面示意圖。 如弟2A圖所示，接供一吟办 曰Η $ ’、放心件2】，並將複數半導體 曰曰片,置於該散熱件21上。該散熱件21係為—全屬. 板，八材質可為一具高導熱係數之全屬鈉，而$主、胃_ - 曰片2?且女^ 双< 孟屬銅，而该+導體 :丰導；曰电’作用面❿及-相對之另-表面22b， ¥心曰片之電性作用面22a具有複數電性連接墊 晶片22係可藉由一例如銀膠之導熱膠黏層222 而另-表面饥接置於該散熱件21上，俾透過 J / ”、 18039 10 1238506 朦黏層222與該散熱件21所構成的散熱途#(Th—y CO二uctive =th)直接逸散該半導體晶片22運作所產生之 熱量，並可藉由該金屬材皙 土屬材貝之放熱件21以提供電磁遮蔽 (Shielding)效果。 如第2B圖所不，於該表面接置有半導體晶片η之散 熱件21上形成至少—絕緣層23。該絕緣層23可例如為環 氧樹脂（Epoxy純）、聚乙㈣㈣yimide)、氰脂（加敵 _〇、碳纖維（Carbon fiber)、ABF (Ajin〇m〇t〇 Bui】d up 日商味之素公司出產）、雙順丁稀二酸醒亞胺/三氮胖 (BT，Bmnakmnde triazine)、⑨合環氧樹脂與玻璃纖維亦 或光感應（PhGtoimagable)絕緣材料所構成。其中該絕緣 層23係可以單層形式直接形成於該散熱件21上，或以複 數層型式紐形成於散熱件上2卜例如先於該散敎件上形 成-對應半導體晶片設置位置形成有開口之絕緣層231， 再於該絕緣層231上形成另—絕緣層232(如第2b，圖所 示），而該絕緣層231與絕緣層232之材質可選自同—材料 或不同材料。之後即可於該絕緣層上形成圖案化線路層。 如第2C:該示，於該絕緣層23中形成有複數對應至 該電性連接墊22G位置之開口 23()，藉以顯露出該半導體 晶片22之電性連接墊22〇。其中若該絕緣層23之材質為 光感應絕緣層材料，則該開口 23〇係可以曝光、顯影方式 形成’相對若該絕緣層為—般非光感應絕緣層材料，則該 開口 230係可以雷射鑽孔方式形成。 如第2D圖所示，於該絕緣層23及其對應開口 2如處 18039 11 1238506 表面形成有一導電層24 行循程時所需之電流傳導物述進 合金材質，亦或可為導電高八 ^〜、焱之金屬或 料係為具有單、雙鏈交^ 厂，而該導電高分子材 物，例如聚乙块（Polya 《次方曰知相化合 。聚苯胺，…物 0>h〇t〇resist)，Α传利 乾M或;夜態光阻等光阻層 J八丁、刊用印刷、旋塗或貼人笠古斗、f丄 導電層24表面，再藉由曝光、 方：專方式形成於該 成有複數開口 250, #以&、以、方式加以圖案化以形 導12"二 出部分覆蓋於該阻層25下之 ¥电層24〇其中部分阻屉 ^ r ^ 230位置。 s汗250係對應於該絕緣層開口 24之圖所示’接著進行電鑛製程，藉由該導1 24之導電特性，俾 棺田遠蜍电層 於該阻層開口 250内之絕^:可作為電流傳導路徑，以 該絕緣層開π中Ζ 面形成有線路層26以及在 2 6係可藉由複數η ^ '結構2 6 G。其中該圖案化線路層 或導電盲孔料:緣層開口中之例如導電凸塊 U之電性連接塾22Q，亦即， ^至封導體晶片 接墊2 2 0以及複數形成 ^ = U電性連 導電盲孔等導带处拔y 23中例如導電凸塊或 μ 电、“冓260，據以電性延伸出外部。 :第2F圖所示，之後即可移除 该阻層25所霹芸々道个ρ 乂汉无則马 又凰¥电層24。如此即可在該絕緣層23上 18039 12 1238506 形成-圖案化線路層26。當然後續 … 製程，藉以在該絕緣層23上 路^丁線路增層 圖所示）。 夕θ、、泉路層26(如第2F， 如第2G圖所示，復於該線路層 亚令該圖案化防銲層27形成有複 4防1干層 圖案化線路層26’接著即可進行切單作^ Μ露出部分 呈現條片狀或呈現單顆狀之整合 1、，错以形成複數 22與提供該晶片22電性延伸出心：2卜半導體晶片 ϋ 4» ^ ... 、泉路層2 6的半導p & 、:構。“，對應於先前第奸，圖所示之 +::兀件 亦4形成一防銲層27，並令該 β θ，、表路層26上 數開口以顯露出部分圖案化線路Θ二6防^層2 7形成有複 作業，藉以形成複數呈現停 ^接者即可進行切單 熱件2卜半導體晶片現 =狀之整合有散 層線路層26的半導日日片2电性延伸出之多 W 千¥奴几件結構（如第2G，圖所示）。 另^閱第3®，承扣 中亦可在切單作業後 I:二其後製程中本發明 熱件”、半導發…與= 或二態之整合有散· 置複數供電性導接圓=線路層％上設 元件^可例如為輝球、辉=电導==其=該複數導電. 界。同樣地，如第4同仏_ 置接电丨生¥通至外 本發明中亦可在切不，承2〇,圖所示，其後製程中 合有散熱件2卜半於條片狀形態或單顆形態之整 •版日日片22與提供該晶片22電性延伸 18039 13 1238506 出之線路層26的半導體元件結 層26上形成複數等導電元件；二㈣之圓案化線路 2!上之半導體晶片卑提供接置於該散熱件 ra lL ^ 仟以直接電性導通至外界。 ’本發明所揭露之高散熱性之直接導通ϋ 疋件結構之製法，主要係提供至少_妾曰卜通式+導體 黏層接置於一例如為金屬板之散熱件：:日以J過-導 二金屬板來逸散該半導體晶片於運旦效利用 C供抖導體裝置電 ：： ::係整合於其承載件中，俾可縮且=導 独小目的；此外，本發明係於晶片 以達輕 構，並可在該線路結構上 接外接出線路結 該半導體元件結構直接€_ ^ ’以提供 明同時可藉由整合該散置。再者，本發 ^合晶片承載件之製造與半導體封二;： 乂供各戶端較大需求彈性以及簡化半導體業者制俾 協調問題’同時避免習知半導體晶：二、：面 及設備等問題。 …置日爾複雜製程 點及It所述之具體實施態樣’僅係用以例釋本發明之特 太^ ’而非用以限定本發明之可實施範嘴’在未脫離 二明士揭之精神與技術範田壽下，任何運用本發明所揭示 一二而元成之等效改變及修飾，均仍應為下 範圍所涵蓋。 T w專利 【圖式簡單說明】 18039 14 l2385〇6 第1圖係習知之CDBGA半導體封裝件之剖面示意圖; 第2A至2G圖係本發明之高散熱性之直接導通式半導 月息元件結構之製法剖面示意圖； 、 第2B圖係本發明之高散熱性之直接導通式半導體元 :結構之製法中於散熱件上形成有多層絕緣層之剖面：音 圖； 〜 第2F’圖係本發明中於絕緣層上形成多路層 面示意圖； 層並 昂3圖係本發明中於線路層上設置導剖 思圖；以及 面一!4圖係本發明中於多層線路層上設置導電元件之剖 田不思圖〇 主要元件符號說明】 10 封裝結構 11 基板 11a 正面 lib 背面 12 散熱件 13 半導體晶片 13a 電性作用面 13b 非電性作用 14 15 18039 1238506 15 封裝膠體 16 鲜球 111 開孔 21 散熱件 22 半導體晶片 22a 電性作用面 22b 另一表面 220 電性連接墊 222 導熱膠黏層 23 絕緣層 231 絕緣層 232 絕緣層 24 導電層 25 阻層 250 阻層開口 26 線路層 260 導電結構 27 防銲層 28 導電元件1238506 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a method for manufacturing a direct conduction semiconductor element structure with high heat dissipation, especially a semiconductor element structure that integrates a heat sink, a semiconductor wafer and a circuit structure at the same time. Its production method. [Previous technology] With the evolution of semiconductor packaging technology, semiconductor devices have developed different packaging types. Ball grid array (BGA) is an advanced semiconductor packaging technology, which is characterized by A substrate is used to set a semiconductor wafer, and a plurality of solder balls arranged in a grid array are arranged on the back of the substrate by using self-alignment technology, so that semiconductor wafer carriers of the same unit area It can accommodate more input / output connections (I / O connections) to meet the needs of highly integrated semiconductor wafers, so that the entire package unit can be soldered and electrically connected to the outside by these solder balls. A printed circuit board. However, the actual implementation of the above-mentioned package will cause many problems. First, because the density of electronic components and electronic circuits on the semiconductor wafer is high, the heat generated during its operation is large. If the heat generated by the semiconductor wafer is not effectively dissipated in time, , Will severely shorten the performance and life of the semiconductor wafer; Furthermore, the package lacks effective shielding effect and is easily affected by external electromagnetic and noise interference. Please refer to Fig. 1. In order to solve the above problem, a conventional Cavity-down ball grid array packaging structure (5 18039 1238506 cdbga) is a special shape ^?: In Γ The substrate is formed with -open ":: 2: guide :: The package structure 1G placed in the bottom cavity in an inverted manner at least includes: a ball grid array semiconductor crystal U, a plurality of strips 14, a heat sink 12, and at least A solder ball 16. The iron 'wire 14, the sealed body 15 and the plurality of substrates 11 have a front surface 1 丨 — 北 少 _ 门 π 17 · Moon surface 11 b' and is formed with an opening 111, and the heat dissipation member〗 Bl · M η / > 诃 shell is a high-conductivity material such as copper, and it is coupled to the substrate ..., k, 攸 11 front a, so that the soil continues The opening 111 of the plate 11 forms an opening " 13 and the ancient Yu ^ opens downward facing; the semiconductor crystal moon has an active surface 13a (Activesurf surface 13b (lnactive surface) household electricity injection 13), In the meantime, the semiconductor wafer & woman is placed in the opening 111 of the substrate 11 and its life-threatening effect is 13 b To the loose piece 丨 2, jealousy, warehouse / eight electricity 1V4lm month ... and then piece 12 and then,-the wire bonding process, so that the semiconducting f 14 Hj 1 + cattle ¥ version of Japan and Japan 13 electricity Connected to the surface of the substrate 11 is a U-dried V-version 13 pieces and bonding wires 14, and then, the ball implantation process is used to place a plurality of hands on the back m of the substrate η. 16 This is Wucheng formed the bottom cavity with a crystal ball grid array (CDBGA) package, and the mouth structure was 100;-4 package units can use the heat sink to solve its heat dissipation and shielding. But—Generally, to be able to successfully weld the solder ball to the Gubao P brush road board, the height of the solder ball configuration must be greater than the gate occupied by the wire arc, which seriously affects the layout of the substrate (Routabiiity) and solder ball configuration. High 18039 6 1238506: The density of the line arc is extremely high, the speaker, Yu Jin; r ^ ^ 01) 'Increase the difficulty of wire bonding operation; the substrate is placed in the cloth & wafer and wire mold and' —Nuclear epoxy resin is injected into the material, so its mold ruler L is limited by the design and solidification of the semiconductor package. There are some differences that make it impossible to clamp the substrate tightly. If the surface of the substrate is blocked, it will not only reduce the view, but also more likely to contaminate the substrate. In Note II Π: the electrical connection quality; Moreover, the tree chip and the substrate are electrically inserted into the mold cavity, and the system is improperly produced, the second == production, the overlay force, if the injection speed-controlled short-circuit gate problem, the second tongue, the earth force Punching the wire, causing the wire to touch and have reliability. '' Heavy influence on the production quality and product manufacturing of this semiconductor package :: The process of two semiconductor devices' is firstly carried by the wafer carrier: ==: = ?: one, such as Moulded, ::: Electrons required by the semiconductor sealing industry client: the energy path = (which includes the wafer carrier manufacturing industry and the semiconductor: t not = Cheng industry 1 d = = during the manufacturing process Not only the steps and the second boundary: the operator): Because 'when the right client wants to change the functional design, it involves changes and integration. 18039 7 1238506 The level is more complicated' and it does not meet the needs to change-m VL L j „妗, 纟 里 凊 efficiency. So, how to hunt for a simple process, the heat dissipation of a semiconductor device, electromagnetic interference, sealing, etc. can be solved at the same time, such as p A ,,, clothing board pressure and Integrating the process interface has become a problem that is urgently needed to be solved at present. [Summary of the Invention] The mention of the shortcomings of the known technology described above, the main purpose of the present invention is: direct conductive semiconductors for the heat dissipation of horses. Element structure dream method: 冋% integrated wafer carrier manufacturing and half to provide client comparison Dayun and Ka π k Menshiyiziyiyi's clothing 'Tian Qiu flexibility, while simplifying semiconductor semiconductor process and interface integration issues. This edition is a f-cloth style Fengyi Another purpose of the month is to provide-Species The heat dissipation of the direct conduction of the majority of the limb component structure is produced when the value of ¥ rnt discrete chip is used to operate the P ice set to provide electromagnetic shielding effects of semiconductor devices, to avoid external magnetic and magnetic interference. Another purpose of the month is to provide a method for manufacturing a direct conduction element structure with high heat dissipation, which can provide direct electrical V of the semiconductor chip to the outside, thereby improving the electrical quality. Another purpose of this month is to provide a high heat dissipation The method of directing the semiconductor device structure directly avoids the problem that the conventional semiconductor wafers are electrically connected to the circuit board and require complex processes and preparations. “Another object of the present invention is to provide a high heat dissipation. Direct-guided semi-'to component structure manufacturing method, to avoid problems such as molding and layout of the packaging process, and the problem of overflowing glue and layout, which effectively improves the half-body device Production quality and product reliability. 8 18039 1238506 2 For the above disclosure and other purposes, the direct conduction of high heat dissipation of the present invention is connected :::: The structure of the Gyro structure, which mainly includes: On the hot part; forming at least one insulating layer on the scattered part on which + conductor wafer is connected; forming at least one picture layer on the insulating layer, and electrically connecting the patterned circuit layer to the Semiconductor Crystal II: It can be operated in a single operation, and it will be a 70-wire structure with electrical extensions from the car n 4 broadcasted by Wei W. It can also be equipped with a number of power supply guides on the most similar patterned circuit layer. A conductive element connected to the outside world. One of the semiconductor wafers has an electrical active surface and an opposite surface. The electrical active surface of the wafer has a plurality of electrical connections with the other surface through a thermally conductive adhesive layer. In the scattered; = low: the heat is effectively transferred by the heat sink, and the semiconductor wafer: can be connected and a plurality of conductors (such as conductive bumps or conductive blind holes) formed in the insulating layer, and thus extend Line structure. Made of hibiscus, Γ1 ′, the high-heat-dissipating direct-conduction semiconductor device junction of the present invention can form a multi-layered circuit structure by using electric ore, non-electric ore, and deposits. The puzzle said that the layered clothing is based on the "high heat-dissipating :: structural method disclosed in the present invention, which mainly provides at least -semiconducting transmission: the conducting: is connected to a heat-dissipating member such as a metal plate, In order to effectively use the metal plate to dissipate the semiconductor wafer generated during operation, the metal plate is used to provide the electromagnetic shielding effect of the semiconductor device: and the two 18039 9 1238506 body wafers are integrated in their carrier parts. Purpose; In addition, the value is '^ thickness of the limb to achieve light structure' and a majority can be provided on the circuit structure; the outgoing line material is connected to the conductor element and the electrical connection is connected to the material receiving portion to provide further, the present invention At the same time, by integrating the circuit structure, and simultaneously entering the "Seventh," "conductor chip technology process," mention #. = 3 ^ Manufacturing and semiconductor packaging are promoted. 1. Each customer has a large demand, and the process and interface of the industry. H. Use θ to interpolate semiconductor wiring or crystals, and other complex processes and equipment. problem.彳 Electronic device [Embodiment] In order to make the object, features and effects of the present invention: the same as: f with detailed disclosure and detailed description of the drawings, such as two steps: the: t implemented in the form of the evening, described in τ It is the n of the present invention rather than the intention to limit the scope of the present invention. Platinum wheat is shown in Figures 2A to 2G. It is a blessing of the ten main scores of Taipa, which is the direct view of the heat dissipation of the invention. As shown in FIG. 2A, a yin-yin office is provided with a charge, and the rest piece 2], and a plurality of semiconductor pieces are placed on the heat-dissipating piece 21. The heat-dissipating member 21 is-all belong to. The plate, eight materials can be all sodium with a high thermal conductivity, and $ 主 、 胃 _-片 2? And female ^ double < Meng copper, and the + Conductor: Feng Dao; "Electric 'active surface" and-in contrast to-surface 22b, the electrical active surface 22a of the heart sheet has a plurality of electrical connection pads. The chip 22 can be bonded by a thermally conductive adhesive such as silver glue. Layer 222, and the other surface is placed on the heat sink 21, and the heat dissipation path formed by the haze layer 222 and the heat sink 21 is passed through J / ", 18039 10 1238506. (Th-y CO2uctive = th) The heat generated by the operation of the semiconductor wafer 22 is directly dissipated, and an electromagnetic shielding effect can be provided by the heat-dissipating member 21 of the metallic material and the metallic material. As shown in FIG. 2B, the surface is connected to the surface. At least an insulating layer 23 is formed on the heat sink 21 having the semiconductor wafer η. The insulating layer 23 may be, for example, epoxy resin (Epoxy pure), polyethylene yimide), cyanoester (Carbon fiber), carbon fiber (Carbon fiber), ABF (Ajin〇m〇t〇Bui) d up (produced by Nissho Ajinomoto Co., Ltd.), cis-butanedioic acid / imidazine (BT, Bmnakmnde triazine), composite epoxy resin and glass fiber, or PhGtoimagable insulation material. The insulation layer 23 can be formed directly on the heat sink 21 in a single layer, or in multiple layers. On the heat sink, for example, an insulating layer 231 is formed on the cooling member corresponding to the position where the semiconductor wafer is installed, and then another insulating layer 232 is formed on the insulating layer 231 (as shown in FIG. 2b). The material of the insulating layer 231 and the insulating layer 232 can be selected from the same material or different materials. Then, a patterned circuit layer can be formed on the insulating layer. As shown in FIG. 2C, the insulating layer 23 is formed in the insulating layer 23. There are a plurality of openings 23 () corresponding to the position of the electrical connection pad 22G, thereby exposing the electrical connection pad 22 of the semiconductor wafer 22. Where the material of the insulating layer 23 is a light-sensitive insulating layer material, the opening The 23 ° system can be formed by exposure and development. Relative to the non-photosensitive insulation layer material, the opening 230 can be formed by laser drilling. As shown in FIG. 2D, the insulation layer 23 Its pair Opening 2 such as 18039 11 1238506 A conductive layer is formed on the surface. The current conducting material required for 24 lines is described in alloy material, or it can be a metal or material with a high conductivity of ^ ~, 焱, and single or double chains. At the factory, and the conductive polymer material, such as polyethylene block (Polya "the second party is known as the phase combination. Polyaniline, ... object 0 > h〇t〇resist), A Chuanli M or; night light Resistive photoresist layer J Ba Ding, journal printing, spin coating or paste on the surface of the conductive layer 24, and then through exposure, square: formed in a special way on the surface with a plurality of openings 250, # 以 & It is patterned in a way to form a guide 12 " The second output part covers the electric layer 24 under the resistive layer 25, and a part of the resistive drawer ^ r ^ 230 position. s Khan 250 is shown in the figure corresponding to the opening 24 of the insulating layer, and then the electric mining process is performed. Based on the conductive properties of the conductive layer 1 24, the electrical layer of the far-field toad in the resist layer 250 is insulated ^: It can be used as a current conduction path. A wiring layer 26 is formed on the z-plane of the insulating layer, and a 2 6 G can be formed by a complex number η ^ 'in the 26 series. Wherein the patterned circuit layer or conductive blind via material: an electrical connection such as a conductive bump U in the opening of the edge layer 塾 22Q, that is, ^ to the sealed conductor wafer pad 2 2 0 and a plurality of ^ = U electrical properties Connect conductive strips such as conductive blind holes to pull out y 23 such as conductive bumps or μμ, “、 260, which extends electrically to the outside.: As shown in Figure 2F, the resist layer 25 can be removed afterwards. There is no way to do this. You can form a patterned circuit layer 26 on the insulating layer 23 18039 12 1238506. Of course, follow-up ... process to use the insulating layer 23 ^ As shown in the layer build-up diagram of the circuit, Xi θ, and the spring road layer 26 (as shown in Figure 2F, as shown in Figure 2G, the pattern layer solder mask 27 is formed with the pattern 4 solder mask layer 4 to prevent 1 dryness). Layer patterned circuit layer 26 ', and then can be singulated ^ Μ exposed parts appear strip-shaped or single-shaped integration 1, wrong to form a plurality of 22 and provide the wafer 22 electrical extension: 2 Semiconductor wafer ϋ 4 »^ ..., semiconductor layer p 6 & semiconducting p &,: structure.", Corresponding to the previous figure, + :: Also, a solder resist layer 27 is formed, and the β θ is formed on the surface road layer 26 to expose a part of the patterned lines. The second anti-layer 2 7 is formed with a complex operation to form a plurality of stops. Or you can cut a single hot piece 2 semiconductor wafer now = semi-conductor solar chip 2 with integrated scattered circuit layer 26 is electrically extended as much as a few thousand thousand pieces of structure (such as the 2G, the figure In addition, if you refer to Section 3®, after the order is cut, I can also use the hot parts of the present invention in semi-conductor process, semi-conductor, and = or two-state integration. The conductive connection circle = the circuit layer% is provided with a component ^ may be, for example, a glow ball, a glow = conductance == its = the complex number of conductive. Boundary. Similarly, as in the fourth example, the connection is connected to the outside. In the present invention, it is also possible to cut or not, as shown in the figure, and in the subsequent process, a heat sink 2 and a half in a strip-like shape or a single shape are integrated. • The Japanese-Japanese film 22 and the chip 22 are provided. Electrical extension 18039 13 1238506 The semiconductor element junction layer 26 of the circuit layer 26 forms a plurality of conductive elements; the semiconductor wafer on the second round circuit 2! The hot piece ra lL ^ 仟 is directly electrically connected to the outside world. 'The high-heat-dissipating direct conduction ϋ disclosed in the present invention is a manufacturing method of the structure, which mainly provides at least _ 妾 general formula + conductor adhesive layer connected to One example is a heat sink for a metal plate: The J-conductor metal plate is used to dissipate the semiconductor wafer. The C chip is used to supply the jitter conductor device during transportation: :: is integrated in its carrier. In addition, the present invention is based on a chip to achieve light structure, and the circuit structure can be connected to the circuit structure and the semiconductor element structure can be directly connected to the circuit structure. The interspersed. In addition, the present invention combines the manufacture of wafer carriers and semiconductor packaging; 乂 It provides greater flexibility for each client's needs and simplifies the semiconductor industry's manufacturing and coordination issues; while avoiding the familiarity with semiconductor crystals: II: Surfaces and equipment, etc. problem. … The complex process point of Zhiri'er and the specific implementation mode described in It are only used to illustrate the special features of the present invention ^ 'and are not intended to limit the implementable scope of the present invention' Under the spirit and technology of Fan Tianshou, any equivalent changes and modifications using the one or two yuan disclosed by the present invention should still be covered by the following scope. T w patent [simple description of the figure] 18039 14 l2385〇6 Figure 1 is a cross-sectional schematic diagram of a conventional CDBGA semiconductor package; Figures 2A to 2G are direct conductive semiconducting monthly semiconductor device structures with high heat dissipation properties of the present invention Schematic cross-sectional view of the manufacturing method; Figure 2B is a cross-section of a multi-layered insulating layer formed on a heat sink in the manufacturing method of the present invention: a direct-conductive semiconductor device with high heat dissipation of the present invention: sound diagram; ~ Figure 2F 'is the present invention A multi-layered schematic diagram is formed on the insulating layer; the layer 3 is a cross-sectional plan view of the circuit layer provided in the present invention; and the face 1! 4 is a section of the present invention where a conductive element is provided on a multilayer circuit layer Tian Busi Figure 〇 Key component symbols] 10 Package structure 11 Substrate 11a Front side lib Back side 12 Heat sink 13 Semiconductor wafer 13a Electrically active surface 13b Non-electrical interaction 14 15 18039 1238506 15 Packaging gel 16 Fresh ball 111 Opening hole 21 Heat dissipation Component 22 Semiconductor wafer 22a Electrically active surface 22b The other surface 220 Electrical connection pad 222 Thermally conductive adhesive layer 23 Insulating layer 231 Insulating layer 232 Insulating layer 24 Conductive Layer 25 Resistive layer 250 Resistive opening 26 Circuit layer 260 Conductive structure 27 Solder mask 28 Conductive element