1237900 案號：93128630 94年5月17日修正 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種低溫複晶矽薄膜電晶體（low temperature polysilicon thin film transistor，以下 簡稱LTPS TFT)的製作方法，尤指一種自行對準低溫複晶 矽互補式金氧半導體薄膜電晶體（LTPS comp 1 ementary meta卜oxide semiconductor TFT，以下簡稱 LTPS CMOS TFT) 的製作方法。 【先前技術】 由於液晶顯示器具有外型輕薄、耗電量少以及無輻射 污染等特性，故已被廣泛地應用在筆記型電腦、個人數位 助理（PDA)等攜帶式資訊產品上。然而隨著使用者對於顯示 器視覺感受要求的提昇，加上新技術應用領域不斷的擴 展，於是更高畫質、高解析度且具低價位的平面顯示器變 成未來顯示技術發展的趨勢，也造就了新的顯示技術發的 原動力，而LTPS TFT除了具有符合主動式驅動（actively drive)潮流的特性外，其技術是達成上述目標的一項重要 技術突破。 1237900 94年5月17曰修正 TFT-LCD)主 案號：93128630 低溫複晶矽薄膜電晶體液晶顯示器（LTps 要包含有至少-透明基板、-像素陣龍、—掃描線（scan line)驅動電路區與一資料線（data ijne)驅動電路區。其 中，像素陣列區係由複數條彼此平行的掃描線、複數條彼 此平行的資料線以及一液晶分子層所構成，且每一條掃描 線與每一條資料線均分別定義出一像素，而每一像素皆另 包含有一薄膜電晶體與一儲存電容（st〇rage1237900 Case No .: 93128630 Amended on May 17, 1994 9. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a low temperature polysilicon thin film transistor (hereinafter referred to as LTPS TFT). A manufacturing method, in particular a method for manufacturing a self-aligned low-temperature complex crystalline silicon complementary metal-oxide semiconductor thin film transistor (LTPS comp 1 ementary meta oxide semiconductor TFT, hereinafter referred to as LTPS CMOS TFT). [Previous Technology] Due to its thin and light appearance, low power consumption, and no radiation pollution, liquid crystal displays have been widely used in portable information products such as notebook computers and personal digital assistants (PDAs). However, with the improvement of users' requirements for display visual perception and the continuous expansion of new technology application fields, higher-quality, high-resolution and low-cost flat-panel displays have become the trend of future display technology development. In addition to the driving force behind the development of new display technologies, in addition to the characteristics of LTPS TFTs that are in line with the trend of active drive, its technology is an important technical breakthrough to achieve the above goals. 1237900 Revised TFT-LCD on May 17, 1994) Main case number: 93132630 Low temperature polycrystalline silicon thin film transistor liquid crystal display (LTps should include at least -transparent substrate, -pixel array, -scan line drive circuit Area and a data line (data ijne) driving circuit area, wherein the pixel array area is composed of a plurality of scan lines parallel to each other, a plurality of data lines parallel to each other, and a liquid crystal molecular layer, and each scan line and each A data line defines a pixel, and each pixel includes a thin film transistor and a storage capacitor (stOrage).
capacitor)。由於現行之 LTPS TFT-LCD 多係利用 LTPS CMOS TFT的製程技術，以整合標準的驅動積體電路（IC)於液晶 顯示面板之上’因而能夠減少顯示器的尺寸、降低生產成 本並縮短模組處理時間。 請參考第1圖至第5圖，第1圖至第5圖為習知製作 上閘極（top gate)結構之LTPS CMOS TFT 38之方法示意 圖。如第1圖所示，習知的LTPS CMOS TFT 38是由一 n型 低溫複晶矽薄膜電晶體34(以下簡稱NLTPS TFT)與一 p型 低溫複晶矽薄膜電晶體36(以下簡稱PLTPS TFT)所構成。 習知的LTPS CMOS TFT 38是製作於一玻璃基板1〇上，且 玻璃基板10表面包含有一第一區I與一第二區Π，是分 別用來形成驅動1C所需之NLTPS TFT 34與PLTPS TFT 36。 此外，玻璃基板10表面另包含有一像素陣列區（pixel array area，未顯示於第1圖中），是用來形成複數個呈陣 列排列之NLTPS TFT 34，用以作為液晶顯示器之像素單元 1237900 94年5月17日修正 案號：93128630 的開關元件（switching device)。 習知方法是先於玻璃基板10上形成一非晶石夕層 (amorphous silicon layer，α -Si layer，未顯示於第 r 圖中），接著進行一回火（annealing)製程，使得該非晶矽 層再結晶成為一複晶矽層（未顯示於第1圖中）。然後進行 一第一微影暨餘刻製程（photo-etching process，PEP)， 以於玻璃基板10之第一區丨與第二區丨丨上分別形成一圖 案化複晶矽層12，接著進行一低溫沉積製程，以於玻璃基 板10上形成一閘極絕緣（gate insulating，Gi)層μ，並 覆蓋於圖案化複晶矽層12之上，隨後於閘極絕緣層14上 形成一鋁金屬層（未顯示於第1圖中），再進行一第二微影 暨钱刻製私，以於第一區I與第二區Η之該鋁金屬層中分 別形成NLTPS TFT 34與PLTPS TFT 36之閘極電極（gate electrode)16 〇 接著如第2圖所示，利用閘極電極16當作一罩幕（mask) 來進行一離子佈植製程18，將磷離子植入未被閘極電極16 所覆蓋之圖案化複晶矽層12中，以形成複數個n型輕摻雜 區20。如第3圖所示，再於玻璃基板1〇上形成一光阻層（未 顯示於第3圖中），進行一第三微影暨蝕刻製程，以於該光 阻層中形成一圖案化光阻層22，覆蓋於第一區I之閘極電 極16與第二區II上，然後進行一離子佈植製程24，將砷 1237900 案號·· 93128630 94年5月17日修正 離子植入未被圖案化光阻層22所覆蓋之圖案化複晶矽層 12中’以形成二個N型重摻雜區26s與26d。其中，二個 N型重換雜區26s與26d是分別用來當作NLTPS TFT 34之 源極電極與汲極電極，且位於N型重摻雜區26s與26d兩 侧之二輕摻雜區2〇是用來當作NLTps TFT 34之輕摻雜汲 極（lightly doped drain, LDD)，而位於 NLTPS TFT34 之 間極電極16下方之未摻雜的圖案化複晶矽層12是用來當 作 NLTPS TFT 34 之通道（channel)區。 之後去除剩餘的圖案化光阻層22，如第4圖所示，再 於玻璃基板10上形成一另一光阻層（未顯示於第4圖中）， 進行一第四微影暨蝕刻製程，以於該光阻層中形成一圖案 化光阻層28 ’接著利用圖案化光阻層28與pltPS TFT 36 之閘極電極16當作一罩幕來進行一離子佈植製程3〇，將 硼離子植入未被圖案化光阻層28與閘極電極16所覆蓋之 圖案化複晶石夕層12中，以形成二p型重摻雜區323與32d， 分別用來當作PLTPS TFT 36之源極電極與汲極電極，而 位於閘極電極16下方之未掺雜的圖案化複晶矽層12是用 來當作PLTPS TFT 36之通道區。最後如第5圖所示，去除 剩餘的圖案化光阻層28，以分別形成NLTPS TFT 34與PLTPS TFT 36，完成習知LTPS CMOS TFT 38之製作。 簡而言之，習知製作LTPS CMOS TFT 38的方法，是先 1237900 94年5月17日修正 形成NLTPS TFT36與PLTPS TFT 36之閘極電極16之後， 再分別形成N型輕摻雜汲極2〇、N型源極電極與汲極電極， 以及P型源極電極與汲極電極。 上述之習知製作LTPS CMOS TFT 38的方法雖然已利用 閘極電極16作為自行對準的罩幕來形成n型輕摻雜區2〇, 但疋在形成NLTPS TFT 34的源極電極與没極電極時，仍需 要形成另一道光阻罩幕來進行佈植。然而當進行一微影製 程以步進機（stepper)或掃描機台來定義光阻罩幕的圖案 時，由於機器、基板、產品規格之不同或其他人為或非人 為因素，便有可能發生對準度不佳，亦即重疊（〇veHap> 或是錯位（misalignment)情形。例如，如第3圖所示， 可能會造成圖案化光阻層22發生往左偏移的情形，有部分 圖案化複晶矽層25未被摻雜，而使得所形成的N型汲極電 極範圍較預期的小，此外，也相對容易產生寬度不一致的 輕掺雜汲極20，這種不對稱（asymmetry)的輕摻雜汲極 不僅無法有效抑制熱電子效應（h〇t electr〇n effect)，甚 至會產生閘極電極的漏電流而引發元件的提早崩潰。因 此’如何製作寬度-致的輕摻雜沒極’並避免源極電極與 没極電極的範圍過於狹窄，以降低因微影製程所造成的對 準度不佳的問題，藉此減少產出元件的缺陷並提高良率 (yield),是目前LTPS TFT製作流程中的—大課題。 1237900 案號：93128630 94年5月17日修正 【發明内容】 本發明之一目的在於提供一種具有自行對準輕摻雜汲 極、自行對準源極電極與汲極電極之LTPS TFT的製作方 法’以避免因微影製程所造成的誤差。capacitor). Because the current LTPS TFT-LCD mostly uses LTPS CMOS TFT process technology to integrate a standard driver integrated circuit (IC) on the LCD panel, it can reduce the size of the display, reduce production costs, and shorten module processing. time. Please refer to FIGS. 1 to 5, which are schematic diagrams of a conventional method for fabricating a LTPS CMOS TFT 38 with a top gate structure. As shown in FIG. 1, the conventional LTPS CMOS TFT 38 is composed of an n-type low temperature polycrystalline silicon thin film transistor 34 (hereinafter referred to as NLTPS TFT) and a p-type low temperature polycrystalline silicon thin film transistor 36 (hereinafter referred to as PLTPS TFT). ). The conventional LTPS CMOS TFT 38 is fabricated on a glass substrate 10, and the surface of the glass substrate 10 includes a first region I and a second region Π, which are used to form the NLTPS TFT 34 and PLTPS required for driving 1C, respectively. TFT 36. In addition, the surface of the glass substrate 10 further includes a pixel array area (not shown in Fig. 1), which is used to form a plurality of NLTPS TFTs 34 arranged in an array and used as a pixel unit of a liquid crystal display 1237900 94 May 17, 2014 Amendment: switching device of 93132630. A conventional method is to form an amorphous silicon layer (α-Si layer (not shown in the r-th figure)) on the glass substrate 10, and then perform an annealing process to make the amorphous silicon layer The layer recrystallizes into a polycrystalline silicon layer (not shown in Figure 1). Then, a first photo-etching process (PEP) is performed to form a patterned polycrystalline silicon layer 12 on the first region 丨 and the second region 丨 丨 of the glass substrate 10, respectively, and then A low temperature deposition process to form a gate insulating (Gi) layer μ on the glass substrate 10 and cover the patterned polycrystalline silicon layer 12, and then form an aluminum metal on the gate insulating layer 14 Layer (not shown in Figure 1), and then a second lithography and money engraving process is performed to form NLTPS TFT 34 and PLTPS TFT 36 in the aluminum metal layer of the first region I and the second region, respectively. Gate electrode 16 〇 Next, as shown in FIG. 2, an ion implantation process 18 is performed using the gate electrode 16 as a mask to implant phosphorus ions into the non-gate electrode 16 to cover the patterned polycrystalline silicon layer 12 to form a plurality of n-type lightly doped regions 20. As shown in FIG. 3, a photoresist layer (not shown in FIG. 3) is formed on the glass substrate 10, and a third lithography and etching process is performed to form a pattern in the photoresist layer. The photoresist layer 22 covers the gate electrode 16 in the first region I and the second region II, and then an ion implantation process 24 is performed to insert arsenic 1237900 Case No. · 93128630 May 17, 1994 Correction ion implantation In the patterned polycrystalline silicon layer 12 not covered by the patterned photoresist layer 22, two N-type heavily doped regions 26s and 26d are formed. Among them, two N-type re-doped regions 26s and 26d are used as source and drain electrodes of NLTPS TFT 34, respectively, and are two lightly-doped regions on both sides of N-type heavily doped regions 26s and 26d. 20 is used as a lightly doped drain (LDD) of the NLTps TFT 34, and an undoped patterned polycrystalline silicon layer 12 located under the electrode 16 between the NLTPS TFT 34 is used as It is used as the channel area of NLTPS TFT 34. After that, the remaining patterned photoresist layer 22 is removed, and as shown in FIG. 4, another photoresist layer (not shown in FIG. 4) is formed on the glass substrate 10, and a fourth lithography and etching process is performed. In order to form a patterned photoresist layer 28 in the photoresist layer, then use the patterned photoresist layer 28 and the gate electrode 16 of pltPS TFT 36 as a mask to perform an ion implantation process 30. Boron ions are implanted into the patterned polycrystalline stone layer 12 not covered by the patterned photoresist layer 28 and the gate electrode 16 to form two p-type heavily doped regions 323 and 32d, which are used as PLTPS TFTs, respectively. The source electrode and the drain electrode of 36, and the undoped patterned polycrystalline silicon layer 12 below the gate electrode 16 are used as the channel region of the PLTPS TFT 36. Finally, as shown in FIG. 5, the remaining patterned photoresist layer 28 is removed to form NLTPS TFT 34 and PLTPS TFT 36 respectively, and the production of the conventional LTPS CMOS TFT 38 is completed. In short, the conventional method for making LTPS CMOS TFT 38 is to first modify the gate electrode 16 of NLTPS TFT36 and PLTPS TFT 36 on May 17, 1994, and then form N-type lightly doped drain electrodes 2 respectively. 〇, N-type source electrode and drain electrode, and P-type source electrode and drain electrode. Although the conventional method for manufacturing the LTPS CMOS TFT 38 has used the gate electrode 16 as a self-aligned mask to form the n-type lightly doped region 20, the source electrode and the electrode of the NLTPS TFT 34 are being formed. When the electrodes are used, another photoresist mask must be formed for implantation. However, when a lithography process is used to define the pattern of the photoresist mask using a stepper or a scanning machine, due to the differences in machine, substrate, product specifications, or other artificial or non-human factors, it may happen that Poor accuracy, that is, overlap (〇veHap> or misalignment). For example, as shown in FIG. 3, the patterned photoresist layer 22 may be shifted to the left, and some patterns are patterned. The polycrystalline silicon layer 25 is not doped, so that the range of the formed N-type drain electrode is smaller than expected. In addition, it is relatively easy to generate lightly doped drain electrodes 20 with inconsistent widths. This asymmetry Lightly doped drains not only fail to effectively suppress the hot electron effect, they can even cause leakage currents at the gate electrodes and cause the components to prematurely collapse. Therefore, 'How to make width-induced lightly doped And avoid the narrow range of the source electrode and the non-electrode electrode, so as to reduce the problem of poor alignment caused by the lithography process, thereby reducing the defects of the output components and improving the yield. LTPS A major issue in the manufacturing process of TFT. 1237900 Case No .: 93128630 Amended on May 17, 1994 [Summary of the Invention] An object of the present invention is to provide a self-aligned lightly doped drain electrode, self-aligned source electrode, and Manufacturing method of LTPS TFT with drain electrode 'to avoid errors caused by lithography process.
本發明之另一目的在於提供一種自行對準LTPS CMOS TFT的製作方法，以得到均勻對稱的輕摻雜汲極，且不須 增加額外製程。 本發明之一較佳實施例係揭露了 一種於一基板上製作 一雙重自行對準LTPS TFT的方法，該基板表面包含有至少 一第一區與至少一第二區，係分別用來製作至少一 NLTps TFT與至少一 PLTPS TFT。首先於該基板之該第一區與該第 二區上分別形成一未摻雜圖案化複晶矽層，且各該未摻雜 圖案化複晶矽層中皆包含有一源極區、一汲極區，以及一 通道區，再於該基板上方依序形成一介電層與一圖案化導 電層，覆蓋於該等未摻雜圖案化複晶矽層之上，且該第一 區之該圖案化導電層中包含有二個第一開口，接著進行一 苐一離子佈植製程，將N型摻質經由該二個第—開口自行 對準植入該未摻雜圖案化複晶石夕層之該源極區與該汲極區 中，以分別形成一 N型源極電極與一 N型汲極電極，然後 去除該圖案化導電層之寬度一預定距離，以於該圖案化導 1237900 案號：93128630 94年5月17日修正 電層中1成_個第二開口，並同時定義出該·^ TFT之 閘極電極之後進行_第二離子佈植製程，將N型播質 、、二由f 一個第―開σ自行對準植人該第-區之該未摻雜圖 案化稷4層中’以形成二個ν型輕摻雜祕，再於該第 一區=㈣案化導電層中形成該PLTPS TFT之-閘極電 極’取後於該第二區之該源極區與該汲極區中分別形成該 PLTPS m之》p型源極電極與—p型汲極電極。 根據本發明所揭露製作 TFT之方法是先利用圖案 化導電層當作-自行對準單幕來形成_源極與N型沒 極再利用縮小後之圖案化導電層當作一自行對準罩幕來 形成N型輕摻雜汲極，接著形成閘極電極，最後再利用間 極電極當作—自行對準罩幕來形成P型源極與P型没極， 因此本發明利用多次自行對準製程來形成LTps tft，不但 不會增加製程步驟，且可降低製程成本，並得到均勻對稱 的N型輕摻雜汲極，也能避免因為使用多道微影暨蝕刻製 程所可能造成的對位不精準問題。 【實施方式】 本發明揭露一種同時形成NLTPS TFT與PLTPS TFT的 方法，然而本發明之應用並不囿限於此。在本發明之較佳 1237900 案號：93128630 94年5月17曰修正Another object of the present invention is to provide a method for manufacturing a self-aligned LTPS CMOS TFT, so as to obtain a uniform and symmetrical lightly doped drain electrode without adding an additional process. A preferred embodiment of the present invention discloses a method for fabricating a dual self-aligned LTPS TFT on a substrate. The surface of the substrate includes at least a first region and at least a second region. An NLTps TFT and at least one PLTPS TFT. First, an undoped patterned polycrystalline silicon layer is formed on the first region and the second region of the substrate, and each of the undoped patterned polycrystalline silicon layers includes a source region and a drain. A polar region and a channel region, a dielectric layer and a patterned conductive layer are sequentially formed over the substrate, covering the undoped patterned polycrystalline silicon layers, and the first region The patterned conductive layer includes two first openings, and then a one-to-one ion implantation process is performed, and an N-type dopant is self-aligned and implanted into the undoped patterned polycrystalline stone through the two first-openings. In the source region and the drain region of the layer, an N-type source electrode and an N-type drain electrode are respectively formed, and then the width of the patterned conductive layer is removed by a predetermined distance, so that the patterned conductive layer 1237900 Case No .: 93128630 May 17, 1994 Corrected 10% of the second openings in the electrical layer, and at the same time defined the gate electrode of the TFT, and then performed the second ion implantation process, the N-type seeding, 2. Secondly, an un-doped patterned 稷 4 layer implanted in the? -Region is self-aligned by f? In order to form two ν-type lightly doped substrates, the -gate electrode of the PLTPS TFT is formed in the first region = the etched conductive layer, and then the source region and the drain region of the second region are taken out. The p-type source electrode and the p-type drain electrode of the PLTPS m are formed in the regions, respectively. The method for making a TFT according to the present invention is to first use a patterned conductive layer as a self-aligned single screen to form a source and N-type electrode, and then use the reduced patterned conductive layer as a self-aligned mask. To form an N-type lightly doped drain electrode, then to form a gate electrode, and finally to use an inter electrode as a way of self-aligning the mask to form a P-type source and a P-type electrode. The alignment process is used to form LTps tft, which not only does not increase the number of process steps, but also reduces the process cost, and obtains a uniform and symmetrical N-type lightly doped drain electrode. It also avoids the possible problems caused by the use of multiple lithography and etching processes. Inaccurate registration. [Embodiment] The present invention discloses a method for simultaneously forming an NLTPS TFT and a PLTPS TFT. However, the application of the present invention is not limited to this. The best in the present invention 1237900 Case No .: 93132630 Amended on May 17, 1994
貝此例中本發明之自行對準方法亦也可用來形成由NLTpS TFT與PLTPS ΤΠ所構成的LTps CM〇s TI?T。其中，利用本 發明方法所形成之 NLTPS TFT、PLTPS TFT 或 LTPS COMS TFT 係設於一液晶顯示器之周邊電路區（periphery circuit area)之内，用來作為該液晶顯示器之周邊電路的邏輯元件 (logic device)，而用來作為該液晶顯示器之像素單元之 開關元件（switching device)的NLTPS TFT，則亦可利用 本發明之方法同時形成於該液晶顯示器之像素陣列區 (pixel array area)内。 · 現以製作LTPS COMS TFT 74為例來作一說明。請參考 第6圖至第14圖，第6圖至第14圖為本發明之較佳實施 例製作LTPS CMOS TFT 74之方法示意圖。如第6圖所示， 本發明之LTPS CMOS TFT 74是製作於一基板40上，且基 板40表面包含有一 NLTPS TFT區III與一 PLTPS TFT區 IV，是分別用來形成一 NLTPS TFT 70與一 PLTPS TFT 72。 春 其中，基板40是為一透明的絕緣基板，例如一玻璃基板或 石英基板。 本發明方法是先進行一濺鍍製程，以於基板40上形成 〜厚度約介於400埃至6〇〇埃（angstrom，A)之非晶矽層 (未顯示於第6圖與第7圖中），接著進行一回火製程，例 如一準分子雷射退火（excimer laser annealing, ELA)製 12 1237900In this case, the self-alignment method of the present invention can also be used to form LTps CM0s TI? T composed of NLTpS TFT and PLTPS ΤΠ. Wherein, the NLTPS TFT, PLTPS TFT or LTPS COMS TFT formed by the method of the present invention is located in a peripheral circuit area of a liquid crystal display, and is used as a logic element of the peripheral circuit of the liquid crystal display. device), and the NLTPS TFT used as the switching device of the pixel unit of the liquid crystal display can also be simultaneously formed in the pixel array area of the liquid crystal display using the method of the present invention. · Let's take the production of LTPS COMS TFT 74 as an example. Please refer to FIGS. 6 to 14, which are schematic diagrams of a method for fabricating an LTPS CMOS TFT 74 according to a preferred embodiment of the present invention. As shown in FIG. 6, the LTPS CMOS TFT 74 of the present invention is fabricated on a substrate 40, and the surface of the substrate 40 includes an NLTPS TFT region III and a PLTPS TFT region IV, which are used to form an NLTPS TFT 70 and a PLTPS TFT 72. In which, the substrate 40 is a transparent insulating substrate, such as a glass substrate or a quartz substrate. The method of the present invention firstly performs a sputtering process to form an amorphous silicon layer (not shown in FIGS. 6 and 7) with a thickness of about 400 angstroms to 600 angstroms (angstrom, A) on the substrate 40. Middle), followed by a tempering process, such as an excimer laser annealing (ELA) 12 1237900
複晶矽層42。其中，每一圖案化複晶矽層42包含有—源 94年5月π臼修正 顯示於第6 以於基板40之 丨1J形成一圖案化 極區、一汲極區，以及一通道區（皆未顯示於第6圖中）。 且值得注意的是，回火製程也可以實施於第—微影暨钱刻 製私之後。此外，基板4〇與非晶矽層之間可另形成一緩衝 層（未顯示於第6圖中）以保護基板40避免受到回火製程與 蝕刻製程之損傷。 形成該導電層之材料係包含有鋁、鎢(w)、鉻(Cr)或鉬⑽ 至屬離子佈植製程52之佈植濃度約介於 1E14 至 1E16 接著進行一低溫沉積製程，以於基板上形成一厚产 約介於600至800埃之二氧化矽層或氮化矽層，用來當作 一閘極絕緣層44，並覆蓋於圖案化複晶矽層42之上，再 於閘極絕緣層44上依序形成一導電層46與一光阻層（未顯 示於第6圖巾）。然後進行-第二微影暨㈣製程，即先對 該光阻層實施一黃光製程，以形成-圖案化光阻層48，接 著再蝕刻未被圖案化光阻層48所覆蓋之導電層46，如第7 圖所不，以於導電層46中形成二個開口 50。隨後進行一 離子佈植製程52,將N型摻f經由二個開σ 5Q自行對準 植入圖案化複晶♦層42之源極區與祕區中，以分別 NLTPS TFT 70之一源極電極—與汲極電極54d。其中， 13 1237900 案號：93128630 94年5月17日修正 a toms/cm2之間’且N型換質係包含有石申原子（arSenic，As) 或磷原子（phosphorous, P)。 接著如第8圖與第9圖所示，進行一光阻縮小 (trimming)製程，使得圖案化光阻層48之寬度縮小一預定 距離L，再進行一蝕刻製程，去除未被縮小之圖案化光阻 層55所覆蓋之導電層46，使得導電層46之二個開口 50 的寬度變大，以形成二寬度較大之開口 56，並同時定義出 NLTPS TFT 70之一閘極電極58。然後進行一離子佈植製程 Φ 60,將N型摻質經由二個開口 56自行對準植入圖案化複晶 矽層42中，以形成二個N型輕摻雜汲極。其中，光阻 縮小製程係包含有一灰化（ash)製程、一削光阻（descum) 製程、一紫外光照射製程或一加熱固化（curing)製程，離 子佈植製程60之佈植濃度約介於1E12至iE14 atoms/cm2 之間，且N型摻質係包含有磷原子或碎原子。 如第10圖至第12圖所示’在去除縮小之圖案化光阻 層54之後’便於基板40上方形成一光阻層（未顯示於第 10圖至第12圖中）’然後進行一第三微影暨蝕刻製程：先 於該光阻層中形成一圖案化光阻層62，覆蓋於NLTps τπ 70之閘極電極58與PLTPS TFT區IV之通道區之上，之後 再進行一蝕刻製程，去除未被圖案化光卩且層62所覆蓋之導 電層46’以形成PLTPS TFT 72之一閉極電極料。4值得注 14 1237900 立 案號.93128630 94年5月17日修正 思的疋，由於圖案化光阻層62係用來定義出pltps TFT 72 之閘極電極64的圖案並同時用來保護NLTPS TFT 7〇之閘 極電極58，故圖案化光阻層62僅需完全覆蓋住NLTPS TFT 72之閘極電極64即可，因此在進行微影步驟時，可擁有 較大的對準容忍度，就异有些微的偏移誤差，也可確保閘 極電極64的完整性，以避免蝕刻製程對閘極電極64造成 影響。 去除剩餘的圖案化光阻層62後，如第13圖與第14圖 _ 所示，再於基板40上方形成一光阻層（未顯示於第13圖與 第14圖中），然後進行一第四微影暨蝕刻製程，先於該光 阻層中形成一圖案化光阻層66，接著進行一離子佈植製程 68 ’將P型摻質植入未被圖案化光阻層與閘極電極64 所覆蓋之圖案化複晶矽層42之源極區與汲極區中，以分別 形成PLTPS TFT 72之源極電極70s與汲極電極70d。最後 去除圖案化光阻層66，以分別形成NLTPS TFT 70與PLTPS · TFT 72 ’並完成本發明之LTPS CMOS TFT 74之製作。其中， 離子佈植製裎68之佈植濃度約介於 1E14 至 1E16 atoms/cm2 之間’且P型摻質係包含有硼原子（boron, B)或氟化硼 (BF2)。 接著請參考第15圖至第21圖，第15圖至第21圖為 本發明之第二實施例製作LTPS CMOS TFT 120之方法示意 15 l2379〇〇 案號：93128630 94年5月17日修正 圖。如第15圖所示，本發明之LTPS CMOS TFT 120是製作 於—基板80上，且基板80表面包含有一 NLTPS TFT區V 與一 PLTPS TFT區VI，是分別用來形成一 NLTPS TFT 114 與一 PLTPS TFT 116。首先於基板80上形成一複晶矽層（未 顯示於第15圖中），接著進行一第一微影暨蝕刻製程，以 於基板80之NLTPS ΤΠ區V與PLTPS TFT區VI上分別形 成一圖案化複晶石夕層82，再於基板80上依序形成一閘極 絶緣層84，一導電層86與一光阻層88。 然後進行一第二微影暨姓刻製程，如第16圖與第17 圖所示，先於光阻層88中形成二個開口 90，再進行一等 =性蝕刻製程，例如濕蝕刻製程，去除未被光阻層88所覆 蓋之導電層86，以於導電層86中形成二個開口 92，且開 92之見度大於開口 90之寬度，並同時定義出nltpS TFT 114之一閘極電極94。然後利用光阻層當作一罩幕來進 仃一 N型離子佈植製程96，以於圖案化複晶矽層82中形春 成〜個N型重摻雜區98S與98d。接著去除光阻層88，再 利用閘極電極94與導電層86當作一罩幕來進行一 N型離 =佈植製程1〇〇,以於NLTPS聊區v之圖案化複晶石夕層 •中形成複數個N型輕摻雜區1〇2與1〇4。其中，二個n 重摻雜區98s與98d是分別用來當作NLTPS TFT 114之 源極電極與沒極電極，且位於N型重摻雜區98s與98d兩 之—個N型輕摻雜區102是用來當作NLTPS TFT 114之 16 l2379〇〇 輕摻雜 未摻雜 案號：93128630 94年5月17日修正 >及極，而位於NLTPS TFT 114之閘極電極94下方之 的圖案化複晶石夕層82是用來當作NLTPS TFT 114之 通道區。 如第18圖至第19圖所示，於基板80上方形成一光阻 層（未顯示於第18圖中），進行一第三微影暨蝕刻製程，先 於該光阻層中形成一圖案化光阻層104，再蝕刻未被圖案 化光阻層104所覆蓋之導電層86，以形成PLTPS TFT 116 之一閘極電極106，然後利用圖案化光阻層1 當作一罩 幕來進行一離子佈植製程1〇8，以於pltps TFT區VI之源 極區與汲極區中分別形成二P型重摻雜區11〇s與u〇d， 分別用來當作PLTPS TFT 116之源極電極與p型汲極電極。 如第20圖與第21圖所示，在去除剩餘的圖案化光阻 層104之後，隨即進行一第四微影暨蝕刻製程··先於基板 80上形成一圖案化光阻層112，覆蓋於TFT 114之 閘極電極104與PLTPS TFT 116之閘極電極1〇6上方，再 進行一蝕刻製程，去除未被圖案化光阻層U2所覆蓋之導 電層86。隶後去除圖案化光阻層112,以分別形成nltps TFT 114 與 PLTPS TFT 116 ’ 並完成本發明之 ltps CMOS TFT 120 的製作。 值得注意的是，在上述之本發明各實施例中，係以形 17 1237900 案號：93128630 0/1 . 94年5月Π曰修正 成一上閘極結構之LTPS CMOS TFT為主要目的，然本發明 之應用並不囿限於此，本發明方法亦可以同時形成低溫複 晶矽薄膜電晶體液晶顯示器（LTPS TFT-LCD)之掃描線、資 料線、儲存電容與其他低溫複晶矽薄膜電晶體。此外，在 本發明之較佳實施例與第二實施例中，係各別揭露兩種形 成NLTPS TFT與PLTPS ΤΠ之方法，然而本發明之製作^ 法並不限定於此，本發明亦可利用較佳實施例中所敘述之 方法形成NLTPS TFT(如第6圖至第1〇圖），再利用第一 施例中所敘述的方法形成PLTPS TFT(如第11圖至第14 圖），反之亦然。 簡言之，本發明製作LTPS CMOS TFT之方法是先利 圖案化導電層當作-自行對準罩幕，來形成\型源極電極 與N型汲極電極，再利用縮小後之圖案化導電層當作—W 行對準罩幕，來形成N型輕摻雜汲極，接著再形成閘極電 極，最後利用閘極電極當作一自行對準罩幕，來形成p \ 源極電極與P型汲極電極，因此本發明利用多次自行對= 製程來形成LTPS CMOS TFT ’不但不會增加製程步驟，且 可降低製程成本，並得到均勻對稱的N型輕摻雜汲極，也 能避免因為使用多道微影暨蝕刻製程所可能造成的對位 精準問題。 + 相較於習知製作LTPS TFT的方法，本發明主要利用多 18 1237900 94年5月17日修正 道自行對準製程來分別形成源極電極、汲極電極與輕摻雜 汲極，因此可避免因多道微影製程所產生的錯位問題，且 本發明方法與習知方法皆使用四道微影暨蝕刻製程，因此 完全不會增加製程步驟，且可提昇產品的可靠度與電性表 現。又本發明之自行對準方法不僅可用來分別形成NLTps TFT與PLTPS TFT，亦適用於LTPS CMOS TFT的製程中。 以上所述僅為本發明之較佳實施例，凡依本發明申請 專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範 · 圍。 【圖式簡單說明】 第1圖至第5圖為習知製作LTPS CMOS TFT之方法示意 圖。 第6圖至第14圖為根據本發明製作LTps CMOS TFT之 方法較佳實施例之示意圖。 φ 第I5圖至第21圖為本發明之第二實施例製作LTPS CM〇s TFT之方法示意圖。 【主要元件符號說明】 10玻璃基板 12 圖案化複晶矽層 19 1237900 94年5月17日修正 案號：93128630 14 閘極絕緣層 16 閘極電極 18 離子佈植製程 20 N型輕摻雜區 22 圖案化光阻層 24 離子佈植製程 26s N型源極電極 26d N型汲極電極 28 圖案化光阻層 30 離子佈植製程 32s P型源極電極 32d P型汲極電極 34 NLTPS TFT 36 PLTPS TFT 38 LTPS CMOS TFT 40 基板 42 圖案化複晶矽層 44 閘極絕緣層 46 導電層 48 圖案化光阻層 50 開口 52 離子佈植製程 54s N型源極電極 54d N型汲極電極 55 縮小之圖案化光阻層 56 開口 58 閘極電極 60 離子佈植製程 62 圖案化光阻層 64 閘極電極 66 圖案化光阻層 68 離子佈植製程 70 NLTPS TFT 72 PLTPS TFT 74 LTPS CMOS TFT 80 基板 82 圖案化複晶矽層 84 閘極絕緣層 86 導電層 88 圖案化光阻層 90 開口 92 開口 94 閘極電極 96 離子佈植製程复 晶 硅 层 42。 Compound silicon layer 42. Wherein, each patterned polycrystalline silicon layer 42 includes a source-corrected π-mold shown on the 6th in May 1994 to form a patterned pole region, a drain region, and a channel region (1J on the substrate 40). (Not shown in Figure 6). It is also worth noting that the tempering process can also be implemented after the first microlithography and money carving. In addition, another buffer layer (not shown in FIG. 6) may be formed between the substrate 40 and the amorphous silicon layer to protect the substrate 40 from being damaged by the tempering process and the etching process. The material forming the conductive layer includes aluminum, tungsten (w), chromium (Cr), or molybdenum. The implantation concentration of the metal ion implantation process 52 is about 1E14 to 1E16, and then a low-temperature deposition process is performed on the substrate. A silicon dioxide layer or silicon nitride layer with a thickness of about 600 to 800 angstroms is formed thereon, which is used as a gate insulating layer 44 and covers the patterned polycrystalline silicon layer 42. A conductive layer 46 and a photoresist layer are sequentially formed on the electrode insulating layer 44 (not shown in FIG. 6). Then, a second lithography and photolithography process is performed, that is, a yellow light process is performed on the photoresist layer to form a patterned photoresist layer 48, and then a conductive layer not covered by the patterned photoresist layer 48 is etched. 46, as shown in FIG. 7, two openings 50 are formed in the conductive layer 46. Subsequently, an ion implantation process 52 is performed, and the N-type doped f is implanted into the source region and the secret region of the patterned compound 48 through two open σ 5Q self-alignment to separate one source of the NLTPS TFT 70. Electrode—and drain electrode 54d. Among them, 13 1237900 Case No .: 93132630 Amended on May 17, 1994 a toms / cm2 ’and the N-type replacement system contains arSenic (As) or phosphorous (P) atoms. Then, as shown in FIGS. 8 and 9, a trimming process is performed to reduce the width of the patterned photoresist layer 48 by a predetermined distance L, and then an etching process is performed to remove the unreduced patterning. The conductive layer 46 covered by the photoresist layer 55 makes the widths of the two openings 50 of the conductive layer 46 larger to form two wider openings 56, and simultaneously defines a gate electrode 58 of the NLTPS TFT 70. Then, an ion implantation process Φ 60 is performed, and the N-type dopant is self-aligned into the patterned polycrystalline silicon layer 42 through the two openings 56 to form two N-type lightly doped drain electrodes. The photoresist reduction process includes an ash process, a descum process, an ultraviolet irradiation process, or a curing process. The ion implantation process 60 has a planting concentration of about 60%. Between 1E12 and iE14 atoms / cm2, and the N-type dopant system contains phosphorus atoms or broken atoms. As shown in FIGS. 10 to 12 'after removing the reduced patterned photoresist layer 54', it is convenient to form a photoresist layer over the substrate 40 (not shown in FIGS. 10 to 12) 'and then a first Three lithography and etching process: A patterned photoresist layer 62 is formed in the photoresist layer, covering the gate electrode 58 of NLTps τπ 70 and the channel region of PLTPS TFT region IV, and then an etching process is performed. , Removing the unpatterned photoconductor and the conductive layer 46 ′ covered by the layer 62 to form a closed electrode material of PLTPS TFT 72. 4 Worth note 14 1237900 Case No. 93128630 Revised May 17, 1994, because the patterned photoresist layer 62 is used to define the pattern of the gate electrode 64 of pltps TFT 72 and also used to protect NLTPS TFT 7 〇 the gate electrode 58, so the patterned photoresist layer 62 only needs to completely cover the gate electrode 64 of the NLTPS TFT 72, so when performing the lithography step, it can have a larger alignment tolerance, which is different. Some slight offset errors can also ensure the integrity of the gate electrode 64 to prevent the etching process from affecting the gate electrode 64. After removing the remaining patterned photoresist layer 62, a photoresist layer (not shown in FIGS. 13 and 14) is formed on the substrate 40 as shown in FIGS. 13 and 14_, and then a In the fourth lithography and etching process, a patterned photoresist layer 66 is formed in the photoresist layer, and then an ion implantation process 68 is performed to implant a P-type dopant into the unpatterned photoresist layer and the gate electrode. In the source region and the drain region of the patterned polycrystalline silicon layer 42 covered by the electrode 64, a source electrode 70s and a drain electrode 70d of the PLTPS TFT 72 are respectively formed. Finally, the patterned photoresist layer 66 is removed to form NLTPS TFT 70 and PLTPS · TFT 72 ′ and complete the fabrication of the LTPS CMOS TFT 74 of the present invention. Among them, the implantation concentration of the ion-implanted plutonium 68 is about 1E14 to 1E16 atoms / cm2 'and the P-type dopant contains boron (Bron) or boron fluoride (BF2). Please refer to FIG. 15 to FIG. 21. FIGS. 15 to 21 are schematic diagrams of a method for manufacturing an LTPS CMOS TFT 120 according to a second embodiment of the present invention. 15 123790000 Case No .: 93128630 Amended on May 17, 1994 . As shown in FIG. 15, the LTPS CMOS TFT 120 of the present invention is fabricated on a substrate 80, and the surface of the substrate 80 includes an NLTPS TFT region V and a PLTPS TFT region VI, which are used to form an NLTPS TFT 114 and a PLTPS TFT 116. First, a polycrystalline silicon layer (not shown in FIG. 15) is formed on the substrate 80, and then a first lithography and etching process is performed to form a layer on the NLTPS TΠ region V and the PLTPS TFT region VI of the substrate 80, respectively. The polycrystalline spar layer 82 is patterned, and a gate insulating layer 84, a conductive layer 86 and a photoresist layer 88 are sequentially formed on the substrate 80. Then, a second photolithography and surname engraving process is performed. As shown in FIGS. 16 and 17, two openings 90 are formed in the photoresist layer 88, and then a first-rate etching process, such as a wet etching process, is performed. The conductive layer 86 not covered by the photoresist layer 88 is removed to form two openings 92 in the conductive layer 86, and the visibility of the opening 92 is greater than the width of the opening 90, and at the same time, one of the gate electrodes of the nltpS TFT 114 is defined 94. Then, a photoresist layer is used as a mask to perform a N-type ion implantation process 96 to form ~ N-type heavily doped regions 98S and 98d in the patterned polycrystalline silicon layer 82. Next, the photoresist layer 88 is removed, and the gate electrode 94 and the conductive layer 86 are used as a mask to perform an N-type ion implantation process 100, in order to pattern the polycrystalline spar layer in the NLTPS chat area v. • A plurality of N-type lightly doped regions 102 and 104 are formed in the substrate. Among them, the two n-doped regions 98s and 98d are used as the source electrode and the non-electrode electrode of the NLTPS TFT 114, respectively, and are located between the N-type heavily-doped regions 98s and 98d-one N-type lightly doped The region 102 is used as a 16-12379 lightly-doped NLTPS TFT 114. Case No .: 93128630 Amended May 17, 1994 > and is located below the gate electrode 94 of the NLTPS TFT 114. The patterned polycrystalline spar layer 82 is used as a channel region of the NLTPS TFT 114. As shown in FIGS. 18 to 19, a photoresist layer (not shown in FIG. 18) is formed over the substrate 80, and a third lithography and etching process is performed, and a pattern is formed in the photoresist layer first. The photoresist layer 104 is patterned, and then the conductive layer 86 not covered by the patterned photoresist layer 104 is etched to form a gate electrode 106 as one of the PLTPS TFT 116, and then the patterned photoresist layer 1 is used as a mask. An ion implantation process 108 is performed to form two P-type heavily doped regions 11 s and u 0d in the source region and the drain region of the pltps TFT region VI, respectively, and are used as the PLTPS TFT 116. Source electrode and p-type drain electrode. As shown in FIG. 20 and FIG. 21, after removing the remaining patterned photoresist layer 104, a fourth lithography and etching process is performed immediately. A patterned photoresist layer 112 is formed on the substrate 80 to cover An etching process is performed on the gate electrode 104 of the TFT 114 and the gate electrode 106 of the PLTPS TFT 116 to remove the conductive layer 86 not covered by the patterned photoresist layer U2. The patterned photoresist layer 112 is subsequently removed to form nltps TFT 114 and PLTPS TFT 116 ', respectively, and complete the fabrication of the ltps CMOS TFT 120 of the present invention. It is worth noting that in the above-mentioned embodiments of the present invention, the main purpose is to modify the LTPS CMOS TFT with an upper gate structure in the form of 17 1237900 case number: 93128630 0/1. May 1994 The application of the invention is not limited to this. The method of the present invention can also form scan lines, data lines, storage capacitors, and other low-temperature polycrystalline silicon thin-film transistors at the same time. In addition, in the preferred embodiment and the second embodiment of the present invention, two methods for forming the NLTPS TFT and the PLTPS ΤΠ are disclosed separately, but the manufacturing method of the present invention is not limited to this, and the present invention can also be used The method described in the preferred embodiment forms an NLTPS TFT (as shown in Figures 6 to 10), and then uses the method described in the first embodiment to form a PLTPS TFT (as shown in Figures 11 to 14), and vice versa The same is true. In short, the method for fabricating LTPS CMOS TFT according to the present invention is to first use a patterned conductive layer as a self-alignment mask to form a \ -type source electrode and an N-type drain electrode, and then use the reduced patterned conductive layer. The layer is regarded as a W-line alignment mask to form an N-type lightly doped drain electrode, and then a gate electrode is formed. Finally, the gate electrode is used as a self-aligned mask to form a p \ source electrode and P-type drain electrode, so the present invention uses multiple self-pairing = processes to form an LTPS CMOS TFT 'not only does not increase the number of process steps, but also reduces the process cost, and obtains a uniform and symmetrical N-type lightly doped drain electrode. Avoid alignment problems caused by using multiple lithography and etching processes. + Compared with the conventional method for making LTPS TFT, the present invention mainly uses a self-aligning process of 18, 12 37, 900, May 17, 1994 to form a source electrode, a drain electrode, and a lightly doped drain electrode, respectively. Avoiding misalignment problems caused by multiple lithography processes, and the method and the conventional method of the present invention use four lithography and etching processes, so the process steps are not added at all, and the reliability and electrical performance of the product can be improved . In addition, the self-aligning method of the present invention can be used not only to form NLTps TFT and PLTPS TFT separately, but also to be applicable to the manufacturing process of LTPS CMOS TFT. The above description is only a preferred embodiment of the present invention, and any equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the present invention. [Schematic description] Figures 1 to 5 are schematic diagrams of a conventional method for manufacturing an LTPS CMOS TFT. 6 to 14 are schematic diagrams of a preferred embodiment of a method for fabricating an LTps CMOS TFT according to the present invention. φ FIGS. I5 to 21 are schematic diagrams of a method for fabricating an LTPS CM0s TFT according to a second embodiment of the present invention. [Description of main component symbols] 10 Glass substrate 12 Patterned polycrystalline silicon layer 19 1237900 May 17, 1994 Amendment number: 93128630 14 Gate insulation layer 16 Gate electrode 18 Ion implantation process 20 N-type lightly doped region 22 Patterned photoresist layer 24 Ion implantation process 26s N-type source electrode 26d N-type drain electrode 28 Patterned photoresist layer 30 Ion-implantation process 32s P-type source electrode 32d P-type drain electrode 34 NLTPS TFT 36 PLTPS TFT 38 LTPS CMOS TFT 40 Substrate 42 Patterned polycrystalline silicon layer 44 Gate insulating layer 46 Conductive layer 48 Patterned photoresist layer 50 Opening 52 Ion implantation process 54s N-type source electrode 54d N-type drain electrode 55 Zoom out Patterned photoresist layer 56 opening 58 gate electrode 60 ion implantation process 62 patterned photoresist layer 64 gate electrode 66 patterned photoresist layer 68 ion implantation process 70 NLTPS TFT 72 PLTPS TFT 74 LTPS CMOS TFT 80 substrate 82 patterned polycrystalline silicon layer 84 gate insulating layer 86 conductive layer 88 patterned photoresist layer 90 opening 92 opening 94 gate electrode 96 ion implantation process
20 1237900 案號：93128630 94年5月17日修正20 1237900 Case No .: 93132630 Amended on May 17, 1994
98s N型源極電極 98d 100 離子佈植製程 102 104 圖案化光阻層 106 108 離子佈植製程 110s 110d P型汲極電極 112 114 NLTPS TFT 116 120 LTPS CMOS TFT98s N-type source electrode 98d 100 ion implantation process 102 104 patterned photoresist layer 106 108 ion implantation process 110s 110d P-type drain electrode 112 114 NLTPS TFT 116 120 LTPS CMOS TFT
N型 >及極電極 N型輕摻雜汲極 閘極電極 P型源極電極 圖案化光阻層 PLTS TFT 21N-type > and electrode N-type lightly doped drain gate electrode P-type source electrode patterned photoresist layer PLTS TFT 21