CN1249929C - Amplitude limiter for predicting parallel branch and amplitude limiting method - Google Patents

Abstract

The present invention relates to a parallel branch predicting amplitude limiter and an amplitude limiting method, which is used for a self-adaptive determined feedback equalizer. The parallel branch predicting amplitude limiter comprises M<n> fixed coefficient adders, M<n> amplitude limiters, a first multiplexer and n delay units connected in series. The method comprises the following steps that after a signal to be processed and M<n> default values are received, the add operations of the signal and the default values are respectively carried out, M<n> output signals are obtained, and M is a whole number and is greater than 1. The output signals are respectively received and are processed in an amplitude limiting mode, and consequently, M<n> amplitude limiting signals with M<n> electrical levels are respectively output. One of the amplitude limiting signals is selected and output according to selecting signals of n different delay times.

Description

Prediction parallel branch amplitude limiter and amplitude limit method

Technical field

The present invention relates to a kind of prediction parallel branch amplitude limiter (Predicted Parallel Branch Slicer) and amplitude limit method, finger is applied to prediction parallel branch amplitude limiter and the amplitude limit method in the adaptive determining feedback equalizer especially.

Background technology

In recent years, international electronic motor Ssociety of engineers (IEEE) has been stipulated the transmission standard of Gigabit Ethernet network (GigabitEthernet).In this transmission standard, (Unshield Twisted Pair-Category 5, UTP-CAT5) four lines in the transmission line transmit the data of gigabits/second to utilize multiple twin cable-Di five classes that tool not covers.And be to meet transmission rate so fast, the transmission receiver (transceiver) of each network node must overcome symbol intersymbol interference (Inter-Symbol Interference, ISI), echo (Echo), near-end crosstalk (near-end Cross Talk, nEXT) and long-range cross-talk (Far-end Cross Talk, the noise that phenomenon caused such as FEXT).

See also Figure 1A, it is the functional block diagram of the transmission receiver of a network node in the Gigabit Ethernet network, wherein on the signal RX path, be multiple twin cable-Di five class transmission lines 10 that an analog signal is covered through tool not, blender (hybrid) 11, AFE (analog front end) (Analog Front End, AFE) 12 with analog-digital converter (Analog-to-Digital Converter, ADC) after 13 the processing, formation one only has the digital data signal x (n) (long-range cross-talk can be left in the basket) of symbol intersymbol interference phenomenon and sends into follow-up adaptive determining feedback equalizer (Adaptive Decision Feedback Equalizer, ADFE) 16 handle, after removing this symbol intersymbol interference phenomenon, send into the decoder (decoder) 17 of back segment again, bag and information born of the same parents interchanger (Packet and Cell Switch, PCS) 18 handle with medium access controller (Medium Access Controller) 19, last then the numerical data of finishing dealing with is delivered to network node itself, this example is a personal computer 20.And, bag also can be exported some signals with information born of the same parents interchanger 18, and is sent to adaptive determining feedback equalizer 16 via an adaptive echo cancellation element (Adaptive EchoCanceller) 14 and one self adaptation near-end crosstalk cancellation element (Adaptive nEXT Canceller) 15 respectively.And Figure 1B expresses the channel impulse response waveform schematic diagram of a digital data signal x (n), wherein the left side of dotted line is commonly called the intersymbol interference (PrecursorISI) of leading portion symbol, and the right side of dotted line then is called as the intersymbol interference (PostcursorISI) of back segment symbol.

See also Fig. 2 A again, it is the functional block diagram of first kind of known adaptive determining feedback equalizer 16, it is mainly by feed forward equalizer 21 (Feed Forward Equalizer, FFE) with feedback equalizer 22 (FeedBack Equalizer, FBE) finish, feed forward equalizer 21 is respectively in order to eliminate leading portion symbol intersymbol interference and the intersymbol interference of back segment symbol with the major function of feedback equalizer 22, and the coefficient of feed forward equalizer 21 and feedback equalizer 22 comes the computing value of making new advances to upgrade by the first coefficient update device 23 and the second coefficient update device 24 according to error signal e (n) and the data such as old value of itself respectively, will must return digital data signal d (n) after signal y (n) amplitude limitization as for 25 of amplitude limiters.And this adaptive determining feedback equalizer 16 mainly is to carry out a least mean square algorithm (Least-Mean-Square Algorithm, LMS algorithm), and following formula is expressed the mathematical relationship between each signal and coefficient.

$y\left(n\right)=\underset{k=0}{\overset{N_f-1}{\mathrm{\&Sigma;}}}x(n-k)w_k\left(n\right)-\underset{k=1}{\overset{N_b-1}{\mathrm{\&Sigma;}}}d(n-k)f_k\left(n\right)$

d(n)＝Q[y(n)]

e(n)＝d(n)-y(n)

w _k(n+1)＝w _k(n)+μx(n-k)e(n)

f _k(n+1)＝f _k(n)+μd(n-k)e(n)

And the data processing speed of above-mentioned adaptive determining feedback equalizer 16 is to be subject to (the Decision Feedback Loop of the decision feedback loop shown in Fig. 2 A, DLP) limited frequency range and can't speeding, and be to improve this shortcoming, pipeline processing (pipeline) is a good developing direction, so, second kind of known adaptive determining feedback equalizer shown in Fig. 2 B just is developed, its detailed content can be referring to naresh R.Shanbhag, Keshab K.Parhi, " Pipelined adaptive DFEarchitectures using relaxed look-ahead; " IEEE Trans.Signal Processing, vol.43, no.6, pp.1368-1385, June 1995., thus this not with give unnecessary details.And the main difference of itself and first kind of known technology is in has additionally been increased n delay cell in the decision feedback loop, for asking clear expression, a said n delay cell is drawn in figure outside the feedback equalizer 22, but in fact, an extra said n delay cell that increases is arranged among the feedback equalizer 22 often, in the hope of the circuit region of script feedback equalizer 22 is divided into n+1 group's electronic circuit, be all to have a delay cell between each group electronic circuit, and then can utilize this n+1 group's electronic circuit to carry out the pipeline equalization, and then promote whole processing speed.But thus, to make that (coordinate of Fig. 2 C only is used to represent the relative size relation to the waveform response exemplary plot that feedback equalizer 22 seen shown in Fig. 2 C the time of delay of improper increase, so reference axis does not have absolute unit), because extra n the delay cell that increases, to make the back segment symbol intersymbol interference relevant be restricted to zero with a preceding n unit delay time, as arrow indication place, cause feedback equalizer 22 correctly to operate and make the signal to noise ratio of entire system significantly to reduce.Therefore, though can making feedback equalizer 22 be carried out the pipeline running, said method allow processing speed increase, make the signal to noise ratio of entire system significantly to reduce also and cause signal quality to descend, be the problem that causes the time of delay that can solve improper increase, feed forward equalizer 21 in these known technology means must correspondingly carry out design alteration and compensate, but will make that so the circuit of feed forward equalizer 21 is more complicated, but also be to solve the problem that signal quality descends fully.

Summary of the invention

The objective of the invention is to overcome the shortcoming of above-mentioned prior art and provide one to have the adaptive determining feedback equalizer that high signal to noise ratio and processing speed can meet Gigabit Ethernet network demand.

Another object of the present invention is to provide a kind of prediction parallel branch amplitude limit method, be applied in the adaptive determining feedback equalizer.

Purpose of the present invention can realize by following measure:

A kind of prediction parallel branch amplitude limiter, be applied in the adaptive determining feedback equalizer, this prediction parallel branch amplitude limiter comprises: the n power adder of M, in order to common reception one pending signal and after receiving the n power default value of corresponding M respectively, carry out obtaining after the add operation n power output signal of M respectively, and M is the level number of this pending signal and for greater than 2 integer, n is a positive integer; The n power amplitude limiter of M, signal is connected to above-mentioned each adder one to one respectively, and in order to after receiving and handle these output signals respectively, and then the n power of exporting M respectively has the signal of the n power level of M; One multiplexer, signal are connected to the n power amplitude limiter of this M, have above-mentioned each signal of the n power level of M in order to reception; Above-mentioned each signal with n power level of M comprises the multiple error signal of the n power rank level of the multidata signal of the n power level with M and the corresponding M of having at least; And n the delay cell that is connected in series mutually, signal is connected to this multiplexer, the selection signal of corresponding generation n different time of delays is transported to this multiplexer in order at least one output signal that receives this multiplexer, and which arrangement in the possible arrangement of the n power kind of the principle that this multiplexer is selected to be the selection signal of looking n difference of n delay cell output time of delays respectively be M.

In other words, the present invention is a kind of prediction parallel branch amplitude limiter, be applied in the adaptive determining feedback equalizer, this prediction parallel branch amplitude limiter comprises: the adder of the n power fixed coefficient of M, after receiving a pending signal jointly and receiving the n power default value of corresponding M respectively, carry out obtaining after the add operation n power output signal of M respectively, and M is the integer greater than 1; The n power amplitude limiter of M divides level signal to be connected to above-mentioned each adder, and it is to receive and handle above-mentioned each output signal respectively, and then exports the individual amplitude limit signal with n power rank level of M of n power of M respectively; One first multiplexer, signal are connected to the n power amplitude limiter of this M, and it is in order to receive the said amplitude-limiting signal; And n delay cell of serial connection, signal is connected to this first multiplexer, it is to receive the output signal of this first multiplexer and the selection signal of corresponding generation n difference time of delays is transported to this first multiplexer, and then one of selects in the said amplitude-limiting signal that this first multiplexer received and to be exported.

Prediction parallel branch amplitude limiter of the present invention, also comprise one second multiplexer, signal is connected to the n power amplitude limiter and the n that an is connected in series delay cell of this M, its be in order to receive above-mentioned each amplitude limiter the n power error signal of M of output respectively, and, one of select in above-mentioned each error signal that is received and to be exported according to this selection signal of failing of n delay cell of serial connection.

Purpose of the present invention also can realize by following measure:

A kind of prediction parallel branch amplitude limit method is applied in the adaptive determining feedback equalizer, and this method comprises the following step: according to the characteristic of channel, obtain the preceding n item coefficient of feedback equalizer, and then calculate the n power default value of M; After receiving n power the above-mentioned default value of a pending signal and M, carry out obtaining after the add operation n power output signal of M respectively, and M is the level number of this pending signal and is integer greater than 2, n is a positive integer; Receive respectively and above-mentioned each output signal is carried out the amplitude limit processing, and then the individual signal of the n power of exporting M respectively with n power level of M, wherein, above-mentioned each signal with n power level of M comprises most error signals of the n power rank level of most data-signals of the n power level with M and the corresponding M of having at least; The signal of n power level that has M according to the n power of M is to produce the output signal after the amplitude limit processing; And according to this output signal after the amplitude limit processing and n different delay processing, produce the selection signal of n different time of delays, and which arrangement in the possible arrangement of the n power kind of the principle that this multiplexer is selected to be the selection signal of looking n difference of n delay cell output time of delays respectively be M.

In other words, another aspect of the invention is a kind of prediction parallel branch amplitude limit method, be applied in the adaptive determining feedback equalizer, this method comprises the following step: after receiving the n power default value of a pending signal and M, carry out obtaining after the add operation n power output signal of M respectively, and M is the integer greater than 1; Receive respectively and above-mentioned each output signal is carried out the amplitude limit processing, and then the n power of exporting M respectively has the amplitude limit signal of the n power rank level of M; And in the said amplitude-limiting signal, select an output according to the selection signals of n different time of delays.

Prediction parallel branch amplitude limit method of the present invention also comprises the following step: receive respectively and above-mentioned each output signal is carried out the amplitude limit processing, and then export the n power error signal of M respectively; And in above-mentioned each error signal, select an output according to the selection signals of n different time of delays.

The present invention has following advantage compared to existing technology:

One aspect of the present invention makes feedback equalizer can carry out the pipeline operation by n delay cell of extra increase, reaches the purpose that makes that processing speed increases; Make the signal to noise ratio of entire system maintain certain level by the measurable parallel branch amplitude limiter 30 that uses particular design on the other hand and not influence signal quality too many; And the complexity of employed circuit also in control range, is only set up some amplitude limiters and multiplexer basically.

Description of drawings

Figure 1A is the functional block diagram of the transmission receiver of a network node in the Gigabit Ethernet network;

Figure 1B is for expressing the channel impulse response waveform schematic diagram of a digital data signal x (n);

Fig. 2 A is the functional block diagram of first kind of known adaptive determining feedback equalizer;

Fig. 2 B is the functional block diagram of second kind of known adaptive determining feedback equalizer;

Fig. 2 C is the exemplary plot that the waveform response that cause time of delay of improper increase changes;

Fig. 3 is an adaptive determining feedback equalizer functional block diagram of the present invention;

Fig. 4 A to Fig. 4 D is in the ordered Gigabit Ethernet network transmission standard of IEEE, is respectively channel impulse response (channel impulse response) the waveform schematic diagram that measures on multiple twin cable-Di five class transmission lines that 25,50,75 and 100 meters not tool covers at different length.

The exemplary plot that the waveform response that Fig. 5 sees for feedback equalizer in the preferred embodiment of the present invention changes.

Fig. 6 A and Fig. 6 B are the two kind built-in function block diagrams of preferred embodiment of the present invention at prediction parallel branch amplitude limiter; And

Fig. 7 is that the learning curve of known approaches and adaptive determining feedback equalizer of the present invention compares schematic diagram.

Embodiment

See also Fig. 3, be that the present invention develops the adaptive determining feedback equalizer functional block diagram that, it mainly is to replace amplitude limiter simple in the known approaches with a prediction parallel branch amplitude limiter 30, and then can make n the delay cell 36 unlikely signal to noise ratio that influence system of extra increase.The coordinate of Fig. 4 A to Fig. 4 D, Fig. 5 and Fig. 7 only is used to represent the relative size relation, so reference axis does not have absolute unit.For clearly understanding the present invention, please earlier referring to Fig. 4 A to Fig. 4 B, it is in the ordered Gigabit Ethernet network transmission standard of IEEE, at different length, be respectively 25,50, the waveform schematic diagram of measured channel impulse response on multiple twin cable-Di five class transmission lines that 75 and 100 meters not tool covers, and by observing out among the figure, though its waveform changes with the increase of length of transmission line but is very not big, so just can be according to viewed waveform, preestablishing out is not 0 n fixed value coefficient, in order to the response wave shape after 31 combinations of simulated channel and feed forward equalizer, i.e. preceding n coefficient of the waveform seen of feedback equalizer 32.Follow our the fixedly preceding n item coefficient of FBE, and use the LMS algorithm to obtain remaining equalizer coefficients.The post-cursor ISI of n item will be eliminated (carry out this partly the prediction parallel branch amplitude limiter 30 that will be introduced after a while of the hardware of function finish) by the fixed coefficient of n before the FBE before like this, and the post-cursor ISI that is left can be eliminated by the coefficient that the FBE back can be adjusted.For example, work as n=2, when the fixed value coefficient is respectively C1, C2, just the waveform that feedback equalizer 32 is seen shown in the 5th figure, a preceding n coefficient can very approaching optimized result.Can obtain one very near optimization result's equalizer coefficients against doing us like this, yet because preceding n coefficient among the FBE must be fixed as zero in the known technology 2, n item coefficient is not zero a large amount of losses that therefore can cause signal to noise ratio before optimized, because of can significantly improving the low excessively shortcoming of signal to noise ratio in the known approaches against our way.Then we must be again convert the equalizer of a preceding n fixed coefficient to parallel branch amplitude limiter 30, remove pipeline FBE.Shown in it is described in detail as follows:

See also Fig. 6 A again, it is to the present invention is directed to n=2 and signal x (n) is five level, for example-2,-1,0,1,2 pulse amplitude modulating signal (pulse amplitude modulation, PAM) develop the functional block diagram that about prediction parallel branch amplitude limiter 30 inside the time, wherein the parallel branch that mainly is made of 25 (5 2 powers) individual adders 60 and 25 amplitude limiters 61 is formed.The value V that input received of each adder 60 wherein _e ^TT, it is to be optimization coefficient Ve=[C1, C2] with the level value T=[a (n-1) of previous two rank signals, a (n-2)] product, and T just has 25 kinds of possible arrangements under the situation of five level, relatively, in the decision feedback loop, just can additionally increase by two delay cells 62,63 for utilization.And find out that by knowing among the figure b (n) of gained is respectively at 25 kinds of possible signal combination value V behind the signal plus of signal that feed forward equalizer 31 is exported and feedback equalizer 32 outputs _e ^TT carries out add operation and amplitude limitization in advance, and then draws 25 kinds of possible amplitude limit data-signal d and corresponding error signal e, with the multiplexer 64,65 that exports two 25-to-1 respectively to for you to choose.And the principle of selecting is just looked the output x (n-1) of two delay cells 62,63 respectively, and x (n-2) is which arrangement in 25 kinds of possible arrangements.Just can be routed in the feedback equalizer 32 as for these two delay cells 62,63, and then can divide into three groups of electronic circuits to the circuit of feedback equalizer 32 originally and allow processing speed increase to carry out the pipeline running.

See also Fig. 6 B again, it is to the present invention is directed to n=3 and signal x (n) is two level, for example-1, develop the functional block diagram that about prediction parallel branch amplitude limiter 30 inside during 1 pulse amplitude modulating signal, wherein the parallel branch that mainly is made of the adder 70 of the individual fixed coefficient of 8 (2 3 powers) and 8 amplitude limiters 71 is formed.The value V that input received of each adder 70 wherein _e ^TT, it is to be optimization coefficient Ve=[C1, C2, C3] with the first level value T=[a (n-1) of first three rank signal, a (n-2), a (n-3)] product, and T just has 8 kinds of possible arrangements under the situation of two level, relatively, in the decision feedback loop, just can additionally increase by three delay cells 72,73,74 for utilization.And find out that by knowing among the figure signal b (n) that feed forward equalizer 31 is exported is respectively at 8 kinds of possible signal combination value V _e ^TT carries out add operation and amplitude limitization in advance, and then draws 8 kinds of possible amplitude limit data-signal x (n) and corresponding error signal e, with the multiplexer 75,76 that exports two 8-to-1 respectively to for you to choose.And the principle of selecting is just looked the output x (n-1) of three delay cells 72,73,74 respectively, and x (n-2), x (n-3) are which arrangement in 8 kinds of possible arrangements.Just can be routed in the feedback equalizer 32 as for these three delay cells 72,73,74, and then can divide into the four group electronic circuit to the circuit of feedback equalizer 32 originally and allow processing speed increase to carry out the pipeline running.

In sum, also can additionally increase n delay cell so that feedback equalizer can carry out the pipeline operation in the technology of the present invention means, reach the purpose that makes that processing speed increases, but can make because of the particular design of prediction parallel branch amplitude limiter 30 and keep certain level by the signal to noise ratio of entire system not influence signal quality too many.As shown in Figure 7, learning curve comparison schematic diagram for known approaches and adaptive determining feedback equalizer of the present invention, the signal quality of wherein expressing first kind of the slowest known approaches of processing speed is preferable, and the signal quality of the fastest second kind of known approaches of processing speed is relatively poor, technology of the present invention as for the processing speed with known approaches in second then has the signal quality that approaches first kind of known approaches, and the complexity of circuit is also in control range, set up some amplitude limiters and multiplexer, thereby certain effective shortcoming of improving known approaches reaches main purpose of the present invention.

Claims (7)

1, a kind of prediction parallel branch amplitude limiter is applied in the adaptive determining feedback equalizer, and this prediction parallel branch amplitude limiter comprises:

The n power adder of M, in order to common reception one pending signal and after receiving the n power default value of corresponding M respectively, carry out obtaining after the add operation n power output signal of M respectively, and M is the level number of this pending signal and for greater than 2 integer, n is a positive integer;

The n power amplitude limiter of M, signal is connected to above-mentioned each adder one to one respectively, and in order to after receiving and handle these output signals respectively, and then the n power of exporting M respectively has the signal of the n power level of M;

One multiplexer, signal are connected to the n power amplitude limiter of this M, have above-mentioned each signal of the n power level of M in order to reception;

Above-mentioned each signal with n power level of M comprises the multiple error signal of the n power rank level of the multidata signal of the n power level with M and the corresponding M of having at least; And

N delay cell of mutual serial connection, signal is connected to this multiplexer, the selection signal of corresponding generation n different time of delays is transported to this multiplexer in order at least one output signal that receives this multiplexer, and which arrangement in the possible arrangement of the n power kind of the principle that this multiplexer is selected to be the selection signal of looking n difference of n delay cell output time of delays respectively be M.

2, prediction parallel branch amplitude limiter as claimed in claim 1, it is characterized in that, this multiplexer is the combination of one first multiplexer and one second multiplexer, and this first multiplexer all divides level signal a n power amplitude limiter that is connected to this M and the n that is connected in series a delay cell with this second multiplexer.

3, prediction parallel branch amplitude limiter as claimed in claim 2, it is characterized in that, this first multiplexer is to receive from the above-mentioned data-signal of the n power level with M of above-mentioned amplitude limiter and from the above-mentioned selection signal of above-mentioned delay cell, and this second multiplexer is to receive from the above-mentioned error signal of the n power level with M of above-mentioned amplitude limiter and from the above-mentioned selection signal of above-mentioned delay cell; And the output meeting of this first multiplexer is received by this second multiplexer earlier, and this second multiplexer can produce above-mentioned output signal according to this.

4, prediction parallel branch amplitude limiter as claimed in claim 1 is characterized in that, for K adder, the default value of its reception is the product of the level value of a n rank optimization coefficient and previous n rank signal, and wherein K is a positive integer.

5, prediction parallel branch amplitude limiter as claimed in claim 4, it is characterized in that, above-mentioned n rank optimization coefficient is during for the waveform of the transmission line upper signal channel impulse response of the Gigabit Ethernet network transmission standard formulated with n fixed coefficient emulation IEEE, the n of a gained fixed coefficient.

6, a kind of prediction parallel branch amplitude limit method is applied in the adaptive determining feedback equalizer, and this method comprises the following step:

According to the characteristic of channel, obtain the preceding n item coefficient of feedback equalizer, and then calculate the n power default value of M;

After receiving n power the above-mentioned default value of a pending signal and M, carry out obtaining after the add operation n power output signal of M respectively, and M is the level number of this pending signal and is integer greater than 2, n is a positive integer;

Receive respectively and above-mentioned each output signal is carried out the amplitude limit processing, and then the individual signal of the n power of exporting M respectively with n power level of M, wherein, above-mentioned each signal with n power level of M comprises most error signals of the n power rank level of most data-signals of the n power level with M and the corresponding M of having at least;

The signal of n power level that has M according to the n power of M is to produce the output signal after the amplitude limit processing; And

Handle according to this output signal after the amplitude limit processing and n different the delay, produce the selection signal of n different time of delays, and which arrangement in the possible arrangement of the n power kind of the principle that this multiplexer is selected to be the selection signal of looking n difference of n delay cell output time of delays respectively be M.

7, prediction parallel branch amplitude limit method as claimed in claim 6, it is characterized in that, any received default value is to be-n rank optimization coefficient the product with the level value of previous n rank signal, when wherein above-mentioned n rank optimization coefficient is the waveform of transmission line upper signal channel impulse response of the Gigabit Ethernet network transmission standard formulated with n fixed coefficient emulation IEEE, a resulting n fixed coefficient.

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