TWI236751B - Semiconductor package with internal heat pipe - Google Patents

Semiconductor package with internal heat pipe Download PDF

Info

Publication number
TWI236751B
TWI236751B TW093110867A TW93110867A TWI236751B TW I236751 B TWI236751 B TW I236751B TW 093110867 A TW093110867 A TW 093110867A TW 93110867 A TW93110867 A TW 93110867A TW I236751 B TWI236751 B TW I236751B
Authority
TW
Taiwan
Prior art keywords
heat
heat pipe
built
semiconductor package
item
Prior art date
Application number
TW093110867A
Other languages
Chinese (zh)
Other versions
TW200536083A (en
Inventor
Hong-Yuan Huang
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW093110867A priority Critical patent/TWI236751B/en
Application granted granted Critical
Publication of TWI236751B publication Critical patent/TWI236751B/en
Publication of TW200536083A publication Critical patent/TW200536083A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

A semiconductor package with embedded heat pipe mainly includes a substrate, a chip, a heat spreader, an embedded heat pipe and a molding compound. The chip and the heat spreader are disposed on upper surface of the substrate. The embedded heat pipe connects heat-emitting surface of the chip and heat-conducting surface of the heat spreader, and is sealed by the molding compound. Because that heat conduced from the heat spreader passes through the substrate to an external PCB, it can improve the protection of the embedded heat pipe and increase the heat dissipation of the semiconductor package without exposing the embedded heat pipe.

Description

1236751 五、發明說明（1) 【發明所屬之技術領域】 本發明係有關於一種散勒 右關认你βπ里為一樘政熱型半導體封裝構造，特別係 有關於一種内置熱管之半導體封 【先前技術】 《Μ k 隨著半導體晶圓的技術袒M ^ 政把γ J孜術七昇，晶圓之晶片内部線寬已 降低而進入奈米階級，故曰y ^ ^ ^ ^ 故日日片的尺寸能更加縮小，導致單 很1座王 < …里曰逐漸提高，故封裝晶片之半導體封 裝構造將面對更高難度的勒·勒 H ¥ Μ # Hi +又的政熱問題，當一晶片發出的熱量 會衫響封裝構造時，雁.u ^ UCM 九建立適當之導熱機構，例如習知之 HSBGA、CSBGA，其係利用 jji p 片或熱管（heat Plpe)等外加散熱機構裝設於一半導體封丨 裝構造之封膠體上表面或装Ημ々、田+支 ^ * 取W；5C具晶片之裸露表面，或者在基板 增加導熱通孔（thermal vi 、士 旦 Vla)或導熱銅層，以消散晶片熱 里，其中以熱S具有較佳導熱性與寧靜度。 ，，專利公告第501 792號「高散熱封裝元件 -種半導體封裝構造，λ主要包含有—導線架之承載器、 二一封膠體5 —熱管（heat PiPe)，該晶片係置於 μ承載益上，该封膠體係包覆部份該承載器與該晶片，該 熱管之一端係嵌入該封膠内部而鄰近該晶片，該埶管之另 一端則延伸出該封膠體外部，故該熱管係一端為外露且直丨 立設置，不但該熱管缺乏保護，在製作過程與產品使用時 容易碰觸損傷，並且熱管之熱傳導路徑過短不易發導敎 性能。 ” 【發明内容】1236751 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a type of semiconductor package structure that recognizes β π as a thermally conductive semiconductor package, and particularly relates to a semiconductor package with a built-in heat pipe. [Previous technology] "Mk With the technology of semiconductor wafers 袒 M ^ political γ J 术 seven liters, the wafer's internal line width has been reduced and entered the nano class, so y ^ ^ ^ ^ The size of the film can be further reduced, resulting in a single king <… li gradually increasing, so the semiconductor package structure of the package wafer will face a more difficult Le Le H ¥ Μ # Hi + and political and thermal issues, When the heat emitted by a chip will affect the package structure, u ^ UCM will establish an appropriate heat conduction mechanism, such as the conventional HSBGA and CSBGA, which are installed using external heat dissipation mechanisms such as jji p chips or heat pipes (heat Plpe). On the upper surface of a sealing package of a semiconductor package structure or mounting μ々, field + support ^ * Take W; 5C with bare surface of the wafer, or add thermal vias (thermal VI, Stan Vla) or copper on the substrate Layer to dissipate heat from the wafer Wherein S having better heat and thermal conductivity of the quiet. , Patent Bulletin No. 501 792 "High heat dissipation package element-a kind of semiconductor package structure, λ mainly contains-the carrier of the lead frame, two pieces of colloid 5-heat pipe (heat PiPe), the chip is placed in the μ bearing benefit Above, the sealant system covers a part of the carrier and the wafer. One end of the heat pipe is embedded inside the sealant and is adjacent to the wafer. The other end of the heat pipe extends outside the sealant. One end is exposed and set upright. Not only does the heat pipe lack protection, it is easy to touch and damage during the manufacturing process and product use, and the heat conduction path of the heat pipe is too short to easily lead to performance. "[Contents of the Invention]

第6頁 1236751 ----- 五、發明說明（2) 本發明之主要目的係在於提供一 封裝構造，在一基板之上表面設有一 —内置熱管（internal heat pipe)係 面與該散熱機構之導熱面，且被一封 該内置熱管、散熱機構、基板將晶片 部印刷電路板，可在不需要外加於封 之條件下增進該内置熱管之保護，且 本發明之次一目的係在於提供一 封襄構造，當該晶片與該散熱機構設 該晶片之發熱面與該散熱機構之導熱 面’以利水平跨接該内置熱管在該晶 依本發明之内置熱管之半導體封 一基板、一晶片、一散熱機構、一内 遠基板係具有一上表面及一下表面， 含有一晶片接合區及一導熱區，該晶 片接合區’該晶片係具有一發熱面， 基板之導熱區，該散熱機構係具有一 係填充有熱交換溶液，該内置熱管係 凝端’將該内置熱管跨接於該晶片之 之導熱面’使得該蒸發端係熱輕合於 熱搞合於該散熱機構，該封膠體係形 面’以密封該内置熱管與該晶片。 【實施方式】 參閱所附圖式，本發明將列舉以 $ 7頁 種内置熱管之半導趙 晶片與一散熱機構， 跨接在該晶片之發 膠體所密封，藉鎚由、 產生之熱量傳導至 膠體外部之散熱元 製作容易。 種内置熱管之半導體 於該基板之上表面， 面係可為等高共平 片與該散熱機構。< 裝構造，主要包含有 置熱管及一封膠體， 該基板之上表面係包 片係設於該基板之晶 該散熱機構係設於該 導熱面，該内置熱管 具有一蒸發端與一冷 發熱面與該散熱機構 該晶片，該冷凝端係1 成於該基板之上表 下之實施例說明 1236751 五、發明說明（3) 依據本發明之第一具體實施例，請參閱第1圖，一種 内置熱管之半導體封裝構造100係主要包含有一基板11〇、 一晶片120、一散熱機構130、一内置熱管140及一封膠體 150，該基板11〇係具有傳遞電路，例如BT、FR4、FR5構成 之印刷電路板或是多層陶瓷電路板，該基板11 〇係具有一 上表面111及一下表面112，該基板110之上表面ill係包含 有一晶片接合區1 1 3及一導熱區1 14。 請再參閱第1圖，該晶片1 2 0係設於該基板1 1 〇之晶片 接合區11 3 ’該晶片1 2 0係可為各式高度發熱之晶片，如微 處理器晶片或繪圖處理晶片，在本實施例中，該晶片i 2 〇 係為打線連接之晶片，其係具有一朝上之主動表面1 21以 及一貼於該晶片接合區1 1 3之背面1 2 2，以複數個銲線1 2 3 電性連接至該基板11 〇，該晶片1 2 〇係以該主動表面1 21作 為該晶片120之發熱面。該散熱機構丨3〇係由如銅、鋁或其 合金等高導熱性金屬所製成，其係設於該基板丨丨〇之導熱 區1 1 4，该散熱機構1 3 0係具有一導熱面1 31，在本實施例 中，該散熱機構130更形成有一凸接部132，而該基板no 於該導熱區114係設有一對應之容置開口丨丨5，且在本實施 例中’該容置開口 11 5係貫穿該基板丨丨〇該上表面丨丨1及該 下表·面112，利用一環氧膠133或其它黏著劑固定該散熱機馨 構130與該基板11〇之後，該散熱機構13〇之該凸接部132係 嵌入於該容置開口 11 5中，並且以稍凸出於該基板丨丨〇之下 表面11 2為較佳。Page 61236751 ----- 5. Description of the invention (2) The main purpose of the present invention is to provide a package structure, which is provided on the upper surface of a substrate with an internal heat pipe system surface and the heat dissipation mechanism. The heat conduction surface and the printed circuit board of the wafer portion are enclosed by a built-in heat pipe, a heat-dissipating mechanism, and a substrate, which can improve the protection of the built-in heat pipe without external sealing, and a second object of the present invention is to provide A Xiang structure, when the chip and the heat-dissipating mechanism are provided with the heating surface of the wafer and the heat-conducting surface of the heat-dissipating mechanism, so as to horizontally bridge the built-in heat pipe, seal a substrate on the semiconductor of the built-in heat pipe according to the present invention, The chip, a heat dissipation mechanism, and an inner and far substrate have an upper surface and a lower surface, which include a wafer bonding area and a heat conduction area. The wafer bonding area 'the wafer has a heating surface, a heat conduction area of the substrate, and the heat dissipation mechanism. The system has a system filled with a heat-exchange solution. The built-in heat pipe condenses the end of the built-in heat pipe to the heat-conducting surface of the chip, so that the evaporation end is lightly closed. The heat-sealing mechanism is engaged with the heat-dissipating mechanism, and the sealant system is formed to seal the built-in heat pipe and the chip. [Embodiment] Referring to the attached drawings, the present invention will list a $ 7 page semiconductor chip with a built-in heat pipe and a heat-dissipating mechanism, sealed by hair gel connected to the chip, and conducted by the heat generated by the hammer. The heat sink to the outside of the colloid is easy to make. A semiconductor with a built-in heat pipe is on the upper surface of the substrate, and the surface can be a concentric flat plate and the heat dissipation mechanism. < The mounting structure mainly includes a heat pipe and a colloid, the upper surface of the substrate is a package sheet arranged on the substrate, the heat dissipation mechanism is provided on the heat conduction surface, and the built-in heat pipe has an evaporation end and a cooling tube. Heating surface and the chip of the heat-dissipating mechanism, the condensing end 1 is formed on the substrate above and below the table. 1236751 V. Description of the invention (3) According to the first embodiment of the present invention, please refer to FIG. 1, A semiconductor package structure 100 with a built-in heat pipe mainly includes a substrate 110, a wafer 120, a heat dissipation mechanism 130, a built-in heat pipe 140, and a colloid 150. The substrate 110 has a transmission circuit, such as BT, FR4, and FR5. A printed circuit board or a multilayer ceramic circuit board is formed. The substrate 110 has an upper surface 111 and a lower surface 112, and the upper surface ill of the substrate 110 includes a wafer bonding region 1 1 3 and a thermally conductive region 1 14. Please refer to FIG. 1 again. The wafer 1 2 0 is located in a wafer bonding area 11 3 of the substrate 1 1 0. The wafer 1 2 0 can be a variety of highly heat-emitting wafers, such as a microprocessor wafer or a drawing process. Wafer, in this embodiment, the wafer i 2 0 is a wire-connected wafer, which has an upward active surface 1 21 and a back surface 1 2 2 attached to the wafer bonding area 1 1 3, in plural. A plurality of bonding wires 1 2 3 are electrically connected to the substrate 11 o, and the wafer 12 2 uses the active surface 1 21 as a heating surface of the wafer 120. The heat dissipation mechanism 30 is made of a highly thermally conductive metal such as copper, aluminum, or an alloy thereof. The heat dissipation mechanism 1 30 is provided in the heat conduction region 1 4 of the substrate. The heat dissipation mechanism 130 has a thermal conductivity. Surface 1 31. In this embodiment, the heat dissipating mechanism 130 is further formed with a convex contact portion 132, and the substrate is provided with a corresponding accommodation opening in the heat conduction area 114. In this embodiment, ' The accommodating opening 11 5 penetrates the substrate 丨 丨 the upper surface 丨 丨 1 and the following table · surface 112, and then fixes the heat sink 130 and the substrate 110 with an epoxy glue 133 or other adhesive. Preferably, the convex contact portion 132 of the heat dissipation mechanism 130 is embedded in the receiving opening 115, and is preferably slightly protruded from the lower surface 112 of the substrate.

1236751 五、發明說明（4) 說代甲烧、氨、丙酮、甲醇等大汽化潛能之物質，該内置 熱管1 4 0係具有一蒸發端1 4 1與一冷凝端1 4 2，該内置熱管 1 40係跨接於該晶片1 20之發熱面（即主動表面1 2 1 )與該散 熱機構130之導熱面131，並以導熱膠（圖未繪出）連接固 ❼又’以使得該蒸發端1 41係熱耦合於該晶片1 2 〇，及該冷凝 端142係熱耦合於該散熱機構13〇，以避免該内置熱管14〇 不會過度散發熱量給該基板11 0，較佳地，該晶片1 2 〇之發 熱面（即主動表面121)與該散熱機構130之導熱面131係為 等南共平面，以利該内置熱管丨4 〇於不需另行變更外形設 計下·即可水平跨接。此外，利用壓模或液態填塗方式該% 膠體150形成於該基板110之上表面111，以密封該内置熱零 管1 4 0與該晶片1 2 〇，在本實施例中，複數個銲球丨6 〇係設 於該基板110之下表面112。 當該内置熱管之半導體封裝構造1〇〇表面接合在一外 部印刷電路板3〇〇時，該基板11()之該些銲球16〇係接合在 $亥外部印刷電路板3 〇 〇之連接墊（圖未繪出），該散熱機構 1 3 0之凸接部1 3 2係以鲜膏1 7 0接合於該外部印刷電路板 3〇〇 ’^因此，該晶片1 2〇運算時所產生之熱量係可沿著該内 置熱管140傳導至該散熱機構13〇，且該散熱機構13Q係以 該凸接部132通過該基板11〇再傳導至該大面積之外部印部 電路板300，以利用該外部印刷電路板3〇〇作為大尺寸之散 熱板’以達到較佳之熱傳導散熱效果，其係提供一種新的 導…二路彳二’孩内置熱管1 4 〇係連同該晶片1 2 〇能被該封膠體 1 5 0岔封，不需要外露該内置熱管丨4 〇，故製作容易且該内1236751 V. Description of the invention (4) For substances with large vaporization potential such as formazan, ammonia, acetone, and methanol, the built-in heat pipe 1 40 has an evaporation end 1 4 1 and a condensing end 1 4 2. The built-in heat pipe 1 40 is connected across the heating surface of the chip 1 20 (ie, the active surface 1 2 1) and the heat conduction surface 131 of the heat dissipation mechanism 130, and is connected with a heat conductive glue (not shown in the figure) to make the evaporation. The terminal 1 41 is thermally coupled to the chip 120, and the condensing terminal 142 is thermally coupled to the heat sink 13 to prevent the built-in heat pipe 140 from excessively dissipating heat to the substrate 110. Preferably, The heating surface of the chip 12 (ie, the active surface 121) and the heat conduction surface 131 of the heat dissipation mechanism 130 are coplanar, in order to facilitate the built-in heat pipe 丨 4 〇 can be horizontal without changing the external design join. In addition, the% gel 150 is formed on the upper surface 111 of the substrate 110 by a stamper or a liquid filling method to seal the built-in thermal zero tube 140 and the wafer 120. In this embodiment, a plurality of solders are welded. The ball 丨 6 〇 is disposed on the lower surface 112 of the substrate 110. When the surface of the semiconductor package structure 100 with the built-in heat pipe is bonded to an external printed circuit board 300, the solder balls 160 of the substrate 11 () are bonded to the external printed circuit board 300. Pad (not shown in the figure), the convex contact portion 13 of the heat dissipation mechanism 130 is bonded to the external printed circuit board 300 with fresh paste 170, so the chip 120 is used in the calculation. The generated heat can be conducted to the heat dissipation mechanism 13o along the built-in heat pipe 140, and the heat dissipation mechanism 13Q is further conducted to the large-area external printed circuit board 300 through the substrate 110 through the convex portion 132, The external printed circuit board 300 is used as a large-sized heat-dissipating plate to achieve better heat conduction and heat-dissipating effect, which provides a new type of conduction ... two-way two-two built-in heat pipe 1 4 0 series together with the chip 1 2 〇can be sealed by the sealing colloid 150, without the need to expose the built-in heat pipe 丨 4 〇, so the production is easy and the internal

第9頁 1236751 五、發明說明（5) 置熱管140係被該封膠體15〇保護，以使該内置熱管14〇之 毛細導熱結構不會被碰傷而損弱其導熱特性。 ' 依據本發明之第二具體實施例，請參閱第2圖，一種 内置熱管之半導體封裝構造2 〇〇係主要包含有一基板21 〇、 一晶片220、一散熱機構230、一内置熱管240及一封膠體 250 ’如同第一具體實施例這般，該晶片22〇與該散熱機構 230係分別設於該基板21 〇上表面211之晶片接合區2 13與導 熱區21 4，且該内置熱管240係跨接於該晶片220之發熱面 與該散熱機構230之導熱面231，在本實施例中，該晶片 220係為覆晶接合之晶片，在該晶片22〇之主動表面221係 設有複數個凸塊2 2 3，以電性接合該基板21 〇，該晶片2 2 0 之貪面2 2 2則朝上，以作為该晶片2 2 0之發熱面，而該散熱 機構230係以一導熱膠232貼設於該基板21 〇之導熱區21 4， 谷亥導熱區214係設有複數個導熱通孔215(thermal via)， 該些導熱通孔215係貫通該基板210之上表面211與下表面 21 2 ’該些導熱通孔2 1 5内係填充有一導熱材料，其係可選 自於銅、金、及其合金之其中一金屬所構成者，以錶導熱 膠2 3 2黏貼該散熱機構2 3 0與該基板2 1 〇且熱輕合該散熱機 構230至該些導熱通孔215，該封膠體250係形成於該基板 210之上表面211，以密封該内置熱管240與該晶片220，並_ 且複數個銲球260係設於該基板2 10之下表面212 ,該晶片 220運算時所產生之熱量係經由該内置熱管24〇、該散熱機 構2 30與該基板210之該些導熱通孔2 15與該些銲球2 60傳導 至該外部印刷電路板300，故該封膠體250密封該内置為管Page 9 1236751 V. Description of the invention (5) The heat pipe 140 is protected by the sealing gel 15 so that the capillary heat conduction structure of the built-in heat pipe 14 will not be damaged and the heat conduction characteristics will be impaired. '' According to a second specific embodiment of the present invention, please refer to FIG. 2. A semiconductor package structure 2000 with a built-in heat pipe mainly includes a substrate 21, a wafer 220, a heat dissipation mechanism 230, a built-in heat pipe 240, and a The sealing compound 250 ′ is the same as the first embodiment. The wafer 22 and the heat dissipation mechanism 230 are respectively provided on the wafer bonding region 2 13 and the heat conduction region 21 4 on the upper surface 211 of the substrate 21, and the built-in heat pipe 240 It is connected across the heating surface 231 of the wafer 220 and the heat conduction surface 231 of the heat dissipation mechanism 230. In this embodiment, the wafer 220 is a flip-chip bonded wafer, and the active surface 221 of the wafer 22 is provided with a plurality The bumps 2 2 3 are electrically bonded to the substrate 21 0, and the greedy surface 2 2 2 of the wafer 2 2 is facing upwards as the heating surface of the wafer 2 2 0, and the heat dissipation mechanism 230 is The thermally conductive adhesive 232 is attached to the thermally conductive area 21 4 of the substrate 21 〇, and the Guhai thermally conductive area 214 is provided with a plurality of thermal vias 215 (thermal vias) that penetrate the upper surface 211 of the substrate 210 And the lower surface 21 2 ′, the heat-conducting through holes 2 1 5 are filled with Thermal material, which can be selected from one of copper, gold, and its alloys, and is composed of a thermally conductive adhesive 2 3 2 and the heat dissipation mechanism 2 3 0 and the substrate 2 1 0. The heat is lightly combined with the heat dissipation. The mechanism 230 to the thermal vias 215, the sealing compound 250 is formed on the upper surface 211 of the substrate 210 to seal the built-in heat pipe 240 and the wafer 220, and a plurality of solder balls 260 are provided on the substrate 2 10 the lower surface 212, the heat generated during the calculation of the chip 220 is conducted to the heat conduction vias 2 15 and the solder balls 2 60 through the built-in heat pipe 24, the heat dissipation mechanism 2 30 and the substrate 210 External printed circuit board 300, so the sealing compound 250 seals the built-in tube

第10頁 1236751 五、發明說明（6) 240不會影響導熱效果且對該内置熱管240保護良好。 本發明之保護範圍當視後附之申請專利範圍所界定者 為準，任何熟知此項技藝者，在不脫離本發明之精神和範 圍内所作之任何變化與修改，均屬於本發明之保護範圍。Page 10 1236751 V. Description of the invention (6) 240 does not affect the heat conduction effect and protects the built-in heat pipe 240 well. The protection scope of the present invention shall be determined by the scope of the appended patent application. Any changes and modifications made by those skilled in the art without departing from the spirit and scope of the present invention shall fall within the protection scope of the present invention. .

第11頁 1236751 圖式簡單說明1236751 Illustration

【圖式簡單說明】 第1圖：依據本發明之一具體實施例， 列封裝構造之截面示意圖；及 第2圖：依據本發明之第二具體實施例 陣列封裝構造之截面示意圖。 一種散熱型球格陣 ，一種散熱型球格 元件符號簡單說明： 1 0 0封裝構造 110基板 113晶片接合區 1 2 0晶片 123銲線 13 0散熱機構 133環氧膠 140内置熱管 150封膠體 200封裝構造 111上表面 114導熱區 1 21主動表面 131導熱面 141蒸發端 1 6 0 銲球 210基板 21 3晶片接合區 220晶片 223凸塊 230散熱機構 240内置熱管 250 封膠體 211 上表面 214導熱區 221主動表面 231導熱面 241蒸發端 2 6 0 焊球 112下表面 11 5容置開口 1 2 2背面 132 凸接部 1 4 2冷凝端 1 7 0辉膏 2 1 2下表面 21 5導熱通孔222背面 · 232導熱膠 2 4 2冷凝端[Brief description of the drawings] FIG. 1: a schematic cross-sectional view of a package structure according to a specific embodiment of the present invention; and FIG. 2: a schematic cross-sectional view of an array package structure according to a second specific embodiment of the present invention. A type of heat-dissipating ball grid array, a simple explanation of the symbol of a type of heat-dissipating ball grid: 1 0 0 package structure 110 substrate 113 chip bonding area 1 2 0 chip 123 bonding wire 13 0 heat dissipation mechanism 133 epoxy glue 140 built-in heat pipe 150 sealing gel 200 Package structure 111 upper surface 114 heat conduction area 1 21 active surface 131 heat conduction surface 141 evaporation end 1 6 0 solder ball 210 substrate 21 3 wafer bonding area 220 wafer 223 bump 230 heat dissipation mechanism 240 built-in heat pipe 250 sealant 211 upper surface 214 heat conduction area 221 active surface 231 thermal conductive surface 241 evaporation end 2 6 0 solder ball 112 lower surface 11 5 receiving opening 1 2 2 back surface 132 convex joint 1 4 2 condensation end 1 7 0 bright paste 2 1 2 lower surface 21 5 thermal conduction hole 222 backside 232 thermal conductive adhesive 2 4 2 condensation end

第12頁 1236751 圖式簡單說明‘ 3 Ο 0 外部印刷電路板 _Page 12 1236751 Schematic description of ‘3 〇 0 External printed circuit board _

Claims (1)

12367511236751 【申請專利範圍】 1、:種内置熱管之半導體封裝構造，包含： 吞亥基板之上 吞亥晶片係具 基板，其係具有一上表面及一下表面， 糸^含有一晶片接合區及一導熱區； 右找日日片’其係設於該基板之晶片接合區， 有一發熱面； 係具有一導熱面 熱管，其係具有-蒸發端與-冷凝端，該内置 跨接於玆且Η 4 w ^ a ......... 月欠熱機構，其係設於該基 熱管孫味社 /、丨々、丹，一瘵货知興一冷凝端，該 ^ y :接於該晶片之發熱面與該散熱機構之導埶面， ::二發：係熱輕合於該晶片，該冷凝端係熱_合於該> 其係形成於該基板 置熱管與該晶片 申明專利範圍第1項所述之内置熱管之半導艘封 s構i:i該基板之導熱區係設有一容置開d，而該散 ；;該基㈡2應之凸接部’其係經由該容置開口顯露 3二如申請專利範圍第丨項所述之内置熱管之半導體封裝 構造，其中在該基板之導熱區係設有複數個導熱通孔。'"籲 4 .、如申請專利範圍第3項所述之内置熱管之半導體封裝 構泣，其中該些導熱通孔係貫通該基板之上下表面。 5、如申請專利範圍第3項所述之内置熱管之半導體封裝 構造，其中該些導熱通孔内係填充有一導熱材料。 、[Scope of patent application] 1 .: A semiconductor package structure with a built-in heat pipe, including: a semiconductor substrate on a semiconductor substrate, which has an upper surface and a lower surface, and contains a wafer bonding area and a thermal conduction Right; find the sun and the sun's film, which is located in the wafer bonding area of the substrate, has a heating surface; has a heat conduction surface heat pipe, which has an -evaporating end and -condensing end, and the built-in bridge is connected to here and Η 4 w ^ a ......... monthly underheating mechanism, which is located at the base heat pipe Sun Weishe /, 丨 々, Dan, a condensed end of the goods knowing, the ^ y: connected to the chip The heating surface and the guide surface of the heat-dissipating mechanism, :: Second: The heat is lightly coupled to the chip, and the condensing end is thermally coupled to the > It is formed on the substrate with a heat pipe and the wafer. The semi-conducting vessel seal structure i of the built-in heat pipe described in item 1: i. The heat conducting area of the substrate is provided with a receiving opening d, and the fan; the convex part of the base 2 should be passed through the receiving The opening reveals 32. The semiconductor package structure with a built-in heat pipe as described in item 丨 of the patent application scope, wherein Based heat transfer area of the substrate is provided with a plurality of thermal vias. '" 4. The semiconductor package structure with a built-in heat pipe as described in item 3 of the scope of patent application, wherein the thermally conductive vias penetrate the upper and lower surfaces of the substrate. 5. The semiconductor package structure with a built-in heat pipe as described in item 3 of the scope of patent application, wherein the thermally conductive vias are filled with a thermally conductive material. , 第14頁 1236751 · 請ΐ利範圍 — ---^^ 6、 如申凊專利範圍第5項所述之内置熱管之半導體封 媾造，其中該導熱材料係由選自於銅、金、及其合金之复 中/金屬所構成者。 /、 7、 如申凊專利範圍第3項所述之内置熱管之半導體封裝 媾造，其中該散熱機構係以一導熱膠熱辆合至該些導熱通 扎。 …、 g 1如申請專利範圍第丨項所述之内置熱管之半導體封装 構造，其中該晶片之發熱面與該散熱機構之導熱面係為 高與Γ平面。 9、如申請專利範圍第1項所述之内置熱管之半導體封裴 構造，其另包含有複數個銲球，其係設於該基板之下表鲁 面。 1 0、如申請專利範圍第1項所述之内置熱管之半導體封裝 構造，其中該晶片係為打線連接之晶片。 11、如申請專利範圍第1或丨〇項所述之内置熱管之半導體 封裝才拜造，其中該發熱面係為該晶片之主動表面。 1 2、如申請專利範圍第1項所述之内置熱管之半導體封裝 構造，其中該晶片係為覆晶接合之晶片。 1 3、如申請專利範圍第1或丨2項所述之内置熱管之半導體 封裝構造，其中該發熱面係為該晶片之背面。 _Page 14123675 · Please make a profit range --- ^^ 6. The semiconductor package with a built-in heat pipe as described in item 5 of the patent scope, wherein the thermally conductive material is selected from copper, gold, and Compound alloys / metals. /, 7. The semiconductor package with a built-in heat pipe as described in item 3 of the patent application, wherein the heat dissipation mechanism is thermally connected to the heat conduction via a thermally conductive glue. …, G 1 The semiconductor package structure with a built-in heat pipe as described in item 丨 of the patent application scope, wherein the heating surface of the chip and the heat conduction surface of the heat dissipation mechanism are high and Γ planes. 9. The semiconductor sealing structure with a built-in heat pipe as described in item 1 of the scope of the patent application, which further includes a plurality of solder balls, which are arranged on the surface of the base plate. 10. The semiconductor package structure with a built-in heat pipe as described in item 1 of the scope of patent application, wherein the chip is a wire-connected chip. 11. The semiconductor package with a built-in heat pipe as described in item 1 or item 0 of the patent application scope is manufactured, wherein the heating surface is the active surface of the chip. 1 2. The semiconductor package structure with a built-in heat pipe as described in item 1 of the scope of patent application, wherein the wafer is a flip-chip bonded wafer. 1 3. The semiconductor package structure with a built-in heat pipe as described in item 1 or 2 of the patent application scope, wherein the heating surface is the back surface of the chip. _ 第15頁Page 15
TW093110867A 2004-04-19 2004-04-19 Semiconductor package with internal heat pipe TWI236751B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW093110867A TWI236751B (en) 2004-04-19 2004-04-19 Semiconductor package with internal heat pipe

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW093110867A TWI236751B (en) 2004-04-19 2004-04-19 Semiconductor package with internal heat pipe

Publications (2)

Publication Number Publication Date
TWI236751B true TWI236751B (en) 2005-07-21
TW200536083A TW200536083A (en) 2005-11-01

Family

ID=36675033

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093110867A TWI236751B (en) 2004-04-19 2004-04-19 Semiconductor package with internal heat pipe

Country Status (1)

Country Link
TW (1) TWI236751B (en)

Also Published As

Publication number Publication date
TW200536083A (en) 2005-11-01

Similar Documents

Publication Publication Date Title
TWI291752B (en) Semiconductor package with heat dissipating device and fabrication method thereof
TWI285420B (en) Heat stud for stacked chip packsge
TWI290757B (en) Thermal enhance MCM package and the manufacturing method thereof
TWI309549B (en) Printed circuit board with improved thermal dissipating structure and electronic device with the same
US20110024892A1 (en) Thermally enhanced heat spreader for flip chip packaging
JP2000150735A (en) Circuit assembled body and method for connecting radiator to integrated circuit device
TWI301047B (en) Light-emitting heat-dissipating device and manufacturing method thereof
TW571374B (en) System in package structures
JP2008060172A (en) Semiconductor device
JP2007109794A (en) Semiconductor device and method of manufacturing the same
US20090135567A1 (en) Metal thermal interface material and thermal module and packaged microelectronic component containing the material
TWM255996U (en) Heat spreader with heat pipe for semiconductor package
TW200411871A (en) Thermal-enhance package and manufacturing method thereof
TW546796B (en) Multichip package
JP2004006603A (en) Semiconductor power device
CN100447989C (en) Integrated circuit packaging and manufacturing method
TW200805587A (en) Semiconductor package, method of production of same, printed circuit board, and electronic apparatus
TW578282B (en) Thermal- enhance MCM package
CN203192859U (en) Heat-dissipating lead frame structure
US20100140791A1 (en) Integrated circuit packaging structure and method of making the same
TWI236751B (en) Semiconductor package with internal heat pipe
TWI282159B (en) Thermally enhanced thin flip-chip package
TWI248667B (en) Semiconductor package having heat pipes
TW200421571A (en) Semiconductor device
WO2018095233A1 (en) Semiconductor structure and forming method therefor, and packaging structure and forming method therefor

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees