TWI235461B

TWI235461B - Manufacturing method of flash memory

Info

Publication number: TWI235461B
Application number: TW92119490A
Authority: TW
Inventors: Kuang-Chao Chen; Jui-Lin Lu; Ling-Wuu Yang
Original assignee: Macronix Int Co Ltd
Priority date: 2003-07-17
Filing date: 2003-07-17
Publication date: 2005-07-01
Also published as: TW200504943A

Abstract

The present invention is related to a manufacturing method of flash memory which includes forming a patterned tunneling dielectric layer, conductor layer and mask layer on a substrate to form a gate structure; forming a buried drain in the substrate; filling a insulating layer circumferentially around the gate structure and the surface level of the insulating layer lower than the surface level of the patterned conductor layer; forming a material layer on the insulating layer; removing the patterned mask layer; forming another pattered conductor layer on the patterned conductor layer of the gate structure and protruding over the surface of insulating layer; removing the material layer; forming a intergate dielectric layer on the substrate; forming a control gate on the intergate dielectric layer.

Description

1235461_ 五、發明說明（1) 發明所屬之技術領域本發明是有關於一種快閃記憶體的製造方法，特別是有關於一種增加浮置閘極與控制閘極間的重疊面積之快閃記憶體的製造方法。先前技術快閃記憶體元件由於其優越的資料保存特性，所以已成為個人電腦和電子設備所廣泛採用的一種記憶體元件。典型的快閃記憶體元件，一般是被設計成具有堆疊式閘極（Stack-Gate)結構，其中包括一穿隧氧化層，一用來儲存電荷的多晶石夕浮置閘極（F 1 〇 a t i n g G a t e )，一氧化石夕/ 氮化矽/氧化矽（Oxide-Ni tride-Oxide·，ΟΝΟ)結構的介電層，以及一用來控制資料存取的多晶矽控制閘極（C ο n t r ο 1 4 Gate) o 在快閃記憶體的操作上，通常浮置閘極與控制閘極之間的閘極耦合率（Gate-Coupling Ratio ，GCR)愈大，其操作所需之工作電壓將愈低，而快閃記憶體的操作速度與效率就會大大的提升。其中增加閘極耦合率的方法，包括了增加浮置閘極與控制閘極間的接觸面積、降低浮置閘極與控制閘極間之介電層的厚度、以及增加浮置閘極與控制閘極間之介電層的介電常數（Dielectric Constant ;k)等。增加浮置閘極與控制閘極間的重疊面積，有助於增加閘極耦合率，但是在積體電路持續追求高積集度之趨勢下，快閃記憶體元件每一個記憶胞所佔的面積卻因而必須縮減。因此如何在有限的晶片面積下，製作具有高耦合率1235461_ 5. Description of the invention (1) The technical field to which the invention belongs The present invention relates to a method for manufacturing a flash memory, and more particularly to a flash memory that increases the overlapping area between a floating gate and a control gate Manufacturing method. Prior art Flash memory devices have become a widely used memory device in personal computers and electronic devices due to their superior data retention characteristics. A typical flash memory device is generally designed to have a Stack-Gate structure, which includes a tunnel oxide layer, a polycrystalline silicon floating gate (F 1 〇ating Gate), a dielectric layer with a structure of Oxide-Ni tride-Oxide ·, and a polycrystalline silicon control gate (C ο for controlling data access) ntr ο 1 4 Gate) o In flash memory operation, the larger the gate-coupling ratio (GCR) between the floating gate and the control gate, the larger the operating voltage required for its operation. It will be lower, and the operation speed and efficiency of flash memory will be greatly improved. The methods for increasing the gate coupling ratio include increasing the contact area between the floating gate and the control gate, reducing the thickness of the dielectric layer between the floating gate and the control gate, and increasing the floating gate and control. The dielectric constant (Dielectric Constant; k) of the dielectric layer between the gates. Increasing the area of overlap between the floating gate and the control gate will help increase the gate coupling rate. However, under the trend of integrated circuits continuously pursuing a high degree of integration, each memory cell occupied by flash memory elements The area must therefore be reduced. So how to make a high coupling rate in a limited chip area

9677 twf.p td 第7頁 1235461_ 五、發明說明（2) 的快閃記憶體是目前極為重要的課題。發明内容因此，本發明之目的是提供一種快閃記憶體的製造方法，可以增加浮置閘與控制閘之間的重疊面積，進而提高元件的耦合率。根據上述與其它目的，本發明提出一種快閃記憶體的製造方法，此方法係於基底上依序形成穿隧介電層、導體層與罩幕層。接著將穿隧介電層、罩幕層與導體層圖案化，以於基底上形成縱向排列的條狀物，然後，於條狀物之間的基底中形成埋入式汲極區。接著再將條狀物圖案化，以於基底上形成閘極結構，此閘極結構包括圖案化穿隧介電層、圖案化導體層與圖案化罩幕層。然後在閘極結4 構的周圍形成絕緣層，此絕緣層之表面低於圖案化導體層之頂表面，而暴露出閘極結構周圍側壁之部份表面。其後，於閘極結構之間的絕緣層上形成一材料層。接著移除圖案化罩幕層以暴露出閘極結構之圖案化導體層的頂表面。之後於閘極結構之圖案化導體層的頂表面上形成另一圖案化導體層，此圖案化導體層係覆蓋於閘極結構之圖案化導體層的頂表面，並且延伸覆蓋至其周緣的材料層上。換言之，此圖案化導體層的上表面積大於閘極結構之圖案化導體層的上表面積，並與閘極結構之圖案化導體層構成9677 twf.p td Page 7 1235461_ V. Description of the invention (2) The flash memory is currently an extremely important subject. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a flash memory, which can increase the overlap area between the floating gate and the control gate, thereby improving the coupling rate of the components. According to the foregoing and other objectives, the present invention provides a method for manufacturing a flash memory. This method sequentially forms a tunneling dielectric layer, a conductor layer, and a mask layer on a substrate. Then, the tunneling dielectric layer, the mask layer and the conductor layer are patterned to form longitudinally arranged strips on the substrate, and then a buried drain region is formed in the substrate between the strips. The strips are then patterned to form a gate structure on the substrate. The gate structure includes a patterned tunneling dielectric layer, a patterned conductor layer, and a patterned mask layer. An insulation layer is then formed around the gate junction structure. The surface of the insulation layer is lower than the top surface of the patterned conductor layer, and a part of the surface around the gate structure is exposed. Thereafter, a material layer is formed on the insulating layer between the gate structures. The patterned mask layer is then removed to expose the top surface of the patterned conductor layer of the gate structure. Then, another patterned conductor layer is formed on the top surface of the patterned conductor layer of the gate structure. This patterned conductor layer is a material covering the top surface of the patterned conductor layer of the gate structure and extends to the periphery of the material. On the floor. In other words, the upper surface area of the patterned conductor layer is larger than the upper surface area of the patterned conductor layer of the gate structure, and is formed with the patterned conductor layer of the gate structure.

9677 twf.ptd 第8頁 1235461___ 五、發明說明（3) 本發明係降低閘極結構周圍之絕緣層高度，使閘極結構中之導體層的部份側壁表面得以暴露出來，並利用延伸至埋入式汲極上方的圖案化導體層，來使得浮置閘極與控制閘極之間的重疊面積增加，進而提高元件的搞合率。為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說明如下：實施方式第1 A圖至第1 L圖係繪示本發明最佳實施例之一種快閃記憶體的製.造流程上視圖。第2 A圖至第2 L係為第1 A圖至第 1 L圖之I - Γ線的剖面圖。首’先請同時參照第1 A圖及第2 A 圖，提供一基底1 0 0 ，此基底1 0 0例如是矽基底。然後，於謂^ 此基底100上依序形成穿隧介電層102、導體層104與罩幕層1 0 6。穿隨介電層1 0 2之材質例如是氧化石夕，其厚度例如是50埃至1 00埃左右。穿隧介電層1 0 2之形成方法例如是熱氧化法或是低壓化學氣相沉積法（L P C V D )。導體層1 0 4之材質例如是摻雜多晶矽。其形成的方法例如是低壓化學氣相沉積法，以矽甲烷（S i 1 an e )為氣體源沉積一層多晶矽層後，然後再進行摻質植入製程以形成之。其中，沈積製程之操作溫度為 5 7 5 °C至6 5 0 °C之間，操作壓力約在0 · 3 t 〇 r r至0 . 6 t 〇 r r9677 twf.ptd Page 8 1235461___ 5. Description of the invention (3) The present invention is to reduce the height of the insulating layer around the gate structure, so that part of the sidewall surface of the conductor layer in the gate structure is exposed, and it is extended to the buried surface. The patterned conductor layer above the sink-type drain electrode increases the overlapping area between the floating gate and the control gate, thereby increasing the engagement rate of the components. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Embodiments 1A to 1 Figure L is a top view of a flash memory manufacturing process according to a preferred embodiment of the present invention. Figures 2A to 2L are cross-sectional views taken along lines I-Γ in Figures 1A to 1L. First, please refer to FIG. 1A and FIG. 2A at the same time, and provide a substrate 100, which is, for example, a silicon substrate. Then, a tunneling dielectric layer 102, a conductor layer 104, and a mask layer 106 are sequentially formed on the substrate 100. The material of the penetrating dielectric layer 102 is, for example, oxidized stone, and its thickness is, for example, about 50 to 100 angstroms. The formation method of the tunnel dielectric layer 102 is, for example, a thermal oxidation method or a low-pressure chemical vapor deposition method (LPCVD). The material of the conductive layer 104 is, for example, doped polycrystalline silicon. The formation method is, for example, a low-pressure chemical vapor deposition method, after depositing a polycrystalline silicon layer using silicon methane (S i 1 an e) as a gas source, and then performing a dopant implantation process to form it. Among them, the operating temperature of the deposition process is between 5 7 5 ° C and 65 0 ° C, and the operating pressure is about 0 · 3 t 〇 r r to 0.6 t 〇 r r

之間。 U 罩幕層1 0 6之材質例如是氮化矽或氧化矽。當材質為〇氮化矽時，例如是以二氯矽甲烷與氨氣作為反應氣體源，between. The material of the U cover curtain layer 106 is, for example, silicon nitride or silicon oxide. When the material is silicon nitride, for example, dichlorosilicon and ammonia are used as the reaction gas source,

%77t.wf.ptd 第9頁 1235461_ 五、發明說明（4) 利用低壓化學氣相沉積法以形成之。接著請同時參照第1 B圖及第2 B圖。於罩幕層1 0 6上形成一圖案化光阻層1 0 8。然後以光阻層1 〇 8為罩幕，蝕刻穿遂介電層102、導體層104與罩幕層106，以於基底100上形成縱向排列的條狀物2 〇〇，此條狀物2 0 0包括圖案化穿遂介電層102a 、圖案化導體層l〇4a與圖案化罩幕層106a。然後，進行離子植入製程，於條狀物2 0 0之間的基底1 0 0中形成埋入式沒極區（Buried Drain)ll〇。接著請同時參照第1 C圖及第2 C圖。移除上述之圖案化光阻層1 0 8。然後於圖案化的罩幕層1 0 6 a上形成另一圖案. 化光阻層（未繪圖示）。接著以此圖案化光阻層為罩幕，再蝕刻條狀物2 0 0，於基底1 0 0上形成閘極結構3 0 0。此閘極結構3 0 0係由圖案化的穿隧介電層1 0 2 b、圖案化的導體層 1 0 4 b與圖案化的罩幕層1 0 6 b所構成。接著，請同時參照第1 D圖與第2 D圖，在基底1 0 0上形成絕緣層1 1 2，以覆蓋閘極結構3 0 0，並填入閘極結構3 0 0 之間的間隙。絕緣層1 1 2的材質係與罩幕層1 0 6 b之材質具有不同蝕刻選擇性者，絕緣層1 1 2的材質例如是氧化矽、氮化矽或是旋塗式玻璃等。其形成的方法例如是高密度電漿化學氣相沉積法（H D P - C V D )或旋轉塗佈法。接著，請同時參照第1 Ε圖與第2 Ε圖，將罩幕層1 0 6 b表面上所覆蓋的絕緣層1 1 2去除，以暴露圖案化罩幕層1 0 6 b 的表面，留下位於閘極結構3 0 0之間的絕緣層1 1 2 a。去除 •靜罩幕層1 0 6 b表面上之絕緣層1 1 2的方法例如是化學機械研% 77t.wf.ptd Page 9 1235461_ V. Description of the invention (4) It is formed by low pressure chemical vapor deposition. Please refer to Figure 1B and Figure 2B at the same time. A patterned photoresist layer 108 is formed on the mask layer 106. Then, using the photoresist layer 108 as a mask, the dielectric layer 102, the conductor layer 104, and the mask layer 106 are etched through to form a longitudinally arranged stripe 200 on the substrate 100. This stripe 2 0 0 includes a patterned tunnel dielectric layer 102a, a patterned conductor layer 104a, and a patterned mask layer 106a. Then, an ion implantation process is performed to form a buried Drain 110 in the substrate 100 between the strips 200. Please refer to Figure 1C and Figure 2C at the same time. Remove the aforementioned patterned photoresist layer 108. Then, another patterned photoresist layer (not shown) is formed on the patterned mask layer 10a. Then use this patterned photoresist layer as a mask, and then etch the strips 200 to form a gate structure 300 on the substrate 100. The gate structure 3 0 0 is composed of a patterned tunneling dielectric layer 10 2 b, a patterned conductor layer 1 0 4 b, and a patterned mask layer 1 0 6 b. Next, referring to FIG. 1D and FIG. 2D at the same time, an insulating layer 1 12 is formed on the substrate 100 to cover the gate structure 3 0 0 and fill the gap between the gate structures 3 0 0 . The material of the insulating layer 1 1 2 is different from the material of the cover layer 10 6 b with different etching selectivity. The material of the insulating layer 1 1 2 is, for example, silicon oxide, silicon nitride, or spin-on glass. The formation method is, for example, a high-density plasma chemical vapor deposition method (H D P-C V D) or a spin coating method. Next, referring to Figure 1E and Figure 2E at the same time, remove the insulating layer 1 1 2 covering the surface of the mask layer 1 0 6 b to expose the surface of the patterned mask layer 1 0 6 b. The lower insulating layer 1 1 2 a is located between the gate structures 300. Removal • Static masking layer 1 0 6 b The method of insulating layer 1 1 2 on the surface is, for example, chemical mechanical research

9677 twf.ptd 第10頁 1235461 五、發明說明（5) 磨法或回鞋刻法。之後’請同時參照第1 F圖與第2 F圖，將部分的絕緣層 1 1 2 a去除，以使所留下之絕緣層1 1 2 b之表面低於導體層 1 0 4 b之頂表面，以裸露出導體層1 〇 4 b之周圍部份側壁表面。移除部分絕緣層1 1 2 a之方法例如是回餘刻法。其後，請同時參照第1 G圖與第2 G圖，再於絕緣層1 1 2 a 上形成材料層1 1 4，以覆蓋閘極結構3 0 0 ，並填入閘極結構 3 0 0之間的間隙。此材料層1 1 4的材質例如是硼磷矽玻璃 (B P S G )或是磷矽玻璃（P S G )，其係與罩幕層1 0 6 b及絕緣層 1.1 2 b具有不同蝕刻率者。當此材料層1 1 4的材質是硼磷矽玻璃時，硼磷矽玻璃的形成方法例如是常壓化學氣相沉積法，係以矽烷、磷化氫及硼化氫為反應氣體源，反應溫度例如是介於3 5 0 °C至4 5 Ο X：之間。接著，請同時參照第1 Η圖與第2 Η圖，將罩幕層1 0 6 b表面上所覆蓋的材料層1 1 4去除，以暴露圖案化罩幕層1 0 6 b 的表面，留下位於閘極結構3 0 0之間的材料層1 1 4 a。其中，去除罩幕層1 〇 6 b表面上之材料層1 1 4的方法例如是化學機械研磨法或回餘刻法。之後，請同時參照第1 I圖及第2 I圖。移除罩幕層 106b，以暴露出導體層104b之上表面。移除罩幕層106b的方法例如濕式蝕刻法。當罩幕層1 0 6 b之材質為氮化矽時，移除罩幕層1 〇 6 b所用的餘刻劑例如是墙酸。接著，請同時參照第1 J圖及第2 J圖。於圖案4匕導體層 1 0 4 b的頂表面上形成另一圖案化導體層1 1 6 ，此圖案化導9677 twf.ptd Page 10 1235461 V. Description of the invention (5) Grinding method or back shoe carving method. Afterwards, please refer to Figure 1 F and Figure 2 F at the same time and remove part of the insulating layer 1 1 2 a so that the surface of the remaining insulating layer 1 1 2 b is lower than the top of the conductor layer 1 0 4 b Surface, so as to expose a part of the side wall surface around the conductive layer 104b. A method of removing a part of the insulating layer 1 1 2 a is, for example, a back-etching method. After that, please refer to Figure 1 G and Figure 2 G at the same time, and then form a material layer 1 1 4 on the insulating layer 1 1 a to cover the gate structure 3 0 0 and fill in the gate structure 3 0 0 Gap between. The material of the material layer 1 1 4 is, for example, borophosphosilicate glass (B P S G) or phosphosilicate glass (P S G), which has a different etching rate from the cover layer 1 06 b and the insulating layer 1.1 2 b. When the material layer 1 1 4 is borophosphosilicate glass, the formation method of borophosphosilicate glass is, for example, atmospheric pressure chemical vapor deposition method, and silane, phosphine, and hydrogen borohydride are used as reaction gas sources to react. The temperature is, for example, between 3 5 0 ° C and 4 5 Ο X :. Next, referring to the first and second drawings at the same time, remove the material layer 1 1 4 covered on the surface of the mask layer 1 0 6 b to expose the surface of the patterned mask layer 1 0 6 b. A material layer 1 1 a is located between the gate structures 300. Among them, the method of removing the material layer 1 1 4 on the surface of the mask layer 106 b is, for example, a chemical mechanical polishing method or a back-etching method. After that, please refer to Figure 1 I and Figure 2 I at the same time. The cover layer 106b is removed to expose the upper surface of the conductor layer 104b. The method of removing the mask layer 106b is, for example, a wet etching method. When the material of the mask layer 10 6 b is silicon nitride, the post-etching agent used for removing the mask layer 10 6 b is, for example, wall acid. Next, please refer to Figure 1 J and Figure 2 J at the same time. Another patterned conductor layer 1 1 6 is formed on the top surface of the pattern 4 conductor layer 1 0 4 b.

9677 twf.p td 第11頁 1235461_ 五、發明說明（6) 體層1 1 6係覆蓋於圖案化導體層1 〇 4 b的頂表面，並且延伸覆蓋至其周緣的材料層1 1 4 a上。換言之，此圖案化導體層 116的上表面積大於圖案化導體層l〇4b的上表面積與圖案化導體層1 0 4 b構成一浮置閘極4 0 0。形成圖案化導體層1 1 6的步驟，包括先形成一導體材料層，此導體材料層的材質例如是摻雜多晶矽，覆蓋於圖案化導體層1 0 4 b與材料層1 1 4 a的頂表面上。形成此導體材料層的方法例如是低壓化學氣相沉積法然後於此導體材料層上形成一圖案化光阻層（未繪圖示）。接著以此圖案化光阻層為罩幕，蝕刻導體層1 1 6 ，以暴露出材料層.1 1 4 a的頂表面為止。接著請參照第1 K圖及第2 K圖。移除材料層1 1 4 a。移除材料層1 1 4 a之方法例如是回姓刻法。接著請參照第1 L圖及第2 L圖。於基底1 0 0上形成閘間介電層1 1 8 ，以覆蓋圖案化導體層1 0 4 b的側壁與圖案化導體層1 1 6的側壁及上表面。此閘間介電層1 1 8之材質包括氧化矽/氮化矽/氧化矽（Ο N 0 )。閘間介電層1 1 8之形成方法例如是先以熱氧化法形成一層氧化層後，再以低壓化學氣相沈積法形成氮化矽層與另一層氧化層。當然，此閘間介電層1 1 8之材質也可以是氧化矽層或是氧化矽/氮化矽層等。之後，於閘間介電層1 1 8上形成導體層1 2 0以作為一控制閘極。此導體層1 2 0例如是由一層摻雜多晶矽層1 2 2與一層石夕化金屬層1 2 4共同組成的多晶矽化物金屬（Ρ ο 1 y c i d e )9677 twf.p td Page 11 1235461_ 5. Description of the invention (6) The body layer 1 1 6 covers the top surface of the patterned conductor layer 1 0 4 b, and extends to cover the material layer 1 1 4 a at its periphery. In other words, the upper surface area of the patterned conductor layer 116 is larger than the upper surface area of the patterned conductor layer 104b and the patterned conductor layer 104b constitutes a floating gate electrode 400. The step of forming the patterned conductor layer 1 16 includes forming a conductor material layer. The material of the conductor material layer is, for example, doped polycrystalline silicon, and covers the top of the patterned conductor layer 1 0 4 b and the material layer 1 1 4 a. On the surface. The method of forming the conductive material layer is, for example, a low pressure chemical vapor deposition method and then forming a patterned photoresist layer (not shown) on the conductive material layer. Then use this patterned photoresist layer as a mask and etch the conductor layer 1 1 6 to expose the top surface of the material layer 1 1 4 a. Please refer to Figure 1 K and Figure 2 K. Remove the material layer 1 1 4 a. The method of removing the material layer 1 1 4 a is, for example, the method of engraving the surname. Please refer to Figures 1 L and 2 L. An inter-gate dielectric layer 1 1 8 is formed on the substrate 100 to cover the sidewall of the patterned conductor layer 10 4 b and the sidewall and upper surface of the patterned conductor layer 1 16. The material of the inter-gate dielectric layer 1 1 8 includes silicon oxide / silicon nitride / silicon oxide (0 N 0). The inter-gate dielectric layer 1 1 8 is formed by, for example, forming an oxide layer by a thermal oxidation method, and then forming a silicon nitride layer and another oxide layer by a low pressure chemical vapor deposition method. Of course, the material of the inter-gate dielectric layer 1 18 can also be a silicon oxide layer or a silicon oxide / silicon nitride layer. Thereafter, a conductor layer 120 is formed on the inter-gate dielectric layer 1 18 as a control gate. The conductor layer 1 2 0 is, for example, a polycrystalline silicide metal (P ο 1 y c i d e) composed of a doped polycrystalline silicon layer 1 2 2 and a petrified metal layer 1 2 4.

9677twf . pt.d 第12頁 1235461 五、發明說明（Ό 層。摻雜多晶矽形成的方法例如是利用臨場（I η - s i t u )摻雜法。而石夕化金属例如是以金屬氟化物與石夕曱院為氣體源，形成的方法例如是低壓化學氣相沉積法。後續完成快閃記憶體之製程，為熟悉此項技術者所周知，在此不再贅述。如上所述，本發明的特點在於以兩個圖案化的導體層來構成浮置閘極。其中第一個導體層係位於埋入式汲極之間，其係藉著周圍絕緣層之高度高度的縮減，以使其部份側壁表面得以暴露出來。另一導體層係位於上述第一個導體層上並且延伸至埋入式汲極上方。藉由第一導體層所裸露出來的側壁與第二導體層延伸至埋入式汲極上方部分，來使得浮置閘極與控制閘極之間的重疊面積增加’進而提扑高元件的耦合率。由於本發明是在不增加記憶胞單位面積之情況下，就可以增加浮置閘極與控制閘極之間的面積’ 而提高元件的耦合率，因此可以增加元件積集度。在上述的較佳實施例中，係以在一閘極結構之導體層上形成另一個導體層為例’以說明本發明的精神。然而本發明並非僅侷限於上述之應用，亦可在一閘極結構之導體層上依序形成兩個導體層或多個導體層。在閘極結構之導體層上依序形成兩個導體層之方法如下所述。請參照第3圖，依上述第2 A圖至第2 J圖所述之方法’ 形成第2 J圖所述之結構後，在圖案化導體層1 1 6之間的間隙填入材料層3 0 2。材料層3 0 2之表面南度係低於或疋大致等高於圖案化導體層116之表面高度。接著在圖案化導體9677twf. Xixianyuan is a gas source, and the formation method is, for example, a low-pressure chemical vapor deposition method. The subsequent completion of the flash memory process is well known to those skilled in the art and will not be repeated here. As mentioned above, the present invention The feature is that the floating gate is formed by two patterned conductor layers. The first conductor layer is located between the buried drain electrodes, which is reduced by the height of the surrounding insulating layer to make its part A portion of the sidewall surface is exposed. Another conductor layer is located on the first conductor layer and extends above the buried drain. The sidewall exposed by the first conductor layer and the second conductor layer extend to the buried portion. The upper part of the drain is used to increase the area of overlap between the floating gate and the control gate, thereby increasing the coupling rate of the device. Since the present invention does not increase the unit area of the memory cell, it can The coupling ratio of the components is increased by increasing the area between the floating gate and the control gate, so that the component accumulation can be increased. In the above-mentioned preferred embodiment, the conductive layer of a gate structure is used. The formation of another conductor layer is taken as an example to illustrate the spirit of the present invention. However, the present invention is not limited to the above-mentioned application, and two conductor layers or multiple conductor layers may be sequentially formed on a conductor layer of a gate structure. The method of sequentially forming two conductor layers on the conductor layer of the gate structure is as follows. Please refer to FIG. 3 and follow the method described in the above FIGS. 2A to 2J to form the second J figure. After the structure, the material layer 3 2 is filled in the gap between the patterned conductor layers 1 16. The surface south of the material layer 3 2 is lower than or substantially equal to the surface height of the patterned conductor layer 116 . Then the patterned conductor

9677twf.ptd 第13頁 1235461_ 五、發明說明（8) 層116上再形成另一圖案化導體層304 ，圖案化導體層304 係覆蓋圖案化導體層1 1 6並且延伸覆蓋至周緣的材料層3 0 2 上。接著，請參照第4圖，將材料層1 1 4 a及材料層3 0 2移除，以形成一個由閘極結構之導體層1 0 4 b與另外兩個導體層1 1 6、3 0 4所構成的浮置閘極。之後，再於所裸露的浮置閘極的表面上形成閘間介電層1 1 8，並於閘間介電層1 1 8上形成導體層1 2 0以作為一控制閘極。本發明亦可以重複上述形成材料層3 0 2與導體層3 0 4之步驟，在一閘極結構之導體層1 0 4 b上.依序形成多個導體以增加浮置閘極與控制閘極之間的重疊面積，進而提高耦合率。綜所述，本發明係降低閘極結構周圍之絕緣層高度，使閘構中之導體層的部份側壁表面得以暴露出來，並利用延埋入式汲極上方的圖案化導體層，來增加浮置閘極與控制閘極之間的重疊面積，進而在不增加晶片面積的前提之下，達到提高元件的耦合率的目的。雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍内，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。9677twf.ptd Page 13 1235461_ 5. Description of the invention (8) Another patterned conductor layer 304 is formed on the layer 116. The patterned conductor layer 304 covers the patterned conductor layer 1 1 6 and extends to the peripheral material layer 3 0 2 on. Next, referring to FIG. 4, the material layer 1 4 a and the material layer 3 0 2 are removed to form a conductor layer 1 0 4 b with a gate structure and two other conductor layers 1 1 6 and 3 0 4 floating gate. Then, an inter-gate dielectric layer 1 18 is formed on the surface of the exposed floating gate, and a conductor layer 120 is formed on the inter-gate dielectric layer 1 18 as a control gate. The present invention can also repeat the steps of forming the material layer 3 0 2 and the conductor layer 3 0 4 on the conductor layer 10 4 b of a gate structure. Multiple conductors are sequentially formed to increase the floating gate and the control gate. The area of overlap between the poles further improves the coupling rate. In summary, the present invention is to reduce the height of the insulating layer around the gate structure, so that part of the sidewall surface of the conductor layer in the gate structure is exposed, and the patterned conductor layer above the buried drain is used to increase The overlapping area between the floating gate and the control gate can further improve the coupling rate of the components without increasing the chip area. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.

9677t.wf.ptd 第14頁 1235461_ 圖式簡單說明第1 A至第1 L圖為繪示本發明最佳實施例所述之一種快閃記憶體的製造流程上視圖；第2 A至第2 L圖係為第1 A至第1 L圖之I - Γ線之剖面圖；以及第3圖與第4圖係繪示本發明另一種快閃記憶體之製造流程之剖面圖。圖式標不說明 · 1 0 0 :基底 1 0 2 :穿遂氧化層 102a、102b :圖案化穿遂氧化層 1 04、1 20 :導體層 104a、104b、116、304:圖案化導體層籲卜 1 06 :罩幕層 106a、106b :圖案化罩幕層 1 0 8 :圖案化光阻層 1 1 0 ··埋入式汲極 1 1 2、1 1 2 a、1 1 2 b :絕緣層 1 1 4、1 1 4 a、3 0 2 :材料層 118 閘間介電層 122 摻雜多晶矽層 1 24 矽化金屬層 200 條狀物 300 閘極結構 400 浮置閘極9677t.wf.ptd Page 14 1235461_ Brief description of the drawings 1A to 1L are top views showing the manufacturing process of a flash memory according to the preferred embodiment of the present invention; 2A to 2 Figure L is a cross-sectional view taken along line I-Γ of Figures 1 A to 1 L; and Figures 3 and 4 are sectional views showing the manufacturing process of another flash memory according to the present invention. Symbols are not explained.1 0 0: substrate 1 102: tunneling oxide layers 102a, 102b: patterned tunneling oxide layers 104, 120: conductor layers 104a, 104b, 116, 304: patterned conductor layers Bu 1 06: Mask layer 106a, 106b: Patterned mask layer 1 0 8: Patterned photoresist layer 1 1 0 ... Buried drain 1 1 2, 1 1 2 a, 1 1 2 b: Insulation Layer 1 1 4, 1 1 4 a, 3 0 2: material layer 118 inter-gate dielectric layer 122 doped polycrystalline silicon layer 1 24 silicided metal layer 200 strip 300 gate structure 400 floating gate

9677twf.ptd 第15頁9677twf.ptd Page 15

Claims

T235461_ 六、申請專利範圍 1 · 一種快閃記憶體之製造方法，包括下列步驟：於一基底上依序形成一穿隧介電層、一第一導體層與一罩幕層；進行一第一圖案化製程，定義該穿遂介電層、該罩幕層與該第一導體層，以於該基底上形成一條狀物；於該條狀物之間的該基底中形成一埋入式汲極區；進行一第二圖案化製程，定義該條狀物，於該基底上形成一閘極結構，該閘極結構係由一圖案化穿遂介電層、一圖案化罩幕層與一圖案化第一導體層所構成；於該閘極結構的周圍之該基底上形成一絕緣層，該絕緣層之表面低於該圖案化第一導體層之表面'暴露出該圖案化第一導體層之部份側壁表面；於該閘極結構的周圍之該絕緣層上形成一材料層；移除該圖案化罩幕層；於該閘極結構之該圖案化第一導體層的頂表面上形成一圖案化第二導體層，該圖案化第二導體層係覆蓋該圖案化第一導體層的頂表面，並且延伸覆蓋至該圖案化第一導體層周緣的該材料層上，而與該圖案化第一導體層構成一浮置閘極；移除該材料層，以暴露出該圖案化第一導體層之部份側壁表面；於該浮置閘極所裸露的表面上形成一閘間介電層；以及於該閘間介電層上形成一控制閘極。T235461_ VI. Scope of patent application1. A method for manufacturing flash memory, including the following steps: sequentially forming a tunneling dielectric layer, a first conductor layer, and a cover layer on a substrate; performing a first Patterning process, defining the tunneling dielectric layer, the mask layer and the first conductor layer to form a strip on the substrate; forming a buried drain in the substrate between the strips A polar region; performing a second patterning process, defining the strip, and forming a gate structure on the substrate, the gate structure is composed of a patterned tunnel dielectric layer, a patterned mask layer, and a Formed by a patterned first conductor layer; forming an insulation layer on the substrate around the gate structure, the surface of the insulation layer being lower than the surface of the patterned first conductor layer 'exposes the patterned first conductor A part of the sidewall surface of the layer; forming a material layer on the insulating layer around the gate structure; removing the patterned mask layer; on the top surface of the patterned first conductor layer of the gate structure Forming a patterned second conductor layer, the The patterned second conductor layer covers the top surface of the patterned first conductor layer, and extends to cover the material layer on the periphery of the patterned first conductor layer, and forms a floating with the patterned first conductor layer. The gate; removing the material layer to expose a portion of the sidewall surface of the patterned first conductor layer; forming an inter-gate dielectric layer on the exposed surface of the floating gate; and the inter-gate dielectric A control gate is formed on the electrical layer.

9677twf. pt.d 第16頁 1235461 六、申請專利範圍 2 ·如申請專利範圍第1項所述之快閃記憶體之製造方法，其中於該圖案化第一導體層上形成一圖案化第二導體層之後，移除該材料層之前更包括以下步驟： (a )·於該圖案化第二導體層的周圍形成一另材料層，該材料層之表面高度低於或是大致等於該圖案化第二導體層之表面高度； (b).在該圖案化第二導體層上形成一圖案化第三導體層，該圖案化第三導體層係覆蓋該圖案化第二導體層並且延伸至該另一材料層上，並且該圖案化第一、第二與第三導體層構成該浮置閘；以及 (c ) ·移除該另一材料層。 3 .如申請專利範圍第2項所述之快閃記憶體之製造方法，其中該材料層的材質係與該絕緣層具有不同蝕刻率者。 4 .如申請專利範圍第2項所述之快閃記憶體之製造方法，其中形成該圖案化第三導體層與去除該另材料層之步驟之間更包括重複上述（a )至（c )步驟。 5 .如申請專利範圍第1項所述之快閃記憶體之製造方法，其中該材料層的材質係與該絕緣層具有不同蝕刻率者。 6 .如申請專利範圍第5項所述之快閃記憶體之製造方法，其中於該絕緣層之材質包括氧化矽、氮化矽、旋塗式玻璃其中之一。 7.如申請專利範圍第5項所述之快閃記憶體之製造方9677twf. Pt.d Page 16 1235461 6. Application for Patent Scope 2 · The flash memory manufacturing method described in item 1 of the patent application scope, wherein a patterned second conductor layer is formed on the patterned first conductor layer After the conductor layer, before removing the material layer, the method further includes the following steps: (a) forming another material layer around the patterned second conductor layer, the surface height of the material layer being lower than or substantially equal to the patterning The surface height of the second conductor layer; (b) forming a patterned third conductor layer on the patterned second conductor layer, the patterned third conductor layer covering the patterned second conductor layer and extending to the On another material layer, and the patterned first, second and third conductor layers constitute the floating gate; and (c) removing the other material layer. 3. The method of manufacturing a flash memory as described in item 2 of the scope of the patent application, wherein the material of the material layer is different from the insulating layer in the etching rate. 4. The method for manufacturing a flash memory as described in item 2 of the scope of patent application, wherein the steps of forming the patterned third conductor layer and removing the other material layer further include repeating the above (a) to (c) step. 5. The method for manufacturing a flash memory as described in item 1 of the scope of the patent application, wherein the material of the material layer is different from the insulating layer in the etching rate. 6. The method for manufacturing a flash memory as described in item 5 of the scope of patent application, wherein the material of the insulating layer includes one of silicon oxide, silicon nitride, and spin-on glass. 7. Manufacturer of flash memory as described in item 5 of the scope of patent application

9677 twf.ptd 第17頁 1235461___ 六、申請專利範圍法，其中該材料層的材質包括硼磷矽玻璃或磷矽玻璃其中之一〇 8 ·如申請專利範圍第1項所述之快閃記憶體之製造方法，其中於該閘極結構的周圍形成該絕緣層的步驟包括：於該基底上形成一絕緣材料層，以覆蓋該閘極結構之上表面並且填滿該閘極結構的周圍；去除該閘極結構之上表面上所覆蓋的該絕緣材料層，以暴露該罩幕層之表面；以及移除部分該絕緣材料層，使該絕緣材料層之表面介於該圖案化第一導.體層的底表面與該圖案化第一導體層的頂表面之間，而形成該絕緣層。 _ 9 .如申請專利範圍第8項所述之快閃記憶體之製造方 4 法，其中去除該閘極結構之上表面上所覆蓋的該絕緣材料層之方法為化學機械研磨法與回蝕刻法其中之一。 1 0 .如申請專利範圍第8項所述之快閃記憶體之製造方法，其中於移除部分該絕緣材料層之方法包括回蝕刻法。 1 1 , 一種快閃記憶體之製造方法，包括下列步驟：於一基底上依序形成一圖案化穿隧介電層、一圖案化第一導體層；於該圖案化第一導體層之間的該基底中形成一埋入式 >及極區，於該圖案化第一導體層的周圍形成一絕緣層，該絕緣層之表面介於該圖案化第一導體層之底表面與頂表面之 ” 間；9677 twf.ptd Page 17 1235461___ 6. Method of applying for a patent, where the material of the material layer includes one of borophosphosilicate glass or phosphosilicate glass. 08 · Flash memory as described in the first item In a manufacturing method, the step of forming the insulating layer around the gate structure includes: forming an insulating material layer on the substrate to cover an upper surface of the gate structure and fill the periphery of the gate structure; removing The insulating material layer covered on the upper surface of the gate structure to expose the surface of the cover layer; and removing a portion of the insulating material layer so that the surface of the insulating material layer is between the patterned first guide. The insulating layer is formed between the bottom surface of the bulk layer and the top surface of the patterned first conductor layer. _ 9 The method for manufacturing a flash memory as described in item 8 of the scope of patent application, wherein the method of removing the insulating material layer covered on the upper surface of the gate structure is chemical mechanical polishing and etch back Law one of them. 10. The method for manufacturing a flash memory as described in item 8 of the scope of patent application, wherein the method for removing a part of the insulating material layer includes an etch-back method. 1 1. A method for manufacturing a flash memory includes the following steps: sequentially forming a patterned tunneling dielectric layer and a patterned first conductor layer on a substrate; between the patterned first conductor layer An embedded layer and a polar region are formed in the substrate, and an insulation layer is formed around the patterned first conductor layer, and a surface of the insulation layer is interposed between a bottom surface and a top surface of the patterned first conductor layer. Between "

9677 twf.p td 第18頁 1235461__ 六、申請專利範圍於該圖案化第一導體層的周圍之該絕緣層上形成一材料層；於該圖案化第一導體層的頂表面上形成一圖案化第二導體層’該圖案化第二導體層係覆蓋於該圖案化第一導體層的頂表面，並且延伸覆蓋至該圖案化第一導體層周緣的該材料層上，而與該圖案化第一導體層構成一浮置閘極；移除該材料層，以暴露出該圖案化第一導體層之部份側壁表面；於該浮置閘極所裸露的表面上形成一閘間介電層；以及於該閘間介電層上形成一控制閘極。 1 2 .如申請專利範圍第1 1項所述之快閃記憶體之製造4 方法，其中於該圖案化第一導體層上形成一圖案化第二導體層之後，移除該材料層之前，更包括以下步驟： (a ).於該圖案化第二導體層的周圍形成一另材料層，該材料層之表面高度低於或是大致等於該圖案化第二導體層之表面南度； (b).在該圖案化第二導體層上形成一圖案化第三導體層，該圖案化第三導體層係覆蓋該圖案化第二導體層並且延伸至該另一材料層上，並且該圖案化第一、第二與第三導體層構成該浮置閘；以及 (c ) ·移除該另一材料層。 1 3 .如申請專利範圍第1 2項所述之快閃記憶體之製造〇方法，其中該材料層的材質係與該絕緣層具有不同蝕刻率9677 twf.p td Page 18 1235461__ VI. The scope of patent application forms a material layer on the insulating layer around the patterned first conductor layer; forms a pattern on the top surface of the patterned first conductor layer "Second conductor layer" The patterned second conductor layer covers the top surface of the patterned first conductor layer, and extends to the material layer on the periphery of the patterned first conductor layer, and is connected to the patterned first conductor layer. A conductor layer constitutes a floating gate; the material layer is removed to expose a portion of the sidewall surface of the patterned first conductor layer; an inter-gate dielectric layer is formed on the exposed surface of the floating gate And forming a control gate on the inter-gate dielectric layer. 1 2. The method for manufacturing a flash memory as described in item 11 of the scope of patent application, wherein after forming a patterned second conductor layer on the patterned first conductor layer and before removing the material layer, The method further includes the following steps: (a) forming another material layer around the patterned second conductor layer, and a surface height of the material layer is lower than or substantially equal to a surface south of the patterned second conductor layer; ( b) forming a patterned third conductor layer on the patterned second conductor layer, the patterned third conductor layer covers the patterned second conductor layer and extends to the other material layer, and the pattern Forming the first, second and third conductor layers to form the floating gate; and (c) removing the other material layer. 13. The method for manufacturing a flash memory as described in item 12 of the scope of the patent application 〇 The method, wherein the material of the material layer has a different etch rate from the insulating layer

9677 twf·p td 第19頁 1235461 六、申請專利範圍者。 1 4 .如申請專利範圍第1 2項所述之快閃記憶體之製造方法，其中形成該圖案化第三導體層與去除該另材料層之步驟之間更包括重複上述（a )至（c )步驟。 1 5 ·如申請專利範圍第1 1項所述之快閃記憶體之製造方法，其中該材料層的材質係與該絕緣層具有不同蝕刻率者。 1 6 ·如申請專利範圍第1 5項所述之快閃記憶體之製造方法，其中於該絕緣層之材質包括氧化矽、氮化矽、旋塗式玻璃其中之一。 1 7 ·如申請專利範圍第1 5項所述之快閃記憶體之製造方法，其中該材料層的材質包括硼磷矽玻璃或磷矽玻璃其中之一。 1 8 .如申請專利範圍第1 1項所述之快閃記憶體之製造方法，其中於該閘極結構的周圍形成該絕緣層的步驟包括：於該基底上形成一絕緣材料層，以覆蓋該閘極結構之上表面並且填滿該閘極結構的周圍；去除該閘極結構之上表面上所覆蓋的該絕緣材料層，以暴露該罩幕層之表面；以及移除部分該絕緣材料層，使該絕緣材料層之表面介於該圖案化第一導體層的底表面與該圖案化第一導體層的頂表面之間，而形成該絕緣層。 1 9 .如申請專利範圍第1 8項所述之快閃記憶體之製造9677 twf · p td Page 19 1235461 6. Those who apply for a patent. 14. The method for manufacturing a flash memory as described in item 12 of the scope of patent application, wherein the steps of forming the patterned third conductor layer and removing the other material layer further include repeating the above (a) to ( c) steps. 15 · The flash memory manufacturing method according to item 11 of the scope of patent application, wherein the material of the material layer has a different etching rate from the insulating layer. 16 · The flash memory manufacturing method as described in item 15 of the scope of patent application, wherein the material of the insulating layer includes one of silicon oxide, silicon nitride, and spin-on glass. 17 · The method for manufacturing a flash memory according to item 15 of the scope of patent application, wherein the material of the material layer includes one of borophosphosilicate glass or phosphosilicate glass. 18. The method for manufacturing a flash memory as described in item 11 of the scope of patent application, wherein the step of forming the insulating layer around the gate structure includes: forming an insulating material layer on the substrate to cover The upper surface of the gate structure and fills the periphery of the gate structure; removing the insulating material layer covered on the upper surface of the gate structure to expose the surface of the cover layer; and removing part of the insulating material Layer, so that the surface of the insulating material layer is interposed between the bottom surface of the patterned first conductor layer and the top surface of the patterned first conductor layer to form the insulating layer. 19. Manufacture of flash memory as described in item 18 of the scope of patent application

9677 t.wf. p td. 第20頁 -1235461___ 六、申請專利範圍方法’其中去除該閘極結構之上表面上所覆蓋的該絕緣材料層之方法為化學機械研磨法與回触刻法其中之一。 2 〇 ·如申請專利範圍第1 8項所述之快閃記憶體之製造方法，.其中於移除部分該絕緣材料層之方法包括回蝕刻法09677 t.wf. p td. Page 20-1235461 ___ VI. Patent Application Method 'where the method of removing the insulating material layer covered on the upper surface of the gate structure is the chemical mechanical polishing method and the back-contact engraving method. one. 2 〇 The method for manufacturing a flash memory as described in item 18 of the scope of patent application, wherein the method for removing a part of the insulating material layer includes an etch-back method.

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