TWI313043B

TWI313043B - Method of fabricating flash memory

Info

Publication number: TWI313043B
Application number: TW92119491A
Authority: TW
Inventors: Ling-Wuu Yang; Kuang-Chao Chen; Jui-Lin Lu
Original assignee: Macronix Int Co Ltd
Priority date: 2003-07-17
Filing date: 2003-07-17
Publication date: 2009-08-01
Also published as: TW200504944A

Description

1313043 五、發明說明（1) 發明所屬之技術領域本發明是有關於一種快閃記憶體的製造方法，特別是有關於一種增加浮置閘極與控制閘極間的重疊（0 v e r 1 a p ) 面積之快閃記憶體的製造方法。先前技術快閃記憶體元件由於其優越的資料保存特性，所以已成為個人電腦和電子設備所廣泛採用的一種記憶體元件。典型的快閃記憶體元件，一般是被設計成具有堆疊式閘極（Stack- Gate)結構，其中包括一穿隨氧化層，一用來儲存電荷的多晶石夕浮置閘極（F 1 〇 a t i n g G a t e )，一氧化石夕/ 氮4匕石夕/氧4匕石夕（Oxide-Nitride — Oxide ，0N0)結構的介電層，以及一用來控制資料存取的多晶石夕控制閘極（C ο n t r ο 1 Gate) ° 之極閘制控} 與R) 極GC 閘’ -ο 置i 浮a 常R 通ng • 1 -- 上up 作Co 操e-的at 體(G 憶率記合閃耦快極在閘的間大愈效加带與增控度了與速括極作包閘操，置的法浮體方低憶的降記率、閃合積快耦面而極疊，閘重低加的愈增間將。極壓升間電提制作的控工大與之大極需會閘所就置作率浮制控與極閘置浮CO 加 C 增Γ1 及ct 以le 、e 度(D 厚數的常層電電介介的之層間電極介閘之BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a method of fabricating a flash memory, and more particularly to increasing overlap between a floating gate and a control gate (0 ver 1 ap ). A method of manufacturing a flash memory of an area. Prior Art Flash memory components have become a memory component widely used in personal computers and electronic devices due to their superior data retention characteristics. A typical flash memory component is generally designed to have a stacked gate-gate structure including a pass-through oxide layer and a polycrystalline litter floating gate for storing charge (F 1 〇 ating G ate ), a dielectric layer of Oxide-Nitride — Oxide (0N0) structure, and a polycrystalline stone for controlling data access. Control gate (C ο ntr ο 1 Gate) ° pole gate control} and R) pole GC gate ' -ο set i float a constant R pass ng • 1 -- up up Co run e-at body ( G Recalling the rate of flash-coupled fast-connecting poles between the gates, the more effective and the addition of the control and the speed-changing poles, the low-return rate of the floating body, the flash-collecting fast coupling The surface is extremely stacked, and the increase in the weight of the gate is increased. The control of the extreme pressure rise is very large, and the gate is required to be set as the float control and the pole gate floats CO plus C. And ct with the degree of le and e (the thickness of the D-thick layer of the inter-layer electrode

S k 等加增勢於趨助之有度，集積積面高疊求重追的續間持極路閘電制體控積與在極是閘但置’ 浮率加合增耦極閘須率必合而耦因高卻有積具面作的製佔，所下胞積憶面記片個晶一的每限件有元在體何憶如記此閃因央。，減下縮S k, etc., increase in the degree of help, the accumulation of the stacking surface is high, and the continuation of the slab is the same as that of the slab. The rate must be combined and the coupling is high, but there is a system of production. The lower part of the cell memory and the memory of each piece of the crystal are in the body. Reduction

操其間極閘Operating the gate

9676t.wf · ptd 第7頁 1313043 五、發明說明（2) 的快閃記憶發明内容因此，法，可以增元件的耗合根據上製造方法，與罩幕層。於基底上形入式〉及極區基底上形成穿隧介電層圖案化的導構的周圍形頂表面，以除圖案化罩極所裸露的介電層上形本發明閘極之部份在浮置閘所與控制閘極為讓本顯易懂，下體是目前極為重要的課題。本發明之加浮置閘率。述與其它此方法係接著將穿成條狀物 (Buried 浮置閘極、圖案化體層當作成絕緣層暴露出浮幕層以暴上表面與成控制閘係降低浮側壁表面露出來的之間的重發明之上文特舉較目的是與控制目的，基底上隧介電，然後 Drain) 結構，的導體元件之，絕緣置閘極露出浮側壁上極0 置閘極得以暴上表面疊面積述和其佳實施提供一種快閃記憶體的製造方閘之間的重疊面積，進而提高本發明依序形層、罩於條狀。接著此浮置層與圖浮置閘層之表周圍侧置閘極形成閘提出一成穿隧幕層與物之間再將條閘極結案化的極。然面低於壁之部的頂表間介電種快閃介電層導體層的基底狀物圖構包括罩幕層後在浮圖案化份表面面，再層，然記憶體的、導體層圖案化，中形成埋案化，於圖案化的。其中，置閘極結導體層之。接著移於浮置閘後於閘間9676t.wf · ptd Page 7 1313043 V. Description of the invention (2) Flash memory SUMMARY OF THE INVENTION Therefore, the method can increase the component's consumption according to the manufacturing method, and the mask layer. Forming a peripheral shaped top surface of the patterned dielectric layer on the substrate and forming a portion of the gate of the present invention on the dielectric layer exposed by the patterned mask The floating gate and the control gate are extremely easy to understand, and the lower body is an extremely important subject at present. The floating gate ratio of the present invention. And other methods of this method are followed by stripping (Buried floating gate, patterned body layer as an insulating layer exposing the floating layer to expose the surface and forming a control gate to reduce the surface of the floating sidewall exposed The above special purpose of the invention is for the purpose of control, the tunneling dielectric on the substrate, and then the Drain) structure, the conductor element, the insulating gate exposes the pole on the floating sidewall, and the gate overlaps the surface area. The preferred embodiment provides a superimposed area between the manufacturing gates of the flash memory, thereby improving the sequential layering and masking of the present invention. Then, the floating layer forms a gate with the side gates around the surface of the floating gate layer, and a pole is formed between the tunneling layer and the object and then the gate is formed. The bottom surface of the dielectric layer of the flash dielectric layer of the dielectric layer is lower than the wall portion, and the base layer of the dielectric layer of the dielectric layer includes the mask layer and then the surface of the floating patterning layer, and then the layer of the memory and the conductor layer. Patterning, forming a buried pattern, in the patterning. Wherein, the gate is connected to the conductor layer. Then move to the floating gate and then to the gate

周圍之絕緣層的高度，使浮置露出來，再將閘間介電層覆蓋及側壁表面，以增加浮置閘極，進而提高元件的耦I合率。他目的、特徵、和優點能更明例，並配合所附圖式，作詳細The height of the surrounding insulating layer exposes the floating layer, and then the dielectric layer of the gate is covered and the sidewall surface is increased to increase the floating gate, thereby increasing the coupling ratio of the components. His purpose, characteristics, and advantages can be more clearly illustrated and detailed with the drawings.

9676twf.ptd 第8頁 1313043 五、發明說明（3) 說明如下：實施方式第1 A圖至第1 G圖係繪示本發明較佳實施例之一種快閃記憶體的製造流程的上視圖。第2 A至第2 G圖為第1 A至第1 G 圖之I - Γ線的剖面圖。首先請同時參照第1 A圖及第2 A圖，提供一基底1 0 0，此基底1 0 0例如是矽基底。然後，於此基底100上依序形成穿隧介電層102、導體層104與罩幕層 1 ◦ 6。穿隧介電層1 0 2之材質例如是氧化矽，其厚度例如是 5 0埃至1 0 0埃左右。9676twf.ptd Page 8 1313043 V. DESCRIPTION OF THE INVENTION (3) Description is as follows: Embodiments FIGS. 1A to 1G are top views showing a manufacturing process of a flash memory according to a preferred embodiment of the present invention. Figures 2A through 2G are cross-sectional views of the I - Γ line of the first to the first G. First, please refer to FIG. 1A and FIG. 2A simultaneously, and provide a substrate 100, which is, for example, a germanium substrate. Then, the tunnel dielectric layer 102, the conductor layer 104, and the mask layer 1 ◦ 6 are sequentially formed on the substrate 100. The material of the tunneling dielectric layer 102 is, for example, yttrium oxide, and its thickness is, for example, about 50 angstroms to about 100 angstroms.

穿隧介電層1 0 2之形成方法例如是熱氧化法或是低壓化學氣相沉積法（LPCVD )。導體層1 04之材質例如是摻雜多晶矽，其形成的方法例如是低壓化學氣相沉積法，以矽曱烷（S i 1 an e )為氣體源沉積一層多晶矽層後，然後再進行摻質植入製程以形成之。其中，沈積製程之操作溫度為 575 °C至650 °C之間，操作壓力約在0.3torr至0.6torr 之間。罩幕層1 0 6之材質例如是氮化矽或氧化矽，其形成的方法例如是以低壓化學氣相沉積法，以二氯矽甲烷與氨氣作為反應氣體源。接著請同時參照第1 B圖及第2 B圖，於罩幕層1 0 6上形成一圖案化的光阻層1 0 8。然後以光阻層1 0 8為罩幕，蝕刻穿隧介電層102 '罩幕層106與導體層104，於基底100上形成縱向排列的條狀物2 0 0 ，此條狀物2 0 0包括圖案化穿隧介電層102a、圖案化導體層104a與圖案化罩幕層106a。然後％The formation method of the tunneling dielectric layer 102 is, for example, thermal oxidation or low pressure chemical vapor deposition (LPCVD). The material of the conductor layer 104 is, for example, a doped polysilicon, which is formed by, for example, a low pressure chemical vapor deposition method, depositing a polycrystalline germanium layer with a gas source of silane (S i 1 an e ), and then performing doping. The process is implanted to form it. Among them, the deposition process operating temperature is between 575 ° C and 650 ° C, and the operating pressure is between 0.3 torr and 0.6 torr. The material of the mask layer 106 is, for example, tantalum nitride or tantalum oxide, which is formed by, for example, low pressure chemical vapor deposition using dichloromethane and ammonia as a source of a reaction gas. Next, referring to FIGS. 1B and 2B, a patterned photoresist layer 108 is formed on the mask layer 106. Then, the photoresist layer 102 is used as a mask to etch the tunneling dielectric layer 102' of the mask layer 106 and the conductor layer 104 to form a longitudinally arranged strip 20 0 on the substrate 100. 0 includes a patterned tunneling dielectric layer 102a, a patterned conductor layer 104a, and a patterned mask layer 106a. Then %

9676t.wf.ptd 第9頁 1313043 五、發明說明（4) 進行離子植入製程，於條狀物2 0 0之間的基底中形成埋入式汲極區1 1 〇。接著請同時參照第1 C圖及第2 C圖，移除上述之圖案化光阻層1 〇 8。然後於圖案化的罩幕層1 0 6 a上形成另一圖案化光阻層（未繪圖示）。接著以此圖案化光阻層為罩幕，再钱刻條狀物2 0 0，於基底1 0 0上形成浮置閘極結構3 0 0。此浮置閘極結構3 0 0包括圖案化的穿隧介電層1 〇 2 b、圖案化的導體層104b與圖案化的罩幕層l〇6b。其中，圖案化導體層1 0 4 b當作元件之浮置閘極。9676t.wf.ptd Page 9 1313043 V. INSTRUCTIONS (4) An ion implantation process is performed to form a buried bungee region 1 1 基底 in a substrate between strips 200. Next, please refer to FIG. 1C and FIG. 2C simultaneously to remove the above patterned photoresist layer 1 〇 8. Another patterned photoresist layer (not shown) is then formed over the patterned mask layer 10 6 a. Then, the photoresist layer is patterned as a mask, and then the strip is formed by the strip, and the floating gate structure 300 is formed on the substrate 100. The floating gate structure 300 includes a patterned tunneling dielectric layer 1 〇 2 b, a patterned conductor layer 104b and a patterned mask layer 16b. Among them, the patterned conductor layer 1 0 4 b is regarded as the floating gate of the element.

接著請同時參照第1 D圖與第2 D圖，在基底1 〇〇上形成絕緣層1 1 2，以覆蓋該浮置閘極結構3 0 0，並填入浮置閘極結構3 0 0之間的間隙。絕緣層1 1 2的材質係與罩幕層1 〇 6 b之材質不同者，例如是氧化矽、氮化矽或是旋塗式玻璃等。其形成的方法例如是高密度電漿化學氣相沉積法 (H D P - C V D )或旋轉塗佈法。接著請同時參照第1 Ε圖與第2 Ε圖，將罩幕層1 〇 6 b表面上所覆蓋的絕緣層112去除，以暴露圖案化罩幕層i〇6b的表面，留下位於浮置閘極結構3 0 0之間的材料層1 1 2 a。其中，去除罩幕層1 〇 6 b表面上之絕緣層的方法例如是化學機械研磨法（C Μ P )或回钱刻法。Next, referring to FIG. 1D and FIG. 2D, an insulating layer 1 1 2 is formed on the substrate 1 , to cover the floating gate structure 300 and fill the floating gate structure 3 0 0 The gap between them. The material of the insulating layer 1 1 2 is different from the material of the mask layer 1 〇 6 b , and is, for example, yttrium oxide, tantalum nitride or spin-on glass. The method of forming it is, for example, high density plasma chemical vapor deposition (H D P - C V D ) or spin coating. Then, referring to FIG. 1 and FIG. 2 simultaneously, the insulating layer 112 covered on the surface of the mask layer 1 〇 6 b is removed to expose the surface of the patterned mask layer i 〇 6b, leaving the floating layer The material layer 1 1 2 a between the gate structures 300. Among them, a method of removing the insulating layer on the surface of the mask layer 1 〇 6 b is, for example, a chemical mechanical polishing method (C Μ P ) or a money cutting method.

接著請同時參照第1 F圖與第2 F圖，將部分的絕緣層 1 1 2 a去除，以使所留下之絕緣層1 1 2 b之表面低於導體層 (浮置閘極）1 04b之頂表面，以裸露出導體層（浮置閘極）1 0 4 b之周圍部份側壁表面。移除部分絕緣層1 1 2 a之方Then, referring to FIG. 1F and FIG. 2F, part of the insulating layer 1 1 2 a is removed, so that the surface of the remaining insulating layer 1 1 2 b is lower than the conductor layer (floating gate) 1 The top surface of 04b exposes the sidewall surface of the surrounding portion of the conductor layer (floating gate) 104b. Remove part of the insulation layer 1 1 2 a

9676twf.ptd 第10頁 1313043 五、發明說明（5) 法例如是回餘刻法。接著請同時參照第1 G圖與第2 G圖，移除罩幕層1 〇 6 b以暴露出導體層l〇4b的上表面。移除圖案化罩幕層l〇6b的方法例如濕式蝕刻法。當罩幕層1 〇 6 b之材質為氮化矽時’所用的#刻劑例如是墙酸。9676twf.ptd Page 10 1313043 V. Description of invention (5) The method is, for example, a recapture method. Next, referring to FIGS. 1G and 2G, the mask layer 1 〇 6 b is removed to expose the upper surface of the conductor layer 10b. A method of removing the patterned mask layer 16b is, for example, a wet etching method. When the material of the mask layer 1 〇 6 b is tantalum nitride, the #-marking agent used is, for example, wall acid.

接著於在基底1 0 0上形成閘間介電層1 1 4，以覆蓋檔體層（浮置閘極）1 0 4 b的上表面與側壁。閘間介電層1 1 4之材質包括氧化矽/氮化矽/氧化矽（〇 NO )。閘間介電層1 1 4之形成方法例如是先以熱氧化法形成一層氧化層後，再以低壓化學氣相沈積法形成氮化矽層與另一層氧化層。當然，此閘間介電層1 1 4之材質也可以是氧化矽層或是氧化矽/氮化矽層等。之後，於閘間介電層1 1 4上形成導體層1 2 0以做為一控制閘極。此導體層1 2 0例如是由一層摻雜多晶矽層1 1 6與一層石夕化金屬層1 1 8共同組成的多晶石夕化物金屬（Ρ ο 1 y c i d e ) 層。摻雜多晶矽形成的方法例如是臨場（I η - s i t u ) 摻雜法。而石夕化金屬例如是以金屬氣化物與石夕曱烧為氣體源，形成的方法例如是低壓化學氣相沉積法。後續完成快閃記憶體之製程，為熟悉此項技術者所周知，在此不再贅述。An inter-gate dielectric layer 1 14 is then formed over the substrate 100 to cover the upper surface and sidewalls of the body layer (floating gate) 104b. The material of the inter-gate dielectric layer 1 14 includes yttria/tantalum nitride/yttria (〇NO). The inter-gate dielectric layer 141 is formed by, for example, forming an oxide layer by thermal oxidation, and then forming a tantalum nitride layer and another oxide layer by low pressure chemical vapor deposition. Of course, the material of the inter-gate dielectric layer 141 may also be a ruthenium oxide layer or a ruthenium oxide/ruthenium nitride layer. Thereafter, a conductor layer 120 is formed on the inter-gate dielectric layer 1 14 as a control gate. The conductor layer 120 is, for example, a polycrystalline lithiated metal (Ρ ο 1 y c i d e ) layer composed of a layer of a doped polysilicon layer 1 16 and a layer of a layer of a metallized layer 1 1 8 . The method of doping polysilicon is, for example, a presence (I η - s i t u ) doping method. The Shihua chemical metal is, for example, a metal gasification and a stone gas source, and is formed by a low pressure chemical vapor deposition method. Subsequent completion of the flash memory process is well known to those skilled in the art and will not be described here.

如上所述，本發明的特點在於藉由降低浮置閘極周圍之絕緣層的高度，使浮置閘極之部份側壁表面得以暴露出來，再將閘間介電層覆蓋在浮置閘所露出來的上表面及侧壁表面，以增加浮置閘極與控制閘極之間的重疊面積，進而提高元件的耦合率。而且，本發明是在不增加記憶胞單As described above, the present invention is characterized in that a part of the sidewall surface of the floating gate is exposed by lowering the height of the insulating layer around the floating gate, and the dielectric layer of the gate is covered in the floating gate. The exposed upper surface and sidewall surface are increased to increase the overlap area between the floating gate and the control gate, thereby increasing the coupling ratio of the components. Moreover, the present invention does not increase the memory cell list

9676twf.ptd 第11頁 1313043 五、發明說明（6) 位面積之情況下，就可以增加浮置閘極與控制閘極之間的重疊面積，而提高元件的耦合率，因此可以增加元件積集度。雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍内，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。9676twf.ptd Page 11 1313043 V. Description of the invention (6) In the case of the bit area, the overlap area between the floating gate and the control gate can be increased, and the coupling ratio of the components can be increased, so that the component accumulation can be increased. degree. While the present invention has been described above by way of a preferred embodiment, it is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

9676twf.ptd 第12頁 1313043 圖式簡單說明第1 A至第1 G圖係繪示本發明較佳實施例之一種快閃記憶體的製造流程上視圖；以及第2A至第2G圖是第1A至第1G圖之Ι-Γ線的剖面圖。圖式標示說明 · 100 :基底 1 0 2 :穿遂氧化層 102a 104 104a 10 6 10 6a 108 110 112 114 116 118 120 200 300 102b :圖案化穿遂氧化層導體層 •104b 罩幕層 > 1 06b9676twf.ptd Page 12 1313043 BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1G are diagrams showing a manufacturing process of a flash memory according to a preferred embodiment of the present invention; and FIGS. 2A to 2G are 1A. A cross-sectional view of the Ι-Γ line to the 1G map. DESCRIPTION OF SYMBOLS 100: Substrate 1 0 2 : Via oxide layer 102a 104 104a 10 6 10 6a 108 110 112 114 116 118 120 200 300 102b : Patterned through oxide layer conductor layer • 104b mask layer > 1 06b

圖案化導體層圖案化罩幕層圖案化光阻層埋入式汲極 112a '112b ：絕緣層閘間介電層摻雜多晶矽層石夕化金屬層多晶石夕化物金屬層條狀物浮置閘極結構Patterned conductor layer patterned mask layer patterned photoresist layer buried germanium 112a '112b: insulating layer gate dielectric layer doped polysilicon layer layered metal layer polycrystalline stone layered metal layer strip float Gate structure

9676twf.ptd 第13頁9676twf.ptd Page 13

Claims

1313043 六、申請專利範圍 1 . 於種快閃記憶體之製造方法，包括下列步驟基底上依序形成一穿隨介電層、導體層與一罩幕層；進行層與該導一圖案化製程，定義該穿隧介電層、該罩幕，以於該基底上形成一條狀物；子植入製程，於該條狀物之間的該基底中形成一埋入式沒極區；進行一第二圖案化製程，定義該條狀物，於該基底上形成一浮置閘極結構，其中該圖案化的導體層為一浮置閘極；於該層之表面部份側壁移除於該以及於該 2 如法，其中括：於該滿該浮置去除層，以暴進行一第體層一離閘極結構的周圍形成一絕緣層，且使該絕緣該浮置閘極之表面，以暴露出該浮置閘極之浮置低於表面；該罩幕層；浮置閘極的上表面與側壁上形成一閘間介電層1313043 6. Patent application scope 1. A method for manufacturing a flash memory, comprising: forming a pass-through dielectric layer, a conductor layer and a mask layer on a substrate; and performing a patterning process on the layer and the conductive layer Defining the tunneling dielectric layer, the mask to form a strip on the substrate; the sub-implant process, forming a buried-type non-polar region in the substrate between the strips; a second patterning process, defining the strip, forming a floating gate structure on the substrate, wherein the patterned conductor layer is a floating gate; and a sidewall portion of the surface of the layer is removed from the And the method of: wherein: the floating removal layer is formed to form an insulating layer around the gate structure, and the surface of the floating gate is insulated Exposing the floating gate to a lower surface than the surface; the mask layer; forming a gate dielectric layer on the upper surface and the sidewall of the floating gate

閘間申請於該基底閘極浮置露該介電層上形成一控制閘極。專利範圍第1項所述之快閃記憶體之製造方浮置閘極結構的周圍形成該絕緣層的步驟包上形成覆蓋該浮置閘極結構之上表面並且填結構的周圍之一絕緣材料層，閘極結構之上表面上所覆蓋的該絕緣材料罩幕層之表面；以及The gate application applies to form a control gate on the dielectric gate floating on the dielectric layer. The step of forming the insulating layer around the floating gate structure of the flash memory according to the first aspect of the patent includes forming an insulating material covering the upper surface of the floating gate structure and surrounding the filling structure. a layer, the surface of the insulating material cover layer covered on the upper surface of the gate structure;

9676t.wf.ptd 第14頁 1313043 々、申請專利範圍移除部分該絕緣材料層，使該絕緣材料層之表面介於該導體層的底表面與導體層頂表面之間，而形成該絕緣層。 3 .如申請專利範圍第2項所述之快閃記憶體之製造方法，其中該絕緣層之材質包括氧化矽、氮化矽、懸塗式玻璃其中之一。 4.如申請專利範圍第2項所述之快閃記憶體之製造方法，其中該絕緣層之形成方法包括高密度電漿化學氣相沈積法。9676t.wf.ptd Page 14 1313043 々, the patent application scope removes a portion of the insulating material layer such that the surface of the insulating material layer is interposed between the bottom surface of the conductor layer and the top surface of the conductor layer to form the insulating layer . 3. The method of manufacturing a flash memory according to claim 2, wherein the material of the insulating layer comprises one of yttrium oxide, tantalum nitride, and suspension coated glass. 4. The method of manufacturing a flash memory according to claim 2, wherein the method of forming the insulating layer comprises a high density plasma chemical vapor deposition method.

5 .如申請專利範圍第4項所述之快閃記憶體之製造方法，其中形成該絕緣層之反應氣體源包括四-乙基-鄰-矽酸酯及臭氧。 6. 如申請專利範圍第2項所述之快閃記憶體之製造方法，其中去除浮置閘極結構之上表面上所覆蓋的該絕緣材料層之方法為化學機械研磨法與回蝕刻法其中之一。 7. 如申請專利範圍第2項所述之快閃記憶體之製造方法，其中移除部分該絕緣材料層之方法包括回蝕刻法。 8. 如申請專利範圍第1項所述之快閃記憶體之製造方法，其中該罩幕層之材質包括氮化矽或氧化矽。5. The method of manufacturing a flash memory according to claim 4, wherein the source of the reaction gas forming the insulating layer comprises tetra-ethyl-o-phthalate and ozone. 6. The method of manufacturing a flash memory according to claim 2, wherein the method of removing the insulating material layer covered on the upper surface of the floating gate structure is a chemical mechanical polishing method and an etch back method. one. 7. The method of manufacturing a flash memory according to claim 2, wherein the method of removing a portion of the insulating material layer comprises an etch back method. 8. The method of manufacturing a flash memory according to claim 1, wherein the material of the mask layer comprises tantalum nitride or hafnium oxide.

9. 如申請專利範圍第8項所述之快閃記憶體之製造方法，其中移除該罩幕層之方法包括濕式钮刻法。 1 0 .如申請專利範圍第8項所述之快閃記憶體之製造方法，其中當該罩幕層之材質為氮化矽，則移除該罩幕層所用之蝕刻劑包括磷酸。9. The method of manufacturing a flash memory according to claim 8, wherein the method of removing the mask layer comprises a wet button engraving. The method of manufacturing a flash memory according to claim 8, wherein when the mask layer is made of tantalum nitride, the etchant used to remove the mask layer comprises phosphoric acid.

9676twf.ptd 第15頁 1313043 該浮置閘極之間的該基底中形成一埋入式汲極區；該浮置閘極結構周圍形成一絕緣層，該絕緣層之表該浮置閘之底表面與頂表面之間；該浮置閘極的上表面與側壁上形成一閘間介電層；該閘間介電層上形成一控制閘極。 .如申請專利範圍第1 1項所述之快閃記憶體之製造其中於該浮置閘極結構周圍形成該絕緣層的步驟包9676twf.ptd Page 15 1313043 A buried drain region is formed in the substrate between the floating gates; an insulating layer is formed around the floating gate structure, and the insulating layer is at the bottom of the floating gate Between the surface and the top surface; an upper inter-gate dielectric layer is formed on the upper surface and the sidewall of the floating gate; a control gate is formed on the inter-gate dielectric layer. The manufacture of a flash memory as described in claim 11 wherein the step of forming the insulating layer around the floating gate structure

該基底上形成覆蓋該浮置閘極結構之上表面並且填置閘極結構的周圍之一絕緣材料層；除浮置閘極結構之上表面上所覆蓋的該絕緣材料暴露該罩幕層之表面；以及除部分該絕緣材料層，使該絕緣材料層之表面介於層的底表面與導體層頂表面之間，而形成該絕緣 .如申請專利範圍第1 2項所述之快閃記憶體之製造其中該絕緣材料層之材質包括氧化矽。Forming an insulating material layer covering the upper surface of the floating gate structure and filling the periphery of the gate structure; the insulating material covered on the upper surface of the floating gate structure exposing the mask layer a surface; and a portion of the insulating material layer such that the surface of the insulating material layer is interposed between the bottom surface of the layer and the top surface of the conductor layer to form the insulation. The flash memory as described in claim 12 The material in which the insulating material layer is made includes cerium oxide.

.如申請專利範圍第1 3項所述之快問記憶體之製造其中於該絕緣材料層之形成方法包括高密度電漿化沈積法。 .如申請專利範圍第1 3項所述之快閃記憶體之製造The manufacture of the memory of the invention as described in claim 13 wherein the method of forming the layer of insulating material comprises a high density plasma deposition method. Manufacturing of flash memory as described in claim 13

9676twf.ptd 第16頁 1313043 六、申請專利範圍方法，其中形成該絕緣材料層之反應氣體源包括四-乙基鄰-矽酸酯及臭氧。 1 6 .如申請專利範圍第1 方法，其中去除浮置閘極結材料層之方法為化學機械研 1 7 .如申請專利範圍第1 方法，當去除浮置閘極結構料層之方法為化學機械研磨穿隧介電層、與浮置閘極之成一罩幕層並且在形成該閘該罩幕層之步驟，其中該罩者。 1 8 .如申請專利範圍第1 方法，其中移除該罩幕層之 1 9 .如申請專利範圍第1 方法，其中移除部分該絕緣 2項所述之快閃記憶體之製造構之上表面上所覆蓋的該絕緣磨法與回蝕刻法其中之一。 2項所述之快閃記憶體之製造之上表面上所覆蓋的該絕緣材法時，於該基底上依序形成該步驟更包括於該浮置閘極上形間介電層之步驟前更包括去除幕層之材質係與該絕緣層不同 7項所述之快閃記憶體之製造方法包括濕式#刻法。 2項所述之快閃記憶體之製造材料層之方法包括回蝕刻法。9676twf.ptd Page 16 1313043 VI. Patent Application The method wherein the source of the reaction gas forming the insulating material layer comprises tetra-ethyl ortho-phthalate and ozone. 1 6 . The method of claim 1 , wherein the method of removing the floating gate junction material layer is a chemical mechanical study. 17. The method of removing the floating gate structure layer is chemistry. Mechanically tunneling the dielectric layer, forming a mask layer with the floating gate and forming the gate layer in the step of forming the mask layer. 18. The method of claim 1, wherein the mask layer is removed. The method of claim 1 is the method of removing the portion of the flash memory described above. One of the insulating grinding and etchback methods covered on the surface. In the method of insulating material covered on the surface of the flash memory described in the above, the step of sequentially forming the step on the substrate further includes the step of forming the dielectric layer on the floating gate. The method for manufacturing a flash memory including the material for removing the curtain layer and the insulating layer includes the wet method. The method of fabricating a material layer of the flash memory described in the second aspect includes an etch back method.

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