TWI313043B - Method of fabricating flash memory - Google Patents
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- TWI313043B TWI313043B TW92119491A TW92119491A TWI313043B TW I313043 B TWI313043 B TW I313043B TW 92119491 A TW92119491 A TW 92119491A TW 92119491 A TW92119491 A TW 92119491A TW I313043 B TWI313043 B TW I313043B
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1313043 五、發明說明(1) 發明所屬之技術領域 本發明是有關於一種快閃記憶體的製造方法,特別是 有關於一種增加浮置閘極與控制閘極間的重疊(0 v e r 1 a p ) 面積之快閃記憶體的製造方法。 先前技術 快閃記憶體元件由於其優越的資料保存特性,所以已 成為個人電腦和電子設備所廣泛採用的一種記憶體元件。 典型的快閃記憶體元件,一般是被設計成具有堆疊式 閘極(Stack- Gate)結構,其中包括一穿隨氧化層,一用來 儲存電荷的多晶石夕浮置閘極(F 1 〇 a t i n g G a t e ),一氧化石夕/ 氮4匕石夕/氧4匕石夕(Oxide-Nitride — Oxide ,0N0)結構的介電 層,以及一用來控制資料存取的多晶石夕控制閘極(C ο n t r ο 1 Gate) ° 之 極 閘 制 控} 與R) 極GC 閘’ -ο 置i 浮a 常R 通ng • 1 -- 上up 作Co 操e-的at 體(G 憶率 記合 閃耦 快極 在閘 的 間 大 愈 效加带 與增控 度了與 速括極 作包閘 操,置 的法浮 體方低 憶的降 記率、 閃合積 快耦面 而極疊 ,閘重 低加的 愈增間 將。極 壓升間 電提制 作的控 工大與 之大極 需會閘 所就置 作率浮 制 控 與 極 閘 置 浮CO 加 C 增Γ1 及ct 以le 、e 度(D 厚數 的常 層電 電介 介的 之層 間電 極介 閘之BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a method of fabricating a flash memory, and more particularly to increasing overlap between a floating gate and a control gate (0 ver 1 ap ). A method of manufacturing a flash memory of an area. Prior Art Flash memory components have become a memory component widely used in personal computers and electronic devices due to their superior data retention characteristics. A typical flash memory component is generally designed to have a stacked gate-gate structure including a pass-through oxide layer and a polycrystalline litter floating gate for storing charge (F 1 〇 ating G ate ), a dielectric layer of Oxide-Nitride — Oxide (0N0) structure, and a polycrystalline stone for controlling data access. Control gate (C ο ntr ο 1 Gate) ° pole gate control} and R) pole GC gate ' -ο set i float a constant R pass ng • 1 -- up up Co run e-at body ( G Recalling the rate of flash-coupled fast-connecting poles between the gates, the more effective and the addition of the control and the speed-changing poles, the low-return rate of the floating body, the flash-collecting fast coupling The surface is extremely stacked, and the increase in the weight of the gate is increased. The control of the extreme pressure rise is very large, and the gate is required to be set as the float control and the pole gate floats CO plus C. And ct with the degree of le and e (the thickness of the D-thick layer of the inter-layer electrode
S k 等 加 增勢 於趨 助之 有度 ,集 積積 面高 疊求 重追 的續 間持 極路 閘電 制體 控積 與在 極是 閘但 置’ 浮率 加合 增耦 極 閘 須率 必合 而耦 因高 卻有 積具 面作 的製 佔 , 所下 胞積 憶面 記片 個晶 一的 每限 件有 元在 體何 憶如 記此 閃因 央 。 ,減 下縮S k, etc., increase in the degree of help, the accumulation of the stacking surface is high, and the continuation of the slab is the same as that of the slab. The rate must be combined and the coupling is high, but there is a system of production. The lower part of the cell memory and the memory of each piece of the crystal are in the body. Reduction
操 其 間 極 閘Operating the gate
9676t.wf · ptd 第7頁 1313043 五、發明說明(2) 的快閃記憶 發明内容 因此, 法,可以增 元件的耗合 根據上 製造方法, 與罩幕層。 於基底上形 入式〉及極區 基底上形成 穿隧介電層 圖案化的導 構的周圍形 頂表面,以 除圖案化罩 極所裸露的 介電層上形 本發明 閘極之部份 在浮置閘所 與控制閘極 為讓本 顯易懂,下 體是目前極為重要的課題。 本發明之 加浮置閘 率。 述與其它 此方法係 接著將穿 成條狀物 (Buried 浮置閘極 、圖案化 體層當作 成絕緣層 暴露出浮 幕層以暴 上表面與 成控制閘 係降低浮 側壁表面 露出來的 之間的重 發明之上 文特舉較 目的是 與控制 目的, 基底上 隧介電 ,然後 Drain) 結構, 的導體 元件之 ,絕緣 置閘極 露出浮 側壁上 極0 置閘極 得以暴 上表面 疊面積 述和其 佳實施 提供一種快閃記憶體的製造方 閘之間的重疊面積,進而提高 本發明 依序形 層、罩 於條狀 。接著 此浮置 層與圖 浮置閘 層之表 周圍侧 置閘極 形成閘 提出一 成穿隧 幕層與 物之間 再將條 閘極結 案化的 極。然 面低於 壁之部 的頂表 間介電 種快閃 介電層 導體層 的基底 狀物圖 構包括 罩幕層 後在浮 圖案化 份表面 面,再 層,然 記憶體的 、導體層 圖案化, 中形成埋 案化,於 圖案化的 。其中, 置閘極結 導體層之 。接著移 於浮置閘 後於閘間9676t.wf · ptd Page 7 1313043 V. Description of the invention (2) Flash memory SUMMARY OF THE INVENTION Therefore, the method can increase the component's consumption according to the manufacturing method, and the mask layer. Forming a peripheral shaped top surface of the patterned dielectric layer on the substrate and forming a portion of the gate of the present invention on the dielectric layer exposed by the patterned mask The floating gate and the control gate are extremely easy to understand, and the lower body is an extremely important subject at present. The floating gate ratio of the present invention. And other methods of this method are followed by stripping (Buried floating gate, patterned body layer as an insulating layer exposing the floating layer to expose the surface and forming a control gate to reduce the surface of the floating sidewall exposed The above special purpose of the invention is for the purpose of control, the tunneling dielectric on the substrate, and then the Drain) structure, the conductor element, the insulating gate exposes the pole on the floating sidewall, and the gate overlaps the surface area. The preferred embodiment provides a superimposed area between the manufacturing gates of the flash memory, thereby improving the sequential layering and masking of the present invention. Then, the floating layer forms a gate with the side gates around the surface of the floating gate layer, and a pole is formed between the tunneling layer and the object and then the gate is formed. The bottom surface of the dielectric layer of the flash dielectric layer of the dielectric layer is lower than the wall portion, and the base layer of the dielectric layer of the dielectric layer includes the mask layer and then the surface of the floating patterning layer, and then the layer of the memory and the conductor layer. Patterning, forming a buried pattern, in the patterning. Wherein, the gate is connected to the conductor layer. Then move to the floating gate and then to the gate
周圍之絕緣層的高度,使浮置 露出來,再將閘間介電層覆蓋 及側壁表面,以增加浮置閘極 ,進而提高元件的耦I合率。 他目的、特徵、和優點能更明 例,並配合所附圖式,作詳細The height of the surrounding insulating layer exposes the floating layer, and then the dielectric layer of the gate is covered and the sidewall surface is increased to increase the floating gate, thereby increasing the coupling ratio of the components. His purpose, characteristics, and advantages can be more clearly illustrated and detailed with the drawings.
9676twf.ptd 第8頁 1313043 五、發明說明(3) 說明如下: 實施方式 第1 A圖至第1 G圖係繪示本發明較佳實施例之一種快閃 記憶體的製造流程的上視圖。第2 A至第2 G圖為第1 A至第1 G 圖之I - Γ線的剖面圖。首先請同時參照第1 A圖及第2 A圖, 提供一基底1 0 0,此基底1 0 0例如是矽基底。然後,於此基 底100上依序形成穿隧介電層102、導體層104與罩幕層 1 ◦ 6。穿隧介電層1 0 2之材質例如是氧化矽,其厚度例如是 5 0埃至1 0 0埃左右。9676twf.ptd Page 8 1313043 V. DESCRIPTION OF THE INVENTION (3) Description is as follows: Embodiments FIGS. 1A to 1G are top views showing a manufacturing process of a flash memory according to a preferred embodiment of the present invention. Figures 2A through 2G are cross-sectional views of the I - Γ line of the first to the first G. First, please refer to FIG. 1A and FIG. 2A simultaneously, and provide a substrate 100, which is, for example, a germanium substrate. Then, the tunnel dielectric layer 102, the conductor layer 104, and the mask layer 1 ◦ 6 are sequentially formed on the substrate 100. The material of the tunneling dielectric layer 102 is, for example, yttrium oxide, and its thickness is, for example, about 50 angstroms to about 100 angstroms.
穿隧介電層1 0 2之形成方法例如是熱氧化法或是低壓 化學氣相沉積法(LPCVD )。導體層1 04之材質例如是摻雜 多晶矽,其形成的方法例如是低壓化學氣相沉積法,以矽 曱烷(S i 1 an e )為氣體源沉積一層多晶矽層後,然後再進行 摻質植入製程以形成之。其中,沈積製程之操作溫度為 575 °C至650 °C之間,操作壓力約在0.3torr至0.6torr 之間。 罩幕層1 0 6之材質例如是氮化矽或氧化矽,其形成的 方法例如是以低壓化學氣相沉積法,以二氯矽甲烷與氨氣 作為反應氣體源。 接著請同時參照第1 B圖及第2 B圖,於罩幕層1 0 6上形 成一圖案化的光阻層1 0 8。然後以光阻層1 0 8為罩幕,蝕刻 穿隧介電層102 '罩幕層106與導體層104,於基底100上形 成縱向排列的條狀物2 0 0 ,此條狀物2 0 0包括圖案化穿隧介 電層102a、圖案化導體層104a與圖案化罩幕層106a。然後 %The formation method of the tunneling dielectric layer 102 is, for example, thermal oxidation or low pressure chemical vapor deposition (LPCVD). The material of the conductor layer 104 is, for example, a doped polysilicon, which is formed by, for example, a low pressure chemical vapor deposition method, depositing a polycrystalline germanium layer with a gas source of silane (S i 1 an e ), and then performing doping. The process is implanted to form it. Among them, the deposition process operating temperature is between 575 ° C and 650 ° C, and the operating pressure is between 0.3 torr and 0.6 torr. The material of the mask layer 106 is, for example, tantalum nitride or tantalum oxide, which is formed by, for example, low pressure chemical vapor deposition using dichloromethane and ammonia as a source of a reaction gas. Next, referring to FIGS. 1B and 2B, a patterned photoresist layer 108 is formed on the mask layer 106. Then, the photoresist layer 102 is used as a mask to etch the tunneling dielectric layer 102' of the mask layer 106 and the conductor layer 104 to form a longitudinally arranged strip 20 0 on the substrate 100. 0 includes a patterned tunneling dielectric layer 102a, a patterned conductor layer 104a, and a patterned mask layer 106a. Then %
9676t.wf.ptd 第9頁 1313043 五、發明說明(4) 進行離子植入製程,於條狀物2 0 0之間的基底中形成埋入 式汲極區1 1 〇。 接著請同時參照第1 C圖及第2 C圖,移除上述之圖案化 光阻層1 〇 8。然後於圖案化的罩幕層1 0 6 a上形成另一圖案 化光阻層(未繪圖示)。接著以此圖案化光阻層為罩幕,再 钱刻條狀物2 0 0,於基底1 0 0上形成浮置閘極結構3 0 0。此 浮置閘極結構3 0 0包括圖案化的穿隧介電層1 〇 2 b、圖案化 的導體層104b與圖案化的罩幕層l〇6b。其中,圖案化導體 層1 0 4 b當作元件之浮置閘極。9676t.wf.ptd Page 9 1313043 V. INSTRUCTIONS (4) An ion implantation process is performed to form a buried bungee region 1 1 基底 in a substrate between strips 200. Next, please refer to FIG. 1C and FIG. 2C simultaneously to remove the above patterned photoresist layer 1 〇 8. Another patterned photoresist layer (not shown) is then formed over the patterned mask layer 10 6 a. Then, the photoresist layer is patterned as a mask, and then the strip is formed by the strip, and the floating gate structure 300 is formed on the substrate 100. The floating gate structure 300 includes a patterned tunneling dielectric layer 1 〇 2 b, a patterned conductor layer 104b and a patterned mask layer 16b. Among them, the patterned conductor layer 1 0 4 b is regarded as the floating gate of the element.
接著請同時參照第1 D圖與第2 D圖,在基底1 〇 〇上形成 絕緣層1 1 2,以覆蓋該浮置閘極結構3 0 0,並填入浮置閘極 結構3 0 0之間的間隙。絕緣層1 1 2的材質係與罩幕層1 〇 6 b之 材質不同者,例如是氧化矽、氮化矽或是旋塗式玻璃等。 其形成的方法例如是高密度電漿化學氣相沉積法 (H D P - C V D )或旋轉塗佈法。 接著請同時參照第1 Ε圖與第2 Ε圖,將罩幕層1 〇 6 b表面 上所覆蓋的絕緣層112去除,以暴露圖案化罩幕層i〇6b的 表面,留下位於浮置閘極結構3 0 0之間的材料層1 1 2 a。其 中,去除罩幕層1 〇 6 b表面上之絕緣層的方法例如是化學機 械研磨法(C Μ P )或回钱刻法。Next, referring to FIG. 1D and FIG. 2D, an insulating layer 1 1 2 is formed on the substrate 1 , to cover the floating gate structure 300 and fill the floating gate structure 3 0 0 The gap between them. The material of the insulating layer 1 1 2 is different from the material of the mask layer 1 〇 6 b , and is, for example, yttrium oxide, tantalum nitride or spin-on glass. The method of forming it is, for example, high density plasma chemical vapor deposition (H D P - C V D ) or spin coating. Then, referring to FIG. 1 and FIG. 2 simultaneously, the insulating layer 112 covered on the surface of the mask layer 1 〇 6 b is removed to expose the surface of the patterned mask layer i 〇 6b, leaving the floating layer The material layer 1 1 2 a between the gate structures 300. Among them, a method of removing the insulating layer on the surface of the mask layer 1 〇 6 b is, for example, a chemical mechanical polishing method (C Μ P ) or a money cutting method.
接著請同時參照第1 F圖與第2 F圖,將部分的絕緣層 1 1 2 a去除,以使所留下之絕緣層1 1 2 b之表面低於導體層 (浮置閘極)1 04b之頂表面,以裸露出導體層(浮置閘 極)1 0 4 b之周圍部份側壁表面。移除部分絕緣層1 1 2 a之方Then, referring to FIG. 1F and FIG. 2F, part of the insulating layer 1 1 2 a is removed, so that the surface of the remaining insulating layer 1 1 2 b is lower than the conductor layer (floating gate) 1 The top surface of 04b exposes the sidewall surface of the surrounding portion of the conductor layer (floating gate) 104b. Remove part of the insulation layer 1 1 2 a
9676twf.ptd 第10頁 1313043 五、發明說明(5) 法例如是回餘刻法。 接著請同時參照第1 G圖與第2 G圖,移除罩幕層1 〇 6 b以 暴露出導體層l〇4b的上表面。移除圖案化罩幕層l〇6b的方 法例如濕式蝕刻法。當罩幕層1 〇 6 b之材質為氮化矽時’所 用的#刻劑例如是墙酸。9676twf.ptd Page 10 1313043 V. Description of invention (5) The method is, for example, a recapture method. Next, referring to FIGS. 1G and 2G, the mask layer 1 〇 6 b is removed to expose the upper surface of the conductor layer 10b. A method of removing the patterned mask layer 16b is, for example, a wet etching method. When the material of the mask layer 1 〇 6 b is tantalum nitride, the #-marking agent used is, for example, wall acid.
接著於在基底1 0 0上形成閘間介電層1 1 4,以覆蓋檔體 層(浮置閘極)1 0 4 b的上表面與側壁。閘間介電層1 1 4之材 質包括氧化矽/氮化矽/氧化矽(〇 NO )。閘間介電層1 1 4之 形成方法例如是先以熱氧化法形成一層氧化層後,再以低 壓化學氣相沈積法形成氮化矽層與另一層氧化層。當然, 此閘間介電層1 1 4之材質也可以是氧化矽層或是氧化矽/氮 化矽層等。 之後,於閘間介電層1 1 4上形成導體層1 2 0以做為一控 制閘極。此導體層1 2 0例如是由一層摻雜多晶矽層1 1 6與一 層石夕化金屬層1 1 8共同組成的多晶石夕化物金屬(Ρ ο 1 y c i d e ) 層。摻雜多晶矽形成的方法例如是臨場(I η - s i t u ) 摻雜 法。而石夕化金屬例如是以金屬氣化物與石夕曱烧為氣體源, 形成的方法例如是低壓化學氣相沉積法。後續完成快閃記 憶體之製程,為熟悉此項技術者所周知,在此不再贅述。An inter-gate dielectric layer 1 14 is then formed over the substrate 100 to cover the upper surface and sidewalls of the body layer (floating gate) 104b. The material of the inter-gate dielectric layer 1 14 includes yttria/tantalum nitride/yttria (〇NO). The inter-gate dielectric layer 141 is formed by, for example, forming an oxide layer by thermal oxidation, and then forming a tantalum nitride layer and another oxide layer by low pressure chemical vapor deposition. Of course, the material of the inter-gate dielectric layer 141 may also be a ruthenium oxide layer or a ruthenium oxide/ruthenium nitride layer. Thereafter, a conductor layer 120 is formed on the inter-gate dielectric layer 1 14 as a control gate. The conductor layer 120 is, for example, a polycrystalline lithiated metal (Ρ ο 1 y c i d e ) layer composed of a layer of a doped polysilicon layer 1 16 and a layer of a layer of a metallized layer 1 1 8 . The method of doping polysilicon is, for example, a presence (I η - s i t u ) doping method. The Shihua chemical metal is, for example, a metal gasification and a stone gas source, and is formed by a low pressure chemical vapor deposition method. Subsequent completion of the flash memory process is well known to those skilled in the art and will not be described here.
如上所述,本發明的特點在於藉由降低浮置閘極周圍 之絕緣層的高度,使浮置閘極之部份側壁表面得以暴露出 來,再將閘間介電層覆蓋在浮置閘所露出來的上表面及侧 壁表面,以增加浮置閘極與控制閘極之間的重疊面積,進 而提高元件的耦合率。而且,本發明是在不增加記憶胞單As described above, the present invention is characterized in that a part of the sidewall surface of the floating gate is exposed by lowering the height of the insulating layer around the floating gate, and the dielectric layer of the gate is covered in the floating gate. The exposed upper surface and sidewall surface are increased to increase the overlap area between the floating gate and the control gate, thereby increasing the coupling ratio of the components. Moreover, the present invention does not increase the memory cell list
9676twf.ptd 第11頁 1313043 五、發明說明(6) 位面積之情況下,就可以增加浮置閘極與控制閘極之間的 重疊面積,而提高元件的耦合率,因此可以增加元件積集 度。 雖然本發明已以較佳實施例揭露如上,然其並非用以 限定本發明,任何熟習此技藝者,在不脫離本發明之精神 和範圍内,當可作各種之更動與潤飾,因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。9676twf.ptd Page 11 1313043 V. Description of the invention (6) In the case of the bit area, the overlap area between the floating gate and the control gate can be increased, and the coupling ratio of the components can be increased, so that the component accumulation can be increased. degree. While the present invention has been described above by way of a preferred embodiment, it is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.
9676twf.ptd 第12頁 1313043 圖式簡單說明 第1 A至第1 G圖係繪示本發明較佳實施例之一種快閃記 憶體的製造流程上視圖;以及 第2A至第2G圖是第1A至第1G圖之Ι-Γ線的剖面圖。 圖式標示說明 · 100 :基底 1 0 2 :穿遂氧化層 102a 104 104a 10 6 10 6a 108 110 112 114 116 118 120 200 300 102b :圖案化穿遂氧化層 導體層 •104b 罩幕層 > 1 06b9676twf.ptd Page 12 1313043 BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1G are diagrams showing a manufacturing process of a flash memory according to a preferred embodiment of the present invention; and FIGS. 2A to 2G are 1A. A cross-sectional view of the Ι-Γ line to the 1G map. DESCRIPTION OF SYMBOLS 100: Substrate 1 0 2 : Via oxide layer 102a 104 104a 10 6 10 6a 108 110 112 114 116 118 120 200 300 102b : Patterned through oxide layer conductor layer • 104b mask layer > 1 06b
圖案化導體層 圖案化罩幕層 圖案化光阻層 埋入式汲極 112a '112b :絕緣層 閘間介電層 摻雜多晶矽層 石夕化金屬層 多晶石夕化物金屬層 條狀物 浮置閘極結構Patterned conductor layer patterned mask layer patterned photoresist layer buried germanium 112a '112b: insulating layer gate dielectric layer doped polysilicon layer layered metal layer polycrystalline stone layered metal layer strip float Gate structure
9676twf.ptd 第13頁9676twf.ptd Page 13
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TW92119491A TWI313043B (en) | 2003-07-17 | 2003-07-17 | Method of fabricating flash memory |
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