1234925 九、發明說明： 【發明所屬之技術領域】 本發明提供-翻換式電容電路，尤指—種使麟電壓控制振 盪為内的切換式電容電路，可絲減㈣脈綱效應，也因此可 乂抑制在頻率奴正階段以及頻率合成器鎖相階段時的電壓控制振 运為頻率飄移現象。 【先前技術】 電壓控制振盪器(voltage controlled oscillator，VCO)是一個常使 用於操線通§fl系統（wirelessc〇mmunicati〇nSyStems)中，執行頻 率合成（frequency synthesis)工作的元件。例如Wellan(i等人於美 國專利第6,226,506號的專利中所述，無線通訊系統通常需要在接 收路徑電路(receive path circuitry )以及傳送路徑電路（transmit path circuitry)上執行頻率合成的工作。 第1圖為習知技術一電壓控制振盪器10的示意圖。圖中用於 一頻率合成器（frequency synthesizer)的LC式電壓控制振盪器⑴ 包含有一共振腔（resonator)，基本的共振腔結構則包含有一電感 12，輕合於一弟一振盤郎點0SC一P與一弟^一振盈節點〇sc N之 間。一連續式(continuously)可變電容14以及複數個離散式 (discretely)可變電容16與電感12並聯。連續式可變電容14係用 1234925 ^一目標f容健行微_卫作（fine tuning),至於複數個離 放式可16則是用來進行粗調的工作（coarse tuning)。而電 也、私感本身所造成的電阻損失（resistive loss)貝由負電阻值產 生口口（negatlve resistance generat〇r) !⑽ 振盪。 、 一在/等離放式可變電容1δ中的每一個離散式可變電容皆構成 個切換式電容（switched„電路，每 =立的控制訊號(分別叫，N)二 24遠上:N，切換式電容電路2〇可以選擇性地讓一電容 ^ 連上（C_eCt〇rdiS_⑻麵控制顧器10的共 ^、些切換式電容電路料_路/斷路組合可以使此一 π 式共振腔具讀大的電容值變絲圍，因此即可 盪器10可振盪的頻率範圍。 a工x 第2圖為習知技術一切換式電容電路2Ga的示 一一 係耗合於第-振盪節點0.SCJJ以及—節點A之:二一电谷30 %可選擇性崎冑A㈣姐她 係受一控制訊號SW所控制。當開關元件32被導狀 電容3〇的電容值會被加到電壓控制振㊃^1〇把）’ 容值中。當職件32被斷路時（Gpen)r、= 腔之整體電 φ 振盪卽點0SC Ρ 1234925 看進去的電容值就變成電容30之電容值以及.開關元件32在斷路 片、、之可生電容值（Parasitic capacitance )的串聯組合（series combination) 〇 第3圖為習知技術一差動切換式電容電路2〇b的示意圖。由於 差動式的架構具有較好的共模雜訊抑制 (common-mode noise j ction)的此力，因此常被廣泛地使用在高速積體電路的環境 中。在差動切換式電容電路施中，一正端（p〇sitive恤）電容 4〇係轉合於第-振盛節點〇sc_p與一節點a之間。一正端開關 元件（switch element) 42可選擇性地讓節點a連上或不連上接地 點。一負端電容44係輕合於第二振蓋節點〇sc—N以及一節點b 之間。一負端開關元件46可選擇性地讓節點B連上或不連上接地 ”、’占k兩個開關凡件42、46皆受相同的控制訊號sw所控制。當 開關το件42、46被導通時’正端電容4〇與負端電容44之電容值 的串聯組合就會被加到電馳俯器ω的整體電容值。至於各 開關元件42、46 _路時，差動的輸人電容值即變成正端電: 4〇、負端餘44以及其他寄生電容之電顧㈣馳合。整 私電容值在所有的開關元件42、*皆被斷路時會低於所 關元件42、46被導通時的狀態。 幵 第4圖則為習知技術—第二差動切換式電容電路·的示意 1234925 B。弟二是動切換式電容電路2〇c除了包含有鱼第 電容電路2%相同的元件 /絲切換式 低於節點A蛊節點R q 開關元件48，用來降 • t 、、: B之間的開關導通電阻值（如_ switch isance)。故二個開關元皆円 所控制。冬mu 6 48自又相同的控制訊號sw 仏句田開關兀件42 電容44之〜a 破¥通日守’正端電容40與負端 雕# "的串聯組合就會被加到電壓控制振盈器1〇的整 =各值。至於當開關元件42、46、48被斷路時，差動的輸入電 谷值即變成正端電容抓負端電容私以及其他 二的«組合。整體的輸人電容值在所有的開關元件 白被辦路時會低於所有的開關元件C皆被導通時的狀態。 -不响使_是$ 2圖所示的單端式架構或是第3圖及第4圖所 不心動式架構’當切換式電容電路施、施或施被斷路時， 在即點A上（在第3圖及第4圖的差動式架構帽包括節點b) 會產生-瞬時階躍電壓_ (_entaiy她哪_ 。i 述的瞬時階躍賴魏會造成共振腔整體電容值產生不該有變 動’最後，亦造成了賴控制振盪器1G之解產生不該有的飄 移。由於在第2、3、4圖中的例子係使用了 NM〇s開關，因此瞬 時階躍電壓變動係為當開關元件32、42、46、48被斷路時產生的 電壓下降（voltage drop )。 1234925 以乐2圖所示的單端式架構為例，當開關元件32被斷路時， 帶電载子carriers)會被注入（injected)連接於開航件 32第纪與第一端之間的接面電容哪_咖）。帶電 栽子的注人即造成了節點A賴職壓變動。上述的效應即為所 謂的時脈饋通效應（elGek fee論。ugh e_，並且以控制訊號sw… 自開關兀件32的控制端（亦即M〇s電晶體的開極）饋通 (feedthrough)到開關元件32另外兩個端點上（亦即電晶 體的汲極與源極）的形式出現。當開關元件32被導通時，由於節 # 點A係相合於接魅’目此控觀號sw的綱不會造成任何影 響。然而’當開關元件32被斷路時，控制訊號sw的饋通會造成 · -階躍電壓’即節點A上產生的電壓下降。而由於節點A產生了 電壓下降的情形，由開關元件32汲極端的N+擴散子(N+diffusi〇n) 以及P型的基板（Ptypesubstrate)所形成的二極體在斷路狀態下 會有些許_偏壓（fo_d biased)並產絲漏電流〇eakage current)。當接面二極體的洩漏電流緩慢地對節點a進行充電，該 _ 節點電位會恢制接地點電位。於節點A產生的t壓降低以及恢 復的動作會改變電壓控制振盪器10共振腔的負載電容值〇〇ad capacitance)，也就造成了電壓控制振盪器1〇產生了不該存在的 頻率飄移（frequency drift )。 至於當第4圖所不的差動式切換式電容電路2〇c被斷路時，其 •10 1234925 於即A及即點B上亦會遇咖同的時脈綱效應的問題。正# 節點A會因為正端關林42树脈饋通效應以及中央開關元二 48的時脈饋通效應產生不該有的階躍電壓。相同的，負端節㈣ 亦會因為負·關元件46科_通效應以及中央_元件48 的時脈镇通效應產生不該有的階躍電壓。上述於節點A及節點B 產生的階躍電壓改變及恢復都纽變賴控制振盪器1()之共振 腔的電容值纟而造成控她B 1G之頻率產輯時的飄移狀 【發明内容】 因此本發明的目的之-，在於提供—種可以減低時脈饋通效庫 的切換式電容電路，萌決f知技術所面臨的問題。 、 依據本《日月之申明專利範圍’係揭露—種可減低時脈饋通效 應的切換式電容電路，包含有：—第—正端開關元件，用來依據 一产第-控制訊號，選擇性地讓—第一正端節點連上或不連上一第 亂』、中》亥第正^喊點係轉合於_正端電容；一第二正蠕 開關元件，用來依據-第二控制訊號，選擇性地讓該第一正端節 點連上或不連上-第二節點；—第三_元件，用來依據一第三 控制訊號’選擇性地讓該第三節點連上或不連上該第二節點’·以 及-序列控制器’搞合於該等開關元件，用來產生該第一控制訊 1234925 號’該第二控制訊號，以及該第三控制訊號。 卞依據本發明之又-㈣專利細，係揭露—種於斷路—切換式 電容電路時’用來減低時脈綱效應的方法，該方法包含有以; =驟··⑻使用—第—正端開關元件分斷―第—正端節點與—第三 ^點，（b)使用—第二正端關元件分斷該第—正端軌與一第二 =點；以及⑻使用-第三正端開關树分斷該第三節點與該第二 即點；其中該第-正端節點係耦合於一正端電容，且步驟⑼、⑷ 的執行順序係為可變的。 本發明的-個览點在於，藉由依照各開關元件的元件大小由大 至小斷路各_元件，勒換式f容電路可峨漸進式地斷路， 如此-來，脈饋通_以及發生於電壓控制 的頻率飄移即可因而被減小。 本發明的另—侧憂點則在於，藉由使用—第三_元件將最大 的開關元件獨立於—接地點或—電源供應節點，當最大的開關元 倾斷路n經最大的開關元件之賴電流會被輯住。上述 額外使用的_元件即可有效地將最大關關元件（具有最大的 賴電流）從—賊點或―電祕應節關対姐。因此於頻率 合成器處於鎖相時期時，共振腔中切換式電容電路的節點A上之 12 Ϊ234925 屯壓變化可以更小，故電壓控制振盪器⑺可更快地穩定於—穩態 頻率。 【實施方式】' 第5圖為本發明切換式電容電路第—實施例示意圖。第5圖中 的切換式電容電路2Gd包含有—電容5()，—第一開關元件52，一 第二開關元件54 ’-第三開_件％，以及—序列控制器 (sequence controller) 58。在這個實施例中，三個開關元件皆為 NMOS電晶體’第―關元件52其元件大小獻於第二開關元件 54，第二開關元件54係大於第三開關元件56。電容5G係輕合於 一第一振盈節點0SC_P以及一節點A之間。第一開關元件Μ用 來依據-第-控舰號SW卜選擇性地讓節點A連上或不連上節 點C。第二開關元件54用來依據—第二控制訊號挪，選擇性地 讓節點A連上或不連上一第二振盪節點〇sc—N，其中第二振盪節 點OSC—N係搞合至接地點。第三開關元件％用來依據一第三押 制訊號SW3，選擇性地讓節點c連上或不連上第二振盈^ 〇SC_N。序列控制器58則用來產生該第一控制訊號sw卜該第 二控制訊號SW2、以及該第三控制訊號SW3。除了可以如第$图 所示的架構實施以外，此處所使用的開關元件亦可以為+ 晶體’此時第m點OSC_N _合至1源供應節^ (VCC)。至於在使用PMOS電晶體的架構之下，則需要使用與 13 1234925 njvtos %晶體架構下反相的控制訊號。 第6圖為配合第5圖各個控制訊號相對於時間的變化圖6〇。為 了要使得切換式電容電路20d被漸進式地切換至一斷路狀態，序 列控制器58會讓開關元件52、54、56被依照元件大小順序，由 大至i ]依序被_路。由於第一開關元件52係大於其他兩個開關元 口此弟開關元件52會於時最先被斷路。由於第二開關元 件54大於第三開關元件56，因此第二開關元件54則於t2時被斷 籲 路。最後，於b時第三開關元件56才會被斷路。由於節點A上肇 因於日嫌饋通效應的電壓改變主要由.與汲極間之寄生電容值 和汲極與源極間之寄生電容值的比值所決定，#酿與汲極間之 私谷值越小日守，控制訊號從高轉低時由於饋通效應所產生的電壓 改文就會越小。本發明的優點就是因為上述原因，會因時脈饋通 效應產生較大賴下降的較大關元件52會最先被斷路。在第二 開關元件54 _路之前，節點a 一直都會輕合於接地點，因此由 修 第-開關70件52所造成的時脈饋通效應並不會有太大的影響。若 是將第二開關元件54作得非常的小，則當第二開關元件M從導 通狀態切換成為斷路__造成的時脈饋通效應就會小到可以 忽略不計。. 、 然而’當第二開關元件54被斷路時，節點A還是會因為時脈 14 1234925 饋通效應喊受·微的負賴下降（negativevdtage_)。由 ;頂元件52 54 56中有戌漏電流（減哪讓伽）通過，節 點A的電位最終會返_地點電位元件越大，茂漏電 流也就會越大，第三開關元件56社要功效就是要將第一開關元 件52 (最大的開關元件），與接地點間獨立開來，以延遲節點a 的電位返贿義電位。藉由在解合成_鎖相_ (phase lockmgperiod) A , f ^ a 位就可以保持於些微的負偏壓（但是電位緩·變化）更長的時 間。因此頻率合成器可以更快地鎖定電壓控制振盪器W的頻率。 第7圖為配合第5圖各個控制訊號相對於時間的變化圖％。為 了要使得切換式電容電路2Gd被漸進式地切換至—斷路狀態，序 列控制器58必須確保第-_元件52被於請最純斷路。第 二開關元# 54以及第三開關元件56制時於t2時被斷路。 第8圖為配合第5圖各個㈣訊號相對於時間的變化圖8〇。相 同的’為了要使得切換式電容電路观被漸進式地切換至一斷路 狀態，序列控制器58必須確保第一開關元件52於心時最先被斷 路。然而為了更進一步減小當節點A並沒有連接於触點時，由 第-開件52的、麟電流導致節點a電位快速變化，第三開關 元件56會於時被斷路，在第一開關元件&與接地點分斷 15 1234925 (disconnect)以後，第二開關元件54才於t3時被斷路。 第9圖為本發明切換式電容電路第二實施例示意圖。第9圖中 的切換式電容電路20e包含有與前述第一實施例中切換式電容電 · 路20d大致上相同的組成元件，且另外包含有一低通濾波器9〇， ' 用來漸進式地斷路第二開關元件54以及第三開關元件56。此時第 一開關元件52係受第一控制訊號SW1所控制，第二開關元件54 與第三開關元件56則同時受到低通濾波器90所輸出的訊號 鲁 (SAV2〜filter)所控制’其中SW2—filter係為第二控制訊號SW2 經過低通濾波後的信號。另外，在第5圖之中，低通濾波器亦可 以被分別加在第二控制訊號SW2以及第三控制訊號SW3的後方。 第10圖為配合第9圖各個控制訊號相對於時間的變化圖1〇〇。 為了要使得切換式電容電路2〇e被漸進式地切換至一斷路狀態， 序列控制器58必須讓第一開關元件52於ti時最先被斷路。低通 φ 濾波為5>0可以使得SW2—fllter(即用來控制第二開關元件％與第 三開關元件56的訊號）漸進式地從-高邏輯值（logichigh)轉變 成一低邏輯值（logic l〇w)，故可減少於節點A產生的階躍電壓變 動（讀age卿change)。由於第二開關元件54係被漸進式地斷 · 路’、節點A也會被漸進式地自接地點分斷開來。於第二開關元件 · Μ被漸進式地斷路時，在一段延遲時間中，開關元件％中依舊會 16 1234925 存在有連接至接地歸導通路徑（祕徑的電阻值會隨著時間增 加漸漸變大），故時脈饋通效應可因而減輕。她於習吨術，^ 發明在斷路狀態時，„元件54汲極端卿成的寄生二極體 (parasitic diode)的順偏壓會被減低至最小。於每一個時間點上 的時脈饋通效應都會因崎得更低。如第9騎示，第三開關元 件56亦文到低通滤波器90的輸出訊號所控制（即SW2—驗）， 以減低發生於第三«元件本身㈣_通效應。此和第三開 關元件56亦可以直接受第二控制訊號_所控制，而不使舰 過低通濾波後的控制訊號。 第11圖為本發明切換式電容電路第三實施例示意圖。第^圖 中的切換式電容電路20f包含有—正端電容11〇，一負端電容112, -第-正端開關元件114 ’ —第—負端開關元件ιΐ6，—第二正端 開關元件m ’ -第二負端開關树12G，—第三開關元件122， 一中央_元件126，以及-序制器124。在此—實施例中的 開關元件皆為NM0S電晶體，而第—正端開關元件ιΐ4與第一負 端開關元件116實質上具有相_树大小，且皆大於第二正端 開關兀件118與第—貞端開關讀丨取這兩個開關元件實質上亦 -有相同的TL件大小）。另外，第三開關元件⑵實質上具有與第 而開關兀件118以及第二負端開關元件—相同的元件大 小。而中央開關祕126則大於第—正端_元件114與第一負 1234925 端開關元件Γ16。正端電容11G餘合於—第—振盪節點〇父p 與一節點A之間。負端電容112則係耦合於—第二振盈節點 OSC—N與-節點b之間。中央開關元件126用來依據一中央控制 訊號SW—center，選擇性地讓節點a連上或不連上節點b。第一 正端開關元件114用來依據-第一控制訊號sw卜選擇性地 點A連上或不連上節點c。第一負端開關元件ιΐ6用來依據第一 控制訊號sw卜選擇性地讓節點B連上或不連上節點c。第二正 端開關元件118用來依據第二控制訊號SW2，選擇性地讓節點a ^ 連上或不連上接地點，而第二負·關元件12G _來依據第二 控制訊號SW2，選擇性地讓_ B連上或不連上接地點。第三開 · 關7L件122用來依據-第三控制訊號SW3，選擇性地讓節點c連 上或不連上接地點。最後，序列控制器124 _來產生該第一、 第二、第三控制訊號SW1、SW2、SW3以及中央控制訊號 SW center ° 第12圖為配合第11圖各個控制訊號相對於時間的變化圖 128。為了要使得切換式電容電路憲被漸進式地切換至一斷路狀 態’序列控制器124必須使得中央開關元件126於心時最先被斷 路。接下來是第-正端開關元件114以及第—負端開關元件Μ 於t2時被斷路。為了更進—步的防止當節點a、B與接地點分斷 (disconnect)時’由於第一正端開關元件114以及第一負端開關 18 1234925 元件116中洩漏電流的導通而導致負載電容產生變化，因此第三 開關元件122會於t3時被斷路。於·第一正端開關元件114與第_ 負端開關耕116被第三關元件122從接地點分斷之後，第二 正端開關it件118與第二負端開關耕12〇則於㈣被斷路。雖 然第11圖中包含有中央開關元件126，且序列控制器124會產生 中央控制訊號SW—center，實際***開關元件丨26•是一個可選擇 f生加入或不加入的元件，加入此一元件的主要目的是用來降低整 體的開關導it電阻值（tum_Gnswitehfesistanee)。若不加入中央開 關元件126,則切換式電容電路撕本身即為本發明差動切換式電 容電路的另一實施例。 另外，斷路第二與第三正端/負端開關元件的時間點b與U可以 有二種不同的組合。也就是說，時間點〖3可以與h同時、或是b 湏先甚至疋b落後u。對於每一種不同的組合，低通遽波器都 可以分別加入於控制訊號SW2、SW3的後方，以降低各個相對應 開關所造成的時脈饋通效應。 第13圖為本發明切換式電容電路第四實施例示意圖。第圖 中的切換式電容電路2〇g包含有一正端電容⑽，一負端電容 132 ’ 一第一正端開關元件134，—第一負端開關元件，一第 -正端開關το件138，-第二負端開關元件14〇，—第三開關元件 19 1234925 142 、“7^件146 ’―低通濾波ϋ 148，以及一序列控制 益144。在此一實施例中的開關元件皆為PMOS電晶體，第-正 端開關元件m與第-負端難件m實質上具有相同的元件 ，小，亚且皆大於第二正端開關树138與第二負端開關元細 (這兩個開關元件實質上亦具有相同的元件大小）。另外，第三開 ^件142與第二正端開關元件138以及第二負端開關元件⑽ μ貝上亦具有相_元件大小。种央_元件1則大於第一 正端開關元件134與第一負端開關元件136。序列控制器144用 來纽-中央控制訊號SW_ce咖，一第一控制訊號綱，以及 -弟二控制訊號SW2。第二控制訊號連接至低通濾波器⑽的一 輸入端，低通濾、波器148的輸出端則輸出第二控做號眼經過 低通濾、波後的形式，即SW2—flIter。正端電容13〇轉合於一第一振 盧節點OSC—P及一節點A之間。負端電容132輕合於一第二振 盧即點〇SC—N與—節點B之間。中央開槪件146用來依據一 中央控制訊號sw—center，選擇性地讓節點A連上或不連上節點 B。第-正端開關元件134用來依據—第一控制訊號剛，選擇 性地讓節點A連上.或不連上節點c。第一負端開關元件⑽用來 依據第-控制訊號SW1，選擇性地讓節點β連上或不連上節點& 第二正端_元件138絲依據控制職SW—fito，選擇性地讓 節點A連上或不連上一電源供應節點vcc，第二負端開闕元件刚 用來依據控制訊號SWjter，選擇性地讓節點b連上或不連上電 20 1234925 源供應即點vcc。第三開關元件142則絲域控制訊號 SWjito ’選擇性地讓節點c連上或不連上電源供應節點。 士同第11圖使用N]y[〇S的架構’第13圖中的序列控制器可 以產生多個控制職’用來控制巾央關元件146、第—正端/負 ^開關元件’第二正端/負端開關元件，以及第三開關元件。第二 正端/負端開關元件以及第三開關元件使甩的控制訊號可以如先前 所述有多種不同的組合’並且第13圖的架構下亦可以分別於相關 的控制職前加上低職波H，崎—步降低時脈饋通效應。 第Η圖為配合第13圖各個控制訊號相對於時間的變化圖 〇為了要使得七刀換式電谷電路2〇g被漸進式地切換至一斷路狀 態，序列控制器144必須確保中央開關元件146;^時最先被斷 路。接下來是第-正端關元件134以及第—負端_元件136 於t2時被斷路。為了更進-步的防止當節點A與節點B與節點 VCC分斷時’由於第—正端開關元件134以及第—負端開關元件 136中制電流的導通而導致負載電容產生變化，因此第三開關元 件142、第二正端開關元件138、以及第二負端開關元件刚會在 控制訊號SW2Jto雜制下於t3 _斷路。請注意，雖然第13 圖中包含有中央剩元件146 ,且相控制器144會產生中央控 制訊號sw_center ’實際***開關元件146是一個可選擇性加入 1234925 或不加人的元件，加人此—元件社要目的是时降健體的開 關導通電阻值。若不包含有中央_元件146，_換式電容電路 2〇g本身即為本發明差動切換式電容電路的另—實施例。 相較於習糾支術，本發明可漸進式地將—切換式電容電路切換 至一斷路狀態，因此電壓控制紐器财的時脈饋通效庫（合導 致不理想頻率飄移）可被適當地減低。當進行斷路動作時^知 技術的作法會受_脈饋通效應的影響，而於賴控制振盈器⑺ resonator ^ t .. intemal 產生-階躍電動。上述的階躍電壓變動會造成—處於斷路狀 恶的開關元件汲極端所形成的接面二極體被麵的順偏壓，直到 下IV的$_賴電流充電而回到接地點或電源供應電位為止。 依據本U的架構’發生於該内部電容性節點的階躍電壓變動會 n if進仃斷軸辦，本發明的雜可以減低電壓控制振 =:振腔的瞬時電容值改變，因此可降低電壓控制咖1〇 之頻率瞬時飄移。糾，流經最大關關元件的喊電流會被另 二=^開關树所阻擔。上述較小的開關元件即可有效的 ==3(具有最大的'漏電流）從—接地點或-電源供應 〜因此可以在頻率合成器於鎖相期間，維持此振肿 中切換式電容電路内的電容性節點緩慢的電壓變化電： 制減器H)能更為快速達到頻率的鎖定。 吏传电弘 22 1234925 以上所述僅絲發明讀佳實關’凡依本發”請專利範圍 所做之均等變化與修飾，皆應屬本發明專利之涵蓋範圍。 【圖式簡單説明】 第1圖為習知技術一電壓控制振盪器的示意圖。 第2圖為習知技術一切換式電容電路的示意圖。 第3圖為習知技術一差動切換式電容電路的示意圖。 第4圖為習知技術-第二差動切換式電容電路的示意圖。 第5圖為本發明切換式電容電路第一實施例示意圖。 第6圖為配合第5圖各個控制訊號相對於時間的變化圖。 第7圖為配合第5圖各個控制訊號相對於時間的變化圖。 第8圖為配合第5圖各個控制訊號相對於時間的變化圖。 第9圖為本發明切換式電容電路第二實施例示意圖。 第10圖為配合第9圖各個控制訊號相對於時間的變化圖。 第11圖為本發明切換式電容電路第三實施例示意圖。 第12圖為配合第π圖各個控制訊號相對於時間的變化圖。 第I3圖為本㈣城式電容電路第四實補示意圖。 第14圖為配合帛13圖各個控制訊號相對於時間的變化圖。 23 1234925 【主要元件符號說明】 10 電壓控制振盪器 12 電感 14 可變電容 16 離散式可變電容 18 負電阻值產生器 20、20a、20b、20c、20d、20e、 切換式電容電路 20f、20g 24、30、40、44、50 電容 32、52、54、56、122、142 開關元件 40、110、130 正端電容 42、114、118、134、138 正端開關元件 44、112、132 負端電容 46、116、120、136、140 負端開關元件 48、126、146 中央開關元件 90、148 低通滤波器 58、124、144 序列控制器1234925 IX. Description of the invention: [Technical field to which the invention belongs] The present invention provides a switchable capacitor circuit, in particular a switched capacitor circuit that allows the voltage control to oscillate within the Lin voltage, which can reduce the effect of the pulsating ganglia. It can suppress the frequency drift phenomenon during the voltage slave positive phase and the frequency synthesizer phase lock phase. [Prior art] A voltage controlled oscillator (VCO) is a component that is often used in a wireless communication system (wirelesscommunicationSyStems) to perform frequency synthesis. For example, as described by Wellan et al. In US Patent No. 6,226,506, wireless communication systems usually need to perform frequency synthesis on receive path circuitry and transmit path circuitry. Part 1 The figure is a schematic diagram of a voltage-controlled oscillator 10 of the conventional technology. The LC-type voltage-controlled oscillator for a frequency synthesizer in the figure includes a resonator, and the basic structure of the resonator includes a resonator. The inductance 12 is lightly connected between a younger one, a panlang point 0SC, a P, and a younger one ^ a vibrating node 0sc N. A continuously variable capacitor 14 and a plurality of discretely variable The capacitor 16 is connected in parallel with the inductor 12. The continuous variable capacitor 14 uses 1234925 ^ a target f Rong Jian micro tuning (fine tuning), as for the multiple release type 16 is used for coarse tuning (coarse tuning). The resistance loss caused by electricity and private sense itself is caused by the negative resistance value negatlve resistance generatr! ⑽ Oscillation. Each of the discrete variable capacitors in the variable variable capacitor 1δ constitutes a switched capacitor (switched circuit, each = a control signal (respectively, N)) 24 distant: N, switched capacitor circuit 2 A capacitor ^ can be selectively connected (C_eCt〇rdiS_⑻ face control GU 10 common, some switching capacitor circuit material _ circuit / open circuit combination can make this π-type resonant cavity with a large capacitance value into the wire Range, so it can oscillate the frequency range of the oscillating device 10. Fig. 2 is a diagram showing the switching capacitor circuit 2Ga of the conventional technology, which is consumed at the -oscillation node 0.SCJJ and -node A. : Electronic Valley 30% optional rugged A 胄 sister. She is controlled by a control signal SW. When the switching element 32 is guided by the capacitor 30, the capacitance value will be added to the voltage control oscillator (^ 10). 'Capacitance value. When the job 32 is open (Gpen) r, = the overall electric cavity of the cavity φ oscillation point 0SC Ρ 1234925 The capacitance value seen will become the capacitance value of the capacitor 30 and the switching element 32 in the circuit breaker, 、 Series combination of parasitic capacitance 〇 第 3 The figure is a schematic diagram of a differential switching capacitor circuit 20b of the conventional technology. Because the differential architecture has this force of better common-mode noise suppression, it is often widely used. Used in the environment of high-speed integrated circuits. In the differential switching capacitor circuit, a positive-side (positive) capacitor 40 is turned between the -zhensheng node osc_p and a node a. A positive-side switch element 42 can selectively connect node a to or from ground. A negative terminal capacitor 44 is lightly connected between the second cover node osc-N and a node b. A negative-side switching element 46 can selectively connect or not connect node B to ground. ”And“ accounting for the two switches 42 and 46 are controlled by the same control signal sw. When the switches το and 42, 46 When turned on, the series combination of the capacitance of the positive terminal capacitor 40 and the negative terminal capacitor 44 will be added to the overall capacitance of the galvanometer ω. As for the switching elements 42, 46, the differential output The value of the human capacitor becomes the positive terminal: 40%, the negative terminal 44, and other parasitic capacitors. The entire private capacitor value will be lower than the closed component 42 when all the switching elements 42 and * are disconnected. , 46 when they are turned on. 幵 Figure 4 is a schematic diagram of the conventional technology-the second differential switching capacitor circuit 1234925 B. The second is the dynamic switching capacitor circuit 20c in addition to the fish capacitor circuit 2% of the same element / wire switching type is lower than node A 蛊 node R q switching element 48, which is used to reduce the switch on resistance value (such as _ switch isance) between t and t. Therefore, the two switching elements All are controlled by Dong Mu 6 48. The same control signal sw haikuta switchgear 42 capacitor 44 ~ a broken The series combination of the positive terminal capacitor 40 and the negative terminal capacitor 40 will be added to the whole value of the voltage-controlled oscillator 10. As for the switching elements 42, 46, and 48, when they are disconnected, The differential input power valley value becomes the positive terminal capacitance, the negative terminal capacitance, and the other two «combinations. The overall input capacitance value will be lower than that of all the switching elements C when all the switching elements are handled. The state at the time of conduction.-Not ringing is a single-ended structure shown in Figure 2 or a non-hearted structure shown in Figures 3 and 4. 'When the switched capacitor circuit is applied, applied, or applied is disconnected, At point A (the differential architecture caps in Figures 3 and 4 include node b) will produce-instantaneous step voltage _ (_entaiy her_). The instantaneous step described by Lai Wei will cause the entire cavity Capacitance value should not be changed 'Finally, it also caused undesired drift due to the solution of 1G controlled oscillator. Because the examples in Figures 2, 3 and 4 use NMOS switches, the instantaneous order The jump voltage variation is a voltage drop generated when the switching elements 32, 42, 46, 48 are disconnected. 1234925 Take the single-ended structure shown in Figure 2 as an example. When the switching element 32 is disconnected, the charged carriers are injected into the junction between the first part and the first part of the sailing part 32. Capacitance_ca.) The injection of a charged plant causes a change in the working pressure of node A. The above-mentioned effect is the so-called clock feedthrough effect (elGek fee theory. Ugh e_), and the control signal sw ... self-switching The control terminal of the element 32 (ie, the open electrode of the Mos transistor) is fed through to the other two terminals of the switching element 32 (ie, the drain and source of the transistor). When the switching element 32 is turned on, since the node # point A is in line with the connection mode, this control concept sw will not cause any effect. However, when the switching element 32 is disconnected, the feed-through of the control signal sw causes a step voltage, that is, a voltage drop at the node A. Due to the voltage drop at node A, the diode formed by the N + diffuser (N + diffusion) and P-type substrate (Ptype substrate) of the switching element 32 will be slightly broken in the open state. It is biased (fo_d biased) and produces a silk leakage current (oakage current). When the leakage current of the junction diode slowly charges the node a, the potential of the _ node will restore the potential of the ground point. The reduction in t voltage generated at node A and the recovery action will change the load capacitance of the voltage-controlled oscillator 10's resonant cavity (00 ad capacitance), which also causes the voltage-controlled oscillator 10 to generate an undesired frequency shift ( frequency drift). As for the differential switched capacitor circuit 20c shown in Figure 4, when it is disconnected, it will also encounter the same clock-gang effect on both A and B. The positive # node A will generate an undesired step voltage due to the positive-going Guanlin 42 tree-feedthrough effect and the central switch element 48's clock-feedthrough effect. Similarly, the negative terminal node 端 will also generate an undesired step voltage due to the negative-pass element 46 pass effect and the central_element 48 clock-pass effect. The above-mentioned step voltage change and recovery at node A and node B both depend on the capacitance value of the resonant cavity of the control oscillator 1 (), which causes the drift of the frequency of her B 1G control [Content of the invention] Therefore, an object of the present invention is to provide a switched capacitor circuit capable of reducing a clock feedthrough effect library, so as to determine the problems faced by the known technology. According to this "Sun and Moon's Declaration of Patent Scope" is disclosed-a switched capacitor circuit that can reduce the effect of clock feedthrough, including:-the first-positive terminal switching element, used to select according to the first-control signal The first positive terminal node is connected or not connected to the first chaos. The middle and high-frequency points are connected to the positive terminal capacitor; a second positive creeping switching element is used to Two control signals to selectively connect or disconnect the first positive node-the second node;-a third element, which is used to selectively connect the third node according to a third control signal ' Or not connected to the second node and the sequence controller are coupled to the switching elements to generate the first control signal No. 1234925, the second control signal, and the third control signal.卞 According to the invention of this invention- 细 Patent is disclosed, which is a method for reducing the clock effect when a capacitor circuit is switched-off, and the method includes: End switching element breaks off-the first positive end node and the third point, (b) using-the second positive end closing element breaks the first positive end rail and a second = point; and ⑻ use-the third The positive-end switch tree disconnects the third node from the second node; wherein the -positive-end node is coupled to a positive-end capacitor, and the execution order of steps ⑼ and ⑷ is variable. A glance point of the present invention is that, by switching off each element from large to small according to the element size of each switching element, the swap-type f-capacitor circuit can be progressively disconnected. Frequency drift due to voltage control can thus be reduced. Another aspect of the present invention is that by using the third element, the largest switching element is independent of the ground point or the power supply node. When the largest switching element tilts off the circuit n, the largest switching element depends on it. The current will be trapped. The additional _ components mentioned above can effectively remove the largest off component (with the largest current) from the thief point or the electric secretary. Therefore, when the frequency synthesizer is in the phase-locked period, the voltage change at node A234925 of the switched capacitor circuit in the resonant cavity can be smaller, so the voltage-controlled oscillator 稳定 can stabilize at the steady-state frequency more quickly. [Embodiment] FIG. 5 is a schematic diagram of a first embodiment of a switched capacitor circuit according to the present invention. The switched capacitor circuit 2Gd in FIG. 5 includes a capacitor 5 (), a first switching element 52, a second switching element 54'-a third on-%, and a sequence controller 58. . In this embodiment, the three switching elements are all NMOS transistors' first-off elements 52, and their element sizes are dedicated to the second switching element 54, which is larger than the third switching element 56. The capacitor 5G is lightly connected between a first vibration surplus node 0SC_P and a node A. The first switching element M is used to selectively connect the node A with or without the node C in accordance with the No.-control ship SWB. The second switching element 54 is used to selectively connect the node A with or without a second oscillation node 0sc-N according to the second control signal. The second oscillation node OSC-N is connected to the connection. location. The third switching element% is used to selectively connect the node c with or without the second vibration signal ^ SC_N according to a third suppression signal SW3. The sequence controller 58 is used to generate the first control signal sw, the second control signal SW2, and the third control signal SW3. In addition to being implemented in the architecture shown in Fig. $, The switching element used here can also be a + crystal 'at this time the m-th point OSC_N _ is combined to 1 source supply node ^ (VCC). As for the structure using the PMOS transistor, it is necessary to use a control signal that is inverse to that of the 13 1234925 njvtos% crystal structure. Fig. 6 is a graph showing the change of each control signal with respect to time in accordance with Fig. 5; In order for the switched capacitor circuit 20d to be gradually switched to an open state, the sequence controller 58 causes the switching elements 52, 54, and 56 to be sequentially switched in accordance with the element size order, from as large as i]. Since the first switching element 52 is larger than the other two switching elements, the first switching element 52 will be disconnected first. Since the second switching element 54 is larger than the third switching element 56, the second switching element 54 is opened at t2. Finally, the third switching element 56 will be disconnected at b. Because the voltage change at node A caused by the Japanese feedthrough effect is mainly determined by the ratio of the parasitic capacitance between the drain and the drain and the parasitic capacitance between the drain and the source, The smaller the valley value is, the smaller the voltage will be due to the feedthrough effect when the control signal changes from high to low. The advantage of the present invention is that, for the reasons described above, the large closing element 52, which will cause a large drop due to the clock feedthrough effect, will be disconnected first. Before the second switching element 54_, the node a will always be lightly connected to the ground point, so the clock feed-through effect caused by the repair-switch 70-52 will not have much effect. If the second switching element 54 is made very small, the clock feedthrough effect caused when the second switching element M is switched from the on state to the open circuit __ will be negligible. . However, when the second switching element 54 is disconnected, the node A still suffers from negative feedback due to the clock 14 1234925 feedthrough effect (negativevdtage_). From the top element 52 54 56 there is a leakage current (which is reduced to let the gamma) pass, the potential of node A will eventually return _ the larger the potential element, the larger the leakage current, the third switching element 56 The effect is to separate the first switching element 52 (the largest switching element) from the ground point to delay the potential of node a to return the bridging potential. By synthesizing phase lock mgperiod A, f ^ a can be maintained at a slightly negative bias (but the potential slowly changes) for a longer time. Therefore, the frequency synthesizer can lock the frequency of the voltage controlled oscillator W faster. Fig. 7 is a graph showing the change of each control signal with respect to time in accordance with Fig. 5. In order for the switched capacitor circuit 2Gd to be gradually switched to an open state, the sequence controller 58 must ensure that the -th element 52 is disconnected in the purest manner. The second switching element # 54 and the third switching element 56 are opened at t2. Fig. 8 is a diagram showing the change of each signal with respect to time in accordance with Fig. 5; In the same way, in order for the switched capacitor circuit 28 to be gradually switched to an open state, the sequence controller 58 must ensure that the first switching element 52 is first opened when the core is open. However, in order to further reduce when the node A is not connected to the contact, the potential of the node a changes rapidly due to the current of the first-opening member 52, and the third switching element 56 will be disconnected at that time. & 15 1234925 (disconnect) from the ground point, the second switching element 54 was disconnected at t3. FIG. 9 is a schematic diagram of a second embodiment of a switched capacitor circuit according to the present invention. The switched-capacitor circuit 20e in FIG. 9 includes substantially the same constituent elements as the switched-capacitor circuit 20d in the first embodiment described above, and further includes a low-pass filter 90. The second switching element 54 and the third switching element 56 are disconnected. At this time, the first switching element 52 is controlled by the first control signal SW1, and the second switching element 54 and the third switching element 56 are simultaneously controlled by the signal output from the low-pass filter 90 (SAV2 ~ filter). SW2-filter is the signal after the low-pass filtering of the second control signal SW2. In addition, in Fig. 5, a low-pass filter may be added behind the second control signal SW2 and the third control signal SW3, respectively. Fig. 10 is a graph of the change of each control signal with respect to time in accordance with Fig. 9. In order for the switched capacitor circuit 20e to be gradually switched to an open state, the sequence controller 58 must first open the first switching element 52 at ti. Low-pass φ filtering of 5> 0 can make SW2-fllter (the signal used to control the second switching element% and the third switching element 56) gradually change from -high logic value (logichigh) to a low logic value (logic l0w), so it can reduce the step voltage change at node A (read age change). Since the second switching element 54 is progressively disconnected, the node A is also gradually disconnected from the ground point. When the second switching element · M is progressively disconnected, the switching element% will still be 16 in a delay time. 12 12 925 There is a conduction path connected to ground (the resistance value of the secret path will gradually increase with time) ), So the clock feedthrough effect can be reduced accordingly. She has learned that when the circuit is disconnected, the forward bias of the parasitic diode formed by the element 54 will be minimized. The clock feedthrough at each point in time The effect will be even lower because of the ruggedness. As shown in the ninth example, the third switching element 56 is also controlled by the output signal of the low-pass filter 90 (ie, SW2—check) to reduce the occurrence of the third «element itself ㈣_ This and the third switching element 56 can also be directly controlled by the second control signal _ without controlling the ship's low-pass filtered control signal. Figure 11 is a schematic diagram of a third embodiment of a switched capacitor circuit according to the present invention. The switched capacitor circuit 20f in the figure ^ includes-a positive terminal capacitor 110, a negative terminal capacitor 112,-a-positive terminal switching element 114 '-a-negative terminal switching element ιΐ6,-a second positive terminal switch Element m '-the second negative terminal switching tree 12G,-the third switching element 122, a central element 126, and-the sequencer 124. In this embodiment-the switching elements are NMOS transistors, and the first- The positive-side switching element ιΐ4 and the first negative-side switching element 116 substantially have _Tree size, and both are larger than the second positive-side switch element 118 and the first-side switch. Reading these two switching elements is also substantially the same TL element size. In addition, the third switching element ⑵ is substantially It has the same element size as the first switch element 118 and the second negative terminal switching element. The central switch 126 is larger than the first positive terminal element 114 and the first negative 1234925 switching element Γ16. The positive terminal capacitance is 11G and more It is connected between-the first oscillating node 〇 parent p and a node A. The negative terminal capacitor 112 is coupled between the-second oscillating node OSC-N and-node b. The central switching element 126 is used to The control signal SW_center selectively connects node a to or without node b. The first positive-side switching element 114 is used to selectively connect node A to node c or not according to the first control signal sw. The first negative-side switching element ιΐ6 is used to selectively connect node B to or from node c according to the first control signal sw. The second positive-side switching element 118 is used to selectively select the second control signal SW2 according to the second control signal SW2. Ground let node a ^ be connected or not connected to the ground point, and the second negative · Close element 12G _ to selectively connect _ B to ground or not to ground according to the second control signal SW2. The third on / off 7L element 122 is used to selectively-based on the third control signal SW3 The node c is connected or not connected to the ground point. Finally, the sequence controller 124 _ generates the first, second, and third control signals SW1, SW2, SW3, and the central control signal SW center ° Figure 12 shows the cooperation with the 11th Figure 128 shows the change of each control signal with respect to time. In order for the switched capacitor circuit to be gradually switched to an open state, the sequence controller 124 must first open the central switching element 126 when it is at the center. Next, the -positive terminal switching element 114 and the -negative terminal switching element M are disconnected at t2. In order to further advance-when the nodes a and B are disconnected from the ground, the load capacitance is generated due to the leakage current in the first positive switching element 114 and the first negative switching element 18 1234925 element 116. Changes, so the third switching element 122 is disconnected at t3. After the first positive-side switching element 114 and the _th negative-side switching element 116 are disconnected from the ground point by the third closing element 122, the second positive-side switching element 118 and the second negative-side switching element 120 are Being disconnected. Although the center switch element 126 is included in Figure 11 and the sequence controller 124 generates a central control signal SW-center, in fact, the center switch element is a component that can be added or not added. The main purpose of the component is to reduce the overall switch resistance (tum_Gnswitehfesistanee). If the central switching element 126 is not added, the switched capacitor circuit itself is another embodiment of the differential switched capacitor circuit of the present invention. In addition, the time points b and U when the second and third positive / negative switching elements are disconnected may have two different combinations. In other words, the time point [3] can be at the same time as h, or b 湏 first or even 疋 b lags u. For each different combination, a low-pass chirp can be added behind the control signals SW2 and SW3, respectively, to reduce the clock feedthrough effect caused by each corresponding switch. FIG. 13 is a schematic diagram of a fourth embodiment of a switched capacitor circuit according to the present invention. The switched capacitor circuit 20g in the figure includes a positive terminal capacitor ⑽, a negative terminal capacitor 132 ′, a first positive terminal switch element 134, a first negative terminal switch element, and a first-positive terminal switch το member 138. -The second negative terminal switching element 14o, the third switching element 19 1234925 142, "7 ^ 146 '-low-pass filter ϋ 148, and a sequence control benefit 144. The switching elements in this embodiment are all It is a PMOS transistor. The first positive switching element m and the second negative switching element m have substantially the same components. They are smaller and smaller than the second positive switching tree 138 and the second negative switching element (this The two switching elements also have substantially the same element size.) In addition, the third switching element 142 and the second positive-side switching element 138 and the second negative-side switching element ⑽ μ also have a phase element size. _Element 1 is larger than the first positive-side switching element 134 and the first negative-side switching element 136. The sequence controller 144 is used for the central control signal SW_ce, a first control signal outline, and a second control signal SW2. The second control signal is connected to an input terminal of the low-pass filter ⑽, The output of the pass filter and wave filter 148 outputs the second control horn to pass through the low-pass filter and wave after the form, namely SW2-flIter. The positive-end capacitor 130 is transferred to a first oscillator node OSC-P and Between a node A. The negative terminal capacitor 132 is lightly connected between a second oscillation point SCSC-N and -node B. The central opening member 146 is used to selectively select a central control signal sw_center. Let node A be connected or unconnected to node B. The first positive terminal switching element 134 is used to selectively connect node A according to the first control signal, or not connected to node c. The first negative terminal switch Element ⑽ is used to selectively connect node β with or without node according to the -control signal SW1. The second positive terminal_element 138 wire selectively connects node A with or Without being connected to a power supply node vcc, the second negative switching element was just used to selectively connect node b with or without power according to the control signal SWjter. 20 1234925 The source supply point is vcc. The third switching element 142 The silk domain control signal SWjito 'selectively connects node c with or without a power supply node. 士 同 第 11 Using N] y [0S 'architecture' The sequence controller in Figure 13 can generate multiple control positions 'to control the central gate element 146, the first-positive terminal / negative ^ switching element' the second positive terminal / negative Terminal switching element, and third switching element. The second positive / negative switching element and the third switching element allow the control signals of the dumping to be in different combinations as described above, and can also be separated in the structure of FIG. 13 Add the low-level wave H before the relevant control job, and Saki-step reduces the clock feedthrough effect. Figure 为 is the change of each control signal with time in conjunction with Figure 13. 为了 In order to make the seven-blade electric valley The circuit 20g is gradually switched to an open state, and the sequence controller 144 must ensure that the central switching element 146; Next is the -positive terminal element 134 and the -negative terminal element 136 are disconnected at t2. In order to further prevent the load capacitance from changing due to the conduction of the first positive switching element 134 and the negative negative switching element 136 when node A and node B are disconnected from node VCC, the first The three switching elements 142, the second positive-side switching element 138, and the second negative-side switching element will just open at t3_ under the control signal SW2Jto. Please note that although the central component 146 is included in the 13th figure, and the phase controller 144 will generate the central control signal sw_center 'In fact, the central switching element 146 is a component that can be optionally added to 1234925 or not added. —The main purpose of the component society is to reduce the on-resistance of the switch of the healthy body. If the central _component 146 is not included, the 20-g switching capacitor circuit itself is another embodiment of the differential switching capacitor circuit of the present invention. Compared with the rectification technique, the present invention can progressively switch the -switching capacitor circuit to an open state, so the clock feedthrough effect library of the voltage control device (which causes undesired frequency drift) can be appropriately Ground reduction. When the circuit-breaking action is performed, the method of knowing technology will be affected by the pulse feedthrough effect, and it depends on controlling the resonator ⑺ resonator ^ t .. intemal to generate-step electric. The above-mentioned step voltage change will cause the junction diode formed by the drain element of the switch-shaped evil element to be forward-biased by the surface until the $ _IV current of the next IV charges and returns to the ground point or power supply. To the potential. According to the structure of the U ', the step voltage change occurring at the internal capacitive node will be broken if the shaft is broken. The noise of the present invention can reduce the voltage control vibration =: the instantaneous capacitance value of the cavity changes, so the voltage can be reduced The instantaneous frequency shift of the control coffee 10 is controlled. Correction, the shout current flowing through the largest off element will be blocked by another = ^ switch tree. The above small switching elements can effectively == 3 (with the largest 'leakage current) from-the ground point or-the power supply ~ so the switching capacitor circuit can be maintained during the frequency synthesizer during phase lock The capacitive voltage within the capacitive node changes slowly: the subtractor H) can achieve frequency lock more quickly. Li Chuan Dianhong 22 1234925 The above-mentioned only silk inventions read Jiashiguan 'All equivalent changes and modifications made to the scope of patents requested by the patent' shall all fall within the scope of the invention patent. [Simplified description of the drawings] Section Fig. 1 is a schematic diagram of a conventional technology-voltage controlled oscillator. Fig. 2 is a schematic diagram of a conventional technology-switched capacitor circuit. Fig. 3 is a schematic diagram of a conventional technology-differential-switched capacitor circuit. Fig. 4 is Conventional technology-a schematic diagram of a second differential switching capacitor circuit. Fig. 5 is a schematic diagram of a first embodiment of a switched capacitor circuit according to the present invention. Fig. 6 is a graph showing the change of each control signal with respect to time in accordance with Fig. 5. Fig. 7 is a graph showing the variation of each control signal with respect to time in conjunction with Fig. 5. Fig. 8 is a graph showing the variation with time of each control signal in conjunction with Fig. 5. Fig. 9 is a schematic diagram of a second embodiment of a switched capacitor circuit according to the present invention. Fig. 10 is a diagram showing the change of each control signal with respect to time in accordance with Fig. 9. Fig. 11 is a schematic diagram of a third embodiment of the switched capacitor circuit according to the present invention. Fig. 12 is a phase corresponding to each control signal in Fig. Π. The time-dependent change diagram. Figure I3 is the fourth supplementary schematic diagram of the city-type capacitor circuit. Figure 14 is the change diagram of each control signal with time in conjunction with Figure 13. 23 1234925 [Description of the main component symbols] 10 Voltage Control oscillator 12 Inductor 14 Variable capacitor 16 Discrete variable capacitor 18 Negative resistance value generator 20, 20a, 20b, 20c, 20d, 20e, switched capacitor circuit 20f, 20g 24, 30, 40, 44, 50 capacitors 32, 52, 54, 56, 122, 142 Switching elements 40, 110, 130 Positive terminal capacitance 42, 114, 118, 134, 138 Positive switching element 44, 112, 132 Negative terminal capacitance 46, 116, 120, 136, 140 Negative-side switching elements 48, 126, 146 Central switching elements 90, 148 Low-pass filters 58, 124, 144 Sequence controllers