TWI226117B - Flip chip on chip package with improving bonding property of wire-connecting pads - Google Patents
Flip chip on chip package with improving bonding property of wire-connecting pads Download PDFInfo
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- TWI226117B TWI226117B TW092125823A TW92125823A TWI226117B TW I226117 B TWI226117 B TW I226117B TW 092125823 A TW092125823 A TW 092125823A TW 92125823 A TW92125823 A TW 92125823A TW I226117 B TWI226117 B TW I226117B
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- wafer
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- pads
- substrate
- flip
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- 239000000758 substrate Substances 0.000 claims abstract description 34
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 15
- 238000003466 welding Methods 0.000 claims abstract description 8
- 230000003064 anti-oxidating effect Effects 0.000 claims abstract description 7
- 230000003647 oxidation Effects 0.000 claims abstract description 5
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 5
- 235000012431 wafers Nutrition 0.000 claims description 66
- 229910000679 solder Inorganic materials 0.000 claims description 8
- 238000007789 sealing Methods 0.000 claims description 7
- 150000001875 compounds Chemical class 0.000 claims description 3
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical group [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 claims description 2
- 238000012858 packaging process Methods 0.000 claims 6
- 229910052782 aluminium Inorganic materials 0.000 claims 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims 2
- 230000004888 barrier function Effects 0.000 claims 1
- 239000000084 colloidal system Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 13
- 238000004806 packaging method and process Methods 0.000 description 12
- 238000005476 soldering Methods 0.000 description 6
- 239000010931 gold Substances 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- GLGNXYJARSMNGJ-VKTIVEEGSA-N (1s,2s,3r,4r)-3-[[5-chloro-2-[(1-ethyl-6-methoxy-2-oxo-4,5-dihydro-3h-1-benzazepin-7-yl)amino]pyrimidin-4-yl]amino]bicyclo[2.2.1]hept-5-ene-2-carboxamide Chemical compound CCN1C(=O)CCCC2=C(OC)C(NC=3N=C(C(=CN=3)Cl)N[C@H]3[C@H]([C@@]4([H])C[C@@]3(C=C4)[H])C(N)=O)=CC=C21 GLGNXYJARSMNGJ-VKTIVEEGSA-N 0.000 description 1
- 229940126062 Compound A Drugs 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000003963 antioxidant agent Substances 0.000 description 1
- 230000003078 antioxidant effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229940125758 compound 15 Drugs 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Wire Bonding (AREA)
Description
1226117 五、發明說明（1) :發明所屬之技術領域】 本發明係有關於霜S太a 關於一種增強銲線接墊：：：^技術’特別係有 【先前技術】 ^之覆⑽在晶片上封裝結構。 為了達到多晶片高密度封裝之半導體一 習知之覆晶在晶片上封裝結構係為在一基板， J substrate〕或一釘架〔lead卜繼〕上黏著—晶片， 或者以另一覆晶晶片覆晶接人i + 馇，#铕曰曰y + π 述晶片，因在覆晶接合 後该覆日日日日片之凸塊須經過一道回銲步驟，再進行後續 之打線連接、封模、沖切等工程，如我國專利公告第 459360號係亦已揭示有一種覆晶在晶片上封裝結^。 請參閱第1圖，一種習知之覆晶在晶片上封装結構1〇〇 係包含有一基板110、一第一晶片12〇、一第二晶片13〇、 複數個銲線140、封膠體15〇及複數個銲球16〇，該基板u〇 之上表面111係黏著有該第一晶片i 2 0，且在該第一晶片 120之主動面121係形成有複數個凸塊接墊丨22與複數個銲 線接墊1 2 3，該第二晶片1 3 0係覆晶接合在該第一晶片 1 2 0 ’該第二晶片1 3 0之主動面1 3 1上所形成之凸塊1 3 2係接 合在該第一晶片1 2 0之該些凸塊接墊1 2 2，在覆晶接合之 後，習知地需要對該些凸塊1 32加以回銲〔ref 1 owi ng〕， 因此需將組合有第一晶片120與第二晶片130之基板110放 置於一回銲爐以進行回銲步驟，然而因在回銲步驟之高溫 而使得該第一晶片1 2 0之銲線接墊1 2 3形成一氧化層，導致 在後續之打線步驟中，以打線形成之複數個銲線1 4 0不容
mui iirai 第7頁 1226117 五、發明說明（2) 易接合在該些銲線接墊1 2 3，即會有「假銲」現象，因該 氧化層形成於該些銲線接墊i 23而導致焊接不良狀況不易 被觀測到’若繼續形成封膠體丨5 〇於該基板丨丨〇上表面丨u 以及形成銲球160於該基板11〇之下表面112，其所製造的 覆晶在晶片上封裝結構1 0 0將具有相當高之不良率。 【發明内容】 本發明之主要目的係在於提供一種增強銲線接墊銲性 之覆晶在晶片上封裝結構，其一第一晶片上覆晶接合有一 第二晶片，而呈矽晶片在矽晶片上之疊晶結構 〔Chip-on-Chip stack〕，利用該第一晶片之銲線接墊形 成有一抗氧化金屬層，該些銲線接墊在該二晶片之凸塊回 銲步驟中將不會被氧化，以增強該些銲線接墊在凸塊回銲 後之銲性，以利後續銲線之接合，較佳地，該抗氧化金屬 層係為鎳金層〔Ni-Au〕。 依本發明之增強銲線接墊銲性之覆晶在晶片上封裝結 構，其係 複數個銲 晶片係貼 朝上並形 線接墊係 層係為鎳 一晶片之 凸塊，該 墊，該些 主要包含 線，該基 設於該基 成有複數 形成有一 金層〔Ni 主動面， 些凸塊係 銲線係電 片及 曰曰 有一基板、一第一晶片、一第 板係具有一上表面及一下表面，該第一 板之上表面，且該第一晶片之主動面係 個凸塊接墊及複數個銲線接墊，該些鋒 抗氧化金屬層，較佳地，該抗氧化金屬 -Au〕，該第二晶片係覆晶接合於該第 且該第二晶片之主動面係形成有複數個 回銲接合該第一晶片之該些對應凸塊接 性連接該第一晶片之銲線接墊至該基
1麵 麵 第8頁 1226117 五、發明說明（3) 板，較佳地，在該基板之上表面形成有一封膠體與下表面 形成有複數個銲球，以構成一封裝結構，由於該第一晶片 之銲線接墊係形成有一抗氧化金屬層，而避免在第二晶片 之凸塊回銲步驟導致該些銲線接墊氧化，而能達到增強在 回辉後銲線接墊之銲性，以利該些鮮線之接合。 【實施方式】 ' 參閱所附圖式，本發明將列舉以下之實施例說明。
請參閱第2圖，本發明之增強銲線接墊銲性之覆晶在 晶片上封裝結構20 0主要包含有一基板2 1〇、一第一晶片 2 2 0、一第二晶片2 3 0及複數個銲線2 4 〇，該基板21 0係具有 一上表面211及一下表面212，在本實施例中，該基板21〇 係為一種球格陣列封裝基板〔B G A s u b s t r a t e〕，其具有 電性導通該上表面2 11與下表面2 1 2之線路與對應連接墊 〔圖未繪出〕。 該第一晶片2 2 0係以一黏膠2 1 3貼設於該基板2 1 0之上 表面21 1，該第一晶片22 0係具有一主動面221及一對應之 背面22 2，其中該第一晶片2 20之主動面221係朝上並形成 有複數個凸塊接墊223〔bump-connecting pad〕及複數個 銲線接墊224〔wire-connecting pad〕，該些凸塊接墊 223係為矩陣排列，較佳地，在該些凸塊接墊22 3之顯露表 面係形成有一凸塊下金屬層226〔Under Bump Metallurgy layer，UBM layer〕，其材質係可選自於Al/Ni -V/Cu、 T i / N i - V/Cu等等，該些銲線接墊224係為铭墊〔A1 pad〕 或其它習知金屬墊，在該些銲線接墊224之顯露表面係形 1226117 圖式簡單說明 【圖式簡單說明】 第1圖：習知覆晶在晶片上封裝結構之截面示意圖； 第2圖：依據本發明，一種覆晶在晶片上封裝結構之截面 示意圖； 第3圖：依據本發明，該覆晶在晶片上封裝結構在回銲凸 塊步驟中之截面示意圖； 第4圖：依據本發明，該覆晶在晶片上封裝結構在回銲凸 塊步驟中其銲線接墊之局部放大截面示意圖；及 第5圖：依據本發明，該覆晶在晶片上封裝結構之製造流 程圖。 元件符號簡單說明： 1 提供一基板 2 貼設一第一晶片於該基板 3 覆晶接合一第二晶片於該第一晶片 4 回銲該第二晶片之凸塊 5 電漿清洗該第一晶片與該基板 6 打線電性連接該第一晶片與該基板 7 壓模形成封膠體 8 接合鮮球於該基板 9 回鮮鋒球 1 0 0覆晶在晶片上封裝結構 110 基板 111 上表面 112 下表面 120第一晶片 121 主動面 122凸塊接墊
第13頁 1226117 圖式簡單說明 1 2 3 銲線接墊 130 第 二 晶 片 131 主 動 面 132 凸 塊 140 銲 線 150 封 膠 體 160 銲 球 200 覆 晶 在 晶 片 上 封裝： 洁構 210 基 板 211 上 表 面 212 下 表 面 213 黏 膠 220 第 一 晶 片 221 主 動 面 222 背 面 223 凸 塊 接 墊 224 銲 線接墊 225 抗 氧 化金屬層 226 凸 塊 下 金 屬 層 227 保 護 層 230 第 二 晶 片 231 主 動 面 232 背 面 • 233 凸 塊 240 鲜 線 250 封 膠 體 2 6 0 銲球
Claims (1)
1226117 六、申請專利範圍 【申請專利範圍】 1、一種覆晶在晶片上封裝結構，其包含·· 二基其係具有一上表面及一下表面； 一第:晶片，其係貼設於該基板之上表面，該第一 線：ΐ 有複數個凸塊接墊及複數個銲 a鲜線接墊係形成有一抗氧化金屬層； 曰ί I其係覆晶接合於該第一晶片之主動面， μ第一曰日片之主動面係形成有複數個 回銲接合於該些對應凸塊接塾；及&彡二凸塊係 複數個銲線，其係連接該第一曰 板。 咬伐4弟日日片之銲線接墊至該基 2:Π專利範圍第1項所述之覆晶在晶片上封裝-構，其中該些銲線接墊係為鋁墊。 裝、，·= 3構如圍第1項所述之覆晶在晶片上封裝. 構二：该抗氧化金屬層係為鎳金層Ί 4、如申請專利範圍第1 j音％、热 AU〕 構，其中該些凸塊接塾传^=晶片上封裝結 構ΠΠ範圍第1項所述之覆晶在晶片：：裝- 構，其中该些凸塊係為銲料凸塊。 对裝結 6、 如申請專利範圍第i項所述之覆晶 構，其中該基板之上表面係 =片上封裝結 該第一晶片與該些辉線。、有一封膠體，用以密封 7、 如申請專利範圍第1項所述 構，其中該基板之下表面传 =曰曰上封裝結 1成有複數個銲球。 $ 15頁 1226117 六、申請專利範圍 、一種覆晶在晶片上封裝製程，其包含之步驟有： 提供一基板，該基板係具有一上表面及一下表面； 貼設一第一晶片於該基板之上表面，該第一晶片之主 動面係朝上並形成有複數個凸塊接墊及複數個銲線接 墊，該第一晶片之該些銲線接墊係形成有一抗氧化金屬 層； 覆晶接合一第—晶片於該第一晶片之主動面，該第二 晶片之主動面係形成有複數個凸塊； 回銲該些凸塊’以接合於該些對應凸塊接墊；及 打線形成複數個銲線，該些銲線係連接該第一晶片之 銲線接墊至該基板。 9如申明專利範圍第8項所述之覆晶在晶片上封裝製 程’其中該些銲線接墊係為鋁墊。 1 〇、如申請專利範圍第8項所述之覆晶在晶片上封裝製 程’其中該抗氧化金屬層係為鎳金層〔Ni-All〕。 11、如=請專利範圍第8項所述之覆晶在晶片上封裝製 程，其，該些凸塊接墊係形成有一阻障金屬層。 12你士 t β月專利範圍第8項所述之覆晶在晶片上封裝製 程’其中該些凸塊係為銲料凸塊。 13鋥如專利範圍第8項所述之覆晶在晶片上封裝製 矣、包含之步驟有：形成一封膠體於該基板之上 晶片與成銲線之步驟之後，用以密封該第- 14 申3專利範圍第1 3項所述之覆晶在晶片上封裝製
1226117 六、申請專利範圍 程，其另包含之步驟有：形成複數個銲球於該基板之 下表面，在形成封膠體之步驟之後。 1 5、如申請專利範圍第8項所述之覆晶在晶片上封裝製 程，其另包含之步驟有：電漿清洗該第一晶片與該基 板，於打線形成銲線之步驟之前。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW092125823A TWI226117B (en) | 2003-09-18 | 2003-09-18 | Flip chip on chip package with improving bonding property of wire-connecting pads |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW092125823A TWI226117B (en) | 2003-09-18 | 2003-09-18 | Flip chip on chip package with improving bonding property of wire-connecting pads |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TWI226117B true TWI226117B (en) | 2005-01-01 |
| TW200512903A TW200512903A (en) | 2005-04-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW092125823A TWI226117B (en) | 2003-09-18 | 2003-09-18 | Flip chip on chip package with improving bonding property of wire-connecting pads |
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| Country | Link |
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| TW (1) | TWI226117B (zh) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI766192B (zh) * | 2019-10-07 | 2022-06-01 | 矽品精密工業股份有限公司 | 電子封裝件及其製法 |
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