TWI226117B - Flip chip on chip package with improving bonding property of wire-connecting pads - Google Patents

Flip chip on chip package with improving bonding property of wire-connecting pads Download PDF

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Publication number
TWI226117B
TWI226117B TW092125823A TW92125823A TWI226117B TW I226117 B TWI226117 B TW I226117B TW 092125823 A TW092125823 A TW 092125823A TW 92125823 A TW92125823 A TW 92125823A TW I226117 B TWI226117 B TW I226117B
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Taiwan
Prior art keywords
wafer
chip
pads
substrate
flip
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TW092125823A
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Chinese (zh)
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TW200512903A (en
Inventor
Wei-Chang Tai
Shih-Chang Lee
Gwo-Liang Weng
Ching-Hui Chang
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Advanced Semiconductor Eng
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Publication of TWI226117B publication Critical patent/TWI226117B/en
Publication of TW200512903A publication Critical patent/TW200512903A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Wire Bonding (AREA)

Abstract

A flip chip on chip package with improving bonding property of wire-connecting pads comprises a substrate, a first chip attached on the substrate and a second chip flip-chip mounted on the first chip. A plurality of bump-connecting pads and a plurality of wire-connecting pads are formed on the active surface of the first chip. An anti-oxidation metal layer covers on the wire-connecting pads, so as to avoid oxidation of wire-connecting pads during reflowing bumps of the second chip on the bump-connecting pads, and to improve wire-bonding welding property of wire-connecting pads.

Description

1226117 五、發明說明（1) :發明所屬之技術領域】 本發明係有關於霜S太a 關於一種增強銲線接墊：：：^技術’特別係有 【先前技術】 ^之覆⑽在晶片上封裝結構。 為了達到多晶片高密度封裝之半導體一 習知之覆晶在晶片上封裝結構係為在一基板， J substrate〕或一釘架〔lead卜繼〕上黏著—晶片， 或者以另一覆晶晶片覆晶接人i + 馇，#铕曰曰y + π 述晶片，因在覆晶接合 後该覆日日日日片之凸塊須經過一道回銲步驟，再進行後續 之打線連接、封模、沖切等工程，如我國專利公告第 459360號係亦已揭示有一種覆晶在晶片上封裝結^。 請參閱第1圖，一種習知之覆晶在晶片上封装結構1〇〇 係包含有一基板110、一第一晶片12〇、一第二晶片13〇、 複數個銲線140、封膠體15〇及複數個銲球16〇，該基板u〇 之上表面111係黏著有該第一晶片i 2 0，且在該第一晶片 120之主動面121係形成有複數個凸塊接墊丨22與複數個銲 線接墊1 2 3，該第二晶片1 3 0係覆晶接合在該第一晶片 1 2 0 ’該第二晶片1 3 0之主動面1 3 1上所形成之凸塊1 3 2係接 合在該第一晶片1 2 0之該些凸塊接墊1 2 2，在覆晶接合之 後，習知地需要對該些凸塊1 32加以回銲〔ref 1 owi ng〕， 因此需將組合有第一晶片120與第二晶片130之基板110放 置於一回銲爐以進行回銲步驟，然而因在回銲步驟之高溫 而使得該第一晶片1 2 0之銲線接墊1 2 3形成一氧化層，導致 在後續之打線步驟中，以打線形成之複數個銲線1 4 0不容1226117 V. Description of the invention (1): The technical field to which the invention belongs] The present invention relates to the frost S too a. About an enhanced bonding wire pad :: ^ Technology 'especially has the [prior art] ^ cover on the wafer Upper packaging structure. In order to achieve multi-chip high-density packaging of semiconductors, a conventional flip-chip packaging structure on a wafer is adhered to a wafer, a substrate, or a lead frame—a wafer, or another flip-chip wafer. The crystal is connected to the chip i + 馇, # 铕 曰 + y + π, because after the flip-chip bonding, the bumps of the day-to-day film must go through a re-soldering step, and then the subsequent wire connection, mold sealing, Die-cutting and other projects, such as China's Patent Publication No. 459360, have also revealed that a flip-chip packaged on a wafer ^. Please refer to FIG. 1. A conventional flip chip packaging structure 100 includes a substrate 110, a first wafer 120, a second wafer 130, a plurality of bonding wires 140, a sealing compound 15 and A plurality of solder balls 160, the first surface i0 of the substrate u0 is adhered to the first wafer i 2 0, and an active surface 121 of the first wafer 120 is formed with a plurality of bump pads 22 and a plurality of Wire bonding pads 1 2 3, the second wafer 1 3 0 is a bump 1 3 formed by flip chip bonding on the active surface 1 3 1 of the first wafer 1 2 0 'the second wafer 1 3 0 2 are the bump pads 1 2 2 bonded to the first wafer 1 2 0. After flip-chip bonding, it is conventionally necessary to resolder the bumps 1 32 [ref 1 owi ng], so The substrate 110 combining the first wafer 120 and the second wafer 130 needs to be placed in a reflow oven for the reflow step. However, due to the high temperature of the reflow step, the bonding pads of the first wafer 120 An oxide layer was formed in 1 2 3, which resulted in the formation of a plurality of bonding wires 1 4 0 in the subsequent bonding step.

mui iirai 第7頁 1226117 五、發明說明（2) 易接合在該些銲線接墊1 2 3，即會有「假銲」現象，因該 氧化層形成於該些銲線接墊i 23而導致焊接不良狀況不易 被觀測到’若繼續形成封膠體丨5 〇於該基板丨丨〇上表面丨u 以及形成銲球160於該基板11〇之下表面112，其所製造的 覆晶在晶片上封裝結構1 0 0將具有相當高之不良率。 【發明内容】 本發明之主要目的係在於提供一種增強銲線接墊銲性 之覆晶在晶片上封裝結構，其一第一晶片上覆晶接合有一 第二晶片，而呈矽晶片在矽晶片上之疊晶結構 〔Chip-on-Chip stack〕，利用該第一晶片之銲線接墊形 成有一抗氧化金屬層，該些銲線接墊在該二晶片之凸塊回 銲步驟中將不會被氧化，以增強該些銲線接墊在凸塊回銲 後之銲性，以利後續銲線之接合，較佳地，該抗氧化金屬 層係為鎳金層〔Ni-Au〕。 依本發明之增強銲線接墊銲性之覆晶在晶片上封裝結 構，其係 複數個銲 晶片係貼 朝上並形 線接墊係 層係為鎳 一晶片之 凸塊，該 墊，該些 主要包含 線，該基 設於該基 成有複數 形成有一 金層〔Ni 主動面， 些凸塊係 銲線係電 片及 曰曰 有一基板、一第一晶片、一第 板係具有一上表面及一下表面，該第一 板之上表面，且該第一晶片之主動面係 個凸塊接墊及複數個銲線接墊，該些鋒 抗氧化金屬層，較佳地，該抗氧化金屬 -Au〕，該第二晶片係覆晶接合於該第 且該第二晶片之主動面係形成有複數個 回銲接合該第一晶片之該些對應凸塊接 性連接該第一晶片之銲線接墊至該基mui iirai Page 7 1226117 V. Description of the invention (2) Easy to bond to these welding wire pads 1 2 3, there will be "false soldering" phenomenon, because the oxide layer is formed on these welding wire pads i 23 and Leading to poor soldering conditions is difficult to be observed. 'If the sealant continues to form on the substrate, the upper surface of the substrate, and the solder ball 160 is formed on the lower surface, 112 of the substrate. The upper package structure 100 will have a relatively high defect rate. [Summary of the Invention] The main object of the present invention is to provide a flip-chip package structure on a wafer which enhances the solderability of the bonding pads. A flip-chip is bonded to a second wafer on a first wafer, and a silicon wafer is formed on the wafer. On the chip-on-chip stack, an anti-oxidation metal layer is formed by using the bonding pads of the first chip, and these bonding pads will not be used in the bump reflow step of the two wafers. It will be oxidized to enhance the solderability of these bonding wire pads after bump re-soldering to facilitate the bonding of subsequent bonding wires. Preferably, the oxidation-resistant metal layer is a nickel-gold layer [Ni-Au]. The chip-on-wafer packaging structure for enhancing the solderability of the wire bonding pads according to the present invention is a plurality of bonding wafers that are attached upward and the wire bonding pads are nickel-wafer bumps. The pad, the These mainly include wires, and the base is formed on the base to form a plurality of gold layers (Ni active surface, some bumps are wire bonding pads, and a substrate, a first wafer, and a first board have an upper surface And the lower surface, the upper surface of the first plate, and the active surface of the first chip is a bump pad and a plurality of bonding wire pads, the front anti-oxidation metal layers, preferably, the anti-oxidation metal -Au], the second wafer is flip-chip bonded to the first and the active surface of the second wafer is formed with a plurality of back-welds and corresponding bumps of the first wafer are connected to the first wafer by soldering. Wire pad to the base

1麵 麵 第8頁 1226117 五、發明說明（3) 板，較佳地，在該基板之上表面形成有一封膠體與下表面 形成有複數個銲球，以構成一封裝結構，由於該第一晶片 之銲線接墊係形成有一抗氧化金屬層，而避免在第二晶片 之凸塊回銲步驟導致該些銲線接墊氧化，而能達到增強在 回辉後銲線接墊之銲性，以利該些鮮線之接合。 【實施方式】 ' 參閱所附圖式，本發明將列舉以下之實施例說明。1 面面 第 8 页 1226117 V. Description of the invention (3) It is preferable that a gel is formed on the upper surface of the substrate and a plurality of solder balls are formed on the lower surface to form a packaging structure. The wire bonding pads of the wafer are formed with an anti-oxidation metal layer, which avoids the oxidation of the wire bonding pads during the bump reflow step of the second wafer, and can enhance the solderability of the wire bonding pads after the glow. To facilitate the joining of these fresh threads. [Embodiment] With reference to the drawings, the present invention will be described with the following examples.

請參閱第2圖，本發明之增強銲線接墊銲性之覆晶在 晶片上封裝結構20 0主要包含有一基板2 1〇、一第一晶片 2 2 0、一第二晶片2 3 0及複數個銲線2 4 〇，該基板21 0係具有 一上表面211及一下表面212，在本實施例中，該基板21〇 係為一種球格陣列封裝基板〔B G A s u b s t r a t e〕，其具有 電性導通該上表面2 11與下表面2 1 2之線路與對應連接墊 〔圖未繪出〕。 該第一晶片2 2 0係以一黏膠2 1 3貼設於該基板2 1 0之上 表面21 1，該第一晶片22 0係具有一主動面221及一對應之 背面22 2，其中該第一晶片2 20之主動面221係朝上並形成 有複數個凸塊接墊223〔bump-connecting pad〕及複數個 銲線接墊224〔wire-connecting pad〕，該些凸塊接墊 223係為矩陣排列，較佳地，在該些凸塊接墊22 3之顯露表 面係形成有一凸塊下金屬層226〔Under Bump Metallurgy layer，UBM layer〕，其材質係可選自於Al/Ni -V/Cu、 T i / N i - V/Cu等等，該些銲線接墊224係為铭墊〔A1 pad〕 或其它習知金屬墊，在該些銲線接墊224之顯露表面係形 1226117 圖式簡單說明 【圖式簡單說明】 第1圖：習知覆晶在晶片上封裝結構之截面示意圖； 第2圖：依據本發明，一種覆晶在晶片上封裝結構之截面 示意圖； 第3圖：依據本發明，該覆晶在晶片上封裝結構在回銲凸 塊步驟中之截面示意圖； 第4圖：依據本發明，該覆晶在晶片上封裝結構在回銲凸 塊步驟中其銲線接墊之局部放大截面示意圖；及 第5圖：依據本發明，該覆晶在晶片上封裝結構之製造流 程圖。 元件符號簡單說明： 1 提供一基板 2 貼設一第一晶片於該基板 3 覆晶接合一第二晶片於該第一晶片 4 回銲該第二晶片之凸塊 5 電漿清洗該第一晶片與該基板 6 打線電性連接該第一晶片與該基板 7 壓模形成封膠體 8 接合鮮球於該基板 9 回鮮鋒球 1 0 0覆晶在晶片上封裝結構 110 基板 111 上表面 112 下表面 120第一晶片 121 主動面 122凸塊接墊Please refer to FIG. 2. The flip-chip package structure 20 0 of the present invention, which enhances the bonding property of the bonding wire pads, mainly includes a substrate 2 10, a first wafer 2 2 0, a second wafer 2 3 0 and A plurality of bonding wires 2 4 0, the substrate 21 0 has an upper surface 211 and a lower surface 212. In this embodiment, the substrate 21 0 is a ball grid array package substrate [BGA substrate], which has electrical properties. Connect the lines on the upper surface 2 11 and the lower surface 2 1 2 and the corresponding connection pads (not shown). The first wafer 2 2 0 is attached to the upper surface 21 1 of the substrate 2 1 0 with an adhesive 2 1 3. The first wafer 22 0 has an active surface 221 and a corresponding back surface 22 2. The active surface 221 of the first wafer 2 20 faces upward and is formed with a plurality of bump-connecting pads 223 [bump-connecting pad] and a plurality of wire-connecting pads 224 (wire-connecting pad). The 223 series is arranged in a matrix. Preferably, an exposed under metal layer 226 (Under Bump Metallurgy layer, UBM layer) is formed on the exposed surfaces of the bump pads 22 3. The material can be selected from Al / Ni -V / Cu, T i / Ni-V / Cu, etc. The bonding pads 224 are A1 pads or other conventional metal pads. The bonding pads 224 are exposed. Surface configuration 1226117 Brief description of the drawings [Simplified description of the drawings] Figure 1: A schematic cross-sectional view of a conventional flip chip packaging structure on a wafer; Figure 2: A cross-sectional schematic view of a flip chip packaging structure according to the present invention Figure 3: a schematic cross-sectional view of the flip-chip packaging structure on the wafer during the step of resoldering the bump according to the present invention; Figure 4: A partially enlarged cross-sectional view of the bonding pad of the flip-chip packaging structure on the wafer during the re-soldering step according to the present invention; and Figure 5: The flip-chip packaging on the wafer according to the present invention Structure manufacturing flow chart. Brief description of component symbols: 1 Provide a substrate 2 Place a first wafer on the substrate 3 Flip-bond a second wafer to the first wafer 4 Resolder the bumps of the second wafer 5 Plasma cleaning the first wafer The first chip and the substrate 7 are electrically connected to the substrate 6 to form a sealing compound. 8 A fresh ball is bonded to the substrate. 9 A fresh ball 1 0 0 flip chip is packaged on the wafer. 110 The top surface of the substrate 111 is 112. Surface 120 First wafer 121 Active surface 122 Bump pad

第13頁 1226117 圖式簡單說明 1 2 3 銲線接墊 130 第 二 晶 片 131 主 動 面 132 凸 塊 140 銲 線 150 封 膠 體 160 銲 球 200 覆 晶 在 晶 片 上 封裝： 洁構 210 基 板 211 上 表 面 212 下 表 面 213 黏 膠 220 第 一 晶 片 221 主 動 面 222 背 面 223 凸 塊 接 墊 224 銲 線接墊 225 抗 氧 化金屬層 226 凸 塊 下 金 屬 層 227 保 護 層 230 第 二 晶 片 231 主 動 面 232 背 面 • 233 凸 塊 240 鲜 線 250 封 膠 體 2 6 0 銲球Page 13 1226117 Brief description of the drawings 1 2 3 Welding wire pads 130 Second chip 131 Active surface 132 Bump 140 Welding wire 150 Sealing compound 160 Solder ball 200 Chip-on-chip packaging: Clean structure 210 Substrate 211 Upper surface 212 Lower surface 213 Adhesive 220 First wafer 221 Active surface 222 Back surface 223 Bump pads 224 Welding pads 225 Antioxidant metal layer 226 Under bump metal layer 227 Protective layer 230 Second wafer 231 Active surface 232 Back surface • 233 Convex Block 240 Fresh Line 250 Sealing Gel 2 6 0 Solder Ball

Claims (1)

1226117 六、申請專利範圍 【申請專利範圍】 1、一種覆晶在晶片上封裝結構，其包含·· 二基其係具有一上表面及一下表面； 一第:晶片，其係貼設於該基板之上表面，該第一 線：ΐ 有複數個凸塊接墊及複數個銲 a鲜線接墊係形成有一抗氧化金屬層； 曰ί I其係覆晶接合於該第一晶片之主動面， μ第一曰日片之主動面係形成有複數個 回銲接合於該些對應凸塊接塾；及&彡二凸塊係 複數個銲線，其係連接該第一曰 板。 咬伐4弟日日片之銲線接墊至該基 2:Π專利範圍第1項所述之覆晶在晶片上封裝-構，其中該些銲線接墊係為鋁墊。 裝、，·= 3構如圍第1項所述之覆晶在晶片上封裝. 構二：该抗氧化金屬層係為鎳金層Ί 4、如申請專利範圍第1 j音％、热 AU〕 構，其中該些凸塊接塾传^=晶片上封裝結 構ΠΠ範圍第1項所述之覆晶在晶片：：裝- 構，其中该些凸塊係為銲料凸塊。 对裝結 6、 如申請專利範圍第i項所述之覆晶 構，其中該基板之上表面係 =片上封裝結 該第一晶片與該些辉線。、有一封膠體，用以密封 7、 如申請專利範圍第1項所述 構，其中該基板之下表面传 =曰曰上封裝結 1成有複數個銲球。 $ 15頁 1226117 六、申請專利範圍 、一種覆晶在晶片上封裝製程，其包含之步驟有： 提供一基板，該基板係具有一上表面及一下表面； 貼設一第一晶片於該基板之上表面，該第一晶片之主 動面係朝上並形成有複數個凸塊接墊及複數個銲線接 墊，該第一晶片之該些銲線接墊係形成有一抗氧化金屬 層； 覆晶接合一第—晶片於該第一晶片之主動面，該第二 晶片之主動面係形成有複數個凸塊； 回銲該些凸塊’以接合於該些對應凸塊接墊；及 打線形成複數個銲線，該些銲線係連接該第一晶片之 銲線接墊至該基板。 9如申明專利範圍第8項所述之覆晶在晶片上封裝製 程’其中該些銲線接墊係為鋁墊。 1 〇、如申請專利範圍第8項所述之覆晶在晶片上封裝製 程’其中該抗氧化金屬層係為鎳金層〔Ni-All〕。 11、如=請專利範圍第8項所述之覆晶在晶片上封裝製 程，其，該些凸塊接墊係形成有一阻障金屬層。 12你士 t β月專利範圍第8項所述之覆晶在晶片上封裝製 程’其中該些凸塊係為銲料凸塊。 13鋥如專利範圍第8項所述之覆晶在晶片上封裝製 矣、包含之步驟有：形成一封膠體於該基板之上 晶片與成銲線之步驟之後，用以密封該第- 14 申3專利範圍第1 3項所述之覆晶在晶片上封裝製1226117 VI. Scope of patent application [Scope of patent application] 1. A flip-chip package structure on a wafer, which includes ... Two bases with an upper surface and a lower surface; First: wafers, which are attached to the substrate On the upper surface, the first line: ΐ has a plurality of bump pads and a plurality of soldered fresh line pads forming an anti-oxidation metal layer; said I is a flip-chip bonded to the active surface of the first wafer , The active surface of the first solar panel is formed with a plurality of back-welded joints to the corresponding bump joints; and & the second bump is a plurality of bonding wires, which are connected to the first panel. The wire bonding pads of the 4th Japanese and Japanese films are bitten to the base 2: the flip chip described in item 1 of the patent scope is packaged on a wafer, wherein the wire bonding pads are aluminum pads. The structure, · = 3 is structured as a flip chip as described in item 1 on the wafer. Structure 2: The anti-oxidation metal layer is a nickel-gold layer. ] Structure, wherein the bumps are successively transmitted ^ = the flip-chip on wafer described in item 1 of the package structure ΠΠ range :: mounting-structure, wherein the bumps are solder bumps. For the junction 6. The overlying structure as described in item i of the patent application range, wherein the upper surface of the substrate is an on-chip package, the first chip and the glow wires. There is a colloid for sealing. 7. The structure as described in item 1 of the scope of the patent application, wherein the lower surface of the substrate is transferred to the upper package to form a plurality of solder balls. $ 15 页 1226117 VI. Patent application scope, a flip chip packaging process on a wafer, which includes the steps of: providing a substrate, the substrate having an upper surface and a lower surface; mounting a first wafer on the substrate On the upper surface, the active surface of the first wafer faces upward and is formed with a plurality of bump pads and a plurality of welding wire pads, and the welding wire pads of the first wafer are formed with an oxidation-resistant metal layer; A first wafer is bonded to the active surface of the first wafer, and a plurality of bumps are formed on the active surface of the second wafer; the bumps are re-soldered to bond to the corresponding bump pads; A plurality of bonding wires are formed, and the bonding wires are connected to the bonding pads of the first wafer to the substrate. 9 The flip-chip on-chip packaging process described in item 8 of the declared patent scope 'wherein the bonding pads are aluminum pads. 10. The chip-on-wafer packaging process according to item 8 of the scope of the patent application, wherein the oxidation-resistant metal layer is a nickel-gold layer [Ni-All]. 11. If the flip-chip packaging process described in item 8 of the patent scope is requested, the bump pads are formed with a barrier metal layer. 12. The flip-chip on-wafer packaging process described in item 8 of the patent scope of t β month, wherein the bumps are solder bumps. 13) The flip chip is packaged on the wafer as described in item 8 of the patent scope. The steps include: forming a gel on the substrate and forming a bonding wire to seal the first-14 The flip chip described in item 3 of the patent scope of claim 3 is packaged on a wafer 1226117 六、申請專利範圍 程，其另包含之步驟有：形成複數個銲球於該基板之 下表面，在形成封膠體之步驟之後。 1 5、如申請專利範圍第8項所述之覆晶在晶片上封裝製 程，其另包含之步驟有：電漿清洗該第一晶片與該基 板，於打線形成銲線之步驟之前。1226117 6. The scope of patent application, which further includes the steps of forming a plurality of solder balls on the lower surface of the substrate, and after the step of forming a sealing compound. 15. The chip-on-wafer packaging process as described in item 8 of the scope of the patent application, which further includes the steps of: plasma cleaning the first wafer and the substrate, before the step of wire bonding to form a bonding wire.
TW092125823A 2003-09-18 2003-09-18 Flip chip on chip package with improving bonding property of wire-connecting pads TWI226117B (en)

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