TWI225669B

TWI225669B - Method for manufacturing silicide layer

Info

Publication number: TWI225669B
Application number: TW92115754A
Authority: TW
Inventors: Hong-Yuan Chu; Chih-Jian Chen
Original assignee: Taiwan Semiconductor Mfg
Priority date: 2003-06-10
Filing date: 2003-06-10
Publication date: 2004-12-21
Also published as: TW200428527A

Abstract

A method for manufacturing a silicide layer is disclosed. In the method, after an amorphous silicon layer is formed, an incomplete anneal step is performed to reserve a portion of the amorphous silicon layer. Then, a metal layer is formed on the amorphous silicon layer, and a silicidation step is performed to form a silicide layer on the surface of the substrate.

Description

1225669 五、發明說明（1) 【發明所屬之技術領域】本發明是有關於一種石夕化金屬層（Silicide Layer)之製造方法，且特別是有關於一種於非晶矽層（Am〇rph〇us1225669 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a method for manufacturing a silicide layer, and more particularly to an amorphous silicon layer (AmOrph. us

Si 1 icon Layer)上進行矽化金屬步驟以形成矽化金屬層之方法。【先前技術】在互補式金氧半導（CMOS)積體電路（IC)中，隨著半導體製程技術的快速演進，元件的尺寸已縮減到深次微米 (Deep-submicron)階段，甚至奈米（Nan〇meter)階段，藉以增進積體電路的操作性能及運算速度，並降低每顆晶片之_ 製造成本。隨著兀件尺寸的縮減，為了降低電晶體元件之源極 (Source)與汲極⑶^土“的片電阻（Sheet resistanc〇，而發展出矽化金屬製程。此乃係由於電流透過接觸分流至源極與汲極上之矽化金屬層，再進入源極/汲極擴散區中，Λ可明顯降片電阻。在元件設計上，也可採用減少源極/汲極擴散區的面積，來降低源極/汲極與基材之間的接面片電容，、進一步降低元件的電阻電容延遲（RC Delay)。因此，源&極/ 没極擴散區之片電阻的大幅降低，將可使得電晶體元;| 牛' 的操作速度可獲得有效提升，因而使電晶體技術得以高頻率的應用。請參照第1圖至第3圖，第1圖至第3圖係繪示習知矽化金層之製程剖面圖。傳統矽化金屬層之製作，首先提供美材 2〇〇 ’且此基材2 0 0上已形成有閘極206結構。其中/閑&極A method for performing a silicided metal step on a Si 1 icon layer) to form a silicided metal layer. [Previous technology] In the complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC), with the rapid evolution of semiconductor process technology, the size of components has been reduced to the deep-submicron stage, even nanometers. (Nanometer) stage, in order to improve the operating performance and operation speed of the integrated circuit, and reduce the manufacturing cost of each chip. With the shrinking of the size of the element, in order to reduce the sheet resistance of the source and the drain of the transistor element (Sheet resistanc), a silicided metal process has been developed. This is because the current is shunted through the contact to The silicided metal layers on the source and the drain enter the source / drain diffusion region, and Λ can significantly reduce the chip resistance. In the design of the component, the area of the source / drain diffusion region can also be reduced to reduce the source. The chip capacitance between the electrode / drain and the substrate further reduces the RC delay of the device. Therefore, the substantial reduction in the chip resistance of the source & The operating speed of the crystal element can be effectively improved, so that the transistor technology can be applied at a high frequency. Please refer to Figs. 1 to 3, and Figs. 1 to 3 show the conventional gold silicide layer. Cross-sectional view of the manufacturing process. For the production of traditional silicided metal layers, firstly 200 'US material is provided and a gate 206 structure has been formed on this substrate 2000. Among them / leisure &

12256691225669

20 6包括位於基材200上之閘極介電^ ^ ^ 層m上之導電層21〇、以及位於問極介8電層 ==電 2二構侧壁上的間隙壁212。而緊鄰閘極206之：邊的基材200表面則形成有非晶矽層2〇2與非晶矽層2〇4，如 1圖所示之結構。接著，對基材200以及其上之結構進行回火（Anneal)步驟，藉以使非晶矽層202與非晶矽層204内之非晶矽產生再結晶’而使整個非晶矽層202與非晶矽層2〇4分別轉變成結晶矽層21 4與結晶矽層2 1 6。受到矽之材料特性的影響，結晶石夕層2 1 4與結晶矽層2 1 6内之結晶方位均位於一定方向，且_ 甚至會沿著結晶矽層2 1 4之角落與結晶矽層2 1 6之角落分別產生差排（Dislocation)218與差排220之結晶缺陷，如第2 圖所示之結構。待非晶石夕層2 0 2與非晶石夕層2 0 4分別完全轉變成結晶石夕層21 4 與結晶矽層2 1 6後，即可進行矽化金屬的程序。先於結晶石夕層2 1 4與結晶矽層2 1 6上沉積一層金屬層（未繪示），再進行回火步驟，以使此金屬層擴散至結晶矽層21 4與結晶矽層 2 1 6中，並與結晶矽層2 1 4以及結晶矽層2 1 6產生矽化金屬反應。如此一來，分別在結晶矽層2 1 4以及結晶矽層2 1 6中形❿ 成矽化金屬層222以及矽化金屬層2 24，如第3圖所示。由於之前形成結晶矽層21 4與結晶矽層21 6時，結晶矽層21 4 與結晶矽層216中分別產生差排218與差排220。因此，在矽化金屬過程中，若差排218與差排220處於高應力的區域時，差排218與差排220則由兩端向外延伸。如此一來，將20 6 includes a conductive layer 21 on the gate dielectric layer ^ ^ ^ on the substrate 200, and a spacer 212 on the side wall of the interfacial dielectric layer == electrical 2. An amorphous silicon layer 200 and an amorphous silicon layer 204 are formed on the surface of the substrate 200 next to the gate electrode 206, as shown in FIG. Next, an annealing step is performed on the substrate 200 and the structure thereon to recrystallize the amorphous silicon in the amorphous silicon layer 202 and the amorphous silicon layer 204, so that the entire amorphous silicon layer 202 and The amorphous silicon layer 204 is transformed into a crystalline silicon layer 21 4 and a crystalline silicon layer 2 16 respectively. Affected by the material properties of silicon, the crystal orientation in the crystalline silicon layer 2 1 4 and the crystalline silicon layer 2 1 6 are all in a certain direction, and _ will even follow the corner of the crystalline silicon layer 2 1 4 and the crystalline silicon layer 2 The crystalline defects of the dislocation 218 and the dislocation 220 are generated at the corners of 16, respectively, as shown in the structure shown in FIG. 2. After the amorphous stone layer 202 and the amorphous stone layer 204 have been completely transformed into the crystalline stone layer 21 4 and the crystalline silicon layer 2 16 respectively, the procedure of siliciding metal can be performed. A metal layer (not shown) is deposited on the crystalline silicon layer 2 1 4 and the crystalline silicon layer 2 1 6, and then a tempering step is performed to diffuse the metal layer to the crystalline silicon layer 21 4 and the crystalline silicon layer 2 16 and a silicidated metal reaction occurs with the crystalline silicon layer 2 1 4 and the crystalline silicon layer 2 1 6. In this way, a silicided metal layer 222 and a silicided metal layer 2 24 are formed in the crystalline silicon layer 2 1 4 and the crystalline silicon layer 2 1 6 respectively, as shown in FIG. 3. When the crystalline silicon layer 21 4 and the crystalline silicon layer 21 6 are formed before, a difference row 218 and a difference row 220 are generated in the crystalline silicon layer 21 4 and the crystalline silicon layer 216, respectively. Therefore, in the process of metal silicide, if the differential row 218 and the differential row 220 are in a high stress area, the differential row 218 and the differential row 220 extend outward from both ends. As a result, will

第6頁 1225669 五、發明說明（3) 導致結晶石夕層2 1 4與石夕化金屬層2 2 2、以及結晶矽層2丨6與矽化金屬層224之結構的缺陷愈來愈嚴重，甚至造成差排218 與差排2 2 0穿出結晶矽層21 4與結晶矽層21 6而進入到基材 2 0 0之矽主體中。此外，由於矽結晶時，其結晶方位大致上係朝同一方向。因此’在石夕化金屬過程中，受到結晶方位與缺陷密度的影響’金屬原子通常比較會沿某些特定方向擴散。如此一來’將會造成所形成之矽化金屬層222與矽化金屬層224之厚度不一致，而使得矽化金屬層222與矽化金屬層224之均勻度相當差。【發明内容】本發明之目的就是在提供一種矽化金屬層之製造方法，其係在基材表面形成非晶石夕層後，對此非晶碎層進行不完全回火步驟（Incomplete Anneal Step)，僅使此非晶石夕層下面部分轉變成晶體結構，而使非晶矽層之上面部分仍維持非晶石夕結構。因此’後續金屬層之石夕化金屬步驟可在原子非有序排列的非晶石夕層上進行。如此一來，可獲得均勻之金屬矽化層。本發明之另一目的是在提供一種石夕化金屬層之製造方法，其係對非晶矽層進行不完全回火步驟，而在非晶矽層於再❿ 結晶期間所產生之差排尚未發生前停止。於是，進行後續之矽化金屬步驟時，可有效避免差排的發生，進而防止差排延伸進入井區。因此，可避免接面漏電流（juncti〇nPage 6 1225669 V. Description of the invention (3) The defects that cause the structure of the crystalline stone layer 2 1 4 and the petrified metal layer 2 2 2 and the crystalline silicon layer 2 6 and the silicided metal layer 224 are becoming more and more serious. Even the difference row 218 and the difference row 2 2 0 penetrate the crystalline silicon layer 21 4 and the crystalline silicon layer 21 6 and enter the silicon body of the substrate 200. In addition, when silicon is crystallized, its crystal orientation is approximately in the same direction. Therefore, in the process of petrifying the metal, affected by the crystal orientation and defect density, metal atoms usually diffuse in certain specific directions. As a result, the thickness of the silicided metal layer 222 and the silicided metal layer 224 formed will be inconsistent, and the uniformity of the silicided metal layer 222 and the silicided metal layer 224 will be quite poor. [Summary of the Invention] The object of the present invention is to provide a method for manufacturing a silicided metal layer, which comprises forming an amorphous stone layer on the surface of a substrate, and then performing an incomplete annealing step on the amorphous fragmented layer. Only the lower part of the amorphous stone layer is transformed into a crystalline structure, while the upper part of the amorphous silicon layer still maintains the amorphous stone layer structure. Therefore, the metallization step of the subsequent metal layer can be performed on the amorphous stone layer in which atoms are not arranged in an orderly manner. In this way, a uniform metal silicide layer can be obtained. Another object of the present invention is to provide a method for manufacturing a petrified metal layer, which involves performing an incomplete tempering step on an amorphous silicon layer. Stop before it happens. Therefore, when the subsequent metal silicide step is performed, it can effectively avoid the occurrence of the differential row, thereby preventing the differential row from extending into the well area. Therefore, junction leakage current (juncti〇n

Leakage) ° 本發明之又一目的是在提供一種矽化金屬層之製造方法，Leakage) ° Another object of the present invention is to provide a method for manufacturing a silicided metal layer,

第7頁 1225669Page 7 1225669

在並未完全再結晶時叩進行矽化金屬步非晶發層此，不僅層之厚度善元件之根據本發法，至少一表面至藉以使部非晶碎層石夕層之未在基材之可避免矽 —致性赘性能。明之上述包括下列少已形成分之非晶位於此晶結晶的部表面形成 = 陷的影響，提升…屬更了獲侍夂接面之矽化金屬&，有效改目的，提出一種矽化金屬層之製造方步驟：首先提供—基材，其中此基材之一非晶矽層。再進行一第一回火步驟，矽層轉變成一晶體層，其中另一部分之體層上。接著，形成一金屬層位於非晶分上。然後，進行一第二回火步驟，而矽化金屬層。依照本發明一較佳實施例，基材之材料較佳為矽 (Silicon)，金屬層之材料可例如為鈷（c〇bait),且第一回火步驟與第二回火步驟均係採用例如快速熱回火（RapU Thermal Anneal ;RTA)方式來進行。此外’非晶矽層之厚度約為100奈米，且晶體層之厚度較佳為控制在介於2〇奈米至6 0奈米之間。由於晶材表面之非晶矽層僅有底部部分產生結晶，因此矽化金屬步驟係在原子非有序排列的非晶矽層上進行。如此j 一來’在石夕化金屬步驟進行期間，不僅可避免差排產生，更可排除結晶方位之影響。此外，由於非晶矽層與結晶矽之界面如同擴散阻障（Diffusion Barrier) —般，進而可獲得較淺之接面且均勻度佳之石夕化金屬層。【實施方式】When the silicon layer is not completely recrystallized, the silicon layer is amorphous, and the thickness of the layer is not only good. According to the method of the present invention, at least one surface to the surface of the amorphous layer is not on the substrate. Can avoid silicon-induced bulk performance. The above includes the following amorphous components that are formed on the surface of the crystal. The formation of the surface of the crystal = the effect of depression, promotion ... It is a silicided metal & Manufacturing steps: First, a substrate is provided, wherein one of the substrates is an amorphous silicon layer. After the first tempering step, the silicon layer is transformed into a crystalline layer, and the other part is on the bulk layer. Next, a metal layer is formed on the amorphous. Then, a second tempering step is performed while siliciding the metal layer. According to a preferred embodiment of the present invention, the material of the substrate is preferably silicon, and the material of the metal layer may be, for example, cobalt, and both the first tempering step and the second tempering step are used. For example, rapid thermal tempering (RapU Thermal Anneal; RTA). In addition, the thickness of the amorphous silicon layer is about 100 nm, and the thickness of the crystalline layer is preferably controlled between 20 nm and 60 nm. Since only the bottom portion of the amorphous silicon layer on the surface of the crystalline material is crystallized, the metal silicide step is performed on the amorphous silicon layer in which the atoms are not ordered. In this way, during the process of the metallization of the petrochemical stage, not only can the formation of differential rows be avoided, but also the influence of crystal orientation can be excluded. In addition, because the interface between the amorphous silicon layer and the crystalline silicon is like a diffusion barrier, a petrified metal layer with a shallower interface and better uniformity can be obtained. [Embodiment]

1225669 五、發明說明（5) 金屬層之製造方法，其係對非晶石夕層石夕；’以使石夕化金屬反應在未結晶之非晶 θ上進灯因此，可避免差排產生，排除結晶方曰，更可獲得淺接面且均勻度佳之石夕化金屬層。為: 發明之敘述更加詳盡盥完備，春與第6圖之圖示。〃參”、、下歹]描述並配合第4圖二至第6圖’第4圖至第6圖係繪示依照本發明-較佳實轭例的一種矽化金屬層之製程剖面圖。本發材· 電· 二金之屬材層料的Λ'ν首先提供半導體之基材300，其中此基 300之材枓較佳為矽。再利用例如熱 ===3^_例如沉㈣方式形成導電層 ΐί 3°8與導電層310，而在部分之基材300 電電/3Q8與導電層3iq之堆疊結構。待間極介二層;08 ?電層31〇之堆疊結構完成後，利用例雷之及回㈣的方式於閉極介電層_與導構的侧壁形成間隙壁312。其中，閉極介 3=:德ί °、以及間隙壁312構成閘極306。閘極 Γ/π ^306 ^ ^ ^ ^nmplantati〇n) ΪΪ:: 圍之基材300表面形成非晶矽層3〇2與非晶矽層304，而形成如第4圖所示之結構興二曰與非晶矽層304之厚度314可例如為1〇〇奈米。的曰 S邻快速熱回火的方式進行不完全回火步驟，使4刀之非曰曰梦層302與非晶石夕層3〇4產生結晶反應。其第9頁 12256691225669 V. Description of the invention (5) The manufacturing method of the metal layer, which is based on the amorphous stone layer; 'to make the stone metallized reaction react with the uncrystallized amorphous θ to the lamp. Therefore, it can avoid the generation of the differential discharge. Excluding the crystalline side, it is possible to obtain a petrified metal layer with a shallow junction and good uniformity. For: The description of the invention is more detailed and complete, illustrated in spring and Figure 6. [Refer to ",", [Next]] describe and cooperate with Fig. 4 and Fig. 2 to Fig. 6, and Fig. 4 to Fig. 6 are cross-sectional views showing the process of a silicided metal layer according to the preferred embodiment of the present invention. Λ'ν for hair material, electricity, and two-gold metal layer material first provides a semiconductor base material 300, and the material of this base 300 is preferably silicon. Reuse, for example, heat === 3 ^ _ such as sinking method A conductive layer of 3 ° 8 and a conductive layer 310 is formed, and a stacked structure of a part of the substrate 300, electrical and electrical, 3Q8, and a conductive layer 3iq. After the two layers of the interlayer dielectric and the 08-electric layer 31 are completed, use For example, the method of Lei Zhi and Hui Yi forms a gap wall 312 between the closed-electrode dielectric layer and the side wall of the conductive structure. Among them, the closed-electrode dielectric 3 =: 德 ί ° and the gap 312 constitute the gate 306. The gate Γ / π ^ 306 ^ ^ ^ ^ nmplantati〇n) ΪΪ :: An amorphous silicon layer 30 and an amorphous silicon layer 304 are formed on the surface of the surrounding substrate 300, and a structure shown in FIG. 4 is formed. The thickness 314 of the amorphous silicon layer 304 may be, for example, 100 nanometers. The incomplete tempering step is performed in a rapid thermal tempering manner, so that the four-knife dream layer 302 and the amorphous stone layer are formed. 3〇4 Health crystallization reaction. 91225669 Page thereof

^ b曰石夕層3 Ο 2與非晶矽層3 〇 4由非晶系結構再次結晶時，’係從非晶矽層302與非晶矽層3 〇4之底部開始結晶。因匕在此不70全回火步驟完成後，非晶石夕層3 〇 2與非晶石夕層 3 04分別僅有底部的一部分轉變成結晶矽層3丨6與結晶矽層 318 ◊而^其餘尚未結晶的非晶矽層3 02與非晶矽層304則依舊維持非晶系結構，且分別成為非晶矽層3 2 〇位於結晶矽層 316上以及非晶矽層322位於結晶矽層318上，而形成如第5 圖所示之結構。其中，非晶矽層32〇以及非晶矽層322之厚度324較佳是控制在介於2〇奈米至60奈米之間。然後，進行矽化金屬步驟。首先，利用例如濺鍍沉積 < (Sputtering Deposition)的方式形成金屬層（未繪示）位於非晶石夕層3 2 0以及非晶矽層3 2 2上。其中，此金屬層之材料較佳可例如為始，且此金屬層之厚度係依據所欲形成之矽化金屬的厚度而定。接下來，利用例如快速熱回火的方式進行回火步驟，藉以使金屬層之金屬原子擴散到非晶矽層 3 2 0以及非晶矽層3 2 2中，而與非晶矽層3 2 0以及非晶石夕層 322反應，並在基材300之表面生成矽化金屬層326與石夕化金屬層328 ’如第6圖所示。本發明之"特被就是因為對非晶碎層進行不完全回火步驟，而使非晶石夕層之上面部分仍舊維持非晶系結構。由於，非晶石夕結晶時’差排等缺陷通常係在結晶末期才出現。於是，在進行矽化金屬反應時，不僅無差排，且用以進行矽化金屬反應之金屬層，係覆蓋在非晶系結構上，而使石夕化金屬反應不受結晶石夕之結晶方位與結晶缺陷的影^ b When the Shixi layer 3 02 and the amorphous silicon layer 3 04 are recrystallized from the amorphous structure, the '' starts to crystallize from the bottom of the amorphous silicon layer 302 and the amorphous silicon layer 3 04. Because the complete tempering step is not completed here, only a part of the amorphous silicon layer 3 02 and the amorphous stone layer 3 04 are respectively converted into a crystalline silicon layer 3 丨 6 and a crystalline silicon layer 318. ^ The remaining amorphous silicon layer 302 and amorphous silicon layer 304 still maintain the amorphous structure, and become amorphous silicon layers 3 2 0 on the crystalline silicon layer 316 and the amorphous silicon layer 322 on the crystalline silicon. On the layer 318, the structure shown in FIG. 5 is formed. Among them, the thickness 324 of the amorphous silicon layer 32 and the amorphous silicon layer 322 is preferably controlled between 20 nm and 60 nm. Then, a metal silicide step is performed. First, a metal layer (not shown) is formed on the amorphous silicon layer 3 2 0 and the amorphous silicon layer 3 2 2 by, for example, sputtering deposition (Sputtering Deposition). Among them, the material of the metal layer is preferably, for example, and the thickness of the metal layer is determined according to the thickness of the silicide metal to be formed. Next, a tempering step is performed using, for example, a rapid thermal tempering method, so that the metal atoms of the metal layer are diffused into the amorphous silicon layer 3 2 0 and the amorphous silicon layer 3 2 2 and the amorphous silicon layer 3 2 0 and the amorphous stone layer 322 react to generate a silicided metal layer 326 and a stoned metal layer 328 ′ on the surface of the substrate 300 as shown in FIG. 6. The reason of the present invention is that the incomplete tempering step is performed on the amorphous broken layer, so that the upper part of the amorphous stone layer still maintains the amorphous structure. This is because defects such as 'differential discharge' usually occur at the end of crystallization during the crystallization of amorphous stones. Therefore, when the silicidation metal reaction is performed, not only is there no difference, but the metal layer used for the silicidation metal reaction is covered on the amorphous structure, so that the petrified metal reaction is not affected by the crystal orientation and Shadow of crystal defects

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響，更可完全排除差排的影響。再加上，非晶矽層與之結晶矽層之界面在矽化金屬過程中，如同一擴散阻^下因此，可獲得高均勻度之矽化金屬層。早。由上述本發明較佳實施例可知’本發明之一優點就是在矽化金屬過程中，金屬層之矽化金屬步驟可在原子= 序排列的非晶矽層中進行，且非晶矽層與結晶層之界形成一擴散阻障。因此，可獲得厚度相當一致之金屬^ 層。 / ^上述本發明較佳實施例可知，本發明之又一優點就為非晶矽層之不完全回火步驟，.可避免差排產生。因此，在矽化金屬步驟期間，可排除差排對矽化金屬層之产八 ^的影響。如此-纟，可避免时化金屬層厚度不均= 尖峰狀（Spike)結構，進而可防止漏電流路徑的產生。此’可達消減接面漏電流的目的。本發明較佳實施例可知，本發明之再-優點就是因，金屬層之矽化金屬反應係在非晶系結構之非晶矽上進行，因此可排除結晶方位與結晶缺陷的影響。因此，不僅升石夕化金屬層之厚度一致性，更可獲得淺接面之匕金屬層，進而達到改善元件之性能的目的。定ϊ ^發月已以較佳貫施例揭露如上，然其並非用以限 r *明、’，任何熟習此技藝者，在不脫離本發明之精神和二二二當可作各種之更動與潤飾，因此本發明之保護範圍备視後附之申請專利範圍所界定者為準。 1225669 圖式簡單說明【圖式簡單說明】第1圖至第3圖係繪示習知矽化金屬層之製程剖面圖。第4圖至第6圖係繪示依照本發明一較佳實施例的一種矽化金屬層之製程剖面圖。元件代表符號簡單說明 200 基材 202 非晶矽層 204 非晶矽層 206 閘極 208 閘極介電層 210 導電層 212 間隙壁 214 結晶矽層 216 結晶矽層 218 差排 220 差排 222 矽化金屬層 224 矽化金屬層 300 基材 302 非晶矽層 304 非晶矽層 306 閘極 308 閘極介電層 _ ❿It can also completely eliminate the influence of the difference. In addition, the interface between the amorphous silicon layer and the crystalline silicon layer is under the same diffusion resistance during the silicidation process. Therefore, a highly uniform silicided metal layer can be obtained. early. According to the above-mentioned preferred embodiments of the present invention, one of the advantages of the present invention is that during the silicidation process, the silicidation metal step of the metal layer can be performed in an amorphous silicon layer with an atomic = sequential arrangement, and the amorphous silicon layer and the crystalline layer The boundary forms a diffusion barrier. Therefore, a metal layer having a fairly uniform thickness can be obtained. It can be seen from the foregoing preferred embodiments of the present invention that another advantage of the present invention is the incomplete tempering step of the amorphous silicon layer, which can avoid the occurrence of the differential discharge. Therefore, during the metal silicide step, the influence of the differential discharge on the yield of the metal silicide layer can be ruled out. In this way, the uneven thickness of the time-lapsed metal layer can be avoided = Spike structure, and the leakage current path can be prevented. This' can achieve the purpose of reducing the interface leakage current. It can be known from the preferred embodiment of the present invention that the re-advantage of the present invention is that the silicidation metal reaction of the metal layer is performed on amorphous silicon of an amorphous structure, so the effects of crystal orientation and crystal defects can be eliminated. Therefore, not only the consistency of the thickness of the metallization layer, but also the metal layer with a shallow junction can be obtained, thereby achieving the purpose of improving the performance of the device. Dingfa ^ fayue has been disclosed as above with better examples, but it is not used to limit r * Ming, ', anyone who is familiar with this skill can make various changes without departing from the spirit of the present invention and 222 And retouching, therefore, the scope of protection of the present invention is subject to the scope of the attached patent application. 1225669 Simple illustration of the drawings [Simplified illustration of the drawings] Figures 1 to 3 are cross-sectional views showing the process of the conventional silicided metal layer. 4 to 6 are cross-sectional views showing a process of manufacturing a silicided metal layer according to a preferred embodiment of the present invention. Simple description of component representative symbols 200 substrate 202 amorphous silicon layer 204 amorphous silicon layer 206 gate 208 gate dielectric layer 210 conductive layer 212 spacer 214 crystalline silicon layer 216 crystalline silicon layer 218 differential row 220 differential row 222 silicided metal Layer 224 metal silicide layer 300 substrate 302 amorphous silicon layer 304 amorphous silicon layer 306 gate 308 gate dielectric layer _ ❿

第12頁 1225669 圖式簡單說明 310 :導電層 31 2 :間隙壁 314 :厚度 31 6 :結晶矽層 3 1 8 :結晶矽層 320 :非晶矽層 322 :非晶矽層 324 :厚度 3 2 6 :矽化金屬層 3 2 8 :矽化金屬層1225669 on page 12 Simple illustration 310: conductive layer 31 2: spacer 314: thickness 31 6: crystalline silicon layer 3 1 8: crystalline silicon layer 320: amorphous silicon layer 322: amorphous silicon layer 324: thickness 3 2 6: silicided metal layer 3 2 8: silicided metal layer

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Claims

1225669 六、申請專利範圍 1· 一種矽化金屬層（Silicide Layer)之製造方法，至少包括：提供一基材，其中該基材之一表面至少已形成一#晶矽層 (Amorphous Silicon Layer); 進行一結晶步驟，藉以使部分之該非晶矽層轉變成一晶體層；以及對另一部分之該非晶矽層進行一矽化金屬步驟，而在該基材之該表面形成該石夕化金屬層。 2·如申請專利範圍第1項所述之矽化金屬層之製造方法，《其中該基材之材料為矽（Silicon)。 3 ·如申請專利範圍第1項所述之矽化金屬層之製造方法，其中形成該非晶矽層係利用一離子植入（Implantation) 法。 4·如申請專利範圍第1項所述之矽化金屬層之製造方法，其中該結晶步驟係一不完全回火步驟（Incomplete Anneal Step)，且該晶體層位於該#晶矽層之該另一部分下。丨 5 ·如申請專利範圍第1項所述之石夕化金屬層之製造方法，其中該結晶步驟係利用一快速熱回火（RTA)方式。 6 ·如申請專利範圍第1項所述之石夕化金屬層之製造方法，1225669 6. Scope of patent application 1. A method for manufacturing a silicide layer, including at least: providing a substrate, wherein at least one surface of the substrate has formed a #crystalline silicon layer (Amorphous Silicon Layer); A crystallization step is performed to convert a part of the amorphous silicon layer into a crystalline layer; and performing a metal silicide step on another part of the amorphous silicon layer to form the petrified metal layer on the surface of the substrate. 2. The method for manufacturing a silicided metal layer as described in item 1 of the scope of the patent application, wherein the material of the substrate is silicon. 3. The method for manufacturing a silicided metal layer as described in item 1 of the scope of the patent application, wherein the amorphous silicon layer is formed by an implantation method. 4. The method for manufacturing a silicided metal layer according to item 1 of the scope of the patent application, wherein the crystallization step is an Incomplete Anneal Step, and the crystal layer is located in the other part of the #crystalline silicon layer under.丨 5 The method for manufacturing a petrified metal layer as described in item 1 of the scope of patent application, wherein the crystallization step uses a rapid thermal tempering (RTA) method. 6 · The manufacturing method of Shixihua metal layer as described in item 1 of the scope of patent application,

第14頁 1225669 六、申請專利範圍其中該矽化金屬步驟至少包括：形成一金屬層覆蓋在該非晶矽層之該另一部分上；以及進行一熱處理步驟，藉以使該金屬層與該非晶矽層反應而形成該矽化金屬層。 7 ·如申請專利範圍第6項所述之矽化金屬層之製造方法，其中該金屬層之材料為始（Cobalt)。 8 ·如申請專利範圍第6項所述之矽化金屬層之製造方法，馨其中形成該金屬層之步驟係利用一濺鍍沉積（Sputtering Deposition)法。 9 ·如申請專利範圍第6項所述之矽化金屬層之製造方法’ 其中該熱處理步驟係一快速熱回火步驟。 10·如申請專利範圍第1項所述之石夕化金屬層之製级去其中該非晶矽層之厚度為100奈米（Nanometer)。 11·如申請專利範圍第1項所述之矽化金屬層之製二〇太法、，‘ 其中該非晶石夕層之該另一部分的厚度介於奈米多τ米之間。 12· —種矽化金屬層之製造方法，至少包括：曰石提供一基材，其中該基材之一表面至少已形成一井日曰矽Page 14 1225669 6. The scope of the patent application where the silicided metal step includes at least: forming a metal layer overlying the other part of the amorphous silicon layer; and performing a heat treatment step to make the metal layer react with the amorphous silicon layer The silicided metal layer is formed. 7 · The method for manufacturing a silicided metal layer as described in item 6 of the scope of patent application, wherein the material of the metal layer is Cobalt. 8. The method for manufacturing a silicided metal layer as described in item 6 of the scope of patent application, wherein the step of forming the metal layer is by a sputtering deposition method. 9 · The method for manufacturing a silicided metal layer according to item 6 of the scope of the patent application, wherein the heat treatment step is a rapid thermal tempering step. 10. The grade of the petrified metal layer described in item 1 of the scope of the patent application, wherein the thickness of the amorphous silicon layer is 100 nanometers. 11. As described in item 1 of the scope of the patent application, the method for manufacturing a silicided metal layer is 20 watts, ‘wherein the thickness of the other part of the amorphous stone layer is between nanometers and τ meters. 12 · —A method for manufacturing a silicided metal layer, at least comprising: a stone providing a substrate, wherein at least one well of silicon has been formed on one surface of the substrate;

第15頁 1225669 六、申請專到範圍 i行-第-回火步驟，藉以橡部分之該非晶矽層轉變成一晶體層，…一部分之該#晶石夕層位於該晶體層上；以 i該非晶矽層之該另一部分進行一矽化金屬步驟，而在該基材之該表面形成該矽化金屬廣。 13·如申請專利範圍第1 2項所述之矽化金屬層之製造方法，其中該基材之材料為;^。 _ 14. 如申請專利範圍第1 2項所述之石夕化金屬層之製造方法，其中形成該非晶矽層係利用一離子植入法。 15. 如申請專利範圍第1 2項所述之石夕化金屬層之製造方法，其中該第一回火步驟係〆不完全回火步驟。 16. 如申請專利範圍第1 2項所述之石夕化金屬層之製造方法，其中該第一回火步驟係利用一快速熱回火方式。鲁 17. 如申請專利範圍第1 2項所述之石夕化金屬層之製造方法，其中該矽化金屬步驟至少包括：形成一金屬層覆蓋在該非晶矽層之該另一部分上；進行一熱處理步驟，藉以使該金屬層與該非晶矽層反應而形成該矽化金屬層。Page 15 1225669 VI. Application specific line i-step-tempering step, by which the amorphous silicon layer of the rubber part is transformed into a crystalline layer, ... a part of the #crystal stone evening layer is located on the crystal layer; i The other part of the crystalline silicon layer is subjected to a metal silicide step, and the silicide metal is formed on the surface of the substrate. 13. The method for manufacturing a silicided metal layer as described in item 12 of the scope of the patent application, wherein the material of the substrate is; ^. _ 14. The method for manufacturing a petrified metal layer as described in item 12 of the scope of patent application, wherein the amorphous silicon layer is formed by an ion implantation method. 15. The method for manufacturing a petrified metal layer as described in item 12 of the scope of patent application, wherein the first tempering step is an incomplete tempering step. 16. The method for manufacturing a petrified metal layer as described in item 12 of the scope of patent application, wherein the first tempering step uses a rapid thermal tempering method. Lu 17. The method for manufacturing a petrified metal layer as described in item 12 of the scope of patent application, wherein the step of silicidating metal includes at least: forming a metal layer covering the other part of the amorphous silicon layer; performing a heat treatment In step, the metal silicide layer is formed by reacting the metal layer with the amorphous silicon layer.

第16頁以 5669 六、申請專利範圍 1 8·如申請專利範圍第丨7項所述之矽化金屬層之製造方去’其中該金屬層之材料為鈷。 19·如申請專利範圍第17項所述之石夕化金屬層之製造方法，其中形成該金屬層之步驟係利用一濺鍍沉積法。 20·如申請專利範圍第17項所述之矽化金屬層之製造方法，其中該熱處理步驟係一第二回火步驟。 21·如申請專利範圍第17項所述之矽化金屬層之製造方法’其中該熱處理步驟係利用一快速熱回火方式。 2 2 ·如申請專利範圍第1 2項所述之矽化金屬層之製造方法，其中該非晶矽層之厚度為1 0 0奈米。 2 3.如申請專利範圍第12項所述之矽化金屬層之製造方法，其中該非晶矽層之該另一部分的厚度介於20奈米至60 奈米之間。 24. —種矽化金屬層之製造方法，至少包括：提供一基材，其中該基材之一表面至少已形成一非晶矽層；進行一第一回火步驟，藉以使部分之該非晶矽層轉變成一Page 16 with 5669 6. Scope of Patent Application 18 • The method for manufacturing the silicided metal layer as described in item 丨 7 of the scope of patent application, wherein the material of the metal layer is cobalt. 19. The method for manufacturing a petrified metal layer as described in item 17 of the scope of patent application, wherein the step of forming the metal layer is by a sputtering deposition method. 20. The method for manufacturing a silicided metal layer according to item 17 of the scope of the patent application, wherein the heat treatment step is a second tempering step. 21. The method for manufacturing a silicided metal layer according to item 17 of the scope of the patent application, wherein the heat treatment step uses a rapid thermal tempering method. 2 2 · The method for manufacturing a silicided metal layer according to item 12 of the scope of the patent application, wherein the thickness of the amorphous silicon layer is 100 nm. 2 3. The method for manufacturing a silicided metal layer according to item 12 of the scope of the patent application, wherein the thickness of the other part of the amorphous silicon layer is between 20 nm and 60 nm. 24. A method for manufacturing a silicided metal layer, at least comprising: providing a substrate, wherein at least one amorphous silicon layer has been formed on a surface of the substrate; and performing a first tempering step to make a part of the amorphous silicon layer. Layer into one

第17頁 1225669 六、申請專利範圍晶體層’其中另一部分之該扑晶石夕層位於該晶體層上；形成一金屬層位於該非晶石夕廣之該另一部分上；以及進行一第二回火步驟，而在該基材之該表面形成該矽化金屬層。 2 5 ·如申請專利範圍第2 4項所述之矽化金屬層之製造方法’其中該基材之材料為矽。 26·如申請專利範圍第24項所述之矽化金屬層之製造方法，其中形成該非晶石夕層係利用一離子植入法。馨 27·如申請專利範圍第24項所述之矽化金屬層之製造方法’其中該第一回火步驟係一不完全回火步驟。 2 8.如申請專利範圍第2 4項所述之矽化金屬層之製造方法，其中該第一回火步驟係利用一快速熱回火方式。 2 9·如申請專利範圍第2 4項所述之矽化金屬層之製造方法，其中該金屬層之材料為#。 m 3 0·如申請專利範圍第24項所述之矽化金屬層之製造方法，其中形成該金屬層之步驟係利用一濺鍍沉積法。 31·如申請專利範圍第24項所述之矽化金屬層之製造方Page 17 1225669 VI. Patent application scope Crystal layer 'The other part of the pegmatite layer is located on the crystal layer; forming a metal layer on the other part of the amorphous stone set; and performing a second round A fire step is performed to form the silicided metal layer on the surface of the substrate. 2 5 · The method for manufacturing a silicided metal layer according to Item 24 of the scope of the patent application, wherein the material of the substrate is silicon. 26. The method for manufacturing a silicided metal layer according to item 24 in the scope of the patent application, wherein the amorphous stone layer is formed by an ion implantation method. Xin 27. The method for manufacturing a silicided metal layer according to item 24 of the scope of the patent application, wherein the first tempering step is an incomplete tempering step. 2 8. The method for manufacturing a silicided metal layer as described in item 24 of the scope of the patent application, wherein the first tempering step uses a rapid thermal tempering method. 29. The method for manufacturing a silicided metal layer as described in item 24 of the scope of patent application, wherein the material of the metal layer is #. m 3 0. The method for manufacturing a silicided metal layer as described in item 24 of the scope of patent application, wherein the step of forming the metal layer is by a sputtering deposition method. 31. The manufacturer of the silicided metal layer as described in item 24 of the scope of patent application

1225669 六、申請專利範圍法，其中該第二回火步驟係利用一快速熱回火方式。 32.如申請專利範圍第24項所述之矽化金屬層之製造方法，其中該非晶矽層之厚度為1 〇〇奈米。 3 3.如申請專利範圍第24項所述之矽化金屬層之製造方法，其中該非晶矽層之該另一部分的厚度介於20奈米至60 奈米之間。1225669 6. Patent application method, wherein the second tempering step uses a rapid thermal tempering method. 32. The method for manufacturing a silicided metal layer as described in item 24 of the scope of the patent application, wherein the thickness of the amorphous silicon layer is 1000 nm. 3 3. The method for manufacturing a silicided metal layer according to item 24 of the scope of the patent application, wherein the thickness of the other part of the amorphous silicon layer is between 20 nm and 60 nm.

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