1224859 _ 案號 92120560 _±_月 日 修正 五、發明說明（1) 發明所屬之技術領域 本發明係關於一種快閃記憶體，特別是有關一種具 對稱性選擇電晶體之快閃記憶體的布局。 ~ 先前技術 在一典型的快閃記憶體中，如第一圖所示，一快閃 &己憶體電路1 0包括^一 δ己憶胞陣列1 2，係由許多儲存電晶 體（storage transistor)構成，每一儲存電晶體稱為一 記憶胞（m e m 〇 r y c e 1 1 ) ，一 X解碼器j 4及一 Y解碼器1 6分別 從記憶胞陣列1 2的行及列方向選擇特定的記憶胞，被選 擇的記憶胞經由選擇電晶體1 8連接資料線DL，並由感測 放大器20偵測資料線DL的變化，與一參考胞（reference c e 1 1 )比較，於感測放大器2 0的輸出端產生資料信號 OUT 〇 第一圖的電路製作在晶片上時，將因為實際的積體 電路的差異而發生性能表現不同。第二圖係傳統的快閃 記憶體布局的不意圖’該佈局包括在一記憶胞陣列區域 30中，一埋藏擴散（buried diffusion)層34延伸經過擴 散區32，在一選擇電晶體區域4 0中的擴散區32上形成有 多晶矽閘極4 2及44，二者沿著平行記憶胞陣列區域3 〇的 方向延伸，在多晶矽閘極44兩側配置的源/汲極與閘極44 形成許多選擇電晶體4 0，以連接記憶胞陣列區域3 〇的埋 藏擴散層3 4，多晶矽閘極4 2及4 4受控使選擇電晶體導通 或關閉，以選擇特定的記憶胞，然而，由於多晶石夕閘極 4 2及4 4與記憶胞陣列區域3 0平行，導致各個選擇電晶體1224859 _ Case No. 92120560 _ ± _ Month Day Amendment V. Description of the Invention (1) Field of the Invention The present invention relates to a flash memory, and more particularly to the layout of a flash memory with symmetrically selected transistors . ~ The prior art in a typical flash memory, as shown in the first figure, a flash & memory circuit 1 0 includes a delta memory cell array 12 which is composed of many storage transistors (storage transistor), each storage transistor is called a memory cell (mem ryce 1 1), an X decoder j 4 and a Y decoder 16 select specific rows and columns from the memory cell array 12 respectively. Memory cell, the selected memory cell is connected to the data line DL via the selection transistor 18, and the change of the data line DL is detected by the sense amplifier 20, and compared with a reference cell (reference ce 1 1) in the sense amplifier 2 A data signal OUT is generated at the output end of 0. When the circuit of the first figure is fabricated on a chip, the performance will differ due to the actual integrated circuit. The second diagram is the intention of a conventional flash memory layout. The layout includes a memory cell array region 30, a buried diffusion layer 34 extending through the diffusion region 32, and a selective transistor region 40. Polysilicon gates 42 and 44 are formed on the diffusion region 32 in the middle, and both extend along the direction of the parallel memory cell array region 30. The source / drain and gate 44 arranged on both sides of the polysilicon gate 44 form many The transistor 40 is selected to connect the buried diffusion layer 3 4 of the memory cell array region 30, and the polysilicon gates 4 2 and 4 4 are controlled to turn on or off the selection transistor to select a specific memory cell. The spar gates 4 2 and 4 4 are parallel to the memory cell array region 3 0, resulting in various selection transistors.
第6頁 1224859 ___ 案號92120560 _年月曰 修正_ 五、發明說明（2) 彼此之間對記憶胞陣列區域3 0不對稱，多晶矽閘極4 2及 4 4的兩側，藉由接觸窗4 8連接埋藏擴散層3 4及選擇電晶 體的汲/源極。選擇電晶體不對稱的特性容易造成許多不 利的效應，例如不同的選擇電晶體之間的速率不相同， 可能使性能表現劣化。因此，一種具有對稱性選擇電晶 體之快閃記憶體的布局，乃為所翼。 發明内容 本發明的目的，在於提出一種具有對稱性選擇電晶 體之快閃記憶體。 根據本發明，一種具對稱性選擇電晶體之快閃記憶 體的布局，包括一記憶胞陣列，以及一條與許多選擇電 晶體相關的多晶矽閘極，該多晶矽閘極係以垂直於該記 憶胞陣列的方向延伸，使得該許多選擇電晶體對該記憶 胞陣列大體上為對稱者。 實施方式 第三圖係本發明的快閃記憶體布局的示意圖，其包 括在一記憶胞陣列區域5 0中的擴散區5 2，一埋藏擴散層 54延伸經過擴散區52，一選擇電晶體區域60含有多晶矽 閘極6 2及6 4，二者互相平行且以垂直於記憶胞陣列區域 5 0的方向延伸，一金屬導線7 0從記憶胞陣列區域5 0延伸 至多晶矽閘極6 2的一側，分別經接觸窗6 5及6 6連接埋藏 擴散層54及選擇電晶體69的源極，另一金屬導線72在多 晶矽閘極6 2及6 4之間延伸，經接觸窗6 8連接選擇電晶體Page 6 1224859 ___ Case No. 92120560 _Year Month Amendment _ V. Description of the Invention (2) The memory cell array area 30 is asymmetric to each other, and the sides of the polysilicon gates 4 2 and 4 4 are contacted by a window. 4 8 connects the buried diffusion layer 34 and the drain / source of the selection transistor. The asymmetry of the transistor selection is likely to cause many adverse effects. For example, the different rates of different transistor selections may degrade performance. Therefore, the layout of a flash memory with a symmetrical selection of electrical crystals is what is needed. SUMMARY OF THE INVENTION The object of the present invention is to provide a flash memory having a symmetrically selected electric crystal. According to the present invention, a layout of a flash memory with a symmetrical selection transistor includes a memory cell array and a polycrystalline silicon gate associated with a plurality of selected transistors. The polycrystalline silicon gate is perpendicular to the memory cell array. The direction of the extension is such that the plurality of selection transistors are substantially symmetrical to the memory cell array. The third embodiment is a schematic diagram of the flash memory layout of the present invention, which includes a diffusion region 52 in a memory cell array region 50, a buried diffusion layer 54 extending through the diffusion region 52, and a selected transistor region. 60 contains polysilicon gates 6 2 and 64, which are parallel to each other and extend in a direction perpendicular to the memory cell array region 50. A metal wire 70 extends from the memory cell array region 50 to a polysilicon gate 6 2 On the side, the source of the buried diffusion layer 54 and the selection transistor 69 are connected via the contact windows 65 and 66, respectively. Another metal wire 72 extends between the polysilicon gate electrodes 62 and 64, and is connected via the contact window 68. Transistor
1224859 ___案號92120560_年月曰 修正_ 五、發明說明（3) 6 9的汲極，埋藏擴散層5 4係作為記憶胞的位元線。多晶 矽閘極6 2及64分別經由接觸窗74及76輸入電壓，以控制 多晶矽閘極6 2及6 4各自對應的選擇電晶體導通，進而選 擇特定的記憶胞供存取，而接觸窗74及7 6採取相對配置 設計，以減少選擇電晶體所佔的面積。 在本發明的快閃記憶體布局中，由於多晶矽閘極6 2 及6 4垂直於記憶胞陣列區域5 0，使得在多晶矽閘極6 2及 6 4兩側形成的選擇電晶體對記憶胞陣列區域5 0大體上為 對稱性的。由於本發明的快閃記憶體具有對稱性的選擇 電晶體，可以改善傳統的快閃記憶體選擇電晶體的不對 稱所導致的缺點，及其所衍生的各種效應。 以上對於本發明之較佳實施例所作的敘述係為闡明 之目的，而無意限定本發明精確地為所揭露的形式，基 於以上的教導或從本發明的實施例學習而作修改或變化 是可能的，實施例係為解說本發明的原理以及讓熟習該 項技術者以各種實施例利用本發明在實際應用上而選擇 及敘述，本發明的技術思想企圖由以下的申請專利範圍 及其均等來決定。1224859 ___Case No. 92120560_Year Month Amendment_ V. Description of the invention (3) The drain of 6 9 is buried with the 5 4 line as the bit line of the memory cell. The polysilicon gates 6 2 and 64 input voltages through the contact windows 74 and 76, respectively, to control the corresponding selection transistors of the polysilicon gates 6 2 and 64 to be turned on, and then select specific memory cells for access. The contact windows 74 and 7 6 Adopt relative configuration design to reduce the area occupied by the selection transistor. In the flash memory layout of the present invention, since the polycrystalline silicon gate electrodes 6 2 and 64 are perpendicular to the memory cell array region 50, the selective transistor formed on both sides of the polycrystalline silicon gate electrodes 6 2 and 64 are formed on the memory cell array. The region 50 is generally symmetrical. Since the flash memory of the present invention has a symmetrical selection transistor, the disadvantages caused by the asymmetry of the conventional flash memory selection transistor and the various effects derived therefrom can be improved. The above description of the preferred embodiments of the present invention is for the purpose of clarification, and is not intended to limit the present invention to exactly the disclosed form. Modifications or changes are possible based on the above teachings or learning from the embodiments of the present invention. The embodiments are selected and described in order to explain the principle of the present invention and allow those skilled in the art to use the present invention in practical applications in various embodiments. The technical idea of the present invention is intended to be covered by the following patent application scopes and their equivalents. Decide.
1224859 —_案號92120560 年月曰 修正_ 圖式簡单說明 對於熟習本技藝之人士而言，從以下所作的詳細敘 述配合伴隨的圖式，本發明將能夠更清楚地被瞭解，其 上述及其他目的及優點將會變得更明顯，其中： 第一圖係一個典型的快閃記憶體電路的示意圖； 第二圖係傳統的快閃記憶體布局的示意圖；以及 第三圖係本發明的快閃記憶體布局的示意圖。 圖號說明 10 快閃記憶體電路 12 記憶胞陣列 14 X解碼器 16 Y解碼器 18 選擇電晶體 2 0 感測放大器 30 記憶胞陣列區域 32 擴散區 34 埋藏擴散層 40 選擇電晶體區域 4 2 多晶發閘極 44 多晶矽閘極 48 接觸窗 50 記憶胞陣列區域 5 2 擴散區 54 埋藏擴散層1224859 —_Case No. 92120560 Revised _ Brief Description of the Drawings For those skilled in the art, the present invention will be more clearly understood from the detailed descriptions and accompanying drawings made below. Other objects and advantages will become more obvious, among which: the first diagram is a schematic diagram of a typical flash memory circuit; the second diagram is a schematic diagram of a conventional flash memory layout; and the third diagram is a schematic diagram of the present invention Schematic diagram of flash memory layout. Description of drawing number 10 Flash memory circuit 12 Memory cell array 14 X decoder 16 Y decoder 18 Select transistor 2 0 Sense amplifier 30 Memory cell array area 32 Diffusion area 34 Buried diffusion layer 40 Select transistor area 4 2 Multi Transistor gate 44 Polycrystalline silicon gate 48 Contact window 50 Memory cell array region 5 2 Diffusion region 54 Buried diffusion layer
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