TW592017B

TW592017B - Manufacturing method of multi-layer circuit board

Info

Publication number: TW592017B
Application number: TW92109135A
Authority: TW
Inventors: Ming-Hsing Liu; Ming-Hsiang Yang; Yuan-Fa Chu; Lu-Lin Hung
Original assignee: Giga Byte Tech Co Ltd; Neo Led Technology Co Ltd
Priority date: 2003-04-18
Filing date: 2003-04-18
Publication date: 2004-06-11
Also published as: TW200423845A

Abstract

There is provided a manufacturing method of multi-layer circuit board, which comprises providing a metal substrate as the substrate of the multi-layer circuit board; forming an insulating layer with a buffer surface having micro holes on the metal substrate; then forming a circuit layer on the buffer surface; and repeatedly forming the insulating layer and circuit layer to manufacture a multi-layer circuit to conform to the trend of high-density circuit.

Description

592017 五、發明說明（1) :發明所屬之技術領域】於本發明是關於一種多層電路板之製造方法，特別是關種應用半導體技術的多層電路板之製造。【先前技術】 “在電子系統產品中，一般習知用以承載電子元件之印592017 V. Description of the invention (1): The technical field to which the invention belongs] The present invention relates to a method for manufacturing a multilayer circuit board, and particularly to the manufacture of a multilayer circuit board using semiconductor technology. [Prior art] "In electronic system products, it is generally known

Clrcuit Board，PCB)，通常使用玻 m或軟性基材作為基底，再於基底印刷上導電層。藉由一膠合製程，將複數個電路板的製作。層化’經加工處理’完成多層印刷念，印刷電路杯^ έ電子產品走向「輕薄短小」之設計概發展，其中，夕；月向小孔徑、高密度、多層數、細線路方案，但如要$】J =電路板為提高線路密度的良好解決對提高，習知之夕:σ超南密度的趨勢，其製程難度也相求。夕層電路板製程逐漸難以符合現今的需此外，常用之敕〜壓法，塗佈法係於鋼Γ、卜5箔電路板製造方法為‘塗佈法或熱經高溫硬化之後，再=，塗佈一層薄的高接著性樹脂， (Polyinude)以增加'"上第二層較厚的聚亞醯胺樹脂此方法需進行兩次塗佈板制剛性，再進行一次高溫硬化。不能太薄。熱壓法為以取製程成本較高，且其銅箔的厚度一層熱可塑性聚亞醯r #亞醯胺樹脂膜作為基材，先塗上於已硬化之熱可塑性=炉經高溫硬化之後，再將銅箱放置醯胺重新熔融與鋼箔屙二上，利用高溫高壓將可塑性聚亞 _ 土〇，熱壓法製程對於基材的厚度無 592017Clrcuit Board (PCB), usually using a glass substrate or a flexible substrate as a substrate, and then printing a conductive layer on the substrate. Through a gluing process, a plurality of circuit boards are manufactured. Layered 'processed' to complete multi-layer printing concepts, printed circuit cups ^ hand electronic products towards the design of "thin, thin and short", among them, evening; moon direction small aperture, high density, number of layers, thin circuit scheme, but If you want $] J = circuit board is a good solution to increase the density of the circuit, and the habit of knowing: the trend of σ super south density, the process difficulty is also the same. The manufacturing process of evening circuit boards is gradually difficult to meet today's needs. In addition, the common method is the pressing method. The coating method is based on steel Γ and Bu 5 foil circuit boards. The manufacturing method is' coating method or thermally hardened at high temperature, and then =, Apply a thin layer of highly adhesive resin (Polyinude) to increase the "upper second layer of thicker polyurethane resin." This method requires two coatings to make the board rigid, and then high temperature hardening. Not too thin. The hot pressing method is based on the high cost of the manufacturing process, and the thickness of the copper foil is a layer of a thermoplastic polyimide r #imidine resin film as a substrate, which is first coated on the hardened thermoplastic = high temperature hardening of the furnace. Then the copper box was placed on melamine and remelted on the steel foil, and the plasticity was plasticized using high temperature and pressure. The thickness of the substrate for the hot pressing process was 592017.

五、發明說明（2) 法降低。無論是塗佈法或熱壓要再塗佈介電層並壓合銅箱，再製程中需以機械或雷射方式以作為多層電路之導電孔。習小孔徑、咼密度、細線路之多印刷多層電路板大多需利金屬層或銅箔等高導熱性質的板的熱傳導性質，以及抑制電 magnetic interference, EMI 加入含有i素的難燃劑，‘而難全面禁用鹵素的規定，將限制往添加離子性不純物，使基板及在高溫下容易造成基板扭曲可靠度。同時，接著劑會因為層電路板之金屬接著介面強度程中減少甚至避免接著劑的使趨勢。 '、’欲製作多層電路板皆需乂形成夕層電路板，同時， f介電層鑽孔，再填入金屬 σ的多層電路板製程在製作層電路板，有其一定限制。用接著劑或熱壓方式，貼附材料’來改善印刷多層電路磁干擾現象（eleCtr〇 )。但是接著劑的配方中需以符合歐盟2 0 0 4年電子產品其未來發展。且接著劑中往的介電及絕緣特性變差，以變形’這些都會降低基板的化學品的侵融，使得印刷多下降。所以如何在電路板製用’成為多層電路板的發展【發明内容】為改進習知技術的缺點，本發明揭露一種多層電才反之製造方法。係應用已相當成熟之半導體製程來製作多居電路板，以符合高密度電路的趨勢。曰本發明之多層電路板之製造方法，其步驟包含右.，供一金屬基材；於金屬基材之表面形成具有緩衝表而緣層’其緩衝表面具有微孔洞，於絕緣層表面形成電路^V. Description of the invention (2) Method reduction. Regardless of the coating method or hot pressing, the dielectric layer needs to be recoated and the copper box is pressed. In the remanufacturing process, mechanical or laser methods must be used as conductive holes of the multilayer circuit. Xi ’s small-aperture, high-density density, and thin-line printed multilayer circuit boards mostly require the thermal conductivity of high-thermal-conductivity boards such as metal layers or copper foils, and the suppression of electromagnetic interference. EMI contains flame retardants containing the element I, ' It is difficult to completely ban the regulations of halogen, which will restrict the addition of ionic impurities, and make the substrate and the reliability of substrate distortion easily at high temperature. At the same time, the adhesive will reduce or even avoid the tendency of the adhesive due to the strength of the metal bonding interface of the circuit board. ',' To make a multilayer circuit board, it is necessary to form a multi-layer circuit board. At the same time, the f dielectric layer is drilled and then filled with metal σ. The process of making a multilayer circuit board has certain limitations. Adhesives or adhesives are used to improve the magnetic interference (eleCtr0) of printed multilayer circuits. However, the formulation of the adhesive must comply with the future development of EU electronics products in 2004. In addition, the dielectric and insulating properties of the adhesive are deteriorated, and deformation will reduce the invasion of chemicals on the substrate, which will reduce the printing. So how to use it in the manufacture of circuit boards becomes the development of multi-layer circuit boards. [Abstract] In order to improve the shortcomings of the conventional technology, the present invention discloses a method for manufacturing multi-layered electric cells and vice versa. It is based on the application of a well-established semiconductor process to fabricate multi-resident boards to meet the trend of high-density circuits. The manufacturing method of the multilayer circuit board of the present invention includes the steps of: providing a metal substrate; forming a buffer layer on the surface of the metal substrate and an edge layer ', wherein the buffer surface has micro holes, and is formed on the surface of the insulating layer; Circuit ^

第6頁 592017 五、發明說明（3) 層，然後重複於電路層表面形層數’以完成多層電路板。本發明更包含多層雙面電含有.提供一金屬基材；於金衝表面之上絕緣層，其緩衝表表面製作一上電路層；再於金衝表面之下絕緣層，其緩衝表表面製作一下電路層；然後重面形成絕緣層和電路層至所需路板。欲增加絕緣層和電路層的緩衝表面，亦可對絕緣層進行方設置電路層，以增進絕緣層本發明可藉由熱氧化、陽層的表面形成絕緣層，或是化法沉積於金屬基材表面。電路氣相沈積法、物理氣相沉積法技術來完成。再配合光微影技本發明係以金屬基材作為基材形成具有緩衝表面之絕緣其上方再配合光微影技術形成的表面黏著與電性連接之用。後’最後，可再增加金屬披覆矣巴緣層之緩衝表面能增加成絕緣層和電路層至所需的路板之製造方法，其步驟包屬基材之上表面形成具有緩面具有微孔洞；於上絕緣層屬基材之下表面形成具有緩面具有微孔洞；於下絕緣層複於上電路層和下電路層表的層數，以完成多層雙面電附著力，除了於絕緣層製作適當的表面處理，再於其上和電路層之附著力。極氧化和滲氮等方法使電路學沈積法或物理沉積法等方層和金屬披覆層可應用化學、電鍍和無電鍍法等半導體術可製作出高密度電路。夕層電路板的基材，於金屬層’緩衝表面具有微孔洞，電路層，電路層係作為元件電路層表面形成絕緣層之層來隔絕電磁干擾。電路層的附著力，從而省去Page 6 592017 V. Description of the invention (3) layer, and then repeat the number of layers on the surface of the circuit layer to complete the multilayer circuit board. The invention further includes multiple layers of double-sided electrical components. A metal substrate is provided; an insulating layer is formed on the surface of the gold stamping, and an upper circuit layer is made on the surface of the buffer surface; The circuit layer is lowered; then the insulating layer and the circuit layer are formed on the other side to the required circuit board. To increase the buffer surface of the insulating layer and the circuit layer, the insulating layer can be provided with a circuit layer to improve the insulating layer. The present invention can form an insulating layer by thermal oxidation, the surface of the positive layer, or chemically deposited on a metal substrate.材表面。 Wood surface. Circuit vapor deposition, physical vapor deposition technology to complete. The present invention relates to the use of a metal base material as a base material to form an insulation with a buffer surface, and the surface formed by using the photolithography technology above the surface is adhered and electrically connected. After 'Finally, the buffer surface of the metal-coated edge layer can be further increased to form an insulating layer and a circuit layer to the required circuit board manufacturing method. The steps include forming the upper surface of the substrate with a gentle surface and a micro Holes; formed on the lower surface of the upper insulating layer with a slow surface with micro holes; the lower insulating layer is covered with the number of layers on the upper circuit layer and the lower circuit layer surface to complete the multilayer double-sided electrical adhesion, except Make an appropriate surface treatment on the insulating layer, and then attach it to the circuit layer. Methods such as polar oxidation and nitridation allow high-density circuits to be produced by applying semiconductors such as chemical, electroplating, and electroless plating methods to metal-clad layers such as circuit deposition or physical deposition. The base material of the circuit board of the evening layer has micro holes in the buffer layer of the metal layer. The circuit layer and the circuit layer are used as components to form an insulating layer on the surface of the circuit layer to isolate electromagnetic interference. Circuit layer adhesion, thus eliminating

592017 五、發明說明（4) 接著劑的使用，其緩衝表运可藉由表面處理絕緣絕緣層表面鍍上具有微孔祠結構之薄層形成。疋於路板結構中增加金屬彼覆層能更有效隔絕電磁2 = f電以達到本發明的目的。 τ ?支現象，為使對本發明的目的、構造特徵及其功能了解，茲配合圖示詳細說日月如下： V的【實施方式】本發明揭露-種多層電路板之製造方體製程來製作多層電路板，並配合 =用覆使基材表面之絕緣層具有一緩衝表基材的附著力。叩奴幵電路層與請參考第1圖至第4圖，並夂士八nR Μ 流程示意圖。〃、為本赉月弟—實施例之製作 JL;: 一紹金屬基材1〇,如第1圖所示，… 陽極處理以形成均勾之氧化銘絕緣層上Γ緣層11表層形成具有微孔洞之緩衝表面面產生陽極處理之後，會溶解和沉積在處理表到緻密：：面之：：：：此一般需再經封孔處理才能得 H ,, J 發明貫施例則利用此陽極處理之特性，使氧化鋁绢崚厣吝A τ ^ 如笛9二具有微孔洞之緩衝表面。供扪^々圖戶斤示，於緩衝表面進行表面活化步驟，再析 :孔洞可增加銅電路層2〇的附著力。其銅電路層可土而〃路的區域上抗電鍍阻劑，再進行化學析鍍來完592017 V. Description of the invention (4) The use of adhesive, its buffer surface can be formed by surface treatment, insulation, and the surface of the insulation layer is plated with a thin layer with a microporous temple structure. Adding metal cladding layers to the board structure can more effectively isolate the electromagnetic 2 = f electricity to achieve the purpose of the present invention. In order to understand the purpose, structural features, and functions of the present invention, the sun and the moon are described in detail with the illustrations below: V [Embodiment] The present invention discloses a method for manufacturing a multilayer circuit board. Multi-layer circuit board, and cooperating with the coating layer to make the insulating layer on the surface of the substrate have a buffering surface adhesion.叩幵幵 Circuit layer and Please refer to Figure 1 to Figure 4, and Figure 8 schematic diagram of nR Μ flow. 〃, this month's brother—Example of production of JL ;: Yi Shao metal substrate 10, as shown in Figure 1,… anodized to form a uniform oxide layer on the insulating layer Γ edge layer 11 surface layer has After the microporous buffer surface is anodized, it will dissolve and deposit on the treatment surface to be dense :: Surface :::: This generally requires a hole sealing treatment to obtain H ,, J. Inventive examples use this The characteristics of anodic treatment make the alumina silk 崚厣吝 A τ ^ as the flute 92 has a microporous buffer surface. As shown in the figure, the surface activation step is performed on the buffer surface, and reanalysis: the holes can increase the adhesion of the copper circuit layer 20. The copper circuit layer can resist the plating resist on the soil and the road area, and then perform chemical plating to complete

592017 五、發明說明（5) 成或疋利用光微影技術蝕刻铜金屬層以形成電路。 "此時，如第3圖所示，於電路層2〇之表層施以適當之 W匕處理，於電路層2〇表面形成絕緣層21。旅同樣地形成二層，路層20 =絕緣層21之組合，以形成四層電路板。 μ :後’如第4圖所示，沉積-金屬披覆層30於電路層上方，以作為避免雜訊干擾的保護層。 ®制2同樣的方法’本發明可同時在金屬基材的上下表 2電路:如第5圖所示，其為本發明第二實施例 tI不思圖，係為一雙層雙面電路板。係金屬基材1 0之592017 V. Description of the Invention (5) Cheng or Xi uses photolithography to etch the copper metal layer to form a circuit. " At this time, as shown in FIG. 3, an appropriate W treatment is applied to the surface layer of the circuit layer 20 to form an insulating layer 21 on the surface of the circuit layer 20. The brigade similarly forms two layers, a combination of a road layer 20 = an insulating layer 21 to form a four-layer circuit board. μ: Back 'As shown in Fig. 4, the metal-cladding layer 30 is deposited over the circuit layer as a protective layer to prevent noise interference. The same method for making 2 ® The present invention can simultaneously load the following two circuits on the metal substrate: as shown in FIG. 5, it is a schematic diagram of the second embodiment tI of the present invention and is a double-sided double-sided circuit board . Metal base material 1 of 0

下表2分別進行陽極處理以形成均勻之氧化紹絕緣層 12:2氧化紹絕緣層11表層形成具有微孔洞之緩衝表面表面报層20之表層施以適當之氧化處理，於電路層20 絕缘絕緣層，以分別於上下表面形成兩層電路層20和組合，形成雙層雙面電路分別禚包覆金屬披覆層30。成彳％ 3、_ €之、、爰衝表面可籍由表面處理絕緣層使其表面形研；Ϊ;砂在絕緣層之表層進行表面處理，如表面 J Γ…里等，則可得到緩衝表面。The following Table 2 is separately anodized to form a uniform oxide insulation layer 12: 2 The oxide insulation layer 11 The surface layer is formed with a buffer surface with micro holes The surface layer 20 The surface layer is subjected to an appropriate oxidation treatment, and the circuit layer 20 is insulated The insulating layer is formed by forming two circuit layers 20 and a combination on the upper and lower surfaces, respectively, to form a double-layered double-sided circuit and respectively covering the metal coating layer 30.彳% 3, _ €, 爰, the surface can be ground by the surface treatment of the insulation layer; Ϊ; sand on the surface of the insulation layer surface treatment, such as the surface J Γ ..., etc., can be buffered surface.

械工I疋=纟巴緣層表面製作具有微孔洞結構之薄層。在機料賦與某稀=工業或半導體工業領域，為了對所使用的材殊性質的祜二=，常在材料表面上以各種方法形成具有特子的層膜。進行薄膜沈積處理時，需以原子或分熱平衡狀^鉦材=粒子使其形成薄膜，因此，可以得到以〜、然去得到的具有特殊構造及功能的薄膜。如直A thin layer with a micro-hole structure is made on the surface of the mechanics I 疋 = 纟巴缘层. In the field of materials and materials, industrial or semiconductor industries, in order to make a difference in the properties of the materials used, a layer film with characteristics is often formed on the surface of the material in various ways. When performing a thin film deposition process, it is necessary to form a thin film with atomic or thermal equilibrium ^ 钲 = particles to form a thin film. Therefore, a thin film having a special structure and function can be obtained by ~~. As straight

第9頁 592017 五、發明說明（6) 接在其絕緣層表覆成型法、化學法、無電鍍法、 Gel Synthesis ) 本發明之電材料，並應用化無電鍍法等半導式亦可透過膠合上方膠合元件或面處理，再於其之附著力。絕緣化物等絕緣物質緣層的方式很多極處理等。絕緣表面活化的步驟活化或敏化處理度’即増加電路力。舉例來說，可利用離子鈀化使絶吸附在表面雖然本發明以限定本發明，精神和範圍内，專利保護範圍須面製作具有微孔氣相沈積法、氣化學液相合成法等技術來完成< 路層和金屬彼覆學氣相沈積法、體技術來完成。以產生離子元素多層電路層。或上方設置電路層層可為金屬基材，以及陶瓷或高 ’可包含熱氧化層表面不容易附 ’活化基材表面之後，所發揮的層（塗佈、析鍛、一般在絕緣層上合物溶液或膠體形成活化位置，之較佳實施例揭任何熟習相關技當可作些許之更視本說明書所附 ’同結構之薄相凝結法、和溶液〜凝 > 層可為鋼、物理氣相沉絕緣層和電來接著，或疋對絕緣層，以増進絕之化合物，分子等絕緣法、滲氮、耆其他物質或使純性表主要功能為 ' 積）與絕進行化學鍍鈀活化劑進以利於後續露如上所^ 藝者，在不動與潤飾’ 之申請專利層，可利用喷分子束磊晶膠法（Sol- 金和銀等導電積法、電鍍和路層的接合方藉以於電路層進行適當的表緣層和電路層如氧化物或氮材料。形成絕氣相沉積、陽 ’所以可經過面敏感化。經增加附著強緣層間的附著金屬層之前，行敏化處理，的析鍍反應。 ’然其並非用脫離本發明之因此本發明之範圍所界定者Page 9 592017 V. Description of the invention (6) The semiconductive type such as the electroforming material of the present invention and the application of electroless plating method can also be transmitted through the insulating layer surface forming method, chemical method, electroless plating method, and Gel Synthesis. Glue the component or surface to be glued on top, and then adhere to it. Insulating materials such as insulating materials have many types of edge layers, such as electrode treatment. The step of insulation surface activation is the degree of activation or sensitization, i.e., the applied circuit force. For example, ionic palladium can be used to make absolute adsorption on the surface. Although the present invention is to limit the present invention, the scope and scope of the patent must be protected by the technology of microporous vapor deposition, gas chemical liquid phase synthesis, etc. &Lt; Road layers and metal overlays are learned by vapor deposition and bulk technology. To produce ionic elements, multilayer circuit layers. Or the circuit layer on top may be a metal substrate, and ceramic or high may include a thermally oxidized surface that is not easily attached to the surface of the activated substrate after activation (coating, forging, and generally bonding on an insulating layer) Solution or colloid to form an activated site, the preferred embodiment reveals that any familiarity with related techniques can be slightly changed depending on the thin phase coagulation method of the same structure attached to this specification, and the solution ~ coagulation layer can be steel, physical Vapor-sinking insulation layer and electricity come next, or insulate the insulation layer with advanced compounds, molecules and other insulation methods, nitriding, other substances or make the purity meter's main function to be 'product') and insulation with electroless palladium plating The activator is used to facilitate the subsequent exposure of the artist as above. In the application and patent layer of immobility and retouching, the molecular beam epitaxial method (Sol-gold and silver and other conductive deposition methods, electroplating and bonding methods of road layers) can be used. Based on the circuit layer, the appropriate surface edge layer and circuit layer such as oxide or nitrogen materials are formed. Adiabatic vapor deposition and positive electrode can be formed, so the surface can be sensitized. By increasing the adhesion between the strong edge layers, Before the metal layer, line sensitization treatment, plating evolution reaction. 'However, it is not departing from the present invention with the scope of the invention is therefore defined by

第10頁 592017P. 10 592017

592017 圖式簡單說明弟1圖至第4圖為本發第一實施例之製作流程示意圖；及第5圖為本發明第二實施例之結構示意圖。【圖式符號說明】592017 Brief Description of Drawings Figures 1 to 4 are schematic diagrams of the manufacturing process of the first embodiment of the present invention; and Figure 5 is a structural diagram of the second embodiment of the present invention. [Illustration of Symbols]

II

10 金屬基材 11 絕緣層 12 緩衝表面 20 電路層 21 絕緣層 30 金屬彼覆層第12頁10 Metal substrate 11 Insulating layer 12 Buffer surface 20 Circuit layer 21 Insulating layer 30 Metal-to-metal coating page 12

Claims

592017 六、申請專利範圍 1. 一種多層電路板之製造方法，其步驟包含有： (a) 提供一金屬基材； (b) 於該金屬基材之表面形成一絕緣層，其具有一緩衝表面，該緩衝表面具有微孔洞； (c) 於該絕緣層表面製作一電路層； (d) 於該電路層表面形成另一絕緣層；及 (e )重複一次以上步驟（c )至步驟（d)。 2. 如申請專利範圍第1項所述之電路板之製造方法，其中更包含一於最頂端之該絕緣層上方沉積一金屬彼覆層的步驟。 3. 如申請專利範圍第2項所述之電路板之製造方法，其中該於最頂端之該絕緣層上方沉積一金屬彼覆層的步驟，係以化學氣相沈積法、物理氣相沉積法、電鍍和無電鍍法其中之一方法完成。 4. 如申請專利範圍第2項所述之電路板之製造方法，其中該金屬彼覆層材料係選自銅、金和銀所組成的族群其中 ^ 0 5. 如申請專利範圍第1項所述之多層電路板之製造方法，其中該步驟（b )和該步驟（d ) 5係氧化該金屬基材之表層以形成該絕緣層。 6. 如申請專利範圍第1項所述之多層電路板之製造方法，其中該步驟（b )和該步驟（d)’係〉夢氣進入該金屬基材之表層以形成該絕緣層。 7. 如申請專利範圍第1項所述之多層電路板之製造方法，592017 VI. Scope of patent application 1. A method for manufacturing a multilayer circuit board, the steps include: (a) providing a metal substrate; (b) forming an insulating layer on the surface of the metal substrate, which has a buffer surface , The buffer surface has micro-holes; (c) making a circuit layer on the surface of the insulating layer; (d) forming another insulating layer on the surface of the circuit layer; and (e) repeating steps (c) to step ( d). 2. The method for manufacturing a circuit board according to item 1 of the scope of patent application, further comprising a step of depositing a metal-on-metal layer on the topmost insulating layer. 3. The method for manufacturing a circuit board according to item 2 of the scope of the patent application, wherein the step of depositing a metal-on-metal layer over the topmost insulating layer is performed by a chemical vapor deposition method or a physical vapor deposition method. One of the methods of electroplating, electroplating, and electroless plating is completed. 4. The method for manufacturing a circuit board as described in item 2 of the scope of the patent application, wherein the metal-clad material is selected from the group consisting of copper, gold and silver ^ 0 5. As described in the first scope of the patent application The manufacturing method of the multilayer circuit board described above, wherein the step (b) and the step (d) 5 are to oxidize the surface layer of the metal substrate to form the insulating layer. 6. The method for manufacturing a multilayer circuit board according to item 1 of the scope of patent application, wherein step (b) and step (d) 'are> dream gas enters the surface layer of the metal substrate to form the insulating layer. 7. The manufacturing method of the multilayer circuit board as described in item 1 of the scope of patent application,

第13頁 592017 六、申請專利範圍其中該絕緣層係選自陶瓷材料和高分子材料所組成的族群其中之一。 8. 如申請專利範圍第1項所述之多層電路板之製造方法，其中該絕緣層之該緩衝表面係由一表面處理所形成。 9. 如申請專利範圍第8項所述之多層電路板之製造方法，其中該表面處理係選自表面研磨和噴砂處理其中之一方法。 1 0.如申請專利範圍第1項所述之多層電路板之製造方法，其中該絕緣層之該緩衝表面係由一具有微孔洞結構之薄層所形成。 11.如申請專利範圍第1 0項所述之多層電路板之製造方法，其中該具有微孔洞結構之薄層係由喷覆成型法、化學氣相沈積法、氣相凝結法、分子束蠢晶法、無電鍍法、化學液相合成法及溶液一凝膠法其中之一方法所形成。 1 2.如申請專利範圍第1項所述之多層電路板之製造方法，其中該於該絕緣層表面製作一電路層的步驟，係於該絕緣層表面不需電路的區域上抗電鍍阻劑，再於該絕緣層表面進行化學析鍍來完成。 1 3.如申請專利範圍第1項所述之多層電路板之製造方法，其中該於該絕緣層表面製作一電路層的步驟，係沉積一金屬層於該絕緣層表面，再以光微影製程#刻該金屬層。 1 4.如申請專利範圍第1 3項所述之多層電路板之製造方Page 13 592017 6. Scope of patent application The insulation layer is selected from one of the groups consisting of ceramic materials and polymer materials. 8. The method for manufacturing a multilayer circuit board according to item 1 of the scope of patent application, wherein the buffer surface of the insulating layer is formed by a surface treatment. 9. The method for manufacturing a multilayer circuit board according to item 8 of the scope of patent application, wherein the surface treatment is a method selected from the group consisting of surface grinding and sandblasting. 10. The method for manufacturing a multilayer circuit board as described in item 1 of the scope of patent application, wherein the buffer surface of the insulating layer is formed by a thin layer having a micro-hole structure. 11. The method for manufacturing a multilayer circuit board as described in item 10 of the scope of the patent application, wherein the thin layer having a microporous structure is formed by spray coating method, chemical vapor deposition method, vapor condensation method, molecular beam It is formed by one of stupid crystal method, electroless plating method, chemical liquid phase synthesis method and solution-gel method. 1 2. The method for manufacturing a multilayer circuit board as described in item 1 of the scope of patent application, wherein the step of making a circuit layer on the surface of the insulating layer is an anti-plating resist on the surface of the insulating layer where no circuit is required , And then performing chemical plating on the surface of the insulating layer. 1 3. The method for manufacturing a multilayer circuit board according to item 1 of the scope of patent application, wherein the step of fabricating a circuit layer on the surface of the insulating layer is to deposit a metal layer on the surface of the insulating layer, and then photolithography制程 # 刻 This metal layer. 1 4. The manufacturer of the multilayer circuit board as described in item 13 of the scope of patent application

第14頁 592017 六、申請專利範圍法，其中該沉積一金屬層於該絕緣層表面的步驟，係以化學氣相沈積法、物理氣相沉積法、電鍍和無電鍍法其中之一方法完成。 1 5.如申請專利範圍第1項所述之多層電路板之製造方法，其中該電路層材料係選自銅、金和銀所組成的族群其中之一 ° 1 6. —種多層電路板之製造方法，係用以製作多層雙面電路板其步驟包含有： (a)提供一金屬基材，其包含一上表面與一下表面； (b ) 於該金屬基材之上表面形成一上絕緣層，其具有一緩衝表面，該緩衝表面具有微孔洞； (c)於該上絕緣層表面製作一上電路層； (d )於該電路層表面形成另一上絕緣層； (e)於該金屬基材之‘下表面形成一下絕緣層，其具有一緩衝表面，該緩衝表面具有微孔洞； (f )於該下絕緣層表面製作一下電路層；及 (g)於該下電路層表面形成另一下絕緣層。 1 7.如申請專利範圍第1 6項所述之多層電路板之製造方法，更包含於步驟（d )之後，重複一次以上步驟（c )至步驟（d)。 1 8.如申請專利範圍第1 6項所述之多層電路板之製造方法，更包含於步驟（g )之後，重複一次以上步驟（f)至步驟（g)。Page 14 592017 VI. Patent application method, wherein the step of depositing a metal layer on the surface of the insulating layer is performed by one of chemical vapor deposition method, physical vapor deposition method, electroplating and electroless plating method. 1 5. The method for manufacturing a multilayer circuit board as described in item 1 of the scope of patent application, wherein the material of the circuit layer is one selected from the group consisting of copper, gold, and silver ° 1 6. — A multilayer circuit board The manufacturing method is used for manufacturing a multilayer double-sided circuit board. The steps include: (a) providing a metal substrate including an upper surface and a lower surface; (b) forming an upper insulation on the upper surface of the metal substrate Layer, which has a buffer surface with micro-holes; (c) making an upper circuit layer on the surface of the upper insulating layer; (d) forming another upper insulating layer on the surface of the circuit layer; (e) in A lower insulating layer is formed on the lower surface of the metal substrate and has a buffer surface having micro-holes; (f) making a circuit layer on the surface of the lower insulating layer; and (g) the lower circuit layer A lower insulating layer is formed on the surface. 1 7. The method for manufacturing a multilayer circuit board as described in item 16 of the scope of patent application, further comprising step (d), and repeating step (c) to step (d) more than once. 1 8. The method for manufacturing a multilayer circuit board as described in item 16 of the scope of patent application, further comprising step (g), repeating steps (f) to (g) more than once.

592017 六、申請專利範圍 1 9 ·如申請專利範圍第1 6項所述之多層電路板之製造方法，其中該步驟（b)、該步驟（d )、該步驟（e )和該步驟 (g )，係陽極處理該金屬基材之表層以形成該上絕緣層和該下絕緣層以及該缓衝表面，該緩衝表面具有微孔洞。 2 0.如申請專利範圍第1 6項所述之多層電路板之製造方法，其中該步驟（b )、該步驟（d )、該步驟（e )和該步驟 (g )，係氧化該金屬基材之表層以形成該絕緣層。 2 1.如申請專利範圍第1 6項所述之多層電路板之製造方法，其中該步驟（b)、該步驟（d )、該步驟（e )和該步驟 (g )，係滲氮進入該金屬基材之表層以形成該絕緣層。 2 2.如申請專利範圍第1 6項所述之多層電路板之製造方法，其中該上絕緣層與該下絕緣層係選自陶瓷材料和高分子材料所組成的族群其中之一。 2 3.如申請專利範圍第1 6項所述之多層電路板之製造方法，其中該上絕緣層與該下絕緣層之該緩衝表面係經一表面處理所形成。 2 4.如申請專利範圍第2 3項所述之多層電路板之製造方法，其中該表面處理係選自表面研磨和喷砂處理其中之一。 2 5.如申請專利範圍第1 6項所述之多層電路板之製造方法，其中該上絕緣層與該下絕緣層之該緩衝表面係由一具有微孔洞結構之薄層所形成。 2 6.如申請專利範圍第2 5項所述之多層電路板之製造方592017 VI. Scope of patent application 1 9 · The method for manufacturing a multilayer circuit board as described in item 16 of the scope of patent application, wherein step (b), step (d), step (e), and step (g ), The surface layer of the metal substrate is anodized to form the upper insulating layer and the lower insulating layer and the buffer surface, and the buffer surface has micro holes. 20. The method for manufacturing a multilayer circuit board according to item 16 of the scope of patent application, wherein the step (b), the step (d), the step (e), and the step (g) are oxidizing the metal The surface layer of the substrate forms the insulating layer. 2 1. The method for manufacturing a multilayer circuit board according to item 16 of the scope of patent application, wherein the step (b), the step (d), the step (e), and the step (g) are nitriding into The surface layer of the metal substrate forms the insulating layer. 2 2. The method for manufacturing a multilayer circuit board according to item 16 of the scope of the patent application, wherein the upper insulating layer and the lower insulating layer are selected from one of a group consisting of a ceramic material and a polymer material. 2 3. The method for manufacturing a multilayer circuit board according to item 16 of the scope of patent application, wherein the buffer surfaces of the upper insulating layer and the lower insulating layer are formed by a surface treatment. 2 4. The method for manufacturing a multilayer circuit board according to item 23 of the scope of patent application, wherein the surface treatment is selected from one of surface grinding and sandblasting. 2 5. The method for manufacturing a multilayer circuit board according to item 16 of the scope of the patent application, wherein the buffer surfaces of the upper insulating layer and the lower insulating layer are formed by a thin layer having a micro-hole structure. 2 6. The manufacturer of the multilayer circuit board as described in item 25 of the scope of patent application

第16頁 592017 六、申請專利範圍法，其中該具有微孔洞結構之薄層係由喷覆成型法、化學氣相沈積法、氣相凝結法、分子束磊晶法、無電鍛法、化學液相合成法及溶液一凝膠法其中之一方法所形成。 2 7 ·如申請專利範圍第1 6項所述之多層電路板之製造方法，其中該步驟（c)和該步驟（f )，係於該絕緣層表面不需電路的區域上抗電鍍阻劑，再於該絕緣層表面進行化學析鍍來完成， 2 8.如申請專利範圍第1 6項所述之多層電路板之製造方法，其中該步驟（c )和該步驟（f )，係沉積一金屬層於該絕緣層表面，再以光微影製程蝕刻該金屬層。 2 9.如申請專利範圍第28項所述之多層電路板之製造方法，其中該沉積一金屬層於該絕緣層表面的步驟，係以化學氣相沈積法、物理氣相沉積法、電鍍和無電鍍法其中之一方法完成。 3 0.如申請專利範圍第1 6項所述之多層電路板之製造方法，其中該上電路層和下電路層之材料係選自銅、金和銀所組成的族群其中之一。 3 1.如申請專利範圍第1 6項所述之電路板之製造方法，其中於該步驟（d)和該步驟（g )之後，更包含一於該絕緣層上方沉積一金屬披覆層的步驟。 3 2.如申請專利範圍第3 1項所述之多層電路板之製造方法，其中於該絕緣層上方沉積一金屬坡覆層的步驟，係以化學氣相沈積法、物理氣相沉積法、電鍍和無電Page 16 592017 VI. Patent application method, in which the thin layer with microporous structure is formed by spray coating method, chemical vapor deposition method, vapor condensation method, molecular beam epitaxy method, electroless forging method, chemical It is formed by one of a liquid phase synthesis method and a solution-gel method. 2 7 · The method for manufacturing a multilayer circuit board as described in item 16 of the scope of patent application, wherein step (c) and step (f) are anti-plating resists on the surface of the insulating layer where no circuit is required Then, the surface of the insulating layer is chemically plated to complete it. 2 8. The method for manufacturing a multilayer circuit board as described in item 16 of the scope of patent application, wherein step (c) and step (f) are deposition A metal layer is on the surface of the insulating layer, and the metal layer is etched by a photolithography process. 2 9. The method for manufacturing a multilayer circuit board according to item 28 of the scope of the patent application, wherein the step of depositing a metal layer on the surface of the insulating layer is performed by chemical vapor deposition method, physical vapor deposition method, electroplating and One of the electroless plating methods is completed. 30. The method for manufacturing a multilayer circuit board according to item 16 of the scope of the patent application, wherein the material of the upper circuit layer and the lower circuit layer is one selected from the group consisting of copper, gold and silver. 3 1. The method for manufacturing a circuit board as described in item 16 of the scope of patent application, wherein after step (d) and step (g), further comprising a step of depositing a metal coating layer on the insulating layer step. 3 2. The method for manufacturing a multilayer circuit board as described in item 31 of the scope of the patent application, wherein the step of depositing a metal slope coating on the insulating layer is performed by chemical vapor deposition method, physical vapor deposition method, Plating and electroless

第17頁 592017 六、申請專利範圍鍍法其中之一方法完成。 3 3 ·如申請專利範圍第3 1項所述之多層電路板之製造方法，其中該金屬坡覆層材料係選自銅、金和銀所組成的族群其中之一。 3 4. —種多層電路板之製造方法，其步驟包含有： (a)提供一金屬基材； (b )於該金屬基材之表面形成一絕緣層； (c) 於該絕緣層表面製作一電路層； (d) 於該電路層表面形成另一絕緣層；及 (e )重複一次以上步驟（c )至步驟（d)。 3 5 .如申請專利範圍第3 4項所述之電路板之製造方法，其中該於該絕緣層表面製作一電路層的步驟，該絕緣層和該電路層係以膠合方式產生離子元素來接著。 3 6.如申請專利範圍第3 4項所述之電路板之製造方法，其中該電路層可透過膠合以進行元件黏著。 3 7.如申請專利範圍第3 4項所述之電路板之製造方法，其中該絕緣層表面係經一活化處理以增加電路層與絕緣層間的附著力。 3 8.如申請專利範圍第3 4項所述之電路板之製造方法，其中更包含一於最頂端之該絕緣層上方沉積一金屬彼覆層的步驟。 3 9.如申請專利範圍第3 8項所述之電路板之製造方法，其中該於該絕緣層上方沉積一金屬彼覆層的步驟，係以化學氣相沈積法、物理氣相沉積法、電鍍和無電鍵法Page 17 592017 6. Scope of patent application One of the plating methods has been completed. 3 3 · The method for manufacturing a multilayer circuit board according to item 31 of the scope of patent application, wherein the metal slope coating material is one selected from the group consisting of copper, gold and silver. 3 4. A method for manufacturing a multilayer circuit board, the steps include: (a) providing a metal substrate; (b) forming an insulating layer on the surface of the metal substrate; (c) fabricating on the surface of the insulating layer A circuit layer; (d) forming another insulating layer on the surface of the circuit layer; and (e) repeating steps (c) to (d) more than once. 35. The method for manufacturing a circuit board according to item 34 of the scope of the patent application, wherein the step of fabricating a circuit layer on the surface of the insulating layer, the insulating layer and the circuit layer generate ionic elements in a gluing manner, and then . 3 6. The method for manufacturing a circuit board as described in item 34 of the scope of patent application, wherein the circuit layer can be adhered by gluing. 37. The method for manufacturing a circuit board according to item 34 of the scope of the patent application, wherein the surface of the insulating layer is subjected to an activation treatment to increase the adhesion between the circuit layer and the insulating layer. 38. The method for manufacturing a circuit board according to item 34 of the scope of the patent application, further comprising a step of depositing a metal-on-metal layer on the topmost insulating layer. 39. The method for manufacturing a circuit board according to item 38 of the scope of the patent application, wherein the step of depositing a metal-on-metal layer over the insulating layer is performed by a chemical vapor deposition method, a physical vapor deposition method, Electroplating and keyless methods

第18頁 592017 六、申請專利範圍其中之一方法完成。 40.如申請專利範圍第38項所述之電路板之製造方法，其中該金屬彼覆層材料係選自銅、金和銀所組成的族群其中之一。 4 1.如申請專利範圍第3 4項所述之多層電路板之製造方法，其中該步驟（b )和該步驟（d )，係氧化該金屬基材之表層以形成該絕緣層。 4 2.如申請專利範圍第34項所述之多層電路板之製造方法，其中該步驟（b )和該步驟（d )，係滲氮進入該金屬基材之表層以形成該絕緣層。 4 3.如申請專利範圍第3 4項所述之多層電路板之製造方法，其中該絕緣層係選自陶瓷材料和高分子材料所組成的族群其中之一。 4 4.如申請專利範圍第34項所述之多層電路板之製造方法，其中該於該絕緣層表面製作一電路層的步驟，係於該絕緣層表面不需電路的區域上抗電鍍阻劑，再於該絕緣層表面進行化學析鍍來完成。 4 5.如申請專利範圍第3 4項所述之多層電路板之製造方法，其中該於該絕緣層表面製作一電路層的步驟，係沉積一金屬層於該絕緣層表面，再以光微影製程蝕刻該金屬層。 4 6.如申請專利範圍第4 5項所述之多層電路板之製造方法，其中該沉積一金屬層於該絕緣層表面妁步驟，係以化學氣相沈積法、物理氣相沉積法、電鍍和無電鍍Page 18 592017 VI. Scope of patent application One of the methods is completed. 40. The method for manufacturing a circuit board according to item 38 of the scope of the patent application, wherein the metal-to-metal coating material is one selected from the group consisting of copper, gold and silver. 4 1. The method for manufacturing a multilayer circuit board according to item 34 of the scope of the patent application, wherein the step (b) and the step (d) are oxidizing the surface layer of the metal substrate to form the insulating layer. 4 2. The method for manufacturing a multilayer circuit board according to item 34 of the scope of patent application, wherein the step (b) and the step (d) are nitriding into the surface layer of the metal substrate to form the insulating layer. 4 3. The method for manufacturing a multilayer circuit board according to item 34 of the scope of the patent application, wherein the insulating layer is selected from one of a group consisting of a ceramic material and a polymer material. 4 4. The method for manufacturing a multilayer circuit board according to item 34 of the scope of the patent application, wherein the step of making a circuit layer on the surface of the insulating layer is an anti-plating resist on the surface of the insulating layer where no circuit is required , And then performing chemical plating on the surface of the insulating layer. 4 5. The method for manufacturing a multilayer circuit board as described in item 34 of the scope of the patent application, wherein the step of fabricating a circuit layer on the surface of the insulating layer is to deposit a metal layer on the surface of the insulating layer, and then apply light to the surface. A shadow process etches the metal layer. 4 6. The method for manufacturing a multilayer circuit board according to item 45 of the scope of patent application, wherein the step of depositing a metal layer on the surface of the insulating layer is performed by chemical vapor deposition method, physical vapor deposition method, and electroplating And electroless

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