TW556344B

TW556344B - Semiconductor integrated circuit and its layout method

Info

Publication number: TW556344B
Application number: TW091119624A
Authority: TW
Inventors: Masaharu Mizuno; Shigeki Sakai; Naotaka Maeda
Original assignee: Nec Electronics Corp
Priority date: 2001-08-29
Filing date: 2002-08-28
Publication date: 2003-10-01
Also published as: GB0220079D0; GB2382923A; GB2382923B; US6753702B2; US20030051221A1; JP2003152082A; JP3672889B2

Abstract

The master slice type semiconductor integrated circuit includes sequential circuit cells (2) and combinational circuit cells (3), which are alternately arranged in an inner core area on a semiconductor chip (1), and a plurality of selective driving elements (MC101 to MC108, MC201 to MC216 and MC301 to MC316), which are connected in a shape of a tree, for selectively distributing a poliphase clock signal for each division area formed by uniformly dividing the inner core area. The plurality of selective driving elements are placed and connected on the semiconductor chip such that load and wiring length between the sequential circuit cells within the respective division areas and input terminals to which the poliphase clock signal is inputted are equal. Due to this configuration, it is possible to cope with a poliphase clock, and also possible to reduce a clock skew between circuits, and further possible to provide a master slice type semiconductor integrated circuit in which an electric power consumption can be reduced.

Description

556344 五、發明說明（1) 【發明背景】 I發明領域電路本關於：種母片(_ter slice)型半導體積體以外的生痛牛種邏輯€路係藉由共通地實行除了配線步驟座步騾而形成，且僅改變配線步驟。 2·相技藝之說明間内iii道半訂製（senii-cust〇m)設計方法作為在短時复，導體積體電路例如LSI與類似者之技術。尤 i能的單ΐ包括一種母片方法，其中預先準備一含有基本 y, 之母片，例如邏輯閘、正反器、盥類似去妒後使用者你秘，貝似者，然所期望的ΐ ΐ 給定的邏輯電路而確m線圖案且獲得所期呈的+導體積體電路。 jlA顯示習知的母片型半導體積體電路之晶片構造之、，’且圖1B係圖ία之半導體積體電路之電晶體單元之放=平面圖。習知的母片型半導體積體電路101具有陣列構ie其中具有圖1B所示構造的相同尺寸電晶體單元1〇2 以矩陣形式配置於晶片1。在圖1B中，參考編號1〇3表示閘極電極，且參考編號1〇4表示擴散層。、亦且’在習知的母片型半導體積體電路中，藉由使用稱為時鐘樹的時鐘緩衝器之樹狀構造使時鐘信號分配至晶片上之各電路。圖2顯示在習知的母片型半導體積體電路中之時鐘分配方法之平面圖。在時鐘緩衝器之樹狀構造中，時鐘信號CLK從中央處556344 V. Description of the invention (1) [Background of the invention] I The field of the invention is about: the pain logic of breeding cattle other than the semiconductor chip (_ter slice) type semiconductor integrated circuit, which is implemented in common except the wiring steps.骡 is formed, and only the wiring steps are changed. 2. Description of Phase Techniques The semi-custom (senii-custom) design method in iii is used as a technique for complex circuits in a short time, such as LSI and the like. You Yineng's list includes a master film method, in which a master film containing basic y, such as logic gates, flip-flops, toilets, etc. is used to deceive the user after you are jealous.确 ΐ Determine the m-line pattern for a given logic circuit and obtain the + conductive volume circuit as expected. jlA shows the wafer structure of a conventional mother chip semiconductor integrated circuit, and FIG. 1B is a plan view of the transistor unit of the semiconductor integrated circuit of FIG. The conventional mother chip type semiconductor integrated circuit 101 has an array structure, in which the transistor units 102 of the same size having the structure shown in FIG. 1B are arranged on the wafer 1 in a matrix form. In FIG. 1B, reference numeral 103 indicates a gate electrode, and reference numeral 104 indicates a diffusion layer. Also, in a conventional mother chip type semiconductor integrated circuit, a clock signal is distributed to each circuit on a chip by using a tree structure called a clock buffer called a clock tree. FIG. 2 is a plan view showing a clock distribution method in a conventional mother chip semiconductor integrated circuit. In the tree structure of the clock buffer, the clock signal CLK is from the center

556344 五、發明說明（2) --- 的第一時鐘緩衝器1 〇 5分配至複數個第二時鐘緩衝器1 〇 6，且時鐘信號CLK從第二時鐘缓衝器1 0 6分配至複數\固$第三時鐘緩衝器107。再者，時鐘信號CLK從第三時鐘緩衝器分配至電路1 〇 8例如正反器電路與類似者。順序電路斑组合電路自由地放置於晶片上。必要時，時鐘相位% Ί 由使用樹狀構造而分配。另一種母片型半導體積體電路揭露於曰本專利安，開公報（JP-A-平成6- 1 88397 )中。圖3顯示日本專利月木請案公開公報（JP-A-平成6-1 883 9 7 )中所揭露的母片 =體積體電路之晶片構造之平面圖。此半導體積體電路 2〇1具有下列構造：藉由形成基本單元以矩陣形式配置於 ΐ片i ϋ广部核心領域A且更形成一專門用於順序電路的早兀領域C而使内部核心領域A分割成複數個基本單元有^度㈣力的時鐘緩衝器形成於專門用於順序電 ^二兀：域。中’且各基本單元相鄰地形成於可經由最接的位置處。亦且1 了順序電路與類似者以外的，合電路配置於基本單元領_内的領糾。者以係隨機地配置。因&，連接it;體電路中，順序電路數目與攸枯鐘緩衝器至順序電路的 i路之各時鐘缓衝器之負載電容值盘、’、&又，引起規律。因此理*，'習知的半導以二路之：線電阻值不路間之時鐘偏斜之問題。尤其的喷序電配線旁通過該大巨集之巨崔心倘右放置大巨帛，則時鐘巨木領域。所以，不規律的情況變556344 V. Description of the invention (2) --- The first clock buffer 1 05 is allocated to a plurality of second clock buffers 1 06, and the clock signal CLK is allocated from the second clock buffer 106 to the complex number \ 固 $ third clock buffer 107. Furthermore, the clock signal CLK is distributed from the third clock buffer to a circuit 108 such as a flip-flop circuit and the like. The sequential circuit spot combination circuit is freely placed on the wafer. If necessary, the clock phase% 分配 is allocated by using a tree structure. Another type of mother chip type semiconductor integrated circuit is disclosed in Japanese Patent Application Laid-Open Publication (JP-A-Heisei 6-1 88397). FIG. 3 shows a plan view of a wafer structure of a mother body = volume body circuit disclosed in Japanese Patent Tsukigi Application Publication (JP-A-Heisei 6-1 883 97). This semiconductor integrated circuit 201 has the following structure: the internal core area is formed by forming the basic unit in a matrix form in the core area A of the wide area and forming an early area C specifically for sequential circuits. A is divided into a plurality of basic units, and a clock buffer having a high degree of force is formed in a sequence dedicated to the second circuit: a domain. Middle ', and each basic unit is formed adjacently at the most accessible position. Also, except for sequential circuits and similar ones, the combined circuits are arranged in the collar of the basic unit. These are randomly assigned. Because of &, the number of sequential circuits connected to the it circuit, and the load capacitance value of each clock buffer of the i-channel of the sequential circuit buffer to the sequential circuit, ', & Therefore, *, 'the conventional semiconductor has two ways: the line resistance value is not the problem of clock skew between circuits. In particular, the jet sequence electricity passes through the giant giant Cui Xin next to the wiring. If the giant giant is placed to the right, the clock is in the giant wood area. So the irregular situation changes

第8頁順序、且，既然各單元之電螝的i之時鐘閘極部之閘極電衮佶士 2二相等，赵 4、I容值，導致電力消耗增加之問；早兀基極用之區方面，在圖3所示^7具。 :序電路集合地配置於靠近的時母二型：導體積體電路中，因而’隨著順序電路之數目：；驅：器之專用的領域中。 =。所以，最近的順序電二最用4順序電路之領域會 =，，由配線電阻值所造序電路間之距離電路之尺寸變大尤其’隨著整個電路中設計中w生* 卞鐘偏斜會增加。亦 a #丄貝斤故5々預先道順序電路之數日 ^ 倘右在訂製的路至各時鐘緩衝器。之J目’則可均句地指派順序電 3的半導體積體電：之：^圖3所示的組態應用至半地指派順序電路至各= 十例如閉極陣歹，]，則難以均句度指派順序電㉟日士二f ?器。倘若在預期餘裕之中過且，倘若嘗試處理 ±電力扁耗增加之問題。亦路的領域。再者二2:，則難以建立專用於順序屬於相關技藝變大。 6-244282)揭露—種呈一明案公開公報（jp-A_平成電路之半導體積體^有南集積/且大尺寸的時鐘同步在此半導體積體電路执：：中f仵極小時鐘偏斜之技術。等’且由僕緩=狀配線，造連接’使得其配線長度相 "正反器、與類似者所組成的一低階時五、發明說明（4) 鐘樹狀構造連接於栅狀配線構造構造間之時鐘偏斜，同日士可抑制柵狀配線斜。因此，可降低大領j :狀配線構造内之時鐘偏曰本專利申請案公H之時鐘偏斜。露一種可消除正反器間之二、二平成1〇-3〇845〇:>揭體電路及其設計方法間差異（偏斜）的半導體積抑制時鐘線之電力消耗；；=應=時鐘電路之用以閘時鐘電路，具有由路缓導體積體電路係建立。亦】1ϊ::ΐ連接關係在所有單元配置之後才之後，配置於線的正反器按每-功能而叢集 -置於4近處的正反薄問爭緩衝器與多重輸 ^ 集。所以，由各除偏斜。勒】入閑所驅動的負載變成固定。此設計可消露一籍t ^利申凊案公開公報（JP — A—平成1 1 - 1 1 1 850 )揭及H ΐ可輕易地降低時鐘偏斜之組態的時鐘供應電路一一二二α種半導體積體電路設備。時鐘供應電路包括端羡衝器元件，其中一輸入端子連接至一時鐘信號源反哭及一第二緩衝器元件，其中一輸出端子連接至正器了一之時鐘輸入端子，且一時鐘信號供應至各正反 : 益與第二緩衝器元件經由一第三緩衝器元件彼此連使，ΐ任何分支。在觀察布局後’第三緩衝器元件放置於寸與第二緩衝器元件間之配線長度可降低時鐘偏斜之位置處。一 556344 五、發明說明（5) 亦且， 4343)揭露一線製程以外而建構成各中’特定的元領域之特再者，揭露一種時圍繞著供應存器的正反交叉於從區配線。因此斜。曰種本母專Λ申請案公開公報(JH-昭和62 — 、片1半導體積體電之製程皆共诵地與γ 八甲除ί配種邏輯電蹊 =丁，且藉由僅改變配線步驟邏母片型半導體積體電路設備定的：域中於構成各種邏輯電路的内部單申請案公開公報(JP-A 200"9465 1 ) 、，偏斜布局。在此方法中，有時鐘信妒之令妁π 1 復數個&域緩衝益器以陣列形式配詈於γ @ / 構成暫 A η 式置；k桿（配線）上，該棒桿俜域緩衝器起在複數個方向上延伸㈣的距= ’可使傳輸延遲時間均勻化，蕻 J J化，猎U降低時鐘偏【發明概述】有鑒於前述問題特完成本發明。因而，本發的在於提供一種母片型半導體積體電路，鐘且降低電路間之時鐘偏斜。地里夕相位時路，一目的在於提供一種母月型半導體積體· 路，可降低電力消耗。貝15包本^明之半導體積體電路包括複數個順序電路 (2)與複數個組合電路單元（3 )，夺秩 70 口电峪早兀又替地配置於一半導辦曰片上之一内部核心領域中，以及複數個選擇驅動元盈日日 (MC101 至MCl〇8、mc2()1mC216、與MC3()1 至則⑴ 運接On the eighth page, and since the gate electrician 2 of the clock gate of the electric unit of each unit is equal to 2, the capacitance value of Zhao 4 and I leads to an increase in power consumption; As for the area, it is shown in Figure 3 ^ 7. The sequence circuits are collectively arranged in close proximity to the mother type II: conducting volume circuit, so ’along with the number of sequence circuits:; drive: in the dedicated area of the device. =. Therefore, the field of the most recent sequential electric circuit with 4 sequential circuits will be =, the distance between the ordered circuits created by the wiring resistance value will become larger, especially as the whole circuit is designed * when the clock is skewed Will increase. Also a # 丄 Beijin So 5々 several days before the sequential circuit ^ If the right way is to the clock buffer. “J 目” can be used to assign the semiconductor integrated circuit of the sequence 3 :: ^ The configuration shown in FIG. 3 is applied to the sequence of the half-ground sequence to each = ten. For example, a closed-pole array,], it is difficult The average sentence is assigned to a sequence of electronic and electronic devices. If it is within the expected margin, and if you try to deal with the problem of increased power consumption. Areas of Yilu. Furthermore, 2: 2, it is difficult to establish dedicated to the sequence, which is related to the increase in skills. 6-244282) Disclosure—A kind of open publication (jp-A_Heisei Circuit's semiconductor integrated circuit ^ Younannan integrated and large-scale clock synchronization is implemented in this semiconductor integrated circuit :: Medium f 仵 extremely small clock bias Inclined technology, etc., etc., and the connection is made by the servo cable, and the connection is made so that its wiring lengths are equal to those of the "inverter," and a similar low-level time. 5. Description of the invention (4) The bell-tree structure is connected to the grid The clock skew between the structure of the wiring structure can suppress the skew of the grid wiring. Therefore, the clock skew in the large collar j: the structure of the wiring structure can be reduced. The second and the second between the flip-flops, Heisei 10-3080845: > The semiconductor product with the difference (skew) between the body circuit and its design method suppresses the power consumption of the clock line; = shall = the use of the clock circuit The gate clock circuit has a circuit system built by the circuit of the slow-releasing volume. Also] 1ϊ :: ΐ The connection relationship is only after all units are configured, and the flip-flops arranged on the line are clustered-placed by 4 per function. The positive and negative challenge buffers and multiple input sets. The load driven by the train station becomes fixed. This design can reveal a t ^ Lishen case public bulletin (JP — A — Heisei 1 1-1 1 1 850) and H组态 Clock supply circuit with a configuration that can easily reduce the clock skew. One or two alpha semiconductor integrated circuit devices. The clock supply circuit includes a terminal device, where one input terminal is connected to a clock signal source. A second buffer element, one of the output terminals of which is connected to the clock input terminal of the positive one, and a clock signal is supplied to each of the positive and negative: yi and the second buffer element are connected to each other via a third buffer element, ΐ Any branch. After observing the layout, 'the third buffer element is placed at a position where the length of the wiring between the inch and the second buffer element can reduce the clock skew. 1556344 V. Description of the invention (5) Also, 4343) It is a special feature of the "special meta-fields" that exposes outside the front-line process, and exposes a type of wiring that crosses the front and back of the supply register. So oblique. The public announcement of the application of the parent-child Λ application (JH-Showa 62 —, the process of the chip 1 semiconductor integrated circuit is chanted with γ Bajia, and the logic logic is equal to D, and the logic is changed by changing only the wiring steps. The master chip type semiconductor integrated circuit device is defined in the internal single application publication (JP-A 200 " 9465 1) in the domain to form various logic circuits, and the layout is skewed. In this method, there is a clock to be jealous. Let 妁 π 1 a plurality of & domain buffer amplifiers be arranged in an array form at γ @ / to form a temporary A η-type arrangement; on the rod k (wiring), the rod domain buffer extends in multiple directions. The distance = 'can make the transmission delay time uniform, JJization, reduce the clock bias [Summary of the Invention] The present invention has been completed in view of the foregoing problems. Therefore, the present invention is to provide a mother chip semiconductor integrated circuit, The clock and reduce the clock skew between the circuits. The purpose of the ground phase phase is to provide a mother-and-semiconductor semiconductor integrated circuit that can reduce power consumption. The semiconductor integrated circuit of 15 packs includes a plurality of sequences. Circuit (2) with plural groups The circuit unit (3), the rank 70 electrical outlet, is placed in one of the internal core areas of the guide, and several options drive Yuan Yingri (MC101 to MCl08, mc2 () 1mC216, connect with MC3 () 1 to ⑴

第11頁 556344 五、發明說明（6) 成樹狀，用以選擇性分配一多相位時鐘信號予藉由均勻分割該内部核心領域所形成的每一分割領域。該複數個選擇驅動元件（5/[(：101至^1(：1〇8、％〇201至^^216、與此301至 MC316)放置且連接於半導體晶片（1)上，使&各分割領域内的該順序電路單元（2 )與輸入有該多相位時鐘信號的輸入端子間之負載與配線長度彼此相等。Page 11 556344 V. Description of the invention (6) A tree is used to selectively allocate a multi-phase clock signal to each segmented area formed by uniformly dividing the internal core area. The plurality of selection driving elements (5 / [(: 101 to ^ 1 (: 108,% 201 to ^ 216, and 301 to MC316)) are placed and connected to the semiconductor wafer (1) so that & The load and wiring length between the sequential circuit unit (2) and the input terminal to which the multi-phase clock signal is input in each divided area are equal to each other.

亦且，在本發明之半導體積體電路之一組態例子中，該=序電路單元包括：一第一邏輯閘元件（1肝2)，放置於一時鐘輸入部之第一級，其上輸入有該多相位時鐘信號；' 以及一第二邏輯閘元件（INV3)，放置於緊接著該第一 ^輯閘元件之後，其中在該複數個順序電路單元中之將使用的一順序電路單元中，一配線設於該第一邏輯閘元件之一輪出端子與該第二邏輯閘元件之一輸入端子間，且在該順^ 電路單元中之不會用到的一順序電路單元中，該配線不置放於該第一邏輯閘元件之該輸出端子與該第二邏輯閘元件之該輸入端子間，且該第二邏輯閘元件之該輸入端子連接至一電源供應器或地面。Also, in a configuration example of the semiconductor integrated circuit of the present invention, the sequence circuit unit includes: a first logic gate element (1 liver 2), which is placed on a first stage of a clock input section, on which The multi-phase clock signal is input; and a second logic gate element (INV3) is placed immediately after the first gate element, in which a sequence circuit unit among the plurality of sequence circuit units will be used. A wiring is provided between a round-out terminal of the first logic gate element and an input terminal of the second logic gate element, and in a sequential circuit unit that is not used in the sequence circuit unit, the The wiring is not placed between the output terminal of the first logic gate element and the input terminal of the second logic gate element, and the input terminal of the second logic gate element is connected to a power supply or ground.

亦且’在本發明之半導體積體電路之一組態例子中，該順序電路單元包括：一第一邏輯閘元件（NAND1)，放置於輪入有該多相位時鐘信號之該時鐘輸入部之第_級，用以經由一賦能信號而賦能將選擇的一第一狀態或—第二狀態’該第一狀態係一輸出電位基於該多相位時鐘信號而確疋’而該第二狀態係無論該多相位時鐘信號如何該輪出電位皆固定；以及一第二邏輯閘元件（INV3)，其一輪入端子Moreover, in a configuration example of the semiconductor integrated circuit of the present invention, the sequential circuit unit includes: a first logic gate element (NAND1), which is placed in the clock input section in which the multi-phase clock signal is wheeled. The first stage is used to enable the selection of a first state or a second state via an enabling signal. The first state is an output potential determined based on the multi-phase clock signal and the second state. The round-out potential is fixed regardless of the multi-phase clock signal; and a second logic gate element (INV3), one round-in terminal of which

556344 __________ 五、發明說明（7) 連接至該第一邏輯閘元件之一輸出端子’並且其中該複數個順序電路單元中之將使用到的/順序電路單元中，該賦能信號係設定成使得該第一邏輯閘元件變成該第一狀態，且在該複數個順序電路單元中不會用到的一順序電路單元中，該賦能信號係設定成使得該第一邏輯閘元件變成該第 —狀態。亦且，在本發明之半導體積體電路之一組態例子中，當放置於其上藉由該複數個選擇驅動元件中之一選擇驅動凡件而分配有該多相位時鐘信號之該每一分割領域中的_ 順序電路單元，或由一不同的選擇驅每一分割領域中的擇驅動元件之輸出者放置於其上藉由該動元件而分配有該多一順序電路單元不使一選擇驅動元件經相位時鐘信號之該用時，阻止該一選556344 __________ V. Description of the invention (7) Connected to an output terminal of the first logic gate element, and wherein among the plurality of sequence circuit units / sequence circuit units to be used, the enabling signal is set so that The first logic gate element becomes the first state, and in a sequence circuit unit that will not be used in the plurality of sequence circuit units, the enabling signal is set so that the first logic gate element becomes the first- status. Also, in a configuration example of the semiconductor integrated circuit of the present invention, each of the multi-phase clock signals assigned to the multi-phase clock signal when placed on it is selected by one of the plurality of selection driving elements _ Sequential circuit unit in the divided field, or the output of the selected driving element in each divided field is driven by a different selection placed on it by assigning the one more sequential circuit unit by the moving element does not make a selection When the driver uses the phase clock signal, it prevents the selection

本發明置複數個順晶片上之一驅動元件成由均勻分割該複數個選得輸入有該該順序電路亦且，子中，其中列情況：一中之半序電路内部核樹狀，該内部擇驅多相位單元間在本發該複數配線不導體積單元與心領域用以選核心領元件配時鐘信之負載明之半個順序置放於複數個中；以擇性分域所形置並連號的輪與配線導體積電路單一楚之布局包括下列步驟組合電路單元於一半及配置並連接複數個配一多相位時鐘信號成的每一分割領域，接於該入端子長度彼此相等體電路元中之邏輯閘半導體晶片與各分割領According to the present invention, one of the driving elements on a plurality of sequential chips is divided into a plurality of uniformly divided inputs and the sequence circuit is selected. In addition, in the case, the column situation is: a semi-sequence circuit in one has a core tree shape. Selective driving multi-phase units are placed in the plural in the order of the complex wiring non-conducting volume unit and the heart field to select the core collar component and the clock signal in the order of half of the load. The single layout of the wheel and wiring guide volume circuit includes the following steps: combining the circuit unit in half and arranging and connecting each divided area with a plurality of multi-phase clock signals, connected to the input terminals with the same length as each other. Logic gate semiconductor chip and each division collar

XX

之布局之一每一個係形元件與一第組態例成為下二邏輯One of the layouts, each configuration element and the first configuration example become the next two logics

556344______ 五、發明說明（8) " — ------- 閘凡件間，該第一邏輯閘元件係放置於輸入誃夕鐘信號的一時鐘輸入部之第一級且該第一相位時 f於緊接著該第一邏輯閘元件之後，其中在談二係敌電路單元中之將使用的一順序電路單元中，= 個噸序元件之一輸出端子與該第二邏輯閘元件之一輯閘配置配線步驟中彼此連接，且在該複數個順序電^於-不會用到的一順序電路單元中，該配線不置放於該^二中輯閘元件之該輸出端子與該第二邏輯閘元件之該^入二邏間，且該第二邏輯閘元件之該輸入端子係於該配^配^ : 驟中配線連接至一電源供應器或地面。線步亦且，在本發明之半導體積體電路之布局之一組$ 子中，該順序電路單元包括：一第一邏輯閘元件，放置於| _ 輸入有該多相位時鐘信號之該時鐘輸入部之第一級，用/ 經由一賦能信號而賦能將選擇的一第一狀態或一第二狀1 態，該第了狀態係一輸出電位基於該多相位時鐘信號而確定’而該第二狀態係無論該多相位時鐘信號如何該輪出電位皆固定Υ以及一第二邏輯閘元件，其一輸入端子連接至該第_邏輯閘元件之一輸出端子’並且其中該複數個順序電路單元中之將使用到的一順序電路單元中，該赋能信號係設定成使得該第一邏輯閘元件變成該第一狀態，且在該556344______ V. Description of the invention (8) " — ------- Among the gates, the first logic gate element is placed on the first stage of a clock input section for inputting the clock signal and the first The phase time f is immediately after the first logic gate element. Among the sequence circuit units to be used in the second-series enemy circuit unit, one of the output terminals of the ton-sequence element and the second logic gate element A series of gate configuration wiring steps are connected to each other, and in a sequence circuit unit of a plurality of sequential circuits that are not used, the wiring is not placed between the output terminal and the first of the series gate components. The second logic gate element is connected to the second logic chamber, and the input terminal of the second logic gate element is connected to the power distribution system: the wiring in the step is connected to a power supply or ground. In addition, in the step of the semiconductor integrated circuit layout of the present invention, the sequential circuit unit includes: a first logic gate element, which is placed in the clock input of the multi-phase clock signal The first level of the department is energized with / via an energizing signal to select a first state or a second state. The first state is an output potential determined based on the multi-phase clock signal. The second state is that the round-out potential is fixed regardless of the multi-phase clock signal and a second logic gate element, an input terminal of which is connected to an output terminal of the _th logic gate element, and wherein the plurality of sequential circuits In a sequential circuit unit to be used in the unit, the enabling signal is set so that the first logic gate element becomes the first state, and in the

複數個順序電路單元中不會用到的一順序電路單元中，該I 賦能信號係設定成使得該第一邏輯閘元件變成該第二狀態。亦且’在本發明之半導體積體電路之布局之一組態例In a sequence circuit unit not used in the plurality of sequence circuit units, the I-enable signal is set so that the first logic gate element becomes the second state. Also, a configuration example of the layout of the semiconductor integrated circuit of the present invention

第14頁 556344Page 14 556344

五、發明說明（9) 子中，當放置於其上藉由該複數個選擇驅動元件中之一選擇驅動元件而分配有該多相位時鐘信號之該分割領域中之該順序電路單元，或者放置於其上藉由該一選擇驅動元件經由一不同的選擇驅動元件而分配有該多相位時鐘信號之該分割領域中的該順序電路單元不使用時，阻止該一選擇驅動元件之輸出。【較佳實施例之詳細說明】 [第一實施例] 茲將參照附圖說明本發明第一實施例如下。圖4顯示依據本發明第一實施例之母片型半導體積體電路之晶片構造之平面圖。在此實施例之母片型半導體積體電路1中，順序電路單元2與組合電路單元3交替配置於半導體晶片上之内部核心領域中。順序電路單元2中的每一輸出不僅由目前輸入而且亦由輸入之過去歷史所確定。組合電路單元 3中的每一輸出則僅由目前輸入所確定。再者，在此第一實施例中，如圖4所示，内部核心領域分割成16個分割領域Areal、Area2、Area3、Area4、V. Description of the invention (9), when placed on the sequential circuit unit in the segmented field where the multi-phase clock signal is allocated by selecting the driving element by one of the plurality of selection driving elements, or When the sequential circuit unit in the divided field on which the multi-phase clock signal is allocated by the selective driving element via a different selective driving element is not used, the output of the selective driving element is prevented. [Detailed description of a preferred embodiment] [First Embodiment] A first embodiment of the present invention will be described below with reference to the drawings. Fig. 4 shows a plan view of a wafer structure of a mother chip type semiconductor integrated circuit according to a first embodiment of the present invention. In the mother chip type semiconductor integrated circuit 1 of this embodiment, the sequence circuit unit 2 and the combination circuit unit 3 are alternately arranged in the internal core area on the semiconductor wafer. Each output in the sequential circuit unit 2 is determined not only by the current input but also by the past history of the input. Each output in the combination circuit unit 3 is determined only by the current input. Furthermore, in this first embodiment, as shown in FIG. 4, the internal core domain is divided into 16 divided domains Areal, Area2, Area3, Area4,

Area5 、Area6 、Area7 、Area8 、Area9 、ArealO 、Area5, Area6, Area7, Area8, Area9, AreaO,

Areall 、Areal2 、Areal3 、Areal4 、Areal5 、與Areal6 。每一分割領域具有實質上彼此相等的尺寸。為了選擇性分配多相位時鐘信號CLK_A、CLK_B、 CLK — C、CLK — D、CLK —E、CLK —F、CLK —G、與CLK_H 至各分割領域八^&1至八^&16，使用多工器14(：101至肘(：108、肘〇201至Areall, Areal2, Areal3, Areal4, Areal5, and Areal6. Each divided field has a size substantially equal to each other. In order to selectively distribute the multi-phase clock signals CLK_A, CLK_B, CLK — C, CLK — D, CLK — E, CLK — F, CLK — G, and CLK_H to each of the divided fields ^ & 1 to ^ & 16, Use multiplexer 14 (: 101 to elbow (: 108, elbow 〇201 to

第15頁 556344 五、發明說明（ίο) MC216、與MC3 01至MC316用於時鐘分配而形成負載與配線長度皆相同的時鐘樹狀構造。每一多工器具有高驅動力。多工器MC101 至MC108、MC201 至MC216、與MC301 至MC316 從複數個輸入中選擇任一個加以輸出。Page 15 556344 V. Description of the Invention MC216 and MC3 01 to MC316 are used for clock distribution to form a clock tree structure with the same load and wiring length. Each multiplexer has a high driving force. Multiplexers MC101 to MC108, MC201 to MC216, and MC301 to MC316 are selected from a plurality of inputs and output.

時鐘樹狀構造一般預先形成，而不會取決於每一設計所用的順序電路單元2。舉例而言，如圖4所示，多工器 11(：101至虹108配置於晶片之中央上，多工器^^201至1^204 分別配置於四個分割領域Areal至Area4之中央上，多工器 MC205至MC208分別西己置於四個分割領域Area5至Area8之中央上，多工器MC2 0 9至MC212分別配置於四個分割領域 Area9至Areal2之中央上，且多工器MC213至MC216分別配置於四個分割領域Areal3至Areal6之中央上。再者，多工器MC301至MC31 6 —個一個地配置於分割領域Areal至 Areal6之各中央之附近。圖5至8顯示時鐘樹狀構造之電路組態之電路圖。多相位時鐘信號CLK — A至CLK — H從外界共通地分配至多工器 MCI 01至MCI 08。多工器MCI 01至MCI 04之各輸出共通地分配至多工器MC210至MC208。多工器MC105至MC108之各輸出共通地分配至多工器MC20 9至MC216。The clock tree structure is generally formed in advance and does not depend on the sequential circuit unit 2 used in each design. For example, as shown in FIG. 4, the multiplexers 11 (: 101 to Rainbow 108 are arranged on the center of the chip, and the multiplexers ^^ 201 to 1 ^ 204 are respectively arranged on the centers of the four divided areas Areal to Area4. The multiplexers MC205 to MC208 are respectively placed on the center of the four divided areas Area5 to Area8, and the multiplexers MC2 0 to MC212 are placed on the center of the four divided areas Area9 to Areal2, respectively, and the multiplexer MC213 MC216 to MC216 are respectively arranged on the centers of the four divided areas Areal3 to Areal6. Furthermore, multiplexers MC301 to MC31 6 are arranged one by one near the centers of the divided areas Areal to Areal6. Figures 5 to 8 show the clock tree The circuit diagram of the circuit configuration of the multi-phase structure. The multi-phase clock signals CLK — A to CLK — H are shared from the outside to the multiplexers MCI 01 to MCI 08. The outputs of the multiplexers MCI 01 to MCI 04 are shared to the multiplexers. MC210 to MC208. The outputs of multiplexers MC105 to MC108 are shared among multiplexers MC20 9 to MC216.

再者’多工器MC201與MC202之各輸出共通地分配至多工态MC301與MC302，多工器MC203與MC204之各輸出共通地分配至多工器MC303與MC304，多工器MC205與MC20 6之各輸出共通地分配至多工器MC305與MC3 0 6，多工器MC207與 MC208之各輸出共通地分配至多工器5|(：3〇7與％(：3〇8，多工Furthermore, the outputs of the multiplexers MC201 and MC202 are shared among the multiplex MC301 and MC302, and the outputs of the multiplexers MC203 and MC204 are shared among the multiplexers MC303 and MC304, and the multiplexers MC205 and MC20 6 are shared. Outputs are commonly assigned to multiplexers MC305 and MC3 06, and each output of multiplexers MC207 and MC208 are commonly assigned to multiplexer 5 | (: 307 and% (: 308), multiplexer

556344 五、發明說明（11) 器MC209與MC210之各輸出共通地分配至多工器MC309與 MC310，多工器MC211與MC212之各輸出共通地分配至多工器MC311與MC312，多工器MC213與MC214之各輸出共通地分配至多工器MC313與MC314，且多工器MC215與MC216之各輸出共通地分配至多工器MC315與MC316。多工器MC301之輸出分配至分割領域Areai中之順序電路單元2。在圖4中，多工器MC301之輸出分配至正反器 (/F)。類似地，多工器耽3〇2至肊316之輸出分別分配至分割領域Area2至Areal6中之順序電路單元2。。使多相位時鐘信號CLK_A至(：1^_11從外界經其供應至多工器MCI 01至MCI 08的各配線系配置成使得到多工器MC1〇1 至^1(：108的配線長度彼此相等。使多工器此1〇1至肘^〇8之輸出經其供應至多工器M C 2 〇!至M c 2丨6的各配線係配置成使得到多工器MC20 i至MC2! 6的配線長度彼此相等。哭使多工器^2〇1至^216之輸出經其供應至多工 C31 6的各配線係配置成使得到多工器MC3〇l至 =線長度彼此相等。再者，，多工器·1至使广到順其供應至順序電路單元2的各配線係配置成使付」ϋ序電路皁疋2的配線長度彼此相等。三個控制信號SO、S1、與32從外界 MCI 01至MCI 08。二個沪制俨缺cn 「介t、應至夕工态至0 a 控制^ ^S0 ’ S1供應至多工器MC201 、、主音，估—> 2信號S〇供應至多工器虹3〇1至MC316。應 S要=!號之符號對每-多工器而言皆改變，則所需要的綠圖空間會大大地增加。因此，在圖5至8中，其556344 V. Description of the invention (11) The outputs of the MC209 and MC210 are shared among the multiplexers MC309 and MC310, the outputs of the multiplexers MC211 and MC212 are shared among the multiplexers MC311 and MC312, and the multiplexers MC213 and MC214 Each output is commonly assigned to multiplexers MC313 and MC314, and each output of multiplexers MC215 and MC216 is commonly assigned to multiplexers MC315 and MC316. The output of the multiplexer MC301 is distributed to the sequential circuit unit 2 in the divided area Areai. In Figure 4, the output of the multiplexer MC301 is distributed to the flip-flop (/ F). Similarly, the outputs of the multiplexers 302 to 316 are assigned to the sequential circuit units 2 in the division areas Area2 to Areal6, respectively. . The wiring systems of the multi-phase clock signals CLK_A to (: 1 ^ _11 supplied to the multiplexers MCI 01 to MCI 08 from the outside are configured so that the wiring lengths to the multiplexers MC1101 to ^ 1 (: 108 are equal to each other) The output of the multiplexer 101 to elbow ^ 08 is supplied to each wiring system of the multiplexers MC 2 0 to M c 2 丨 6 so that the multiplexers MC20 i to MC2! 6 The wiring lengths are equal to each other. The wirings through which the outputs of the multiplexers ^ 201 to ^ 216 are supplied to the multiplexer C31 6 are configured so that the line lengths to the multiplexers MC3101 to == are equal to each other. Furthermore, The multiplexers 1 to 1 are arranged so that the wirings supplied to the sequential circuit unit 2 are arranged so that the wiring lengths of the sequence circuit soap 2 are equal to each other. The three control signals SO, S1, and 32 are from Outside MCI 01 to MCI 08. Two Shanghai-made systems lack cn "Introduction t, should be working mode to 0 a control ^ ^ S0 'S1 is supplied to the multiplexer MC201, and the main tone, and estimated-> 2 signal S〇 supply The multiplexer rainbow 301 to MC316. The sign that S should =! Is changed for each multiplexer, so the required green map space will be greatly increased. Therefore, FIGS 5 to 8,

556344 五、發明說明（12) 僅由三個控制信號SO、S1、與S2所代表。然而，控制信號 SO、S1 、與S2對每一多工器而言皆不同。下文將說明在此第一實施例中之半導體積體電路之時鐘樹狀構造之操作。在此第一實施例中，多相位時鐘信號 (：1^_八至(：1^ — 11可經由多工器1*(：101至1^108、^^201至 MC216、與MC301至MC316選擇性分配至各分割領域Areai至 Area 16 〇圖9顯不用於時鐘分配的多〆發 iVil丄 U 丄芏MUi III V, ^ υ 1 至MC216、與MC301至MC316之控制信號s〇、S1、與S3和分配至晶片上之各分割領域Areai至Areai 6的時鐘信號間之關係。然而，圖9僅顯示多工器MCI 01至MCI 04、MC201至 MC2 04、與MC3 01至MC3 04之控制信號s〇、S1、與S3以及分配至分割領域Areai至Area4之時鐘信號。虽控制化號3〇、si、與S3皆為” 〇〇〇’，時，多工器MC1 〇1 至MCI 08選擇並輸出時鐘信號cu—A。類似地，當控1制信號山S1、與^皆為"〇〇1"時，多工器MC101至1^108選擇並輸二日= 信號CLK_B，#其皆為"〇1〇"時則選擇並輸出時鐘 ίΛ :甘皆為"〇11"時則選擇並輸出時鐘信號 Μ嘴;® '皆為1 〇〇"時則選擇並輸出時鐘信號CLK-E， ^時Λ /Λ信飢K—F當其皆為"1Q1"時，當其皆為時則選擇並輸出時鐘信號CLK_H。一且田八白為m 輸出而丨：為:0。”時，MC201·16選擇並牛例而a ，在MC201之情況中，Mcl〇1之輪 556344 五、發明說明（13) 出）。類似地，當控制信 MC216選擇並輸出第二 ^白為時，1〇2〇1至中，ΜΠ02之輪出），當J 在_!之情況入（舉例而言，在MC2H白/ 10時則選擇並輸出第二| 之情況中，MC104之輸出）。11入（舉例而言，在MC201 且當控制信號S。為"丨"時則選擇並:兄MC二之二出）’ 言’在MC301之情況中，MC2〇2之輸出）。牛例而因此，倘若各多工器MC101至虹1〇4、MC2〇l 與MC3IH臟3G4之控制信㈣、S1、與S3之值設定成 =圖 9所不，則時鐘信號CLK—A或以[c可選擇性分配至分割領曰域Areal與Area2，且時鐘信號CLK—(^tCLK_D可選擇性分配至分割領域Area3與Area4。類似的控制可進行於其他多工器MC105 至MC108、MC20 5 至MC216、與MC3 0 5 至MC316 上。所以，多相位時鐘信號CLK—A至CLK—H可選擇性分配至分割領域Area5 至Area6 〇應注意：多相位時鐘信號CLK_A SCLK_H中哪一個時鐘信號分配至哪個數目的分割領域係由半導體積體電路之規格所決定。然後，控制信號SO、S1、與S3之設定係實行於順序電路單元2與組合電路單元3皆形成於晶片上之後的配線步驟中。亦即，連接至電源供應器的配線圖案係形成來用以設定控制信號之值為π 1π，且連接至地面的配線圖案556344 V. Description of the invention (12) It is represented by only three control signals SO, S1, and S2. However, the control signals SO, S1, and S2 are different for each multiplexer. The operation of the clock tree structure of the semiconductor integrated circuit in this first embodiment will be described below. In this first embodiment, the multi-phase clock signals (: 1 ^ _eight to (: 1 ^ -11) can be passed through the multiplexer 1 * (: 101 to 1 ^ 108, ^^ 201 to MC216, and MC301 to MC316 Selective allocation to each segmented area Areai to Area 16 〇 Figure 9 shows multiple transmissions iVil 丄 U 丄芏 MUi III V not used for clock distribution, ^ υ 1 to MC216, and control signals s0, S1, and MC301 to MC316 The relationship with S3 and the clock signals assigned to the divided areas Areai to Areai 6 on the chip. However, Figure 9 only shows the control of the multiplexers MCI 01 to MCI 04, MC201 to MC2 04, and MC3 01 to MC3 04 Signals s0, S1, and S3, and the clock signals allocated to the divided areas Areai to Area4. Although the control numbers 30, si, and S3 are "00", the multiplexers MC1 〇1 to MCI 08 The clock signal cu-A is selected and outputted. Similarly, when the control signals S1, S1 and ^ are both " 〇〇1 ", the multiplexers MC101 to 1 ^ 108 select and output the second day = signal CLK_B, # When all of them are " 〇1〇 ", the clock is selected and outputted. Λ: When all are " 〇11 ", the clock signal M is selected and outputted; ® 'are all 1 〇 When "" selects and outputs the clock signal CLK-E, when ^ Λ / Λ is hungry K-F when both are " 1Q1 ", when they are both, select and output the clock signal CLK_H. For m output:: 0: ", MC201 · 16 selects and combines the example and a. In the case of MC201, the wheel of MclO1 556344 V. Invention description (13)) Similarly, when the control When the letter MC216 selects and outputs the second white, it is 1021 to the middle, and the round of MII02 comes out. When J enters in the case of _! (For example, when MC2H white / 10, it selects and outputs the second In the case of ||, the output of MC104). 11 in (for example, in MC201 and when the control signal S. is " 丨 " then select and: brother MC two out) In the case, MC2 0 2). Therefore, if the values of the control signals, S1, and S3 of each of the multiplexers MC101 to Rainbow 104, MC2101, and MC3IH dirty 3G4 are set to = not shown in Figure 9, the clock signal CLK-A or [C can be selectively assigned to the division domains Areal and Area2, and the clock signal CLK — (^ tCLK_D can be selectively assigned to the division domains Area3 and Area4. Similar control can be performed on other multiplexers MC105 to MC108, MC20 5 to MC216, and MC3 0 5 to MC316. Therefore, the multi-phase clock signals CLK_A to CLK_H can be selectively assigned to the divided areas Area5 to Area6 〇 It should be noted: which of the multiphase clock signals CLK_A SCLK_H The number of divided areas allocated is determined by the specifications of the semiconductor integrated circuit. Then, the setting of the control signals SO, S1, and S3 is performed on the wiring after the sequence circuit unit 2 and the combination circuit unit 3 are formed on the wafer. In the step, that is, the wiring pattern connected to the power supply is formed to set the value of the control signal to π 1π and is connected to the ground.

第19頁 556344 五、發明說明（14) 係形成來用以設定控制信號之值為” Q ,，。下使用的剩餘順序電路單元2之處理如圖10B題 Γ 單元2之—組態例子之電路圖，且順=路單元2之電路符號。圖wm〇B所示的 ”貝斤電路单元2為一D型正反哭，B甘丄及傳輸閘加謂4所組成。且其由反相謂V1至丽也人φ ^ Γη &例中’ & #成使得在形成順序電路單元2與早r3t晶片上之步驟中，配線不會位於每-順出端Λ鐘輸入部之第'級閑(反相器INV2)之輸線;Π:;)級閘(反相器1_之輸入端子間(圖-之虛電路順ί電路單元2是否不同係取決於半導體積體配晋阶始寺°而定。對於將使用的順序電路單元2而言，於 -ΐ =驟中形成配線圖案，用以連接時鐘輸人部之第、巧NV2之輸出端子與下一級閘丨訂3之輸入端子。另一 f面，對於不會用到的順序電路單元2而言，不备 =於時鐘輸入部之第 '級閘INV2之輪二門 IN?之輪入端子間，且於配置配線步驟 ;級瞻3之輸入端子CB至電源供應器或地面的以下結果’在將使用的順序電路單元2之時鐘輸入 =二，閘INV3之輸人端子CB與輪出端子〇之電位;梦信號CLK (CLK —A至CLK —H)而改變’如圖UA所示在里面，在不會用到的順序電路單元2之時鐘輸入部中，;1Page 19, 556344 V. Description of the invention (14) is used to set the value of the control signal to "Q,". The processing of the remaining sequence circuit unit 2 used below is shown in Figure 10B. Γ Unit 2-Configuration Example Circuit diagram, and cis = circuit symbol of circuit unit 2. The "Baijin circuit unit 2" shown in the figure wmOB is a D-type positive and negative cry, composed of B Ganji and transmission gate plus four. And it is inversely referred to as V1 to Liye φ ^ Γη & in the example '&# so that in the step of forming the sequential circuit unit 2 and the early r3t wafer, the wiring will not be located at every -send out Λ clock The input line of the 'stage idle (inverter INV2); Π :;) stage gate (between the input terminals of the inverter 1_ (Figure-the virtual circuit of the circuit unit 2 is different depends on the semiconductor The product is based on the degree of the first stage. For the sequential circuit unit 2 to be used, a wiring pattern is formed in -ΐ = step, which is used to connect the output terminal of the first and second NV2 of the clock input department to the next stage. The input terminal of the gate 3 is ordered. On the other side, for the sequential circuit unit 2 that will not be used, it is not prepared = between the wheel input terminals of the second stage IN of the 'stage gate INV2 of the clock input part, And in the configuration and wiring steps; the following results from the input terminal CB of the stage 3 to the power supply or the ground ': the clock input of the sequence circuit unit 2 to be used = two, the input terminal CB of the gate INV3 and the output terminal 〇 Potential; the dream signal CLK (CLK —A to CLK —H) changes' as shown in Figure UA, in the order circuit will not be used In the clock input section of element 2; 1

第20頁 556344 五、發明說明（15) 級閘INV3之輸入端子CB與輸出端子〇之電位不合改變，如二HB所示。因而，基於時鐘信號CLK的開關操9作不會實 _ 每一多工器MC301至MC316之負載係順序電路元2 時鐘輸入部之第一級閘。因此，倘若順序電路單元2 地指派至各多工器MC301至MC316，則連接至各多工器一 MC301至MC316的閘之數目彼此相等。所以，$工的 MC3〇1至化316之負載彼此相等而不會產生任何浮置=。為亦且，在此第-實施例中，設計成使得配線不會於不會用到的剩餘順序電路單元2之時鐘輸入部之第一級閘之輸出端子與下一級閘之輸入端子間。因此，在此剩順序電路單元2中，反相器INV3與圖12中畫有斜線㈣輸、閘TG1至TG4變成非負載電晶體。所以，相較於所有順序電路單元無論其使用如何皆變成負載之習知的半導體積體路而言，可降低電力消耗。、應注意，在此第一實施例中，設計成使得時鐘信號之相位數目為八，多工器亂101至紅108、1^201至1^216、盥 MC301至MC316之輸入信號之數目分別為八、四、盥二，時鐘樹之級之數目為三且晶片上的分割領域之數目為;六: :然，其數目不僅限於前述數值。亦I，在此第一實施例，所有時鐘樹皆藉由使用多工器而構成。然而，其不僅限於多工器。其中一部分得為時鐘緩衝器，而非多^器。抑亦且，在此第一實施例中，順序電路單元2與組合電路單7〇3父替地配置於每一列上。然而，順序電路單元2與Page 20 556344 V. Description of the invention (15) The potential of the input terminal CB and the output terminal 0 of the stage gate INV3 does not change as shown in Figure 2HB. Therefore, the switching operation based on the clock signal CLK will not be implemented. The load of each multiplexer MC301 to MC316 is the first-stage gate of the clock input section of the sequential circuit element 2. Therefore, if the sequence circuit unit 2 is assigned to each of the multiplexers MC301 to MC316, the number of gates connected to each of the multiplexers MC301 to MC316 is equal to each other. Therefore, the load of MC3101 to Hua316 of $ work is equal to each other without any floating =. In addition, in this first embodiment, it is designed so that the wiring is not between the output terminal of the first-stage gate of the clock input section of the remaining sequential circuit unit 2 and the input terminal of the next-stage gate that will not be used. Therefore, in this remaining sequence circuit unit 2, the inverter INV3 and the diagonal lines in FIG. 12 are drawn, and the gates TG1 to TG4 become unloaded transistors. Therefore, compared with the conventional semiconductor integrated circuit in which all sequential circuit units become loads regardless of their use, power consumption can be reduced. It should be noted that in this first embodiment, the number of phases of the clock signal is designed to be eight, the number of input signals of the multiplexer random 101 to red 108, 1 ^ 201 to 1 ^ 216, and MC301 to MC316 are respectively It is eight, four, and two. The number of levels of the clock tree is three and the number of divided areas on the chip is; six: Of course, the number is not limited to the foregoing value. Also, in this first embodiment, all clock trees are constructed by using a multiplexer. However, it is not limited to multiplexers. Part of it has to be a clock buffer, not a multiplier. Furthermore, in this first embodiment, the sequential circuit unit 2 and the combined circuit sheet 703 are alternately arranged on each column. However, the sequential circuit unit 2 and

第21頁 556344 五、發明說明（16) 組ί電路單元3得交替地配置於每一行上。亦且，順序雷路早兀2與組合電路單元3得以棋格狀配置。路、一 2與組合電路單元3交替配置之理由係為了均句 :::等元2。於分割領域内，㈣吏從多工器起的 [第二實施例] 圖1 3A係依據本發明第二實施例之順序電路路圖，且圖13β顯示圖13A之順序電路單元電類似於圖1〇Am〇B之組態部分具有相同m。，所示的順序… 器，且扠有反相器iNV1、INV3 生止反與反AND閘NANDI。、專輪閑TG1至K4、在此第二實施例中，不同於垂得在形成順序電路單元2盥έ人雷 / ’ 設計成使中，每-順序電路翠元2;:; = :3於/曰片上之步驟之輸出端子與下一級閘“”趴里\ σ之第—級閘NAND1 的順序電路單元”，於配置配輪二端子部連接。在將使用號CLK—EN設定為”丨，，的配線圖案（·連乂驟中形成時鐘賦能信圖案）。在不會用到的剩餘 ^ w電源供應器的配線能信號CLK-EN設定為"〇”的電路單元2中，形成時鐘賦案)。以線圖案(連接至地面的配線；所以，在將使用的順序下一級閘INV3之輸入端子⑶鱼略早兀2之時鐘輸入部中， >、輪出端子C之電位基於時鐘 556344 五、發明說明（17) 信號CLK(CLK—A至CLLH)而改變，面，在不會用到的順序電路單元 f所示。另一方級閘INV3之輸入端子CB與輸出二^時鐘輪入部中，下一 14B所示。在此情況中，不奮而之電位不改變，如圖作。仃基於時鐘信號CLK的開關操結果，在未使用的剩餘順序 IM3與圖15甲劃有斜線的诗輪路^ 702中，反相器體。因此，可獲得低偏變成非負載電晶一實施例。計/、低電力4耗之效果，類似於第應注意’在此第二實施你丨由邻之篦一铋門缺二耳％例中，反and間用於時鐘輪入邛弟、，及閘。然而不限於反AND閉若使用麵閉，則對於將使用的順序電路，號CLK EN得設定為"〇"，且對於不會用到的順γ電里：早兀2而$時鐘賦能信號CU_EN得設定為，，〗"。缺而广須使時鐘之相位等於第—實施例所述'電^右 2，則必須在緊接於反AND閉之時鐘輸端子處裝設一級反相器。丁之引次在輸出 [第三實施例] 在依據第一與第二實施例之半導體積體電路中，於使用的順序電路單元2中，阻止輸人時鐘錢傳輸至下、— 級閘（反相器INV2)使順序電路單元2之操作停止。相反地，在依據第三實施例之半導體積體電路中，抑制鐘樹狀構造的多工器之輸出使連接至多工器之下游的順序Page 21 556344 V. Description of the invention (16) Group 3 circuit units 3 must be alternately arranged on each row. Also, the sequential lightning circuit 2 and the combination circuit unit 3 are arranged in a checkerboard pattern. The reason that the circuit, one 2 and the combination circuit unit 3 are alternately arranged is for equal sentence ::: equal element 2. In the field of segmentation, [second embodiment] from the multiplexer FIG. 13A is a sequential circuit diagram according to the second embodiment of the present invention, and FIG. 13β shows the electrical circuit similar to the sequence circuit unit of FIG. 13A The configuration part of 1〇Am〇B has the same m. In the sequence shown ..., and the inverters iNV1, INV3 are crossed and the AND gate NANDI is generated. Special round-trip idles TG1 to K4. In this second embodiment, it is different from the vertical circuit that forms the sequential circuit unit 2 and is designed to make every-sequential circuit Cuiyuan 2;:; =: 3 The output terminal of the step on the chip is connected to the next-stage gate "" Sequence circuit unit of the first-stage gate NAND1 of the first stage gate σ ", which is connected to the second terminal of the configuration wheel. When the use number CLK-EN is set to"丨,, Wiring pattern (· Clock enabling letter pattern is formed in the successive steps). In the circuit unit 2 where the wiring power signal CLK-EN of the remaining ^ w power supply is not used is set to "0", a clock scheme is formed. In a line pattern (wiring connected to the ground; therefore, in In the order of the input terminal ⑶ of the next stage gate INV3, the clock input part of the slightly earlier U2, > The potential of the round-out terminal C is based on the clock 556344 V. Description of the invention (17) The signal CLK (CLK-A to CLLH ), It is shown in the sequence circuit unit f, which will not be used. The input terminal CB and the output of the second-stage gate INV3 are shown in the next 14B. In this case, do not fight The potential does not change, as shown in the figure. 仃 Based on the switching operation results of the clock signal CLK, the inverter body is in the unused remaining sequence IM3 and Figure 15A with a slanted line ^ 702. Therefore, it is possible to An example of obtaining a low bias to become a non-loaded transistor. The effect of the calculation and / or low power consumption is similar to that of the first attention. And room is used for clocks to enter the younger brother, and the gate. However, it is not limited to anti-AND closing With the surface closed, for the sequential circuit to be used, the number CLK EN must be set to "quot; 〇", and for the unused γ-channel: early 2 and the $ clock enable signal CU_EN must be set to, If you want to make the phase of the clock equal to the "electrical right 2" described in the first embodiment, you must install a first-level inverter directly at the clock input terminal of the anti-AND switch. In the output [Third Embodiment] In the semiconductor integrated circuit according to the first and second embodiments, in the sequence circuit unit 2 used, the input clock money is prevented from being transmitted to the lower-level gate (inverter INV2) stops the operation of the sequence circuit unit 2. On the contrary, in the semiconductor integrated circuit according to the third embodiment, the output of the multiplexer with a bell-tree structure is suppressed and the sequence connected downstream of the multiplexer is suppressed.

第23頁 556344 五、發明說明（18) 電路單元2之操作停止。 —盥ί此H:例中用於時鐘分配的多工器係藉由對第 ί條m、i?B、與i?c所示。此賦能端子_依據；止條件而控制。啤斤圖1 7 A顯示八個絡λ ^ 1固翰入與一個輸出之多工器，具有賦能賦处山，且用作^多工器MC101至MC1〇8。倘若供給"1"至 S2 : ί :EN 2 ί停止條件，則此多工器依據控制信號s。至亚輸出八個輪入信號中之任-個。另-方面，i s:二賦能端子EN作為停止條件，則無論控制信於 so至S2如何其總是輸出"〇"。唬端子：ΠΒ:用不::,入。與一個輸出之多工器，具有賦能為夕工器MC201至MC216。倘若供給"1"至條件，則此多工器依據控制㈣。與若供給"〇"至m入作之任一個。另一方面，倘 s〇與以如何其總是輸出"〇! μ止條件’則無論控制信號圖17C顯不一個輪入與一個輸出之工能端子ΕΝ，且用作為多工謂斯麗⑴。其工、有喊控制信號別而選擇並輸出二個輸入信號中之任一個：：： ”0:至賦作為停止條件，則無 J二给其總是輸出，，〇”。 ^ ^ Ιύυ如何現在，如圖16所示，讓我們假設存在於分割領虼Page 23 556344 V. Description of the invention (18) The operation of the circuit unit 2 is stopped. — This H: The multiplexer used in the clock distribution in the example is shown by m, i? B, and i? C. This enabling terminal is controlled according to the conditions. Fig. 17 A shows eight multiplexers with λ ^ 1 solid input and one output. It has an energizing multiplexer and is used as ^ multiplexers MC101 to MC108. Provided that "1" to S2: ί: EN 2 ί stop condition, this multiplexer is based on the control signal s. To Ya output any one of the eight turn signals. On the other hand, if s: the second enabling terminal EN is used as a stop condition, it will always output " 〇 " regardless of the control signals from so to S2. Blind terminal: ΠΒ: use or not ::, enter. Multiplexers with one output, with enablers MC201 to MC216. If the "1" condition is supplied, this multiplexer is based on control. And if supply "quota" to "m" any of the entries. On the other hand, if s〇 and how it always outputs " 〇! Μstop condition ', then regardless of the control signal, Fig. 17C shows one rotation and one output function terminal EN, and it is used as a multi-tasking siri Alas. It can select and output any one of the two input signals according to the control signal and the output signal :: ”0: To assign as a stop condition, then there is no J 2 to always output it, 0”. ^ ^ How about Ιύυ Now, as shown in Figure 16, let us assume that the

第24頁 556344 - Ill· 五、發明說明（19) 一real、Area2、與Area6，以及Areal3 至Areal6(斜線所指不的部分）中的所有順序電路單元2皆不使用。在此情況中，用以驅動二個分割領域Areal iArea2之，序電路單元2的多工器MC201，MC202之輸出受抑制。此係藉由供給"〇"至如圖17B所建構成的多工器肊2〇1與 ^202之賦能端子EN而完成。因此，停止分配時鐘芦號至二割領域Areal與柝“2 ^換言之，時鐘信號之開關停止， 2之以Λ止在分割領域Areal與Area2中的所有順序電路單元刼作。甚至可藉由抑制多工器MC3〇1 貫行類似於前述操作的操作。 <輸出而工写驅動分割領域A·6之順序電路單元2的多輸受到抑制。此抑制係藉由供給"〇'，至如圖建構的多工器MC306之賦能端子εν而完成。，此，停止分配時鐘信號至分割領域Area6。換古日、釦仏號之開關停止，藉以停止在此分i彳領# Α、" β 中的所有料電料元2之操作。以域Area6Page 24 556344-Ill. V. Description of the Invention (19)-All sequential circuit units 2 in Real, Area2, and Area6, and Areal3 to Areal6 (the parts indicated by the slashes) are not used. In this case, the outputs of the multiplexers MC201 and MC202 of the sequence circuit unit 2 used to drive the two realm areas Areal iArea2 are suppressed. This is accomplished by supplying " 〇 " to the energizing terminals EN of the multiplexers 肊 201 and ^ 202 constructed as shown in Fig. 17B. Therefore, stop allocating the clock Alu to the area Areal and 柝 "2 ^ In other words, the switching of the clock signal is stopped, and 2 is to stop all sequential circuit units in the area Areal and Area2 to operate. It can even be suppressed by The multiplexer MC3〇1 performs an operation similar to the foregoing operation. &Lt; Multiple inputs of the sequential circuit unit 2 of the output and the write driving division area A · 6 are suppressed. This suppression is provided by supplying " 〇 'to The enabling terminal εν of the multiplexer MC306 constructed as shown in the figure is completed. Then, stop distributing the clock signal to the divided area Area6. The switch for the ancient day and the deduction number stops, thereby stopping at this point i 彳领 # Α 、 " Operation of all materials and materials in β2. Take Area6

再者’用以驅動在四個分割領域A ；J t ^ ^ ^€21 3 ；]Μ〇2ΐΓ^ ΙΓ ^ =制係藉由供給|| 〇’，至如圖】7Β所建出工=Furthermore, ′ is used to drive A in four segmented areas; J t ^ ^ ^ € 21 3;] M〇2ΐΓ ^ ΙΓ ^ = system is provided by the supply || 〇 ′, as shown in Figure 7B.

Μ。1 6之賦能端子Ε Ν。因此，停止夕-=J 域teaU至Areal6。換ϋ至刀割領停止在分割領域Areal3^reaH::開關停止’藉以之操作。甚至可蕤由太、有順序電路單元2 ^ #s y 爸主了精由抑制多工器MC313至MC31R夕仏b — 仃類似於前述操作的操作。輸出而貫第25頁 556344 五、發明說明（20) Ί ’雖然未圖示於圖16中，倘若假在於八個分割領域_至“8中的所有順序電存 2 ’口則一用=，動在八個分割領域Areal ^rea8中的順序電 Α)ϋΜπ〇α_4之輸出受抑制。此抑制係措由供給0至如圖17Α所建構的多工器肊1〇1至肊1〇4之賦能端子ΕΝ。因此，停止分配時鐘信號至分割領域Areai^Μ. 1 6 enabling terminal EN. Therefore, stop the evening-= J domain teaU to Areal6. Change to the cutting collar and stop in the realm of division Areal3 ^ reaH :: switch stop ’. You can even use the sequential circuit unit 2 ^ #s y to control the multiplexer MC313 to MC31R evening 仏 b — 仃 operation similar to the previous operation. Output continues on page 25 556344 V. Description of the invention (20) 虽然 'Although it is not shown in FIG. 16, if it lies in eight divided fields _ to “all sequences in 8 are stored 2’ then use ==, Sequential power in the eight segmented areas Areal ^ rea8 is suppressed. The output of the ΔΜπ〇α_4 is suppressed. This suppression measures from supply 0 to the multiplexer 肊 101 to 肊 104 which is constructed as shown in FIG. 17A. Enabling terminal EN. Therefore, stop distributing clock signals to the split area Areai ^

Areas。換言之，時鐘信號之開關停止，藉以停止在分領域人1^&1至奸638中的所有順序電路單元〗之操作。在^ 情況中，甚至可藉由抑制多工器虹2〇1至趴2〇8或多工 MC301至MC308之輸出而實行類似於前述操作的操作。° 各多工器MC101 至MC108 、MC201 至MC216 、與MC301 至 MC31 6之賦能端子EN之停止條件設定為"丨"或"〇”係基於導體積體電路之規格而定。㈣，在順序電路單元土2與組合電路單tg3形成於晶片上之後的配線步驟中設定賦能子EN。 # —亦即，在配置步驟完成之後檢查是否存在有順序電路早兀2皆未使用的分割領域。倘若判斷存在有順序電路單元2白未使用的分割領域，則用以分配時鐘信號至該分到領域的多工器之賦能端子EN設定為"〇，，。 ° 在圖16所示的例子中，判斷出分割領域Area6中之序電路單元2皆未使用。因此，多卫說州之賦能端子㈣設定為”0”。亦且，判斷出分割領域中的序電路單元2皆未使用。因此，多工器MC3〇1與以“？或工器MC201與MC202之賦能端子EN設定為”〇”。再者，判斷Areas. In other words, the switch of the clock signal is stopped, thereby stopping the operation of all the sequential circuit units in the sub-field person 1 ^ & 1 to 638. In the case of ^, it is even possible to perform an operation similar to the aforementioned operation by suppressing the output of the multiplexer rainbow 201 to 208 or the multiplex MC301 to MC308. ° The stop conditions for the multiplexers MC101 to MC108, MC201 to MC216, and MC301 to MC31 6 are set to "" 丨 " or " 〇 '' based on the specifications of the conductive body circuit. ㈣ , Set the energizer EN in the wiring step after the sequential circuit unit soil 2 and the combined circuit unit tg3 are formed on the wafer. # — That is, after the configuration step is completed, it is checked whether there is any sequence circuit that is not used. Segmented field. If it is judged that there is an unused segmented field of the sequential circuit unit 2, the enable terminal EN of the multiplexer used to distribute the clock signal to the segmented field is set to " 〇 ,,. In the example shown, it is determined that none of the sequence circuit units 2 in the divided area Area 6 is used. Therefore, the daemon said that the enabling terminal ㈣ of the state is set to "0". Also, the sequence circuit units in the divided area are determined 2 are not used. Therefore, the multiplexer MC3〇1 and "? OR Enable terminals EN of the MC201 and MC202 are set to "0". Furthermore, judgment

556344 五、發明說明（21) 出分割領域人^313至人1^316中的順序電路單元2比用。所以，多工器以313至化316或多工器MC213^ 賦能端子Μ設定為"0"。然後，⑨了前述端子端子ΕΝ皆設定為"1”。 |〜賦能端子ΕΝ係藉由連接配線圖案至賦能端子⑽而役定。倘若賦能端子EN設定為” 1 "，則連接於社人0 應器的配線圖案。倘若其設定為"〇"，則連：“= 面的配線圖案。丧於、，、〇口至地如前所述，在依據此第三實施中，停止分配時鐘信號至僅由未使積f電路構成的分割領域，藉以停止未使順.电路單兀2所作。因此，相較於習知的技Π:;?;:;:之操力消耗可降低，類似於第一實施例。+導體積體電路之電如前所述，依據本發明，順序電 :交替地配置於半導體晶片上之内部核有連接成樹狀的複數個選擇驅動元件，用=，且裝汉相位時鐘信號予藉由均勾分割内部核二選擇性分配多分割領域。然後，該複數個選 ^域所形成的每一得在半導體晶片上古〃配置並連接成使到各分割領域内的順序電路單元之部份=輸入端子上彼此相等。因此，可在負載與配線長度配線長度相等的時鐘^二二夕才、位時鐘信號且負載與之時鐘偏斜。 &。所以’可降低順序電路間亦且’順序電路單元包括第弭閘兀件，設置於第五、發明說明（22) 一一、、及¥鐘輸入部，以及第二邏輯間的順序電路單元而言，連接，其令對於將使用件之輸出端子與第二邏輯閑：：：=於第-邏輯間元會：到的順序電路翠元而言’=、:以且對於不疋件之輪出端子與第二邏輯閘元件之置於弟一邏輯閘 =閑元件之輸入端子連接至電源供J =間’且第二，損失可降低至最小，同時維二電=電力亦且，順序電路單元包括. f的負載構造。第一級時鐘輸入部，用以賦能第閉元件，放置於基於多相位時鐘信號而決定，〜、，其令輸出電位係 :立f固定的無論將經由賦能信號所其中輸出電如何；以及第二邏輯閘元件，1 ^擇的多相位時鐘信號輯閘元件之輸出端子，呈二二輪入端子連接至第一邏言，賦能信號設定成使得第1輯i用:順序電路單元而且對於不會使用的順序電路單元件變成第-狀態，得第一邏輯閜元件變成第二狀離二，賦能信號設定成使用的順序電路單元所消耗二H既然可降低未使低至最小，同時維持相等的負播故電力消耗之損失可降再者，倘若在該複數個選 2，° 件之下游的分割領域中之順2擇驅動元件之一選擇驅動元成阻止該選擇驅動元件之輸電路單元皆未使用，則設計序電路單元所消耗的電力7且因此，可降低未使用的順小，同時維持相等的負載構造可抑制電力消耗之損失至最第28頁 M6344 圖式簡單說明平面顯示f知的母片型半導體積體電路之晶片構造之二？ is係-半導體積體電路之電晶體單元之放大平面圖；配方、去/工不在習知的母片型半導體積體電路中之時鐘分灰又平面圖；造之平面頁圖不·另一習知的母片型半導體積體電路之晶片構電路曰顯^依據本發明第一實施例之母片型半導體積體〜曰曰乃構造之平面圖；路级ΓΛ不部依第—實施例之時鐘樹狀構造的電路組Γ之顯另不依邱據、本發明第-實施例之時鐘樹狀構造的電心之另一部分之電路圖；圖7顯示依據本發明第—每路組態之又另一部分之電路圖只;⑽之時鐘树狀構造的電圖8顯示依據本發明第一路組態之再另一部分之電路圖貝靶例之牯鐘树狀構造的電圖9顯示具有用於時鐘制信號與分配至晶片上-冋驅動力的夕工器之控圖10A顯示在本發明第域的時鐘信號間之關係；一組態例子之電路圖；只施例中之順序電路單元之圖10Β顯示圖10Α所示的圖1 1 Α與1 1Β顯示在本笋具^電路單元之電路符號；元之時鐘輸入部之操作；*月第—實施例中之順序 ---^ _ 556344 圖式簡單說明556344 V. Description of the invention (21) The sequence circuit unit 2 in person ^ 313 to person 1 ^ 316 in the segmentation field is compared. Therefore, the multiplexer uses 313 to 316 or multiplexer MC213 ^ to enable the terminal M to be set to " 0 ". Then, the aforementioned terminal terminals EN are all set to "1". | ~ The enabling terminal EN is fixed by connecting the wiring pattern to the enabling terminal ⑽. If the enabling terminal EN is set to "1", then Wiring pattern connected to company 0 reactor. If it is set to " 〇 ", then: "= wiring pattern of the surface. As described above, in the third implementation, stop distributing the clock signal to the The segmentation field composed of the product f circuit is used to stop the non-obedience. The circuit unit 2 is made. Therefore, compared with the conventional technique Π:;?; :::, the operating power consumption can be reduced, similar to the first implementation For example, the electricity of the + conducting volume circuit is as described above. According to the present invention, the sequence electricity: the internal cores alternately arranged on the semiconductor wafer are connected with a plurality of selection driving elements connected in a tree shape, and a phase clock is installed. The signal is divided into multiple division areas by dividing the internal core and then selectively dividing each other. Then, each of the plurality of selection areas is arranged on the semiconductor wafer and connected to form sequential circuit units in each division area. Part = The input terminals are equal to each other. Therefore, a clock with the same load and wiring length as the wiring length can be used, the bit clock signal, and the load is skewed from the clock. &Amp; so 'can reduce the sequence circuit Also 'order The circuit unit includes a first gate element, which is provided in the fifth, description of the invention (22), a clock input unit, and a second circuit. The sequential circuit unit is connected between the second logic, which makes The output terminal and the second logic are free :: == in the first logic interval: to the sequence circuit Cuiyuan '= ,: and for the placement of the unused wheel output terminal and the second logic gate element Diyi logic gate = the input terminal of the idle element is connected to the power supply for J = between 'and the second, the loss can be reduced to the minimum, while the second dimension power = electricity, and the sequence circuit unit includes the load structure of f. The first stage The clock input unit is used to energize the first closed element, and is determined based on the multi-phase clock signal. The output potential is fixed: regardless of the output power through the energization signal; and the second The logic gate element, the output terminal of the selected multi-phase clock signal gate element, is connected to the first logic word by two or two round-in terminals. The enable signal is set so that the first series i is used: sequence circuit unit and Sequential circuit board that will be used The first logic element becomes the second state, the second logic element becomes the second state, the energization signal is set to the second circuit consumed by the used sequential circuit unit. Since the H can be reduced, the power is not minimized, and the same negative power is maintained. The loss of consumption can be reduced. If one of the two optional drive elements in the segmented field downstream of the plurality of selected drive elements is selected to drive the element to prevent the transmission circuit units of the selected drive element from being unused, Design the power consumed by the sequence circuit unit 7 and therefore, reduce the unused power while maintaining the same load structure. The loss of power consumption can be suppressed to the maximum on page 28. M6344 The diagram simply illustrates the master chip type shown in the flat display. The second structure of the semiconductor integrated circuit chip structure? Is the enlarged plan view of the transistor unit of the semiconductor integrated circuit; the formula, removal / work are not in the conventional mother chip semiconductor integrated circuit, the clock is grayed out and the plan view; The plan page view is not a wafer structure of another conventional mother chip semiconductor integrated circuit. The mother chip semiconductor integrated circuit according to the first embodiment of the present invention is A plan view of the structure; The circuit level ΓΛ does not follow the circuit tree structure of the clock tree structure of the first embodiment according to the embodiment of the circuit tree Γ; FIG. 7 shows a circuit diagram of yet another part of each configuration according to the present invention; FIG. 8 shows a clock tree structure of the present invention. FIG. 8 shows a circuit diagram of another part of the first configuration according to the present invention. Figure 9 of the clock tree structure shows the control of the clock device with the clock signal and the driving force assigned to the wafer- 冋 driving force. Figure 10A shows the relationship between the clock signal in the third domain of the present invention; a circuit diagram of a configuration example; Fig. 10B of the sequential circuit unit in the embodiment only shows Figs. 1A and 11B shown in Fig. 10A. The circuit symbols of the circuit unit are shown in this example; the operation of the clock input unit of the yuan; Order in --- ^ _ 556344 Schematic illustration

圖1 2顯不在本發明笛，丨rb X 之非負載電晶體；弟—實施例中之剩餘順序電路單元路圖圖UA係依據本發明第二實施例之壞序電路單元之電圖13B顯示圖12A所示的順序一圖HA與14B顯示在本發明第二徐單元之電路符號；疋之時鐘輸入部之操作；〜只施例中之順序電路™ 圖1 5係說明在本發明第二每早 70之非負載電晶體之圖；例中之剩餘噸序電腺抑圖1 6係說明在本發明第三每早兀之操作停止之情況之圖；以及&例中之剩餘順序電路w 圖17A至17C顯示在本發明第= 早順序電路單元之操作的選擇 ^實施例中用之魬態。 M钕止剩餘【符號說明】 1 母片型半導體積體電路 2 順序電路單元 3 組合電路單元電路Fig. 12 shows a non-load transistor of the present invention, rb X; the circuit diagram of the remaining sequential circuit unit in the embodiment-UA is an electrical diagram of a bad sequence circuit unit according to the second embodiment of the present invention. The sequence shown in Fig. 12A-HA and 14B are shown in the circuit symbol of the second Xu unit of the present invention; the operation of the clock input section of the present invention; ~ only the sequence circuit in the embodiment; A diagram of a non-loaded transistor at 70 every morning; the remaining ton-sequence electricity glands in the example are shown in FIG. 16 are diagrams illustrating the situation where the operation is stopped at the third early stage of the invention; and the remaining sequence circuit in the & example w FIGS. 17A to 17C show states used in the selection of the operation of the early sequence circuit unit according to the present invention. M neodymium only remaining [Description of symbols] 1 Mother-chip semiconductor integrated circuit 2 Sequential circuit unit 3 Combination circuit unit Circuit

101 習知的母片型半導體積體 102 電晶體單元 103 閘極電極 104擴散層 105 第一時鐘緩衝器 106 第二時鐘緩衝器101 Conventional mother chip semiconductor integrated body 102 Transistor unit 103 Gate electrode 104 Diffusion layer 105 First clock buffer 106 Second clock buffer

556344 圖式簡單說明 107 第三時鐘緩衝器 108 電路 201 半導體積體電路 Areal〜Areal6 分割領域 INV1〜INV8 反相器 MC101〜MC105 多工器 MC201〜MC216 多工器 MC301〜MC316 多工器 NAND1 反AND 閘 TG1〜TG4 傳輸閘556344 Brief description of the diagram 107 Third clock buffer 108 Circuit 201 Semiconductor integrated circuit Areal ~ Areal6 Divided field INV1 ~ INV8 Inverter MC101 ~ MC105 Multiplexer MC201 ~ MC216 Multiplexer MC301 ~ MC316 Multiplexer NAND1 Inverse AND Gate TG1 ~ TG4 Transmission gate

Claims

556344 六、申請專利範圍 !· 一種母片型半導體積體電路，包含：配置ί數ΐ順序電路單元與複數個組合電路單元，交替地複叙f導體晶片上之一内部核心領域中；以及 -多選擇驅動元件，連接成樹狀，用以選擇性分配的每一分===號予藉由均勻分割該内部核心領域所形成，該複數個選擇驅動元件係配置並連接於該半導使得輸入有該多相位時鐘信號的輸入端子與各 ^μ域内的該順序電路單元間之負戟與配線長度彼此相導體積體電路，其中含：鏠輸入部之一第一以及者該弟一邏輯閘元件順序電端子與路單元於該第該輸入一電源 2.如申請專利範圍第1項之母片型半該複數個順序電路單元中之每一個包一第一邏輯閘元件，放置於一時級，其上輸入有該多相位時鐘信號；一第二邏輯閘元件，放置於緊接之後，並且複數個順序電路單元中配線設於該第一邏輯閘元件之一輸入端子間，的一順序電路單元中， C子與該第二弟-邏軏閉元件之該輸之將使用的一元件之一輸出且在該順序電该配線不置放邏輯閘元件之入端子連接至其中在該路單元中，一該第二邏輯閘中之不會用到一邏輯間元件端子間，且該供應器或地面556344 6. Scope of patent application! · A mother-chip semiconductor integrated circuit, comprising: configuring a sequence circuit unit and a plurality of combination circuit units to alternately recapitulate an internal core area on an f-conductor wafer; and- Multiple selection driving elements are connected in a tree shape, and each point for selective allocation is formed by uniformly dividing the internal core area. The plurality of selection driving elements are configured and connected to the semiconductor to enable input. The multi-phase clock signal input terminal and the sequence circuit unit in each ^ μ domain are connected to each other and the wiring length is a volumetric body circuit, which includes: 之一 one of the input parts first and the brother a logic gate The component sequential electrical terminals and circuit units are at the first input and a power supply. 2. If the mother chip type of the first patent application scope is half of each of the plurality of sequential circuit units, each of the plurality of sequential circuit units includes a first logic gate component and is placed at a time level. , The multi-phase clock signal is inputted thereon; a second logic gate element is placed immediately after, and the wiring device is arranged in a plurality of sequential circuit units; In a sequential circuit unit between one of the input terminals of the first logic gate element, one of a component to be used for the output of C and the second brother-logic shut-off element is output and the wiring is electrically connected in the sequence. The input terminal of the non-positioned logic gate element is connected to one of the second logic gates in the circuit unit, and the logic terminal element is not used, and the supplier or the ground

第32頁 556344 六、申請專利範圍 3該複如數申個:專序利電:圍严1項之母片型半導體積體電路，其中一第一、羅卓。路早兀中之每一個包含：級，其輪入’放置於該時鐘輸入部之-第- 擇一第一狀,ίί二時鐘信號，且基於一賦能信號而選於該多相位；鐘，J:t態，該第-狀態係-輸出電位基位時鐘信號如何‘二ί定，而該第二狀態係無論該多相一曾 17该輸出電位皆為固定丨以及弟一邏輯閘元件，Α 閘元件之-輸出端子，並；輪入端子連接至該第-邏輯其中在該順序電路單中，該職能产跋在中將使用的一順序電路單元 :狀態，且該第狀Ϊ賦能信號係設定成使得該第-邏輯閉元件ΐί t姑如里申請專利範圍第1項之母片型半導體積體電路’其中其上藉由該複ΐ個選擇驅動元件中之-選擇驅動刀配有該多相位時鐘^號之該每一分割領域中的順序電路單元，或者放置於其上藉由該一選擇驅動元件經，一不同的選擇驅動元件而分配有該多相位時鐘信號之$ 每一分割領域中的一順序電路單元不使用時，阻止^ — μ 擇驅動元件之輸出。選Page 32 556344 VI. Scope of patent application 3 This is as many as possible: special order Leeden: mother chip semiconductor integrated circuit with strict enumeration 1, one of which is Luo Zhuo. Each of the Luzaowu includes: a stage, which is placed in the clock input section-the first-choose one, two clock signals, and is selected in the multi-phase based on an enable signal; the clock , J: t state, the first state is how the output potential base clock signal is determined, and the second state is that the output potential is fixed regardless of the polyphase, the output potential, and the logic gate element. , A-output terminal of the gate element, and the turn-in terminal is connected to the-logic where a sequence circuit unit that will be used in the sequence circuit sheet, the function will be used in the sequence: state, and the first endowment The energy signal is set so that the first logic-closed element can be used as the mother chip semiconductor integrated circuit of the first scope of the patent application, wherein one of the plurality of selection driving elements is selected to drive the knife. The sequential circuit unit in each of the divided fields equipped with the multi-phase clock ^ number, or placed thereon, is allocated with the multi-phase clock signal by the selection driving element via, a different selection driving element One order in each segmented field When the sequence circuit unit is not used, it prevents ^ — μ from choosing the output of the drive element. selected

麵第33頁 556344 六、申請專利範圍 5. -種母片型丰導 —^ 一驊： 1體電路之布局方法，包含下列步配置複數個嘴 μ 匕3下半導體晶片上之〜_ :單凡與複數個組合電單元於〆配置並連接複核心領域中， ·以及分配一多相位時鐘信=選擇驅動元件成樹狀，用以選擇性形成的每一分割領域〜予藉由均勻分割該内部核心領域所其中該複數個選。片上，使得輪入有該件配置並連接於該半導體晶領域内的該順序電政m &鐘信號的輪入端各分割路早-間之負載與配線長度彼二相等。 t、广申:Φ專利範圍第5項之母片型半導體并方法，其中千导體積體電路之布局該複f個順序電路單元中況：-配線不置放於—第一：：形成為下列情件間’該第-邏輯閘元件係放置於輸第二邏輯間元號的一時鐘輸入部之第一黎铷八有該多相位時鐘信緊接著該第一邏輯閘元件之後^ 一邏輯閘元件係放置於其中在該複數個順序電路單元 =單：中，該第-邏輯閘元件之一輸出：該複數個順序電路單元中不會用=此連接，且在該配線不置放於該第一邏輯閘元；序電路單元中，邏輯閘元件之該輸入端子間，且該第二端子與該第二〜、輯閘元件之該輸第34頁 ):)6344See page 33, 556344. 6. Patent application scope 5.-A mother chip type guide-^ 骅: 1-body circuit layout method, which includes the following steps to configure a plurality of mouths on a semiconductor wafer under 3 ~~: single Where a plurality of combined electric units are arranged and connected in a complex core area, and a multi-phase clock signal is assigned = a driving element is selected into a tree shape for selectively forming each of the divided areas ~ by internally dividing the interior uniformly There are several options in the core area. On the chip, the wheel-in end of the sequential electrical m & clock signal with the configuration and connected to the semiconductor crystal field is divided into the load and the wiring length of the divided circuits are equal to each other. t. Guangshen: Φ method of mother chip type semiconductor in item 5 of the patent scope, in which the layout of the thousand-conductor volume body circuit should be in the f sequence circuit units:-wiring is not placed in-first :: formed as the following Between the pieces of information, the first logic gate element is placed in the first input terminal of a clock input unit for the second logic interval, and the multi-phase clock signal is immediately after the first logic gate element ^ a logic gate The element is placed in the sequence circuit unit = single: in, one of the-logic gate elements is output: the connection is not used in the sequence circuit unit =, and the wiring is not placed in the first A logic gate; in the sequence circuit unit, between the input terminals of the logic gate element, and the second terminal and the second ~, the input of the gate element page 34):) 6344

'申請專利範圍 =係於該配置配線步驟中配線連接至一電源供應器或方、、利辨*圍第5項之母片型半導體積體電路之布局 ί;:序電路單元包含·· 一第一邏轾夕一 a k 閑70件’放置於輸入有該多相位時鐘信號鐘輸入部之筮一处热上 ^ <第一級，且基於一賦能信號而選擇-第狀態或一第二壯能々如A 士狀態’該第一狀態係一輸出電位基於該多序目位0^·鐘信' h 於確疋’而該第二狀態係無論該多相位時鐘、戒如何該輸出電位皆固定；以及一第一邏輯閑元件，其一輸入端子連接至該第一邏輯閘元件之一輸出端子，並且敗w其中該複數個順序電路單元中之將使用到的一順序電單几中’該賦能信號之值係設定成使得該第一邏輯閘元於一配置配線步驟中變成該第一狀態，且在該複數個順電路單元中不會用到的一順序電路單元中，該賦能信號之值係設定成使得該第一邏輯閘元件於該配置配線步驟中變成該第二狀態。 •、如申請專利範圍第5項之母片型半導體積體電路之布局方法，其中當放置於其上藉由該複數個選擇驅動元件中之選擇驅動元件而分配有該多相位時鐘信號之該每一分割項域中的一順序電路單元，或者放置於其上藉由該一選擇驢動元件經由一不同的選擇驅動元件而分配有該多相位時'Scope of patent application = the layout of the mother chip semiconductor integrated circuit with the wiring connected to a power supply or a square power supply in the configuration and wiring step 5; the sequence circuit unit contains ... The first logic 70 ak idle 70 pieces' are placed on one of the heat inputs of the multi-phase clock signal clock input part ^ < first stage, and selected based on an enabling signal-the first state or the first The second state can be like the state of A. 'The first state is an output potential based on the multi-order position 0 ^ · Zhongxin' h is determined. 'The second state is the output regardless of the multi-phase clock or how. The potentials are all fixed; and a first logic idle element, an input terminal of which is connected to an output terminal of the first logic gate element, and a sequential electric bill of the plurality of sequential circuit units to be used. "The value of the enabling signal is set so that the first logic gate becomes the first state in a configuration and wiring step, and in a sequential circuit unit that will not be used in the plurality of parallel circuit units, The value of the enabling signal is It is set so that the first logic gate element becomes the second state in the configuration and wiring step. • The layout method of the mother chip type semiconductor integrated circuit such as the item 5 in the scope of patent application, wherein when placed on it, the multi-phase clock signal is allocated with the multi-phase clock signal by the selection driving element of the plurality of selection driving elements. When a sequential circuit unit in each of the divided term domains is placed on it, or the multi-phase is allocated by the selective donkey moving element through a different selective driving element

第35頁 556344 六、申請專利範圍鐘信號之該每一分割領域中的一順序電路單元不使用時阻止該一選擇驅動元件之輸出。Page 35 556344 VI. Patent application scope When a sequential circuit unit in each of the divided fields of the clock signal is not used, the output of the selected driving element is prevented.