JPH05243534A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH05243534A JPH05243534A JP4270892A JP4270892A JPH05243534A JP H05243534 A JPH05243534 A JP H05243534A JP 4270892 A JP4270892 A JP 4270892A JP 4270892 A JP4270892 A JP 4270892A JP H05243534 A JPH05243534 A JP H05243534A
- Authority
- JP
- Japan
- Prior art keywords
- phase clock
- wiring
- integrated circuit
- semiconductor integrated
- cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体集積回路に関し、
特に２相クロックの配線構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
Particularly, it relates to a wiring structure of a two-phase clock.
【０００２】[0002]
【従来の技術】従来例の半導体集積回路の２相クロック
配線のレイアウト図を図３に示す。この図では、スタン
ダードセル列での２相クロックの配線φ１，φ２を示し
ている。図中、１，２は各々、第１相のクロックφ１を
受けるラッチ回路のセル，第２相のクロックφ２を受け
るラッチ回路のセルであり、３〜８は所望機能をもつセ
ルである。2. Description of the Related Art FIG. 3 shows a layout diagram of a two-phase clock wiring of a conventional semiconductor integrated circuit. In this figure, two-phase clock wirings φ1 and φ2 in the standard cell column are shown. In the figure, 1 and 2 are cells of a latch circuit that receives a first-phase clock φ1, a cell of a latch circuit that receives a second-phase clock φ2, and 3 to 8 are cells having a desired function.
【０００３】この回路では、２相のクロック配線φ１，
φ２が、図のようにセル列間の配線チャンネル領域で第
１相クロックφ１と第２相クロックφ２と隣接し、平行
して配線され、各々のラッチ回路のセル１，２に分配さ
れていた。In this circuit, two-phase clock wiring φ1,
.phi.2 was adjacent to the first-phase clock .phi.1 and the second-phase clock .phi.2 in the wiring channel region between the cell columns as shown in the figure, and was wired in parallel and distributed to the cells 1 and 2 of each latch circuit. ..
【０００４】[0004]
【発明が解決しようとする課題】この従来例の構造で
は、前述したように第１相クロックφ１と第２相クロッ
クφ２がスキューを小さくするがために各々隣接し平行
して配線されるため、隣接の距離が長いと、クロストー
クにより誤動作する問題があった。In the structure of this conventional example, as described above, the first-phase clock φ1 and the second-phase clock φ2 are wired adjacent to each other in order to reduce the skew. If the adjacent distance is long, there is a problem that malfunction occurs due to crosstalk.
【０００５】本発明の目的は、このような問題を解決
し、クロストークを少なくして誤動作を除くようにした
半導体集積回路を提供することにある。An object of the present invention is to provide a semiconductor integrated circuit which solves such a problem and reduces crosstalk to eliminate malfunction.
【０００６】[0006]
【課題を解決するための手段】本発明の構成は、２相ク
ロックで動作し、順序回路と組合せ回路とを有し、高さ
の等しい所望の機能をもつセルがゲートアレイまたはス
タンダードセル方式のレイアウトにより構成された集積
回路において、前記２相クロック配線のうち第１相のク
ロック配線をセル高の等しいセル列上辺または下辺に沿
って平行に配線し、第２相のクロック配線を同セル列下
辺または上辺に沿って平行に配線することを特徴とす
る。The structure of the present invention operates with a two-phase clock, has a sequential circuit and a combinational circuit, and cells having a desired function of the same height are of the gate array or standard cell type. In the integrated circuit configured by the layout, the first-phase clock wirings of the two-phase clock wirings are wired in parallel along the upper side or the lower side of the cell row having the same cell height, and the second-phase clock wirings are arranged in the same cell row. It is characterized in that wiring is provided in parallel along the lower side or the upper side.
【０００７】[0007]
【実施例】図１は本発明の第１の実施例でのスタンダー
ドセルの概略レイアウト図である。図において１，２は
ラッチ機能回路セル、３〜７は所望の機能のセル、φ１
は第１相のクロック配線、φ２は第２相のクロック配線
である。セル列とセル列の間はセル間を接続し所望の機
能を得るための配線チャンネル領域であり、通常自動化
が図られ多層のアルミ等で配線される領域である。1 is a schematic layout diagram of a standard cell according to a first embodiment of the present invention. In the figure, 1 and 2 are latch function circuit cells, 3 to 7 are cells having desired functions, and φ1
Is a first-phase clock wiring, and φ2 is a second-phase clock wiring. Between the cell rows is a wiring channel area for connecting the cells to obtain a desired function, which is usually an area where automation is performed and wiring is made of a multi-layer aluminum or the like.
【０００８】本実施例では、第１相のクロック配線φ１
を各セル列の上辺に平行して配線し、第１相クロック使
用のラッチ回路セル１に入力されている。同様に、第２
相クロック配線φ２は同セル列の下辺に平行して配線
し、第２相クロック使用のラッチ回路セル２に入力され
ている。In this embodiment, the first phase clock wiring φ1
Are wired in parallel to the upper side of each cell row and are input to the latch circuit cell 1 using the first phase clock. Similarly, the second
The phase clock wiring φ2 is wired in parallel with the lower side of the cell row and is input to the latch circuit cell 2 using the second phase clock.
【０００９】図２（ａ），（ｂ）は本発明の第２の本実
施例の部分平面図である。本実施例は、図１と異なり、
レイアウトの簡単な平面図であり、図２（ａ）は前述と
同様のラッチ回路セル１，２と、電源線１０，グランド
線１１をセル内に配設している。２相クロックの第１相
クロック配線φ１は、電源線１０の外側に隣接平行し
て、電源線と同一の金属層により配線し、ラッチ回路セ
ル１にコンタクトホール１２を介し入力されている。同
様に、第２相クロック配線φ２は、グランド線１１の外
側に隣接平行して前記と同一の金属層で配線している。FIGS. 2A and 2B are partial plan views of the second embodiment of the present invention. This embodiment differs from FIG. 1 in that
FIG. 2A is a simple plan view of the layout. In FIG. 2A, the same latch circuit cells 1 and 2, the power supply line 10 and the ground line 11 are arranged in the cell. The first-phase clock wiring φ1 for the two-phase clock is arranged adjacent to and parallel to the outside of the power supply line 10 by the same metal layer as the power supply line, and is input to the latch circuit cell 1 through the contact hole 12. Similarly, the second-phase clock wiring φ2 is arranged adjacent to and parallel to the outside of the ground line 11 in the same metal layer as described above.
【００１０】本実施例の構成によれば、第１相，第２相
クロック配線を隣接させていないので、クロストークに
よる誤動作をなくし、相互のクロックスキューも小さく
なる。According to the configuration of this embodiment, since the first-phase and second-phase clock wirings are not adjacent to each other, malfunction due to crosstalk is eliminated and mutual clock skew is reduced.
【００１１】図２（ｂ）は図２（ａ）と異なり、いずれ
のクロック配線φ１，φ２も電源線１０，グランド線１
１の内側に隣接平行して配線されている。なお、第１相
のクロック配線φ１と第２相のクロック配線φ２の間
は、セル内部配線等の他の信号配線が走るべく領域が十
分あるものとする。Unlike FIG. 2A, FIG. 2B is different from FIG. 2A in that both clock wirings φ1 and φ2 have a power supply line 10 and a ground line 1.
It is wired in parallel with the inside of 1. It is assumed that there is a sufficient area between the first-phase clock wiring φ1 and the second-phase clock wiring φ2 so that other signal wirings such as cell internal wiring can run.
【００１２】この図２の例では、クロック配線をグラン
ド線１１，電源線１０に隣接平行に配線しシールドした
形になっているので、図１の構造よりも一層他信号の影
響を受けにくくし、クロックスキューを小さくできる。In the example of FIG. 2, since the clock wiring is shielded by wiring in parallel with the ground line 11 and the power supply line 10 in parallel, it is more difficult to be affected by other signals than the structure of FIG. , Clock skew can be reduced.
【００１３】[0013]
【発明の効果】以上説明したように本発明は、２相クロ
ック配線における第１相クロック配線と第２相クロック
配線を各々同志の隣接平行配線をなくし、クロストーク
により誤動作をなくし、また各々のクロック配線も等長
配線にしやすく、互いのクロックスキューも小さくなる
という効果がある。As described above, according to the present invention, the first-phase clock wiring and the second-phase clock wiring in the two-phase clock wiring do not have the adjacent parallel wirings of each other, and the malfunction due to the crosstalk is eliminated. There is an effect that it is easy to make the clock wirings of equal length and the mutual clock skew is also reduced.
【図１】本発明の第１の実施例のレイアウト図。FIG. 1 is a layout diagram of a first embodiment of the present invention.
【図２】（ａ），（ｂ）は本発明の第２の実施例のレイ
アウト図。2A and 2B are layout diagrams of a second embodiment of the present invention.
【図３】従来例の半導体集積回路のレイアウト図。FIG. 3 is a layout diagram of a conventional semiconductor integrated circuit.
１，２ 第１相，第２相クロックを受けるラッチ回路
セル ３〜８ 機能セル（組合せ回路） １０ 電源線 １１ グランド線 １２ φ１，φ２の金属線とラッチ回路への入力線と
のコンタクトホール1, 2 First-phase and second-phase clock latch circuit cells 3-8 Functional cells (combinational circuit) 10 Power supply line 11 Ground line 12 Contact holes between metal wires of φ1 and φ2 and input lines to the latch circuit
Claims (2)
せ回路とを有し、高さが等しい所望の機能をもつセルが
ゲートアレイまたはスタンダードセル方式のレイアウト
により構成された半導体集積回路において、前記２相ク
ロック配線のうち第１相のクロック配線をセル高の等し
いセル列上辺または下辺に沿って平行に配線し、第２相
のクロック配線を同セル列下辺または上辺に沿って平行
に配線することを特徴とする半導体集積回路。1. A semiconductor integrated circuit that operates with a two-phase clock, has a sequential circuit and a combinational circuit, and has cells having a desired function with the same height in a gate array or standard cell layout. Among the two-phase clock wirings, the first-phase clock wirings are wired in parallel along the upper side or the lower side of the cell row having the same cell height, and the second-phase clock wirings are wired in parallel along the lower side or the upper side of the same cell row. A semiconductor integrated circuit comprising:
配線がセル内の電源線及び接地線に沿ってそれぞれ配線
されたものである請求項１記載の半導体集積回路。2. The semiconductor integrated circuit according to claim 1, wherein the first-phase clock wiring and the second-phase clock wiring are wired along a power supply line and a ground line in the cell, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4270892A JPH05243534A (en) | 1992-02-28 | 1992-02-28 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4270892A JPH05243534A (en) | 1992-02-28 | 1992-02-28 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05243534A true JPH05243534A (en) | 1993-09-21 |
Family
ID=12643574
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4270892A Pending JPH05243534A (en) | 1992-02-28 | 1992-02-28 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05243534A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6753702B2 (en) | 2001-08-29 | 2004-06-22 | Nec Electronics Corporation | Semiconductor integrated circuit and its layout method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61226943A (en) * | 1985-03-30 | 1986-10-08 | Toshiba Corp | Standard cell for automatic disposal wiring |
| JPH01251738A (en) * | 1988-03-31 | 1989-10-06 | Toshiba Corp | Standard cell |
| JPH02303145A (en) * | 1989-05-18 | 1990-12-17 | Kawasaki Steel Corp | Cell for integrated circuit |
-
1992
- 1992-02-28 JP JP4270892A patent/JPH05243534A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61226943A (en) * | 1985-03-30 | 1986-10-08 | Toshiba Corp | Standard cell for automatic disposal wiring |
| JPH01251738A (en) * | 1988-03-31 | 1989-10-06 | Toshiba Corp | Standard cell |
| JPH02303145A (en) * | 1989-05-18 | 1990-12-17 | Kawasaki Steel Corp | Cell for integrated circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6753702B2 (en) | 2001-08-29 | 2004-06-22 | Nec Electronics Corporation | Semiconductor integrated circuit and its layout method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19980908 |