TW543144B - Method for forming metal layer of semiconductor device - Google Patents
Method for forming metal layer of semiconductor device Download PDFInfo
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- TW543144B TW543144B TW091110428A TW91110428A TW543144B TW 543144 B TW543144 B TW 543144B TW 091110428 A TW091110428 A TW 091110428A TW 91110428 A TW91110428 A TW 91110428A TW 543144 B TW543144 B TW 543144B
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 103
- 239000002184 metal Substances 0.000 title claims abstract description 103
- 238000000034 method Methods 0.000 title claims abstract description 46
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 239000010410 layer Substances 0.000 claims abstract description 193
- 239000011229 interlayer Substances 0.000 claims abstract description 31
- 238000001020 plasma etching Methods 0.000 claims abstract description 7
- 239000007789 gas Substances 0.000 claims description 13
- 239000011521 glass Substances 0.000 claims description 12
- 230000008021 deposition Effects 0.000 claims description 10
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 7
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 7
- 239000010936 titanium Substances 0.000 claims description 7
- 229910052719 titanium Inorganic materials 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 229910001069 Ti alloy Inorganic materials 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 238000007872 degassing Methods 0.000 claims description 3
- 229910000838 Al alloy Inorganic materials 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 claims 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 2
- 238000001816 cooling Methods 0.000 claims 2
- 239000011261 inert gas Substances 0.000 claims 2
- 239000000463 material Substances 0.000 claims 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 239000013078 crystal Substances 0.000 claims 1
- 230000000873 masking effect Effects 0.000 claims 1
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims 1
- 230000007547 defect Effects 0.000 abstract description 2
- 230000000694 effects Effects 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 description 11
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 5
- 229910052786 argon Inorganic materials 0.000 description 3
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 235000017166 Bambusa arundinacea Nutrition 0.000 description 1
- 235000017491 Bambusa tulda Nutrition 0.000 description 1
- 241001330002 Bambuseae Species 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 235000015334 Phyllostachys viridis Nutrition 0.000 description 1
- 239000011425 bamboo Substances 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000528 statistical test Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02134—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising hydrogen silsesquioxane, e.g. HSQ
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/312—Organic layers, e.g. photoresist
- H01L21/3121—Layers comprising organo-silicon compounds
- H01L21/3122—Layers comprising organo-silicon compounds layers comprising polysiloxane compounds
- H01L21/3124—Layers comprising organo-silicon compounds layers comprising polysiloxane compounds layers comprising hydrogen silsesquioxane
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Description
543144 五、發明說明(l) 發明領域: 本發明係有關於一種半導體裝置金屬層之平坦化堆疊 方法,且特別有關於一種半導體裝置金屬層之製造方法, 該方法包含下列所述之步驟:以高頻電漿触刻法(RF plasma etching )去除接觸窗中殘留之原始氧化層,於接 觸窗中形成金屬接合層以增進與層間絕緣層之接合,在低 壓下於接觸窗中形成既定厚度之第一金屬層以提高階梯覆 蓋率(step coverage),以及形成既定厚度之第二金屬 層藉以使該金屬層平坦化(planarizing)。 習知技術說明: 一般說來,當半導體裝置集積度(integrity )增 加’接觸面積將減少,以及代表蝕刻部位傾斜度之縱橫尺 寸比(aspect ratio)將會提高。通常,當接觸窗面積與 縱橫尺寸比增加,接觸窗之階梯覆蓋率將會減少。因此, 電流流動將會劣化,且電阻值將會降低,如此將會降低半 導體裝置之可靠度。 溫度,電功率,壓力等因素會影響在接觸窗上沉積金 屬層之階梯覆蓋率。雖然,可以藉由調整電功率與壓力來 增加接觸窗之階梯覆蓋率,但是,該步驟具有某些限制。 其中,階梯覆蓋率可以隨溫度加以調整。然而,若溫度過 高,堆疊在接觸窗側牆上之金屬會擴散到其他部分(例 如,層間絕緣層)如此將會使得金屬線斷線 (disconnected )。反過來說,若溫度過低,金屬線會接
543144 五、發明說明⑵ " - 通(connected ),但是,階梯覆蓋率雖因影子效應 (shadowing effect )而提高,卻造成金屬流劣化' 上述,對於以金屬接合法製造之25 6Mega或高於 256Mega之高集積密度記憶體裝置,係藉由化 相 法(CVD)將鶴金屬沉積在接觸窗中,然後,藉由 1 (etch-back )將鎢金屬層平坦化。 法 工f I 1在接觸f上堆疊嫣金屬層以及使用回蝕法進行 w π # ± 、洱古 干夕困難,堵如·過多的步驟使得 匕呵,以及無法精準控制回蝕法將造成鎢金屬 過度蝕刻。 心从瑪贪屬層 一此外鎢之電阻值較鋁或銅為高,因此接觸電阻也 咼0 u 發明概述 因此 製造方法 之階梯覆 本發明尚有另— 線所引起 為達 層之製造 本發明的 本發明的 蓋率 及一層間 層間絕緣 使該下導 之缺陷,並 到以上之目 方法,該方 絕緣層於具 層之既定部 電層曝光; 目的是提供一種半導體裝置金屬層之 另 目的則疋k面接觸窗底面與側牆 目=為避免由於半導體裝置金屬線斷 提高經濟效力。 的,本發明提出一種半導體裝置金屬 法包括下列步驟:形成一下導電層以 =既定底部結構之一晶圓上;蝕刻該 ^以形成一接觸窗,並藉由該接觸窗 藉由氣體去除法(degassing)消除 543144 五、發明說明(3) 該晶圓接觸窗以及該層間絕緣層所包含之水氣;於氣體去 除後’以高頻電漿#刻法去除暴露於該接觸窗底面之該下 導電層所殘留之原始氧化層;形成一金屬接合層於該接觸 向以及該層間絕緣層之全部表面,並使該金屬接合層與該 下導電層相連接;形成一第一金屬層於該金屬接合層上; 形成一第一金屬層於該第一金屬層上;以及在該第二金屬 層上塗佈一抗反射層後’利用光罩蝕刻形成一圖案 (pattern ) 〇 上述層間絕緣層是旋塗式破璃(s〇G )層、jjSQ (hydrogen si lsesquioxane )層、高密度電漿(HDP) 層、或任何其他金屬間介電層(IMD)。 上述金屬接合層是鈦、鈦合金、氮化鈦層、或鈦/氮 化鈦層。 上述第一金屬層以及第二金屬層是鋁或鋁合金。 上述第一金屬層之沉積條件為:1〜2〇千瓦之直流功 率,1〜500每分鐘標準立方公分(sccm )之鈍氣供給量, 加熱1§溫度低於40 0 °C ’以及作業壓力低於〇· 5mT〇rr。其 中該加熱器溫度為環境溫度(ambient temperature), 且晶圓溫度是以電漿在2 0 〇〜4 〇 〇 °c範圍間進行加熱。 上述第一金屬層之沉積條件為·· 1〜2 〇千瓦之直流功 率,以及1〜1〇〇〇每分鐘標準立方公分(sccm)之鈍氣供 給量。 較佳實施例的詳細說明:
5142-4875-PF(N);ahddub.ptd 第7頁 543144 五、發明說明(4) ----- 本發明之較佳實施例將配合圖式加以說明。 如第1圖所示,形成一下導電層丨0以及一層間絕緣層 1 2於/、有既疋底部結構之晶圓1上’其後,形成一光阻層 1 4於該層間絕緣層1 2上,以形成一接觸窗於開孔部位。曰 該層間絕緣層丨2可以使用旋塗式玻璃(s〇G )層、jjSq (hydrogen silseSqUi〇xane)層、高密度電漿(HDp) 層、或任何其他金屬間介電層(丨MD )。 如第9圖所示,該圖表示當使用旋塗式玻璃層、HSq 層、南密度電漿層、或任何其他金屬間介電層作為層間絕 緣層12日守之介層孔電阻質(via resistance)。在該圖 中’全部的統計測試樣本為1〇〇 %。在HSQ層中,1〇〇 %的 HSQ層為低電阻質。另一方面,在旋塗式玻璃層中,電阻 質則界於1 Ω與1 〇 〇 Ω之範圍間。 當旋塗式玻璃層之回蝕厚度自15〇 nm增加至22〇nm時, 電阻質與該電阻質分布可以得到改善。 換句話說’當使用旋塗式玻璃層時,以回I虫法進行I虫 刻是較佳的方式,如此可獲得5 0 0〜4〇〇〇埃的殘留厚度。 如弟2圖所示’以接觸孔光罩飯刻(c 〇 n七a c t ^ a s k e t ch i ng )法利用一光組層i 4對該層間絕緣層丨2進行蝕 刻,然後對該下導電層1 〇進行曝光,如此可得到一接觸窗 1 6 〇 藉由氣體去除法(degassing)去除該晶圓接觸窗16 以及該層間絕緣層1 2所包含之水氣。 此時,在暴露於該接觸窗16底面之該下導電層10會形
5142-4875-PF(N);ahddub.ptd 第8頁 543144 五、發明說明(5) 成小尺寸之一原始氧化層1 8。 如第3圖所示,藉由高頻電漿蝕刻法(rf Plasma etching )去除該原始氧化層18。 如第4圖所示,形成一金屬接合層2 〇於該接觸窗1 6以 及該層間絕緣層1 2之全部表面,並使該金屬接合層2 〇與該 下導電層1 0相連接。該金屬接合層2 〇之功能是用來改善接 合性質,以使得堆疊在該層間絕緣層丨2與該下導電層丨〇之 金屬線容易接合。 θ 該金屬接合層2 0係為鈦、鈦合金、氮化鈦層、或鈦/ 氮化鈦層。 該金屬接合層20形成300〜1〇〇〇埃堆疊厚度之條件 為:5〜2 0千瓦之直流功率,1 〇〜2 〇 〇每分鐘標準立方公分 (seem)之鈍氣供給量,溫度5〜4 00 °C,以及20〜 1 OOmTorr之壓力。 然而,該金屬接合層20形成300〜1〇〇〇埃堆疊厚度之 較佳條件為:1 2千瓦之直流功率,5 〇〜1 〇 〇每分鐘標準立 方公分(seem)之氬氣供給量,溫度2〇〇〜3〇〇。〇,以及4〇 〜600mTorr之壓力。 當該金屬接合層2 0塗佈完成後,第一反應室溫度最好 由室溫開始加熱。 如第5圖所示’堆疊完畢之該金屬接合層2 〇之晶圓1移 動至第二反應室,在既定溫度與低壓下,於該金屬接合層 20上,形成一第一金屬層22。 该第一金屬層22之沉積條件為:沉積厚度2500〜3〇〇〇
5142-4875-PF(N);ahddub.ptd 第9頁 543144
杗,1〜2 0千瓦之直流功率,1〜5 〇 〇每分鐘標準立方公分 (seem)之氬氣供給量,溫度1〇〜4〇〇。〇,壓力〇〇1〜 LTmTorr。其中,較佳之沉積壓力為〇· 〇1〜〇. 5mT〇rr。 當该第一金屬層22塗佈完成後,第二反應室溫度由室 溫開始加熱,且以電漿將該晶圓1溫度加熱至2〇〇〜3〇() 當该第一金屬層22塗佈完成後,形成該第一金屬層22 之晶圓可以置於室溫下進行冷卻以降低溫度。 如第6圖所示,形成該第一金屬層22之該晶圓}仍置於 相同之反應室(第二反應室),在既定溫度與壓力下,於 該第一金屬層22上,形成一第二金屬層24。 此時’於沉積該第二金屬層24前’可以溫度2〇〇〜3〇〇 C將已冷卻之該晶圓1預熱丨〇〜3 〇 〇秒。 :1〜20千瓦之直 seem )之氬氣供 該第二金屬層24之較佳沉積條件為 流功率,1〜1 0 0 〇每分鐘標準立方公分( 給量,以及溫度450〜550 °c。 形成該第二金屬層24後 進行冷卻。 了以將该晶圓1置於室溫下 如第7圖與第8圖所示 又、竹科移勤至旣令g试 ,,然後在合成後之該晶圓1上塗佈一抗反射層/ 光罩I虫刻形成一圖案(pattern)。 曰 再> ,該第一 層間絕 圖10a至圖l〇d係顯示在不同層間絕緣層12 金屬層22與該第二金屬層24之包埋特性(^ · characteristics)。圖 l〇a 係顯示使用 為
543144
五、發明說明(7) 緣層12之情形。圖1〇b係顯示使用高密度電漿氧化層作 層=絕緣層12之情形。圖1Gc係顯示使用旋塗式玻璃層作 為層間絕緣層12並回蝕220nm之情形。圖1〇d係顯示使用 塗式玻璃層作為層間絕緣層12並回蝕15〇nm2情形。 比較圖10c與圖10d,當使用旋塗式玻璃層並回蝕 2j0nm,該接觸窗16之覆蓋與平坦化過程會進行地較為順 因此,如上所述,在一種半導體裝置金屬層之製生 法中,包含有下列步驟:以高頻電漿蝕刻法去除接^ = 所殘留之原始氧化層,於接觸窗中形成金屬接合層以5中 與層間絕緣層之接合,在低壓下於接觸窗中形成既定^進 之第一金屬層以提高階梯覆蓋率(step c〇verage),二度 及形成既定厚度之第二金屬層藉以使該金屬層平坦化以 (planarizing)。由於接觸窗底面與側牆之階梯覆蓋μ 提高,因此避免了由於半導體裝置金屬線斷線所引起¥ 陷,並提高經濟效力。 缺
5142-4875-PF(N);ahddub.ptd 第11頁 543144 圖式簡單說明 上述本發明之目的、特性以及優點,在配合相關圖式 進行以下詳細說明後將更為清楚,其中: 第1圖係表示,依照本發明於晶圓上塗佈一下導電層 與一層間絕緣層; 第2圖係表示,依照本發明於層間絕緣層與下導電層 之部分區域進行曝光以形成一接觸窗; 第3圖係表示,依照本發明以高頻電漿蝕刻法去除接 觸窗中所殘留之原始氧化層; 第4圖係表示,依照本發明於接觸窗與層間絕緣層上 面塗佈金屬接合層; 第5圖係表示,依照本發明於金屬接合層上面塗佈第 一金屬層; 第6圖係表示,依照本發明於第一金屬層上面塗佈第 二金屬層; 第7圖係表示,依照本發明於第二金屬層上面塗佈抗 反射層; 第8圖係表示,依照本發明對金屬接合層、第一金屬 層、第二金屬層與抗反射層進行银刻以形成圖案; 第9圖係表示,依照本發明於不同形式之層間絕緣層 下,接觸電阻值(介層孔電阻質)之累積機率;以及 第10a圖至第10d圖係表示,依照本發明於不同形式之 層間絕緣層下,覆蓋第一金屬層與第二金屬層之狀態特 性。
5142-4875-PF(N);ahddub.ptd 第12頁 543144 圖式簡單說明 符號說明: 1〜晶圓; 1 2〜層間絕緣層 1 6〜接觸窗; 20〜金屬接合層 24〜第二金屬層 2 8〜圖案。 1 0〜下導電層; 1 4〜光阻層; 18〜原始氧化層 22〜第一金屬層 2 6〜抗反射層;
5142-4875-PF(N);ahddub.ptd 第13頁
Claims (1)
- 543144 i號 91110428 曰 六、申請專利範圍 .1.—種半導體裝置金屬層之製造方法,包^^ 驟· …ΐ續形成一下導電層以及一層間絕緣層於具有既定底 邛結構之一晶圓上; - 钱刻該層間絕緣層之既定部分以形成一接觸窗,並 此而使該下導電層曝光; 曰 藉由氣體去除法(degassing)去除該接觸窗以及該 層間絕緣層所包含之水氣; / 形成一金屬接合層於該接觸窗以及該層間絕緣層之全 部表面’其中該金屬接合層與該下導電層相連接; 形成一第一金屬層於該金屬接合層上; 形成一第二金屬層於該第一金屬層上;以及 塗佈一抗反射層於該第二金屬層上後,藉由光罩蝕刻 (masking etching)形成一圖案(pattern)。 2 ·如申請專利範圍第1項所述之方法,其中該層間絕 緣層之材料係為旋塗式玻璃(S0G )層、HSQ層以及高密度 電漿(HDP )層所組成之族群中之一者。 3·如申請專利範圍第2項所述之方法,其中該旋塗式 玻璃層是以回姓法(e t c h b a c k )餘刻而成,且該旋塗式 玻璃層具有500〜4000埃的殘留厚度。 4 ·如申請專利範圍第1項所述之方法,其中更包括下 列步驟··在氣體去除後進行蝕刻,藉以去除暴露於該接觸 固底面之該下導電層所殘留之原始氧化層。 5 ·如申請專利範圍第4項所述之方法,其中該原始氧543144 曰 修正 化層係以尚頻電漿餘刻法(r F p 1 a s m a e t c h i n g )去除。 •如申明專利範圍第1項所述之方法,其中該金屬接 合層的材料係為鈦、鈦合金、氮化鈦層以及鈦/氮化鈦層 所組成之族群中之一者。 曰 一 7 ·如申請專利範圍第1或6所述之方法,其中將該金屬 接$層形成300〜1 0 00埃厚度之條件為:5〜20千瓦之直流 f率’10〜200每分鐘標準立方公分(sccm)之鈍氣供給 呈’ /皿度5〜4〇〇°c,以及2〇〜i〇〇mTorr之壓力。8.如申請專利範圍第7項所述之方法,其中該金屬接 合層之形成條件為:12千瓦之直流功率,50〜100每分鐘 標準立方公分(seem)之鈍氣供給量,溫度20 0〜300 °C, 以及40〜6〇mTorr之壓力。 9 ·如申請專利範圍第1項所述之方法,其中該金屬接 合層之形成溫度是由室溫開始加熱。 I 〇 ·如申請專利範圍第1項所述之方法,其中該第一金 屬層以及該第二金屬層是由鋁或鋁合金形成。 II ·如申請專利範圍第1項所述之方法,其中該第一金 屬層沉積厚度為2500〜3000埃。 》12 ·如申請專利範圍第1或11項所述之方法,其中該第 一金屬層之沉積條件為:!〜2〇十瓦之直流功率,1〜500 每分鐘標準立方公分(sccm)之鈍氣供給量,溫度10〜 400 t。 1 3 ·如申睛專利範圍第1 2項戶斤述之方法’其中該純氣 為氮氣。543144 案號 91110428 曰 修正 六、申請專利範圍 1 4.如申請專利範圍第1或11項所述之方法,其中該第 一金屬層係於0.01〜0.7 mTorr壓力下沉積。 1 5.如申請專利範圍第1 4項所述之方法,其中該壓力 為(K 0 1 〜0 · 5mTorr 〇 1 6.如申請專利範圍第1或11項所述之方法,其中該第 一金屬層之沉積溫度是由室溫開始加熱。 1 7.如申請專利範圍第1項所述之方法,其中更包括一 步驟,該步驟是於該第一金屬層形成後,於室溫下冷卻該 晶圓。18.如申請專利範圍第1項所述之方法,其中更包括一 步驟,該步驟是於形成該第二金屬層前,在溫度2 00〜3 00 °0下,預熱(preheating)該晶圓10〜300秒。 1 9.如申請專利範圍第1項所述之方法,其中該第二金 屬層之沉積條件係為:1〜2 0千瓦之直流功率,以及1〜 1 00 0每分鐘標準立方公分(seem )之鈍氣供給量。 2 0.如申請專利範圍第1 9項所述之方法,其中該鈍氣 為氣。2 1.如申請專利範圍第1或1 9項所述之方法,其中該第 二金屬層之沉積溫度係為450〜550 °C。 2 2.如申請專利範圍第1項所述之方法,其中更包括一 步驟,該步驟是於該第二金屬層形成後,於室溫下冷卻該 晶圓。 23.如申請專利範圍第1項所述之方法,其中該抗反射 層是由鈦/氮化鈦層所構成。5142-4875-PFl(N);ahddub.ptc 第16頁
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KR100207523B1 (ko) * | 1996-11-20 | 1999-07-15 | 윤종용 | 금속배선층 형성방법 |
KR19990005816A (ko) * | 1997-06-30 | 1999-01-25 | 김영환 | 반도체장치의 콘택형성방법 |
TW408359B (en) * | 1997-08-29 | 2000-10-11 | Seiko Epson Corp | Semiconductor device and manufacture thereof |
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2001
- 2001-05-23 KR KR10-2001-0028492A patent/KR100433846B1/ko not_active IP Right Cessation
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2002
- 2002-05-17 TW TW091110428A patent/TW543144B/zh not_active IP Right Cessation
- 2002-05-22 DE DE10223482A patent/DE10223482A1/de not_active Ceased
- 2002-05-22 JP JP2002147281A patent/JP2003031658A/ja active Pending
- 2002-05-23 US US10/154,078 patent/US6780777B2/en not_active Expired - Fee Related
Cited By (3)
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CN104253087A (zh) * | 2014-04-18 | 2014-12-31 | 上海华虹宏力半导体制造有限公司 | 铝金属工艺接触孔的填充方法 |
CN104253087B (zh) * | 2014-04-18 | 2019-06-11 | 上海华虹宏力半导体制造有限公司 | 铝金属工艺接触孔的填充方法 |
TWI792896B (zh) * | 2021-02-25 | 2023-02-11 | 日商斯庫林集團股份有限公司 | 基板處理方法及基板處理裝置 |
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KR100433846B1 (ko) | 2004-06-04 |
US6780777B2 (en) | 2004-08-24 |
KR20020089715A (ko) | 2002-11-30 |
US20020175140A1 (en) | 2002-11-28 |
JP2003031658A (ja) | 2003-01-31 |
DE10223482A1 (de) | 2003-05-15 |
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