530342 A7 B7 五、發明説明（） 快元件之操作速度之方法。 習知之技術中提出可以利用金屬與矽反應產生矽化 金屬用以提昇元件之操作速度。此外，自行對準之矽化鈦 (T i s i 1 i c i d e)也經常被用來做爲降低閘極、汲極與源極之 電阻値以提昇元件之操作速度。傳統之矽化金屬製程簡述 如下，通常，先行沈積一金屬層於基板表面以及閘極之表 面。然後，對基板施以一熱處理製程，使金屬層與砍起反 應產生矽化金屬。然後再將未反應之金屬層去除，上述之 製程便是一般的自行對準梦化金屬製程。 然而，在標準的矽化鈦製程中通常需要兩步驟之熱 處理過程，上述之矽化鈦製程中將導致短路或橋接之現 象，其製程説明如下。首先先行沈積一鈦金屬層於及氮化 鈦金屬層MOS電晶體之上，一般上述之M〇S電晶體具 有間隙壁環繞於閘極之四周，然後利用熱退火將上述之鈦 金屬與閘極、汲極與源極產生化學反應，此梦驟一般爲低 溫熱退火（annealing)，製程之溫度約爲6〇〇到70〇°C之 間。隨後利用濕蝕刻將未參與反應之鈦金屬層與氮化鈦金 屬層選擇性地去除，再執行一高溫熱退火用以降低矽化鈦 之電阻値，此高溫熱退火之溫度介於8 0 0到9 〇 〇亡之間。 然而在上述之形成矽化金屬之熱退火過程中，矽原子爲一 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公董） ： ：---•冬-- (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 530342 A7 B7 五、發明説明（ 種潛在的擴散源，因此，其 C暴於上述 < 原因，矽原子將可能 辟ίι間隙壁之表面而與其上之鈦金屬產生反應，在間隙 二表面形成發化金屬，此⑪化金屬將造成問極與汲極 極間之短路 發明目的及概述： 程 發月之主要目的爲提供一種自行對準矽化金屬製 ^請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 一本發明之再一目的爲利用閘極結構之雙間隙壁以 自=準梦化金屬，以解決傳統砍化金屬製程之橋接或短路 之問越。 本發明包含形成電晶體於基板之上，氧化矽層形成於閘 *結構與基板之表面後，利用非等向性独刻技術㈣氧化石夕 層，以形成由氧化矽組成之第一間隙壁於閘極結構之側壁之 上。再利用化學氣相沈積法形成一氮化矽層於閘極結構 :間隙壁以及基板之上。同理，利用非等向性触刻製程，將 氮化矽層蝕刻，形成第二間隙壁於第一間隙壁之侧壁之上。 接著利用閘極與雙間隙壁作爲離子佈植之罩幕，進行離子摻 雜形成汲極與源極於基板之中。一鈦或鈦/氮化鈦之導電層 在完成汲極與源極之製作之後，沈積於閘極結構、雙間隙壁 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） •、π * J·. 530342 A7 B7 五、發明説明（ 與基板之上。然後以低溫熱退吹，腺咎,七„ a 、逆人將鈥（或鈦/氮化鈦）與閘 極、汲極與源極產生反應以形成矽仆斗，μ a ^ , 織1矽化鈦，上迷之低溫埶退火 之溫度約爲6 0 0至7 0 〇 〇c之間。而μ、七土 A ^ _ ΓΊ 而上迷未參與反應之導電 層則利.用溼蝕刻法選擇性地去降。垃耸1、Α ^ u方陈。接者再於溫度介於3 0 〇 至9〇(TC間進行-高溫熱退火製程，用以降低發化献之電 阻値。最後，矽化金屬分别自行對準形成於閘極、與汲極/ 源極之上。在完成矽化金屬製程之後，將第二間隙壁去除， 一般而言，可以利用熱磷酸溶液將第二間隙壁剥除。因矽原 子擴散而形成於第二間隙璧上之矽化鈦將一併被去除。 圖式簡單説明： 第一圖爲本發明之形成具雙間隙壁閘極結構之截面圖。 第二圖爲本發明形成鈦金屬層於閘極與基板上之截面圖。 第三圖爲本發明在閘極、汲極與源極上形成自行對準石夕化金 屬之截面圖。 —,0—.---— (請先閱讀背面之注意事項再填寫本頁) 玎 經濟部智慧財產局員工消費合作社印製 發明詳細説明： 如第一圖所示，以一晶面爲（Ί 00)之單晶半導體爲基 板，如P型或N型之發基板2。接著，製作做爲元件間隔 離之絶緣區域4，通常可以使用淺溝渠絶緣技術（s h a丨丨0 w trench isolation; STI)或是場氧化絶緣技術製作上述之絶 緣區域4。舉例而言，淺溝渠絶緣技術爲利用微影及蝕刻方 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 530342530342 A7 B7 V. Description of the invention () Method of operating speed of fast components. It is proposed in the known technology that a metal can react with silicon to generate a silicide metal to increase the operating speed of the device. In addition, self-aligned titanium silicide (T i s i 1 i c i d e) is also often used to reduce the resistance of the gate, drain, and source to increase the operating speed of the device. A brief description of the traditional silicided metal process is as follows. Generally, a metal layer is first deposited on the substrate surface and the gate surface. Then, the substrate is subjected to a heat treatment process, so that the metal layer reacts with the chopping to generate silicided metal. Then the unreacted metal layer is removed, and the above process is a general self-aligning dream metal process. However, a two-step heat treatment is usually required in a standard titanium silicide process. The above-mentioned titanium silicide process will cause a short circuit or a bridge. The process is described below. First, a titanium metal layer is deposited on top of the MOS transistor with a titanium nitride layer. Generally, the above MOS transistor has a barrier wall surrounding the gate electrode, and then the above titanium metal and the gate electrode are thermally annealed. The drain and the source produce a chemical reaction. This dream step is generally low temperature thermal annealing (annealing), and the process temperature is about 600 to 70 ° C. Subsequently, the titanium metal layer and the titanium nitride metal layer that are not involved in the reaction are selectively removed by wet etching, and then a high temperature thermal annealing is performed to reduce the resistance of the titanium silicide. The temperature of the high temperature thermal annealing is between 80 ° Between 0 and 900 deaths. However, in the above-mentioned thermal annealing process for forming silicided metal, the silicon atom is a paper standard applicable to the Chinese National Standard (CNS) A4 specification (210X297). ： --- • Winter-(Please read the note on the back first Please fill in this page again) Order printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs Printed by 530342 A7 B7 V. Description of the invention (a potential source of diffusion, therefore, its C is violating the above reasons, and the silicon atom will probably break the gap It reacts with the titanium metal on the surface to form a chemical metal on the two surfaces of the gap. This chemical metal will cause a short circuit between the question and drain electrodes. Purpose and summary of the invention: Cheng Fayue's main purpose is to provide a self-aligned silicidation. Made of metal ^ Please read the notes on the back before filling this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Another purpose of the present invention is to use the double gap wall of the gate structure to self-quasi dream metal, to Solve the problem of bridging or short circuit in the traditional metal cutting process. The invention includes forming a transistor on a substrate, a silicon oxide layer is formed on the gate * structure and the surface of the substrate, and then using a non-isotropic monolithic etching technique to oxidize the stone oxide layer to form a first spacer composed of silicon oxide On the sidewall of the gate structure. Then, a chemical vapor deposition method is used to form a silicon nitride layer on the gate structure: the spacer and the substrate. Similarly, the silicon nitride layer is etched by using an anisotropic touch-etching process to form a second gap wall on the side wall of the first gap wall. Next, the gate and the double gap wall are used as a mask for ion implantation, and ion doping is performed to form a drain electrode and a source electrode in the substrate. A titanium or titanium / titanium nitride conductive layer is deposited on the gate structure and double-spaced wall after the fabrication of the drain and source electrodes. The paper size applies the Chinese National Standard (CNS) A4 specification (210 × 297 mm). π * J ·. 530342 A7 B7 V. Description of the invention (and on the substrate. Then blow back with low temperature heat, gland blame, seven "a", "Inverse people will" (or titanium / titanium nitride) with the gate, drain The electrode reacts with the source to form a silicon servant, μ a ^, weave 1 titanium silicide, and the temperature of the low-temperature 埶 annealing of the above fan is about 600 to 7 00c. And μ, Qitu A ^ _ ΓΊ The conductive layer that is not involved in the reaction is advantageous. Wet selective etching is used to drop it. The tower is 1. A ^ u Fang Chen. Then the temperature is between 300 and 90 (TC). A high-temperature thermal annealing process is performed to reduce the resistance 发. Finally, the silicide metal is aligned and formed on the gate and the drain / source respectively. After the silicide process is completed, the second process is completed. Removal of the gap wall, in general, the second gap wall can be peeled off using a hot phosphoric acid solution. It is formed in the second gap due to the diffusion of silicon atoms. The titanium silicide on it will be removed together. Brief description of the drawings: The first figure is a cross-sectional view of the present invention forming a double-gap gate structure. The second figure is a titanium metal layer formed on the gate and the substrate according to the present invention. The third figure is a cross-sectional view of the present invention forming self-aligned petrified metal on the gate, drain and source. —, 0 —.---— (Please read the notes on the back before filling (This page) Detailed description of the invention printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs: As shown in the first figure, a single crystal semiconductor with a crystal plane (Ί 00) as the substrate, such as a P-type or N-type hair substrate 2. Next, as the isolation region 4 for isolation between components, the above-mentioned insulation region 4 can usually be fabricated using shallow trench isolation technology (STI) or field oxidation insulation technology. For example, Shallow trench insulation technology uses lithography and etching. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 530342.
、發明説明（ 與基拓 、 極土 <上。然後以低溫熱退火將鈦（或鈦/氮化鈦）與閘 、* ;及極與源極產生反應以形成矽化鈦，上述之低溫熱追火 之溫户么 一 …、 皿又、、力爲600至7〇(rc之間。而上述未參與反應之導電 層則利用漫触刻法選擇性地去除。接著再於溫度介於3〇0 900¾間進行_高溫熱退火製程，用以降低矽化鈦之電 且値。最後，矽化金屬分别自行對準形成於閘極、與汲極/ 〈。在完成石夕化金屬製程之後，將第二間隙壁去除， 一般而言，可以利用熱嶙酸溶液將第二間隙壁剥除。因矽原 子擴散而形成於第二間隙璧上之矽化鈦將一併被去除。 圖式簡單説 明 第一圖爲本發明之形成具雙間隙壁閘極結構之截面圖。 第二圖爲本發明形成鈦金屬層於閘極與基板上之截面圖。 第二圖爲本發明在閘極、汲極與源極上形成自行對準矽化金 屬之截面圖。 ,0 .----- (請先閱讀背面之注意事項再填寫本頁)、 Explanation of the invention (with Giotto, polar soil < above. Then, titanium (or titanium / titanium nitride) and gate, *; and electrode and source are reacted to form titanium silicide by low temperature thermal annealing. Warmly chasing the fire in the warmth ..., the plate, and the force is between 600 and 700. The above-mentioned conductive layer that does not participate in the reaction is selectively removed by the diffuse touch engraving method. _ High temperature thermal annealing process is performed between 300 900 ¾ to reduce the electrical and magnetic properties of titanium silicide. Finally, the silicide metal is aligned and formed on the gate electrode and drain electrode respectively. After that, the second gap wall is removed. Generally, the second gap wall can be peeled off with a hot galvanic acid solution. The titanium silicide formed on the second gap wall due to silicon atom diffusion will be removed together. Brief description The first picture is a cross-sectional view of a gate structure with a double-gap wall formed according to the present invention. The second picture is a cross-sectional view of a titanium metal layer formed on the gate and the substrate according to the present invention. A cross-sectional view of self-aligned silicide metal is formed on the drain and source. .----- (Please read the notes on the back before filling this page)
、1T 經濟部智慧財產局員工消費合作社印製 發明詳細説明： 如第一圖所示，以一晶面爲（1〇〇)之單晶半導體爲基 板，如P型或N型之矽基板2。接著，製作做爲元件間隔 離之絶緣區域4，通常可以使用淺溝渠絶緣技術（sha丨丨〇w trench iS0|ati0n; ST|)或是場氧化絶緣技術製作上述之絶 緣區域4。舉例而言，淺溝渠絶緣技術爲利用微影及蚀刻方 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 530342 A7 B7 五、發明説明（） 21作淺溝渠於基板之中，以化學氣相沈積之氧化層回填進 ^淺4渠中，接著再利用回蝕刻或是化學機械研磨法將氧化 二予以平坦化。此外，場氧化區域之形成是在含氧蒸氣之環 θ下和用熱氧化法，溫度在8 5 0」〇 5 〇它間產生二氧化矽， 瑕後再利用澄蝕刻去除作爲氧化罩幕之氮化矽。 技 接著，在基板2之上形成一閘極氧化層6，通常閘極 ，化層6可以在含氧環境之中，於溫度75〇至之間 ^形成，一般厚度約A 1 5至6〇 ;矣之F日 1 ，il是利用化 子氣相沈積法也可以完成閘極氧化層6之製作。隨後，利 用化學氣相法沈積複晶矽層8覆蓋閘極氧化層6之上，厚 2 1()00至4000埃之間。接著，定義—光阻圖案於複晶 片日8之上，以蝕刻技術蝕刻上述之複晶矽層8以及閘極 乳化層6以定義閘極結構之圖案。再去除光阻。 接著，利用閘極結構作爲一離子佈植之罩幕，利用 佈植技術植入離子於基板2之中， 於霏近閘極又側形成輕 微摻雜汲極(|ight丨y doped drain)1〇，以降低於通道中之熱 經濟部智慧財產局員工消費合作社印製 之化下 2 壓。 低間 如之 例度 與4構成 結形 極法 閘積ο 於沈4 成相氏 形氣攝層學爲 砍化約 化用度氧利溫 一以程 ，可製圖層， _矽法第化積 閲氧沈 參，相 面氣 表學 板 基 至 ο ο (請先閱讀背面之注意事項再填寫本頁)1, 1T Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives, Printed Invention Details: As shown in the first figure, a single crystal semiconductor with a crystal plane of (100) is used as the substrate, such as a P-type or N-type silicon substrate 2 . Next, as the isolation region 4 which is used as the element separation, the above-mentioned insulating region 4 can usually be fabricated using shallow trench insulation technology (sha 丨 丨 w trench iS0 | ati0n; ST |) or field oxidation insulation technology. For example, the shallow trench insulation technology uses lithography and etching. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 530342 A7 B7. 5. Description of the invention (21) Make shallow trenches in the substrate. A chemical vapor deposition oxide layer is backfilled into the shallow trenches, and then etch back or chemical mechanical polishing is used to planarize the second oxide. In addition, the field oxidation region is formed under the oxygen-containing vapour ring θ and thermal oxidation method, and the silicon dioxide is generated at a temperature between 850 ″ and 50 °. After the flaw is removed, it is removed by clear etching as an oxidation mask. Silicon nitride. Next, a gate oxide layer 6 is formed on the substrate 2. Generally, the gate electrode and the chemical layer 6 can be formed in an oxygen-containing environment at a temperature of 75 to ^, and the thickness is generally about A 1 to 5 to 60. ; F day 1, il is the use of chemical vapor deposition method can also complete the gate oxide layer 6 production. Subsequently, a chemical vapor deposition method is used to deposit a polycrystalline silicon layer 8 over the gate oxide layer 6 to a thickness of 21 (00 to 4000 angstroms). Next, define the photoresist pattern on the polycrystalline silicon wafer 8. The polycrystalline silicon layer 8 and the gate emulsified layer 6 are etched by an etching technique to define the pattern of the gate structure. Then remove the photoresist. Then, the gate structure is used as a mask for ion implantation, and implantation technology is used to implant ions in the substrate 2 to form a lightly doped drain near the gate. 〇, in order to reduce the hot print in the channel of the Ministry of Economic Affairs Intellectual Property Bureau employee consumer cooperative printed on the pressure. The example of the low level and the 4 constitute a knot-shaped polar method gate product ο Yu Shen 4 Cheng Xiang ’s aerosol stratigraphy is used to cut down and reduce the temperature with oxygen and temperature, and can make layers, _ silicon method Read the oxygen sink ginseng, the surface gas table science board to ο ο (Please read the precautions on the back before filling this page)
準 標 家 ί國 一國 I中 用 適 I釐 一公 530342 A7Prospective bidders: One country, one country, one medium, one cent, one public 530342 A7
經濟部智慧財產局員工消費合作社印製 一步驟爲間隙壁（side wall spacer)之製作，此步骤利用非等 向性蝕刻技術蝕刻氧化矽層，以形成由氧化矽組成之第一= 隙壁1 2於閘極結構之側壁上。 口 利用化學氣相沈積法，例如低壓化學氣相沈積法形成一 氮化矽層於閘極結構、第一間隙壁1 2以及基板2之上 氣 化石夕層之形成溫度約爲500-700。〇，形成氮化矽之反應氣& 通常爲 SiH4，NH3，N2，N2O 或 SiH2Cl2，NHi N at。 〇，2 , IN 2 Ο ° 同理，利用非等向性蝕刻製程，將氮化矽層蝕刻，形成第二 間隙壁14於第一間隙壁12之側壁之上。上述由氧化石夕以及 氮化發所組成之雙間隙壁12、14之寬度，可以藉由控制個 别沈積氧化矽層與氮化矽層之厚度而決定。 如第二圖所示，接著利用閘極結構與雙間隙壁」2、] 4 作爲離子佈植之罩幕，進行離子摻雜以形成汲極與源極]6 於基板2之中。製作汲極與源極之技術爲熟知知技術，在 此不加以贅述。一包含鈥或鈥/氮化鈥（Ti/TiN)之導電層18 在完成没極與源極之製作之後，沈積於閘極結構、雙間隙壁 1 2、Ί 4與基板2之上。然後以低溫熱退火將鈥（或鈦/氮化 欽）與閘極8、没極、源極1 6產生反應，以形成石夕化鈥，上 述之低溫熱退火之溫度約爲600至700 °C之間。而上述未 參與反應之導電層則利用溼蝕刻法選擇性地去除。接著再於 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇X297公釐） (請先閲讀背面之注意事項再填寫本頁) 1· 項再填」 裝· 訂 530342 A7 B7 五、發明説明（ 溫度介於8 0 〇至9 〇 〇它間進行一高溫熱退火製 裎 ，用以降 低矽化鈦之電阻値。最後，矽化金屬分别自行對準形成、、 極、與汲極/源極之上。 7 於 閘 上述之發化金屬（矽化鈦）製程也可能因爲矽原子擴 至第二間隙壁14之上，而與其上之鈦金屬產生反應，形成 矽化鈦於第二間隙壁1 4之上。因此，本發明在完成矽化金 屬製程之後，必須將第二間隙壁1 4去除，一般而言，可以 利用熱磷酸溶液將第二間隙壁1 4剝除。因矽原子擴散而形 成於氮化石夕間隙壁上之石夕化鈇將一併被去除，因此本發明顯 然可以解決傳統製程上，因矽擴散而造成矽化金屬形成於間 隙壁所造成之橋接或短路之問題。 本發明以一較佳實施例説明如上，而熟悉此領域技藝 者，在不脱離本發明之精神範圍内，當可作些許更動潤飾， 其專利保護範圍更當視後附之申請專利範圍及其等同領域 而定。 經濟部智慧財產局員工消費合作社印製 準 標 家 國 國 中 用 一適. I釐 公 97 2The consumer property cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints a step for the production of side wall spacers. This step uses anisotropic etching to etch the silicon oxide layer to form the first silicon oxide layer = the gap wall 1 2 on the sidewall of the gate structure. A chemical vapor deposition method, such as a low pressure chemical vapor deposition method, is used to form a silicon nitride layer on the gate structure, the first spacer wall 12 and the substrate 2 at a temperature of about 500-700. 〇, the reaction gas to form silicon nitride & usually SiH4, NH3, N2, N2O or SiH2Cl2, NHi N at. 〇, 2, IN 2 0 ° Similarly, a silicon nitride layer is etched by using an anisotropic etching process to form a second spacer wall 14 on a side wall of the first spacer wall 12. The width of the above-mentioned double spacers 12, 14 composed of oxidized stone and nitrided hair can be determined by controlling the thickness of the silicon oxide layer and the silicon nitride layer respectively deposited. As shown in the second figure, the gate structure and the double-spacer walls 2 and 4 are used as a mask for ion implantation, and ion doping is performed to form a drain and a source] 6 in the substrate 2. The technique of making the drain and source is a well-known technique and will not be described in detail here. A conductive layer 18 containing “or nitride” (Ti / TiN) 18 is deposited on the gate structure, the double spacers 1, 2, 4 and the substrate 2 after the fabrication of the electrodes and the source is completed. Then low temperature thermal annealing is used to react “(or titanium / nitride) with the gate electrode 8, non-electrode, and source electrode 16 to form petrified”. The above-mentioned low temperature thermal annealing temperature is about 600 to Between 700 ° C. The non-reactive conductive layer is selectively removed by a wet etching method. Then apply the Chinese National Standard (CNS) A4 specification (21 × 297 mm) to this paper size (please read the precautions on the back before filling out this page) 1. Fill in the items again Binding 530342 A7 B7 V. Invention Note (The temperature is between 800 and 900, and it is subjected to a high temperature thermal annealing to reduce the resistance of titanium silicide. Finally, the silicide metal is aligned to form the,,, and drain / source, respectively. 7 The process of the above-mentioned metallized metal (titanium silicide) in the gate may also cause the silicon atom to expand above the second spacer 14 and react with the titanium metal thereon to form titanium silicide on the second spacer 1 4. Therefore, after the silicidation metal process is completed, the second spacer 14 must be removed in the present invention. Generally, the second spacer 14 can be stripped by using a hot phosphoric acid solution. It is formed by silicon atom diffusion. The stone puppet on the nitrided stone wall will be removed together, so the present invention can obviously solve the problem of bridging or short circuit caused by the silicide metal formed on the wall due to silicon diffusion in the traditional process. A preferred embodiment is described above, and those skilled in the art can make some modifications without departing from the spirit of the present invention. The scope of patent protection should be based on the scope of the attached patent application and its equivalent. The Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints a standard for the national and national level.