CN104517850B - The forming method of transistor - Google Patents
The forming method of transistor Download PDFInfo
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- CN104517850B CN104517850B CN201310463703.3A CN201310463703A CN104517850B CN 104517850 B CN104517850 B CN 104517850B CN 201310463703 A CN201310463703 A CN 201310463703A CN 104517850 B CN104517850 B CN 104517850B
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- chemical solution
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- contact hole
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- drain region
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- 238000000034 method Methods 0.000 title claims abstract description 36
- 239000000126 substance Substances 0.000 claims abstract description 61
- 239000011248 coating agent Substances 0.000 claims abstract description 60
- 238000000576 coating method Methods 0.000 claims abstract description 60
- 238000010438 heat treatment Methods 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 238000004140 cleaning Methods 0.000 claims abstract description 17
- 238000006243 chemical reaction Methods 0.000 claims abstract description 7
- 239000000243 solution Substances 0.000 claims description 67
- 238000000137 annealing Methods 0.000 claims description 28
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 26
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 15
- 229910052796 boron Inorganic materials 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 12
- 239000011259 mixed solution Substances 0.000 claims description 9
- 229910052759 nickel Inorganic materials 0.000 claims description 9
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 8
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 8
- ZLMJMSJWJFRBEC-UHFFFAOYSA-N Potassium Chemical compound [K] ZLMJMSJWJFRBEC-UHFFFAOYSA-N 0.000 claims description 7
- YZCKVEUIGOORGS-IGMARMGPSA-N Protium Chemical compound [1H] YZCKVEUIGOORGS-IGMARMGPSA-N 0.000 claims description 7
- QMMRZOWCJAIUJA-UHFFFAOYSA-L nickel dichloride Chemical compound Cl[Ni]Cl QMMRZOWCJAIUJA-UHFFFAOYSA-L 0.000 claims description 7
- 229910001453 nickel ion Inorganic materials 0.000 claims description 7
- 229910052700 potassium Inorganic materials 0.000 claims description 7
- 239000011591 potassium Substances 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910045601 alloy Inorganic materials 0.000 claims description 6
- 239000000956 alloy Substances 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 6
- 206010010144 Completed suicide Diseases 0.000 claims description 5
- 229910021641 deionized water Inorganic materials 0.000 claims description 5
- 229910021586 Nickel(II) chloride Inorganic materials 0.000 claims description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 4
- 239000008367 deionised water Substances 0.000 claims description 4
- 229960002163 hydrogen peroxide Drugs 0.000 claims description 4
- 239000007788 liquid Substances 0.000 claims description 3
- 239000002210 silicon-based material Substances 0.000 claims description 3
- 230000008859 change Effects 0.000 claims description 2
- VIKNJXKGJWUCNN-XGXHKTLJSA-N norethisterone Chemical compound O=C1CC[C@@H]2[C@H]3CC[C@](C)([C@](CC4)(O)C#C)[C@@H]4[C@@H]3CCC2=C1 VIKNJXKGJWUCNN-XGXHKTLJSA-N 0.000 claims 1
- 239000011435 rock Substances 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 75
- 238000002955 isolation Methods 0.000 description 13
- 239000000463 material Substances 0.000 description 7
- 229910021332 silicide Inorganic materials 0.000 description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910021334 nickel silicide Inorganic materials 0.000 description 5
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 238000001556 precipitation Methods 0.000 description 4
- 238000009841 combustion method Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000006722 reduction reaction Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910005883 NiSi Inorganic materials 0.000 description 2
- FKNQFGJONOIPTF-UHFFFAOYSA-N Sodium cation Chemical compound [Na+] FKNQFGJONOIPTF-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000006227 byproduct Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- XLYOFNOQVPJJNP-ZSJDYOACSA-N heavy water Substances [2H]O[2H] XLYOFNOQVPJJNP-ZSJDYOACSA-N 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- IPLJNQFXJUCRNH-UHFFFAOYSA-L nickel(2+);dibromide Chemical group [Ni+2].[Br-].[Br-] IPLJNQFXJUCRNH-UHFFFAOYSA-L 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000002000 scavenging effect Effects 0.000 description 2
- 229910000033 sodium borohydride Inorganic materials 0.000 description 2
- 239000012279 sodium borohydride Substances 0.000 description 2
- 229910001415 sodium ion Inorganic materials 0.000 description 2
- 229910001868 water Inorganic materials 0.000 description 2
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 description 1
- 241000370738 Chlorion Species 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910021585 Nickel(II) bromide Inorganic materials 0.000 description 1
- NPYPAHLBTDXSSS-UHFFFAOYSA-N Potassium ion Chemical class [K+] NPYPAHLBTDXSSS-UHFFFAOYSA-N 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 description 1
- 229910052794 bromium Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000002242 deionisation method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- -1 halide ions Chemical class 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
- 229910021484 silicon-nickel alloy Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A kind of forming method of transistor, including substrate is provided；Form source region, drain region and the grid on substrate being located in substrate；The blanket dielectric layer on substrate and source region, drain region and grid；Contact hole is formed in the dielectric layer, the contact hole is exposed one or more in source region, drain region and grid；Chemical solution is passed through into contact hole, the chemical solution is formed coating in the inwall of the contact hole and bottom；The first heat treatment is carried out, makes the coating and source region being in contact with the coating, drain region or grid reaction, to form contact layer；Selective cleaning is carried out to the transistor, to remove unreacted coating.Technical scheme has advantages below compared with prior art：It the coating formed by way of being passed through chemical solution into affiliated contact hole, can be very good to be covered in the inside of the contact hole, and then make that the contact layer thickness to be formed is uniform, and the effect for forming contact layer is more preferable.
Description
Technical field
The present invention relates to semiconductor applications, and in particular to a kind of forming method of transistor.
Background technology
CMOS (Complementary Metal Oxide Semiconductor, CMOS)
It is the elementary cell in modem logic circuit, wherein comprising PMOS and NMOS, and each PMOS or nmos pass transistor position
In on a dopant well (Well), and the PMOS and NMOS all by grid (Gate), the p-type in the substrate of grid both sides or
Person's N-type source region (Source) area or drain region (Drain) area and passage (Channel) structure between source region and drain region
Into.
Because CMOS size is less and less, accordingly, the size of various pieces is also required to corresponding, proportional in CMOS
Reduction.With MOS（Metal Oxide Semiconductor, MOS）Exemplified by transistor, the source region in MOS transistor
(Source) channel dimensions between drain region (Drain) are by the proportional diminution of the size with MOS；Meanwhile multiple MOS it
Between grid (Gate) between the size of space be also gradually reduced.
When being connected with each other between multiple MOS transistors, generally by the source region of single MOS transistor, drain region and grid
The interlayer dielectric layer of extremely upper one layer of insulation of growth, and it is corresponding with the source region, drain region and grid in the interlayer dielectric layer
Contact hole is opened up on position（Contact Hole）, expose the source region, the part in drain region, then in the contact hole
To form metallic conduction connector, the source region of the metallic conduction connector and other MOS transistors, drain region are connected filling metal, are entered
And realize the interconnection between multiple MOS transistors.
But the electric conductivity between the metallic conduction connector and the source region, drain region is unsatisfactory.And the conduction
Performance is directly related with the contact resistance of the metallic conduction connector, in order to reduce the contact resistance, and then improves electric conductivity
Can, it usually needs before the metallic conduction connector is formed, source region, drain region and grid in the contact hole are exposed
One layer of contact layer is pre-formed on partial surface.
The existing method for forming the contact layer is that by way of deposition, one layer of gold is formed in the contact hole
Category, and by annealing, react the metal level and the surface of source region, drain region exposed portion, to form silicide
（Silicide）；This mode for forming the silicide turns into silicide rear（Silicide Last）
The silicide can effectively reduce the contact resistance between source region, drain region and the metallic conduction connector.
However, with the reduction of transistor size, the width of contact hole also reduces therewith so that the deep width of the contact hole
Than becoming bigger, metal material is difficult to the bottom for reaching contact hole, causes to add deposited metal material in the contact hole
Difficulty.
In addition, prior art is in order in the contact layer of contact hole bottom acquisition predetermined thickness, the larger gold of meeting deposit thickness
Belong to layer, so as to form the metal level of adequate thickness on contact hole surface, this adds difficulty subsequently to remove the metal level
The content of the invention
The present invention solves the problems, such as to be to provide a kind of forming method of transistor, to reduce the manufacture difficulty of transistor.
To solve the above problems, the present invention provides a kind of forming method of transistor, including：
Substrate is provided；
Form source region, drain region and the grid on the substrate being located in the substrate；
The blanket dielectric layer on the substrate and the source region, drain region and grid；
Form contact hole in the dielectric layer, make the contact hole expose one in source region, drain region and grid or
Person is multiple；
Chemical solution is passed through into the contact hole, makes the chemical solution in the inwall and bottom shape of the contact hole
Into coating；
The first heat treatment is carried out, makes the coating and the source region being in contact with the coating, drain region or grid anti-
Should, to form contact layer；
Selective cleaning is carried out to the transistor, to remove unreacted coating.
Optionally, the step of forming the source region, drain region includes：
Source region, the corresponding position in drain region form groove in the silicon substrate；
Germanium silicon material is filled in the groove, to form the source region, drain region.
Optionally, the step of forming the contact layer includes：The contact layer of formation is nickel suicide contact layer.
Optionally, the step of forming the contact layer includes：The contact layer is doping type contact layer.
Optionally, the doping type contact layer is boron doping type contact layer.
Optionally, the step of being passed through chemical solution includes：The chemical solution contains boron hydrogen radical ion and nickel ion.
Optionally, the chemical solution includes the first chemical solution with boron hydrogen radical ion and second with nickel ion
Chemical solution, first chemical solution and the second chemical solution are passed through the contact hole simultaneously, or each lead into described connect
Contact hole.
Optionally, the chemical solution is the mixed solution of potassium borohydride and nickel chloride.
Optionally：Scope of the temperature of the mixed solution at 0~30 degree Celsius；
Scope of the pH value of the mixed solution 3~6.
Optionally, after the step of being passed through chemical solution, before the step of carrying out the first heat treatment, in addition to following step
Suddenly：
Using contact hole described in deionized water rinsing and coating.
Optionally, first heat treatment is short annealing heat treatment or microwave combustion method.
Optionally, scope of the temperature of first heat treatment at 200~300 degrees Celsius, annealing time was at 30~180 seconds
Scope.
Optionally, the step of selectivity cleaning includes：The unreacted impurity is removed using wet selective cleaning.
Optionally, the coating is nickel coating or ni-b alloy coating, using sulfuric acid solution and hydrogen peroxide
The mixed solution of solution carries out the wet selective cleaning.
Optionally, cleaning temperature is in the range of 120~200 degrees Celsius, and scavenging period is in the range of 30~1800 seconds.
Optionally, also comprise the following steps after the step of selectively cleaning：
The second heat treatment is carried out to the transistor.
Optionally, the temperature of second heat treatment is higher than the temperature of the described first heat treatment, and second heat treatment
Time be less than first heat treatment time.
Optionally, second heat treatment is heat-treated for short annealing, and the temperature of short annealing heat treatment is 300~500
Degree Celsius scope, scope of the processing time at 1~90 second.
Optionally, scope of the annealing time at 0.2~2.5 millisecond of second heat treatment, annealing temperature 700~
900 degrees Celsius of scope.
Compared with prior art, technical scheme has advantages below：
By being passed through chemical solution into the contact hole, the chemical solution is set to form covering in the contact hole
Layer；The coating formed in this way can be very good to be covered in the inside of the contact hole；After this, to coating
It is heat-treated, the contact layer for making the exposed portion of coating and source region and drain region react and be formed required for transistor；So
The contact layer thickness of formation is uniform, and compared with the method for existing formation transistor, the effect of the transistor of formation is more preferable.
Further, the nickel suicide contact layer of formation has relatively low resistivity, advantageously reduces contact resistance.
Further, using coating described in deionized water rinsing, the impurity remained on the coating can be removed as far as possible,
Condition is provided for follow-up heat treatment step.
Further, the annealing first uses short annealing heat treatment or microwave combustion method, can make the covering
While layer and the exposed portion in the source region, drain region are reacted, the other parts of coating and transistor are avoided to occur as far as possible anti-
Should.
Further, there is preferably selectivity using the mixed liquor of sulfuric acid solution and hydrogenperoxide steam generator, can removing
Reduce the damage to transistor other parts while the residual coating.
Further, the metastable phase nickel silicide that the second heat treatment can contain the possibility in the contact layer is carried out
（NixSiy）It is converted into the relatively low nickel silicide of resistivity（NiSi）, advantageously reduce the contact resistance of the contact layer.
Brief description of the drawings
Fig. 1 to Fig. 6 is the structural representation of each step transistor of the embodiment of forming method one of transistor of the present invention.
Embodiment
Because existing transistor size reduces, the size of each structure of transistor internal also accordingly reduces, described to connect
The depth-to-width ratio increase of contact hole, existing depositional mode are difficult to preferably form metal level in the contact hole.
Therefore, the present invention provides a kind of method that can preferably form transistor.
The present invention provides a kind of forming method of transistor, comprises the following steps：
Step S1, there is provided substrate；
Step S2, form source region, drain region and the grid on the substrate being located in the substrate；
Step S3, the blanket dielectric layer on the substrate and the source region, drain region and grid；
Step S4, contact hole is formed in the dielectric layer, the contact hole is exposed in source region, drain region and grid
One or more；
Step S5, chemical solution is passed through into the contact hole, make the chemical solution the contact hole inwall with
And coating is formed on bottom；
Step S6, carry out the first heat treatment, make the coating and the source region being in contact with the coating, drain region or
Grid reacts, to form contact layer；
Step S7, selective cleaning is carried out to the transistor, to remove unreacted coating.
Chemical solution is passed through into the contact hole, because the chemical solution is that liquid is easier to enter contact hole
In, without being influenceed by contact hole depth-to-width ratio, compared with existing chemical vapor deposition manner, reduce technology difficulty.
Further, the coating is formed by chemical solution, the coating can be made more to be formed uniformly on
Inside the contact hole, condition is provided to form the contact layer for follow-up heat treatment.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Referring to Fig. 1~Fig. 6, the knot of each step transistor of the embodiment of forming method one of transistor of the present invention is illustrated
Structure.
As shown in figure 1, perform step S1, there is provided substrate 100.In the present embodiment, the substrate 100 is silicon substrate, but this
Invent without limitation, the substrate 100 can also be formed using other backing materials used in the prior art.
With continued reference to Fig. 1, step S2 is performed, forms source region 110, drain region 120 in the substrate 100, area and is located at
Grid 130 on the substrate 100.
The present embodiment forms grid by taking the transistor of pmos type as an example on the substrate 100 between source region 110, drain region 120
130, p-type doping is carried out to substrate 100 with grid 130 afterwards, to form the source region 110 of p-type, drain region in the substrate 100
120.In the present embodiment, the source region 110, drain region 120 are formed using stress germanium silicon.Specifically, source region 110, drain region are formed
120 the step of, includes：Source region, the corresponding position in drain region form groove in the silicon substrate；Germanium is filled in the groove
Silicon materials, to form the source region, drain region.But whether the present invention is to using stress material formation source region 110, drain region 12 not to make
Limitation.
The grid 130 of the present embodiment includes：It is sequentially located at grid oxygen on the substrate 100, polysilicon layer and positioned at described
Side wall 131 in grid oxygen, polysilicon layer side wall.
It should be noted that the present invention not to the source region 110 in the PMOS, the structure in drain region 120 and grid 130,
Shape and material therefor impose any restrictions.
In the present embodiment, isolation structure 101 is also provided with substrate 100, in the present embodiment, the isolation structure
101 be shallow groove isolation structure（Shallow Trench Isolation,STI）.
It is described but whether the present invention is to forming the either type of isolation structure 101 of isolation structure 101 and not being restricted
Isolation structure 101 can also be that other isolation structure types such as local oxidation is isolated（Local Oxidation of
Silicon,LOCOS）.
Referring to Fig. 2, step S3 is performed, in the substrate 100 and source region 110, the drain region 120 and overlying of grid 130
Lid dielectric layer 30.
In the present embodiment, the dielectric layer 30 includes：
Oxide-isolation layer 90, it is covered on the isolation structure 101, source region 110, drain region 120 and grid 130；
It is sequentially arranged in stop-layer 80 in the oxide-isolation layer 90, oxide-isolation layer 70.
With reference to referring to figs. 2 and 3 execution step S4, formation contact hole 140, makes the contact in the dielectric layer 80
Expose one or more in source region 110, drain region 120 and grid 130 in hole 140.
In the present embodiment, some hard mask layers 50 are formed on the dielectric layer 30, also in some hard mask layers
The photoresist layer 40 of patterning is formed on 50.
Wherein, described some hard mask layers 50 include such as a-C（Amorphous carbon mould）Deng APF,（Advanced
Patterning Film）, but the present invention is not limited this.
Afterwards, the pattern for etching the photoresist layer 40 that will be patterned into is transferred in hard mask layer 50, forms the hard of patterning
Mask layer 50；It is afterwards mask with the hard mask layer 50 of patterning, leads to the material of dielectric layer 30 that overetched side removes part, directly
Untill source region 110 and drain region 120 is exposed, to form the contact hole 140.
This sentence expose source region 110, drain region 120 contact hole exemplified by, can also be formed expose grid in other embodiments
The contact hole 140 of pole 130.
Further, the hard mask layer 50 and photoresist layer 40 are removed, exposes the surface of the dielectric layer 30.
With reference to reference to figure 4 and Fig. 5, step S5 is performed, chemical solution 150 is passed through into the contact hole 140, makes describedization
Learn solution 150 and form coating 160 in the inwall of the contact hole 140 and bottom（Fig. 5）.
In the present embodiment, the chemistry can be made to reach by the way that transistor is immersed in the chemical solution 150
Solution 150 is passed through the purpose of the contact hole 140.
But above method is only the method that chemical solution is passed through used by the present embodiment, how the present invention is to be passed through
Chemical solution does not do any restrictions.
It should be noted that the contact hole 140 is arranged in the dielectric layer 30, the shape after chemical solution 150 is passed through
Into the coating 160 be also possible to be formed on the surface of the dielectric layer 30.
The coating 160 is used in subsequent steps, with the source region 110, the exposed portion substrate in drain region 120
100 react to form contact layer.
The chemical solution 150 is liquid, can be easily entered in the contact hole 140, without being connect
The limitation of the depth-to-width ratio of contact hole 140, and then the coating 160 that the chemical solution 150 is formed can be easier to and preferably be formed
Inside the contact hole 140（The surface of source region 110 and the exposed portion of drain region 120 including inwall and bottom）.
Compared to existing formation metal level（Equivalent to the coating 160 of the present invention）Method, the present invention can be formed
Uniform fold will not increase the thickness positioned at the surface coating 160 of dielectric layer 30 in the coating 160 of the bottom of contact hole 140
Degree, the difficulty for removing the coating 160 outside contact hole 140 is reduced, also reduces material cost.
In the present embodiment, nickel ion is included in the chemical solution 150（Ni2 +）And boron hydrogen radical ion（BH4 -）, institute
With the coating 160 of formation be ni-b alloy precipitation, the ni-b alloy precipitate in follow-up heat treatment step with institute
State source region 110, the reaction of drain region 120 forms boron doped nisiloy contact layer.
Forming doping type contact layer is advantageous in that, lifts the electrical connection properties of the contact layer.
But the present invention does not limit the material of the coating 160, can also basis be actually needed which kind of material obtained
Coating, change the ion included in the chemical solution 150 accordingly.For example, if desired for formed cobalt silicide coating,
Nickel ion in the chemical solution 150 can be replaced with cobalt.This is not limited by the present invention.
Accordingly, the boron hydrogen radical ion of the chemical solution 150 can also replace with other ions according to actual conditions, this
Invention is not construed as limiting to this.
Chemical reaction of the chemical solution 150 in the contact hole 140 is reduction reaction, and reactive chemistry formula is as follows：
BH4 -+2H2O=BO2 -+4H2↑ (R1)
BH4-+2Ni2++2H2O=2Ni↓+BO2 -+4H++2H2↑ (R2)
BH4 -+H2O=B↓+OH-+2.5H2↑ (R3)
In the present embodiment, the chemical solution 150 includes the first chemical solution of boron hydrogen radical ion, and bag
The second chemical solution containing nickel ion.First chemical solution and the second chemical solution are added to the contact hole simultaneously
In 140, to improve manufacture efficiency.But the present invention is without limitation or is separately added into first chemical solution
With the second chemical solution, and the present invention is not also limited the sequencing for adding first chemical solution and the second chemical solution
System.
In the present embodiment, the chemical solution 150 is potassium borohydride（KBH4）And nickel chloride（NiCl2）Mixed solution.
It is advantageous in that using potassium borohydride and nickel chloride, in addition to producing hydrogen and nickel, boron precipitation, other by-products
The equal soluble by-products of thing, other precipitations or hard to tolerate miscellaneous as solution is together drained, can will not be being produced after completion of the reaction
Matter, reduce the probability that the impurity in addition to nickel, boron is included in the coating of generation.
It should be noted that the present invention is to potassium borohydride in the chemical solution 150（KBH4）And nickel chloride（NiCl2）'s
Mixed proportion is not limited.
In addition, the potassium borohydride（KBH4）In potassium ion（K+）Other salts such as sodium ion can also be replaced with（Na+）, i other words, the potassium borohydride can be replaced with sodium borohydride（NaBH4）.
Meanwhile the nickel chloride（NiCl2）In chlorion (Cl-) other halide ions such as bromine can also be replaced with
（Br-）, i other words, the nickel chloride can be replaced with nickelous bromide（NiBr2）.
Further, in the present embodiment, when the chemical solution 150 is passed through in the contact hole 140, described in holding
Scope of the temperature of chemical solution 150 at 0~30 degree Celsius, while keep model of the pH value of the chemical solution 150 3~6
Enclose.
It is such to be advantageous in that, in the range of above-mentioned temperature range and PH, be advantageous to the ni-b alloy precipitation
Produce, and then inside the contact hole 140（The oxide-isolated layer surface may be included）Form the coating 160.
, can be according to actual conditions using other but the present invention is not limited to the temperature range and PH scopes
Temperature value and pH value.
In the present embodiment, after forming the coating 160 in the contact hole 140, before step S5, in addition to
Following steps：
Using deionization（Deionized Water,DIW）Water rinses the contact hole 140 and coating 160.
It is such to be advantageous in that, the impurity remained on the contact hole 140 and coating 160 can be rinsed out（Such as
Reacted accessory substance or unreacted remaining chemical solution etc. in the chemical solution 150）, advantageously reduce follow-up step
The probability of other impurities is formed in rapid.
Referring to Fig. 5, perform step S6, carry out the first heat treatment, make the coating 160 and with the coating 160
Source region 110, drain region 120 or the grid 130 being in contact react, to form contact layer 170.
Because the source region 110 in the present embodiment, drain region 120 are germanium silicon source area, drain region, coating 160 is ni-b alloy, institute
So that the contact layer 170 formed after heat treatment is the nickel suicide contact layer of doping boron.
The nickel silicon alloy contact layer of the doping boron has relatively low resistivity, advantageously reduces the source region 110, drain region
Contact resistance between 120 and metallic conduction connector.
In the present embodiment, the heat treatment is heat-treated using short annealing（Rapid Thermal Annealing,
RTA）Mode, react the exposed portion in the part of covering layer 160 and the source region 110, drain region 120, with described in formation
Contact layer 170.
It is advantageous in that using short annealing heat treatment, can optionally makes the coating 160 and the source region
110th, the exposed portion reaction in drain region 120, while avoid the other parts of coating 160 and transistor to react as far as possible.
In the present embodiment, scope of the temperature of heat treatment at 200~300 degrees Celsius, annealing time was at 30~180 seconds
Scope, with the contact layer 170 of thickness preferably needed for formation.
But the present invention can also use such as microwave combustion method（Micro-Wave）Deng other heat treatment modes, accordingly,
The temperature and time of heat treatment is adjusted also with actual heat treatment situation, the invention is not limited in this regard.
With continued reference to Fig. 6, step S7 is performed, selective cleaning is carried out to institute's transistor, to remove unreacted coating
160.The unreacted coating in the contact hole 140 and in the oxide-isolation layer 70 is gone by this step S6
Remove, condition is provided to form metallic conduction connector in the contact hole 140.
In the present embodiment, the selectivity cleaning uses wet-cleaning, is fully removed with more residual in transistor
Remaining coating.
Further, using the mixed solution using sulfuric acid solution and hydrogenperoxide steam generator（SPM）Cleaned, cleaning temperature
Spend the scope at 120~200 degrees Celsius, scope of the scavenging period at 30~1800 seconds.It is such to be advantageous in that, this solution tool
There is preferable selectivity, the damage to transistor other parts can be reduced while the residual coating is removed.
In the present embodiment, also comprise the following steps after the step of selectively cleaning：
The second heat treatment is carried out to the source region 110, drain region 120 and coating 160.
It should be noted that the contact layer 170 formed after step S6 the first heat treatment（In the present embodiment
To adulterate the nickel suicide contact layer of boron）In may contain metastable phase nickel silicide（NixSiy）, but the nisiloy of this metastable phase
The resistivity of compound is with respect to nickel silicide（NiSi）With higher resistivity, it is unfavorable for reducing contact resistance.
Carrying out the effect of second heat treatment is：Can be by these metastable phase nickel silicides（NixSiy）It is converted into relatively low
The nickel silicide of resistivity（NiSi）, advantageously ensure that the low-resistivity of the contact layer 170.
In the present embodiment, the annealing temperature of second heat treatment is higher than the annealing temperature of the described first heat treatment, together
When, annealing time of second annealing time being heat-treated also less than the first heat treatment.It is such to be advantageous in that, make the contact
While layer 170 changes, reduce the probability that transistor miscellaneous part changes as far as possible.
Specifically, in the present embodiment, in the present embodiment, second heat treatment is heat-treated using short annealing, its
In, scope of the annealing temperature at 300~500 degrees Celsius, scope of the annealing time at 1~90 second.
But the present invention is not restricted to the second heat treatment by the way of, equally, heat treatment time and temperature also may be used
To be adjusted correspondingly according to the heat treatment mode actually used.For example, in another embodiment of the invention, it can also adopt
Annealed with Microsecond grade（Micro Second Annealing,MSA）Mode, now, annealing time is at 0.2~2.5 millisecond
Scope, scope of the annealing temperature at 700~900 degrees Celsius.
Then conductive plunger is formed on the contact layer 170, because the quality that contact layer 170 is formed is preferable, can guarantee that
Effective between conductive plunger and source-drain area electrically connects.
The present embodiment Transistor forming method also includes the other parts for forming transistor, this step and prior art phase
Together, here is omitted.
So far the manufacturing process of Transistor forming method of the present invention is completed.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (19)
- A kind of 1. forming method of transistor, it is characterised in that including：Substrate is provided；Form source region, drain region and the grid on the substrate being located in the substrate；The blanket dielectric layer on the substrate and the source region, drain region and grid；Contact hole is formed in the dielectric layer, the contact hole is exposed one in source region, drain region and grid or more It is individual；Chemical solution is passed through into the contact hole, the chemical solution is formed in the inwall of the contact hole and bottom and covers Cap rock, the coating are formed by the chemical reaction of the chemical solution；The first heat treatment is carried out, makes the coating and source region being in contact with the coating, drain region or grid reaction, with Form contact layer；Selective cleaning is carried out, to remove unreacted coating.
- 2. the method as described in claim 1, it is characterised in that the substrate is silicon substrate, forms the source region, the step in drain region Suddenly include：Source region, the corresponding position in drain region form groove in the silicon substrate；Germanium silicon material is filled in the groove, to form the source region, drain region.
- 3. the method as described in claim 1, it is characterised in that the step of forming the contact layer includes：The contact layer of formation For nickel suicide contact layer.
- 4. the method as described in claim 1, it is characterised in that the step of forming the contact layer includes：The contact layer is Doping type contact layer.
- 5. method as claimed in claim 4, it is characterised in that the doping type contact layer is boron doping type contact layer.
- 6. the method as described in claim 1, it is characterised in that the step of being passed through chemical solution includes：The chemical solution contains There are boron hydrogen radical ion and nickel ion.
- 7. method as claimed in claim 6, it is characterised in that the chemical solution includes the first change with boron hydrogen radical ion Solution and the second chemical solution with nickel ion are learned, first chemical solution and the second chemical solution are passed through described connect simultaneously Contact hole, or each lead into the contact hole.
- 8. method as claimed in claim 6, it is characterised in that the chemical solution is molten for the mixing of potassium borohydride and nickel chloride Liquid.
- 9. method as claimed in claim 8, it is characterised in that scope of the temperature of the mixed solution at 0~30 degree Celsius；Scope of the pH value of the mixed solution 3~6.
- 10. the method as described in claim 1, it is characterised in that after the step of being passed through chemical solution, carry out the first heat treatment The step of before, it is further comprising the steps of：Using contact hole described in deionized water rinsing and coating.
- 11. the method as described in claim 1, it is characterised in that first heat treatment is short annealing heat treatment or micro- Ripple is heat-treated.
- 12. method as claimed in claim 11, it is characterised in that the temperature of first heat treatment is at 200~300 degrees Celsius Scope, scope of the annealing time at 30~180 seconds.
- 13. the method described in claim 1, it is characterised in that the step of selectivity is cleaned includes：Cleaned using wet selective Remove the unreacted impurity.
- 14. method as claimed in claim 13, it is characterised in that the coating is that nickel coating or ni-b alloy cover Layer, the wet selective cleaning is carried out using the mixed solution of sulfuric acid solution and hydrogenperoxide steam generator.
- 15. method as claimed in claim 14, it is characterised in that cleaning temperature is in the range of 120~200 degrees Celsius, clearly The time is washed in the range of 30~1800 seconds.
- 16. the method as described in claim 1, it is characterised in that also include after the step of selectively cleaning：The second heat treatment is carried out to the transistor.
- 17. method as claimed in claim 16, it is characterised in that the temperature of second heat treatment is higher than at the described first heat The temperature of reason, and the time of second heat treatment is less than the time of the first heat treatment.
- 18. method as claimed in claim 17, it is characterised in that second heat treatment is heat-treated for short annealing, quickly Scope of the temperature of annealing heat-treats at 300~500 degrees Celsius, scope of the processing time at 1~90 second.
- 19. method as claimed in claim 17, it is characterised in that the annealing time of second heat treatment is in 0.2~2.5 milli The scope of second, scope of the annealing temperature at 700~900 degrees Celsius.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW530342B (en) * | 1999-08-10 | 2003-05-01 | Taiwan Semiconductor Mfg | Formation method of self-aligned silicide using dual spacer |
| CN1484285A (en) * | 2002-09-18 | 2004-03-24 | 上海宏力半导体制造有限公司 | Method for forming self-alignment metal silicide |
| US7005358B2 (en) * | 2003-07-31 | 2006-02-28 | Advanced Micro Devices, Inc. | Technique for forming recessed sidewall spacers for a polysilicon line |
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2013
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW530342B (en) * | 1999-08-10 | 2003-05-01 | Taiwan Semiconductor Mfg | Formation method of self-aligned silicide using dual spacer |
| CN1484285A (en) * | 2002-09-18 | 2004-03-24 | 上海宏力半导体制造有限公司 | Method for forming self-alignment metal silicide |
| US7005358B2 (en) * | 2003-07-31 | 2006-02-28 | Advanced Micro Devices, Inc. | Technique for forming recessed sidewall spacers for a polysilicon line |
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