3 1 23twf.doc A7 B7 五、發明説明（ί ) 本發明是有關於積體電路結構及製造方法，且特別是 有關於一種自彳了對準金屬砂化物（Salicide)之結構及製造方 法，使用表面升局的淺溝渠隔離(Elevated Shallow Trench Isolation ; Elevated STI)技術和金屬離子植入技術（Metal Ion Implantation Technology ； Mesotaxy) ° 積體電路，是由許多的元件和隔離元件的元件隔離區 所組成。元件隔離區係用以防止載子（Carrier)通過半導體 基底而在相鄰支元件間移動，傳統上，元件隔離區形成於 稠密的半導體電路比如是動態隨機記憶體(DRAM)中相鄰 的場效電晶體（FET)間，藉以減少由場效電晶體產生的電 荷遺漏（Charge Leakage)。元件隔離區時常以厚場氧化層 (FOX)的型式延伸，而在半導體表面下形成之，而目前較 新的元件隔離結構爲淺溝渠隔離結構。 請參照第1A-1D圖，其繪示習知一種淺溝渠隔離之製 造流程剖面示意圖。 首先，請參照第1A圖，例如使用化學氣相沉積法 (CVD)，在半導體基底10上，依序形成墊氧化層12和氮 化矽層14，。其次，例如使用微影飩刻法，依序非等向性 地蝕刻部分氮化矽層14、部分墊氧化層12、以及部分半 —導體基底10，在半導體基底10、墊氧化層12、以及氮化 矽層14中，形成溝渠16。接著，例如使用熱氧化法’在 溝渠16內側之半導體基底10表面上，形成一襯氧化層 18(Liner Oxide) ° 接著，請參照第1B圖，例如使用常壓化學氣相沉積 3 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ：----„----1---------訂 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 3 123twf.doc 3 123twf.doc 經濟部中央標準局員工消費合作社印製 A7 _______B7_ 五、發明説明（〉） 法（Atmospheric Pressure Chemical Vapor Deposition ； APCVD)，沉積絕緣材料，較佳的是四鄰乙氧基矽酸鹽 (Tetraethyl Orthsilicate ; TEOS)，塡滿溝渠 16，並使四鄰 乙氧基砂酸鹽覆蓋氮化砂層14，形成絕緣層20。因以四 鄰乙氧基矽酸鹽構成的絕緣層20須經密實化（Densification) 的步驟，比如在溫度約l〇〇〇°C下，進行時間約1〇〜30分鐘， 而經密實化之後，四鄰乙氧基矽酸鹽會收縮。 接著，請參照第1C圖，在密實化之後，進行例如使 用化學機械硏磨法（Chemical Mechanical Polishing; CMP) 或回蝕法，以氮化矽層14爲蝕刻終點，硏磨或蝕刻去除 氮化砂層14上的部分絕緣層20。然而，化學機械硏磨法 進行時，由於絕緣層20較氮化矽層14軟，因此約與氮化 矽層14表面在同一平面上的絕緣層20會有輕微凹入的現 象。 接著，請參照第1D圖，例如使用熱磷酸溶液，移去 氮化矽層14，而留下墊氧化層14表面上之絕緣層20。隨 後，例如使用氫氟酸(HF)浸蝕移除墊氧化層12，由於以四 鄰乙氧基矽酸鹽構成的絕緣層2〇的蝕刻速率較熱氧化之 墊氧化層12快速許多，造成移除墊氧化層12時，絕緣層 20移去的厚度較墊氧化層12大，使絕緣層20約與半導體 » 基底10位在同一高度；而値得注意的是，在絕緣層20和 半導體基底10表面鄰接的部分，常因過度蝕刻使得絕緣 層20表面會產生凹陷22。如果要將此半導體做成互補式 金氧半導體（CMOS)，通常在此時進行起始電壓調整 4 本紙張尺.度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) ft------IT------^ 3 123twf.doc A7 B7 五、發明説明（4) (Threshold Voltage Adjustment)的離子植入（未圖示）。 凹陷22的產生導致半導體基底10和絕緣層20鄰接 處的角落24尖銳，使得後續形成閘極氧化層時，在角落24 處的閘極氧化層較薄，而容易在閘極形成後施加電壓時， 由角落24尖端處產生遺漏電流（Leakage Current)。 而當半導體元件完成後，因過度蝕刻而在鄰接半導體 基底10表面所形成的凹陷22，將會累積電荷，進而降低 元件的起始電壓（Threshold Voltage)，產生一不正常的次 起始電流（Sub-Threshold Current)，此即所謂頸結效應（Kink Effect)。起始電壓的降低和次起始電流的產生，都會降低 元件的品質，導致製程的良率(Yield)減少，故係爲半導體 製程所不樂見。 另一方面，當元件的積集度(Integration)逐漸增加，使 得金氧半電晶體（Metal Oxide Semiconductor ; MOS)元件的 汲極與源極的電阻，逐漸上升至與金氧半電晶體通道 (Channel)的電阻相當時，爲了調降汲極與源極的片電阻 (Sheet Resistance)，並確保金屬與金氧半電晶體間的淺接 面（Shallow Junction)的完整，一種稱爲自行對準金屬砂化 物製程的應用，便漸漸地應用在0.5微米以下的超大型積 體電路(Very Large Scale Integration ; VLSI)的製程裡。 請參照第2A-2C圖，其繪示習知一種自行對準金屬矽 化物的製造流程剖面示意圖，採用淺溝渠隔離爲元件隔離 區。 首先，請參照第2A圖，提供具有淺溝渠隔離結構的 5 本紙張·尺度適用中國國家標準（CNS ) A4規格（210X297公釐） _ _ ______— . V/' Λ — I (請先聞讀背面之注意事項再填寫本頁) 訂 經濟部中央標準局貝工消費合作社印製 3 123twf. doc 3 123twf. doc 經濟部中央標準局員工消費合作杜印製 A7 B7 五、發明説明（仏） 半導體基底50，半導體基底5〇包括主動區域和元件隔離 W ’兀件际離區是淺溝渠1½[離5 2。其次，例如使用乾式氧 化法，在半導體基底50上，形成薄的閘極氧化層54。接 著，例如使用低壓氣相沉積法，沉積多晶矽材料，在閘極 氧化層54上，並進行微影蝕刻步驟，形成閘極56。之後， 通常使用例如離子植入法，在閘極56的兩側和淺溝渠隔 離52之間的半導體基底50表面下，分別在閘極56的兩 側同時形成輕摻雜源極區62、輕摻雜汲極區64。 接著’請參照第2B圖’使用例如低壓化學氣相沉積 法和乾式蝕刻法，在閘極56和閘極氧化層54的側邊形成 間隙壁66。然後，使用例如離子植入法，植入高濃度的雜 質，在閘極56的兩側之半導體基底50表面下，分別形成 重摻雜源極區68、重摻雜汲極區70。 接著’請參照第2C圖，例如使用金屬濺鍍法（Metal Sputtering)，形成一層金屬材料，例如鈷(cobalt)，之後進 行回火步驟，則在源極68、汲極70、以及閘極56的表面 上’鎢與矽反應形成矽化鈷層72。然後，進行選擇性蝕刻 步驟，蝕刻移除未反應的金屬。 .由上述可知，習知的自行對準金屬矽化物的製造方法 依序包括金屬薄膜沉積、回火、以及移除未反應的金屬三 個製程步驟。不論是在閘極56頂端或是鄰近間隙壁66的 重摻雜源極區68或重摻雜汲極區70的邊緣，如果金屬移 除的不夠乾淨或是金屬矽化物過度生長，通常會導致閘極 56到重摻雜源極區68、重摻雜汲極區70電流的遺漏路徑。 6 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） : ^ (請先閱讀背面之注意事項再填寫本頁) -'•3 1 23twf.doc A7 B7 V. INTRODUCTION TO THE INVENTION (ί) The present invention relates to integrated circuit structures and manufacturing methods, and in particular to a structure and manufacturing method for self-aligned metal salicide (Salicide), Elevated Shallow Trench Isolation (Elevated STI) technology and Metal Ion Implantation Technology (Mesotaxy) using integrated surface lift ° Integrated circuit, which is composed of many components and element isolation areas of isolation components composition. The element isolation region is used to prevent carriers from moving between adjacent branches through the semiconductor substrate. Traditionally, the element isolation region is formed in dense semiconductor circuits such as adjacent fields in dynamic random memory (DRAM). In order to reduce the charge leakage generated by the field effect transistor (Charge Leakage). Element isolation areas often extend in the form of thick field oxide (FOX) and are formed under the semiconductor surface. The newer element isolation structure is currently a shallow trench isolation structure. Please refer to Figures 1A-1D for a schematic cross-sectional view of the manufacturing process of a conventional shallow trench isolation. First, referring to FIG. 1A, for example, a chemical vapor deposition (CVD) method is used to sequentially form a pad oxide layer 12 and a silicon nitride layer 14 on a semiconductor substrate 10. Secondly, for example, using a photolithography method, a part of the silicon nitride layer 14, a part of the pad oxide layer 12, and a part of the semi-conductive substrate 10 are sequentially anisotropically etched, and the semiconductor substrate 10, the pad oxide layer 12, and A trench 16 is formed in the silicon nitride layer 14. Next, for example, a thermal oxidation method is used to form a liner oxide layer 18 (Liner Oxide) on the surface of the semiconductor substrate 10 inside the trench 16. ° Next, refer to FIG. 1B, for example, atmospheric pressure chemical vapor deposition. Applicable to Chinese National Standard (CNS) A4 specification (210X297 mm): ---- „---- 1 --------- Order (Please read the precautions on the back before filling this page) Ministry of Economic Affairs Printed by the Consumer Standards Cooperative of the Central Standards Bureau 3 123twf.doc 3 123twf.doc Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 _______B7_ V. Atmospheric Pressure Chemical Vapor Deposition (APCVD) Law, Depositing Insulation Materials, Tetraethyl Orthsilicate (TEOS) is preferred to fill the trench 16 and cover the nitrided sand layer 14 with the tetra-ethoxy oxalate to form the insulating layer 20. Because of the tetra-ethoxy silicon The insulating layer 20 composed of an acid salt must be subjected to a densification step, for example, at a temperature of about 1000 ° C, for a time of about 10 to 30 minutes, and after the densification, the tetra-ethoxysilicic acid Salt will shrink. Next, referring to FIG. 1C, after densification, for example, chemical mechanical polishing (CMP) or etch-back is performed, and the silicon nitride layer 14 is used as an end point for etching, and the nitride is removed by honing or etching. Part of the insulating layer 20 on the sand layer 14. However, when the chemical mechanical honing method is performed, since the insulating layer 20 is softer than the silicon nitride layer 14, the insulating layer 20 on the same plane as the surface of the silicon nitride layer 14 will have Slightly concave phenomenon. Next, referring to FIG. 1D, for example, using a hot phosphoric acid solution, the silicon nitride layer 14 is removed, leaving the insulating layer 20 on the surface of the pad oxide layer 14. Then, for example, hydrofluoric acid ( (HF) The pad oxide layer 12 is removed by etching. Since the etching rate of the insulating layer 20 made of tetra-ethoxy silicate is much faster than that of the thermally oxidized pad oxide layer 12, the insulating layer is removed when the pad oxide layer 12 is removed. The removed thickness of 20 is larger than that of the pad oxide layer 12, so that the insulating layer 20 is about the same height as the semiconductor »substrate 10; however, it should be noted that the adjacent portions of the insulating layer 20 and the surface of the semiconductor substrate 10 are often overexposed. Etching makes the insulating layer 20 The surface will produce a depression 22. If this semiconductor is to be made into a complementary metal-oxide-semiconductor (CMOS), the starting voltage is usually adjusted at this time 4 paper rulers. The degree applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) ) (Please read the precautions on the back before filling this page) ft ------ IT ------ ^ 3 123twf.doc A7 B7 V. Description of the invention (4) Ion implantation of (Threshold Voltage Adjustment) Into (not shown). The generation of the recess 22 causes the corner 24 of the semiconductor substrate 10 and the insulating layer 20 to be sharp, so that when the gate oxide layer is subsequently formed, the gate oxide layer at the corner 24 is thin, and it is easy to apply a voltage after the gate is formed. Leakage Current is generated at the tip of corner 24. After the semiconductor device is completed, the recess 22 formed on the surface of the adjacent semiconductor substrate 10 due to over-etching will accumulate electric charges, thereby reducing the threshold voltage of the device and generating an abnormal secondary starting current ( Sub-Threshold Current), which is the so-called Kink Effect. The decrease of the starting voltage and the generation of the sub-starting current will reduce the quality of the device, which will lead to a decrease in the yield of the process. Therefore, it is not desirable for the semiconductor process. On the other hand, as the integration of the device gradually increases, the resistance of the drain and source of the metal oxide semiconductor (MOS) device gradually rises to the channel with the metal oxide semiconductor (MOS) When the resistance of the channel is equal, in order to reduce the sheet resistance of the drain and source, and to ensure the integrity of the shallow junction between the metal and the metal-oxide semiconductor, a type is called self-alignment. The application of metal sanding process is gradually applied in the process of Very Large Scale Integration (VLSI) below 0.5 micron. Please refer to Figures 2A-2C, which shows a cross-sectional schematic diagram of a conventional self-aligned metal silicide manufacturing process, using shallow trench isolation as a component isolation area. First, please refer to Figure 2A, and provide 5 papers with shallow trench isolation structure. The dimensions are applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) _ _ ______ —. V / 'Λ — I (Please read first Note on the back, please fill in this page again.) Order Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Printed by the Shellfish Consumer Cooperative, 3 123twf. Doc 3 123twf. Doc Printed by the Central Standards Bureau of the Ministry of Economic Affairs, consumer printed by Du A7 B7 V. Description of Invention (仏) Semiconductor The substrate 50 and the semiconductor substrate 50 include an active region and an element isolation region. The inter-device isolation region is a shallow trench 1½ [nm 5 2]. Next, a thin gate oxide layer 54 is formed on the semiconductor substrate 50 using, for example, a dry oxidation method. Next, for example, a low-pressure vapor deposition method is used to deposit a polycrystalline silicon material on the gate oxide layer 54 and perform a lithography etching step to form the gate electrode 56. Thereafter, generally, for example, an ion implantation method is used to form a lightly doped source region 62 and a light-doped source region 62 on both sides of the gate 56 below the semiconductor substrate 50 between the sides of the gate 56 and the shallow trench isolation 52, respectively. Doped drain region 64. Next, referring to FIG. 2B, a spacer 66 is formed on the sides of the gate electrode 56 and the gate oxide layer 54 using, for example, a low pressure chemical vapor deposition method and a dry etching method. Then, a high-concentration impurity is implanted using, for example, an ion implantation method, and a heavily doped source region 68 and a heavily doped drain region 70 are respectively formed under the surface of the semiconductor substrate 50 on both sides of the gate 56. Next, please refer to FIG. 2C. For example, a metal sputtering method (Metal Sputtering) is used to form a layer of metal material, such as cobalt, and then a tempering step is performed. Then, the source 68, the drain 70, and the gate 56 On the surface, tungsten and silicon react to form a cobalt silicide layer 72. Then, a selective etching step is performed to remove unreacted metal by etching. As can be seen from the above, the conventional self-aligned metal silicide manufacturing method sequentially includes three process steps of metal film deposition, tempering, and removal of unreacted metal. Whether at the top of the gate 56 or the edge of the heavily doped source region 68 or the edge of the heavily doped drain region 70 adjacent to the spacer 66, if the metal is not removed cleanly or the metal silicide is excessively grown, it will usually result in The leakage path of the current from the gate 56 to the heavily doped source region 68 and the heavily doped drain region 70. 6 This paper size applies to China National Standard (CNS) A4 (210X297 mm): ^ (Please read the precautions on the back before filling this page)-'•
3 123twf.doc 3 123twf.doc 濟 % 中 央 擦 準 局 貝 % A7 -- -------—— ___B7 五、發明説明（（） -—- 有鑑於此’本發明的主要目的就是在提供一種自行對 準金屬矽化物之結構及製造方法，使用金屬離子植入技 術，可以降低接合面的歐姆接觸。 本發明的另一目的是在提供一種表面升高的淺溝渠隔 離結構之製造方法，.降低閘極到源/汲極區的遺漏電流（此 點因本發明不需去除殘餘的金屬）和避免頸結效應（此點是 因本發明利用昇高的淺溝渠絕緣法）。 根據本發明之主要目的，提出一種自行對準金屬矽化 物之結構’此結構包括具有表面升高的淺溝渠絕緣結構的 半導體基底，半導體基底包括主動區域，此淺溝渠絕緣結 構用以隔離主動區域，且表面升高的淺溝渠絕緣結構表面 高於主動區域表面。在部分主動區域上，有閘極氧化層。 在閘極氧化層上，有閘極。在閘極側邊，有間隙壁。分別 在閘極兩側與表面升高的淺溝渠絕緣結構之間的半導體基 底表面下，有源極區和汲極區。在部分源極區表面和部分 汲極區表面、以及閘極表面下，有金屬矽化物層。 根據本發明之主要目的，提出一種自行對準金屬矽化 物之製造方法。首先，提供具有表面升高的淺溝渠絕緣結 構的半導體基底，半導體基底包括主動區域，此淺溝渠絕 緣結構用以隔離主動區域，且此表面升高的淺溝渠絕緣結 構表面高於主動區域表面，其中主動區域上已形成閘極氧 化層、以及閘極。其次，分別在閘極兩側和表面升高的淺 溝渠絕緣結構之間的半導體基底表面下，形成輕摻雜源極 區和輕摻雜汲極區。然後，在閘極的側邊，形成間隙壁。 7 本紙垠尺度適用中國國家榡準（CNS ) A4規格（210X297公釐）3 123twf.doc 3 123twf.doc Economic% Central Correction Bureau% A7 -------------- ___B7 V. Description of the invention (() ------ In view of this, the main purpose of the present invention is to Provided is a structure and manufacturing method for self-aligning metal silicide, which can reduce ohmic contact of a joint surface by using metal ion implantation technology. Another object of the present invention is to provide a method for manufacturing a shallow trench isolation structure with a raised surface. Reduce the leakage current from the gate to the source / drain region (this point is because the invention does not need to remove the residual metal) and avoid the neck-knot effect (this point is because the invention uses a raised shallow trench insulation method). According to The main object of the present invention is to provide a structure for self-aligning metal silicide. This structure includes a semiconductor substrate having a shallow trench insulation structure with a raised surface. The semiconductor substrate includes an active area. The shallow trench insulation structure is used to isolate the active area. And the surface of the shallow trench insulation structure with a raised surface is higher than the surface of the active area. On some active areas, there is a gate oxide layer. On the gate oxide layer, there is a gate electrode. On the electrode side, there is a gap wall. Below the surface of the semiconductor substrate between the gate trench and the surface of the shallow trench insulation structure, the source region and the drain region. On the surface of the source region and the drain region, respectively. There are metal silicide layers under the surface of the region and under the gate. According to the main purpose of the present invention, a method for manufacturing self-aligned metal silicide is proposed. First, a semiconductor substrate having a shallow trench insulation structure with a surface raised is provided. The semiconductor substrate includes an active region. This shallow trench insulation structure is used to isolate the active region, and the surface of the shallow trench insulation structure raised above this surface is higher than the surface of the active region, and a gate oxide layer and a gate electrode have been formed on the active region. Next A lightly doped source region and a lightly doped drain region are formed under the semiconductor substrate surface on both sides of the gate and between the shallow trench insulation structures on the surface. Then, a gap is formed on the side of the gate. 7 The paper size is applicable to China National Standard (CNS) A4 (210X297 mm)
訂Order
3 123twf.doc A7 經濟部中央標準局員工消費合作社印製 B7 五、發明説明U ) 接著，以間隙壁爲罩幕，分別在間隙壁兩側和表面升高的 淺溝渠絕緣結構之間的半導體基底表面下，形成重摻雜源 極區和重摻雜汲極區。之後，進行金屬離子植入和回火步 驟，以間隙壁和表面升高的淺溝渠絕緣結構做爲罩幕層， 在閘極表面和重摻雜源極區表面、以及重摻雜汲極區表面 下形成一金屬砂化物層。 根據本發明之另一目的，提出一種形成表面升高的淺 溝渠絕緣結構之方法。首先，提供半導體基底上，在半導 體基底上，形成閘極氧化層。其次，在閘極氧化層上，形 成多晶矽層。然後，在該多晶矽層上，形成一氮化矽層。 接著，在該半導體基底和該閘極氧化層、以及該多晶矽層 中，形成一溝渠。之後，在該溝渠內側表面上，形成一襯 氧化層。隨後，形成一絕緣層塡滿該溝渠。然後，去除該 氮化矽層。接著，去除在該氮化矽層上的部份該絕緣層。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： '第1A-1D圖繪示習知一種淺溝渠隔離之製造流程剖面 示意圖； 第2A-2C圖繪示習知一種自行對準金屬矽化物的製造 流程剖面示意圖，採用淺溝渠隔離做爲元件隔離區； 第3A-3E圖繪示依照本發明之一較佳實施例，一種表 面升高的淺溝渠隔離之製造流程剖面示意圖，而第3E圖 8 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂 3 123twf.doc A7 B7 五、發明説明（9 ) 繪示後續此淺溝渠隔離製程，形成閘極之剖面示意圖； 第4A-4C圖繪示爲接續第3A-3E圖，一種自行對準 金屬矽化物之製造流程剖面示意圖； 第5圖繪示在矽（111)中矽化鈷化合物的厚度與離子植 入劑量的函數對應圖；以及 第6圖繪示分別在矽（111)、矽（001)中矽化鈷化合物 面積的覆蓋率與離子植入劑量的函數對應圖。 圖式之標記說明： 10、50、110 :半導體基底 12 :墊氧化層 14、116 :氮化砍層 16、118 :溝渠 18、120 :襯氧化層 20、122 :絕緣層 22 :凹陷 24 :角落 52 :淺溝渠隔離 54、112 :閘極氧化層 5 6、12 6 :鬧極 62、130 :輕摻雜源極區 64、132 :輕摻雜汲極區 66、134 :間隙壁 68、136 :重摻雜源極區 70、138 :重摻雜汲極區 9 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ' (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中央標準局員工消費合作社印製 3 123twf.doc 3 123twf.doc 經濟部中央標準局員工消費合作社印製 A7 ______B7 五、發明説明（8 ) 72、140 :金屬矽化物層 114 :第一多晶砂層 124 :第二多晶矽層 128 :主動區域 實施例 請參照第3A-3E圖，其繪示依照本發明一較佳實施 例，一種表面升高的淺溝渠隔離的製造流程剖面示意圖， 已揭露於"A Novel 0.25 β m Shallow Trench Isolation Technology, 1996 IEEE IEDM 96-837〜96-840 , by C. Chen， J.W.Chou.,and S.W.Sun, United Microelectronics, Advanced Technology Development Department, Science-Based Industrial Park，Hsin-Chu, Taiwan，R.O.C."— 文中，而第 3E 圖繪示後 續此淺溝渠隔離製程，形成閘極之剖面示意圖。 首先’請參照第3A圖，提供半導體基底110。其次， 例如使用乾式氧化法，在半導體基底110上，形成厚度約 5〇埃的閘極氧化層112。接著，例如使用低壓化學氣相沉 積法’沉積薄的一層多晶矽，在閘極氧化層112上形成第 一多晶矽層1U。接著，例如使用化學氣相沉積法，沉積 厚的一層絕緣材料’例如氮化矽，形成氮化矽層116。然 後，例如使用微影蝕刻法，依序蝕刻部分氮化矽層116、 部分第一多晶矽層114、以及部分閘極氧化層112,在氮 化矽層.116、第一多晶矽層丨η、閘極氧化層112、以及半 導體基底110中，形成溝渠118。之後，例如使用熱氧化 法，在溝渠118內側之第一多晶矽層114、閘極氧化層112、 (CNS ) Α4規格（210x297公釐） ϋ·1 II 1 m -- 1^1 - 1. s^- —------ I- . 丁 ^言 - -. (請先閲讀背面之注意事項再填寫本頁) 3 1 23twf.doc A7 B7 五、發明説明（f ) 以及半導體基底110表面上，形成襯氧化層120 ° 接著，請參照第3B圖，在溝渠118和氮化矽層Π6 上，形成絕緣層122，形成的方式比如是使用常壓化學氣 相沉積法，沉積絕緣材料，較佳的是四鄰乙氧基矽酸鹽， 塡滿溝渠118,並使四鄰乙氧基矽酸鹽溢出溝渠118,形 成絕緣層122。因以四鄰乙氧基矽酸鹽構成的絕緣層122 須經密實化的步驟，比如在溫度約l〇〇〇°C下，進行時間約 10〜30分鐘，而經密實化之後，四鄰乙氧基矽酸鹽會收縮。 接著，請參照第3C圖，在密實化之後，例如使用化 學機械硏磨法或回蝕法，以氮化矽層116爲蝕刻終點，硏 磨或鈾刻去除氮化矽層116上的部分絕緣層122。然而， 化學機械硏磨法進行時，由於絕緣層122較氮化矽層116 軟，因此約與氮化矽層116表面在同一平面上的絕緣層122 會有輕微凹入的現象。 接著，請參照第3D圖，移除氮化矽層116，移除的 方式是比如使用熱磷酸溶液，移去氮化矽層116，而留下 第一多晶砂層114表面上之絕緣層122。隨後，例如使用 氫氟酸浸鈾移除高於第一多晶矽層114表面上之部分絕緣 層122。如果要將此半導體做成互補式金氧半導體 (CMOS)，通常在此時進行起始電壓調整(Threshold Voltage Adjustment)的離子植入（未圖示）。 接著，請參照第3E圖，例如使用低壓化學氣相沉積 法，沉積一層多晶矽材料，在第一多晶矽層114、絕緣層 122上形成第二多晶矽層124。然後，形成閘極126，形成 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中央標準局員工消費合作社印製 3 1 23twf.doc A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（P) 的方式比如使用微影蝕刻法，依序鈾刻部分第二多晶敬層 124、部分第一多晶矽層114、以及部分閘極氧化層112， 則未被蝕刻的相鄰部分第二多晶矽層124和部分第一多晶 矽層II4形成閘極126。 sra參照第4A-4C圖，其繪示爲接續第3A_3E圖，一 種自行對準金屬矽化物之製造流程剖面示意圖。 首先，請參照第4A圖，提供具有表面升高的淺溝渠 隔離結構的半導體基底110,其包括主動區域128，此淺 溝渠隔離結構包括絕緣層122，用以隔離主動區域128， 其中絕緣層I22表面高於該主動區域128表面，且主動區 域128上已形成閘極氧化層112、以及第一多晶砂層U4 和第二多晶矽層124所構成的閘極126，半導體基底11〇 形成的方式例如第3A-；3E圖中所示。爲解決短通道的熱電 子效應’通常在閘極126兩側和絕緣層122之間半導體基 底110表面下，分別形成輕摻雜源極區130、輕摻雜汲極 區132’形成的方式比如使用離子植入法並以閘極126和 絕緣層122爲罩幕’依製程需要植入三價或五價雜質。 接著’請參照第4B圖，在閘極U〇兩側形成間隙壁 166，形成的方式比如低壓化學氣相沉積法和乾式蝕刻法。 然後’使用例如離子植入法，並以閘極126、絕緣層122、 以及間隙壁丨34爲罩幕，植入高濃度的雜質，在閘極126 的兩側之半導體基底11〇下，分別形成重摻雜源極區136、 重摻雜汲極區138。進行金屬離子植入步驟，利用絕緣層 I22和間隙壁134爲罩幕，植入金屬材料，例如鈷(c〇balt)、 12 (請先閱讀背面之注意事項再填寫本頁) i -、τ r 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 3 1 23 twf. doc A7 B7 五、發明説明（（\ ) 鉻(Chromium)、鈦(Titanium)、以及鎢等。 接著，請參照第4C圖，進行回火步驟，在閘極126、 重摻雜源極區136、以及重摻雜汲極區138的表面下形成 金屬砂化物層140。舉例而言，根據已揭露於"Coalesence of Buried CoSi2 Layers Formed by mesotaxy in Si(l 11),J. Appl. Phys. 70(12),15 December 1991 p.7354-7361 by Yon-Fen Hsieh ,Robert Hull,Alice E. White and Ken T. Short, AT&T Bell Laboratory,Murray Hill,New Jersey 07974"一文中，在 約1001^¥能量和約350°(：的溫度下，植入約1.1\1017離 子/cm 2劑量的鈷，然後經過在約56(TC下約1小時的回火， 接著再經過在1000°C下約1〜24小時的回火，不論在矽（111) 或是矽(001)中，都將形成一層連續的矽化鈷(CoSi2)層，厚 度約500埃。此連續的矽化鈷層中，所有的矽化鈷連接在 —起。此金屬矽化物層的厚度和面積的覆蓋率（Areal Coverage)是植入劑量的函數，而且矽基底的晶格方向將影 響面積的覆蓋率，如第5圖所示和第6圖所示，其中第5 圖繪示在矽（111)中矽化鈷沉積物的厚度與離子植入劑量的 函數對應，而第6圖繪不分別在砍（111)、砂（〇〇1)中砂化 鈷沉積物面積的覆蓋率與離子植入劑量的函數對應。 綜而言之，上述本發明較佳實施例具有下列的特點： 1·本發明之自行對準金屬矽化物製程，包括表面升高 的淺溝渠隔離技術、離子植入法形成淺溝渠隔離。不需要 金屬移除步驟，而且幾乎沒有閘極到源/汲極區的電流遺 漏。 (請先閱讀背面之注意事項再填寫本頁)3 123twf.doc A7 Printed by the Consumer Cooperatives of the Central Bureau of Standards, Ministry of Economic Affairs, B7. V. Description of the invention U) Next, the gap wall is used as a screen, and the semiconductor between the shallow trench insulation structures on both sides of the gap wall and the surface is raised. Below the surface of the substrate, a heavily doped source region and a heavily doped drain region are formed. Then, metal ion implantation and tempering steps are performed, and the shallow trench insulation structure with the spacer and the surface raised is used as the cover layer, and the gate surface, the surface of the heavily doped source region, and the heavily doped drain region A metal sand layer is formed under the surface. According to another object of the present invention, a method for forming a shallow trench insulation structure with a raised surface is proposed. First, a semiconductor substrate is provided, and a gate oxide layer is formed on the semiconductor substrate. Secondly, a polycrystalline silicon layer is formed on the gate oxide layer. Then, a silicon nitride layer is formed on the polycrystalline silicon layer. Next, a trench is formed in the semiconductor substrate, the gate oxide layer, and the polycrystalline silicon layer. After that, an oxide-lined layer is formed on the inner surface of the trench. Subsequently, an insulating layer is formed to fill the trench. Then, the silicon nitride layer is removed. Then, a part of the insulating layer on the silicon nitride layer is removed. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in detail with the accompanying drawings as follows: A brief description of the drawings: 'Section 1A Figure -1D shows a cross-sectional schematic diagram of a conventional manufacturing process for shallow trench isolation; Figures 2A-2C show a schematic cross-sectional schematic diagram of a conventional manufacturing process for self-aligned metal silicide, using shallow trench isolation as a component isolation area; Figures 3A-3E show a schematic cross-sectional view of the manufacturing process of a shallow trench isolation with a raised surface according to a preferred embodiment of the present invention, and Figure 3E Figure 8 This paper size applies Chinese National Standard (CNS) A4 specification (210X297) (%) (Please read the precautions on the back before filling this page) Order 3 123twf.doc A7 B7 V. Description of the invention (9) Draw the subsequent shallow trench isolation process to form a schematic cross-section of the gate; Figure 4A-4C The drawing is a schematic diagram of the cross-section of a self-aligned metal silicide manufacturing process following Figures 3A-3E. Figure 5 shows the corresponding function of the thickness of the cobalt silicide compound in silicon (111) and the ion implantation dose. And Figure 6 illustrates the silicon, respectively (111), Si (001) and the function coverage ion implantation dose of the compound COSI area map. Description of the symbols of the drawings: 10, 50, 110: semiconductor substrate 12: pad oxide layer 14, 116: nitride cutting layer 16, 118: trench 18, 120: lining oxide layer 20, 122: insulating layer 22: depression 24: Corner 52: Shallow trench isolation 54, 112: Gate oxide 5 6, 12 6: Alarm 62, 130: Lightly doped source region 64, 132: Lightly doped drain region 66, 134: Spacer wall 68, 136: heavily doped source region 70, 138: heavily doped drain region 9 This paper size applies to Chinese National Standard (CNS) A4 specification (210X297 mm) '(Please read the precautions on the back before filling this page) Order printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 3 123twf.doc 3 123twf.doc Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 ______B7 V. Description of the invention (8) 72, 140: Metal silicide layer 114: First Polycrystalline sand layer 124: Second polycrystalline silicon layer 128: Active area embodiment Please refer to FIGS. 3A-3E, which shows a schematic cross-sectional schematic diagram of a manufacturing process for a shallow trench isolation with a raised surface according to a preferred embodiment of the present invention. , Disclosed in " A Novel 0.25 β m Shallow Trench Isolation Technology, 19 96 IEEE IEDM 96-837 ~ 96-840, by C. Chen, JWChou., And SWSun, United Microelectronics, Advanced Technology Development Department, Science-Based Industrial Park, Hsin-Chu, Taiwan, ROC " — In the text, Figure 3E shows a schematic cross-section of the subsequent shallow trench isolation process to form the gate electrode. First, referring to FIG. 3A, a semiconductor substrate 110 is provided. Next, for example, a dry oxidation method is used to form a gate oxide layer 112 on the semiconductor substrate 110 with a thickness of about 50 angstroms. Next, for example, a low-pressure chemical vapor deposition method is used to deposit a thin layer of polycrystalline silicon to form a first polycrystalline silicon layer 1U on the gate oxide layer 112. Next, for example, a chemical vapor deposition method is used to deposit a thick layer of insulating material ', such as silicon nitride, to form a silicon nitride layer 116. Then, for example, using a photolithographic etching method, a portion of the silicon nitride layer 116, a portion of the first polycrystalline silicon layer 114, and a portion of the gate oxide layer 112 are sequentially etched, and the silicon nitride layer 116, the first polycrystalline silicon layer is sequentially etched. In the gate oxide layer 112 and the semiconductor substrate 110, a trench 118 is formed. After that, for example, using a thermal oxidation method, the first polycrystalline silicon layer 114, the gate oxide layer 112, (CNS) A4 size (210x297 mm) inside the trench 118 ϋ · 1 II 1 m-1 ^ 1-1 s ^-—------ I-. 丁 ^ 言--. (Please read the notes on the back before filling out this page) 3 1 23twf.doc A7 B7 V. Description of the Invention (f) and the semiconductor substrate An oxide layer 120 ° is formed on the 110 surface. Next, referring to FIG. 3B, an insulation layer 122 is formed on the trench 118 and the silicon nitride layer Π6. The formation method is, for example, atmospheric pressure chemical vapor deposition to deposit insulation. The material, preferably tetra-ethoxy silicate, fills the trench 118 and allows the tetra-ethoxy silicate to overflow the trench 118 to form an insulating layer 122. Because the insulating layer 122 made of tetra-o-ethoxy silicate must be subjected to a densification step, for example, at a temperature of about 1000 ° C, the process takes about 10 to 30 minutes, and after the densification, the tetra-o-ethoxy Base silicates will shrink. Next, referring to FIG. 3C, after compaction, for example, using chemical mechanical honing or etch-back, the silicon nitride layer 116 is used as an etching end point, and honing or uranium etching is used to remove a part of the insulation on the silicon nitride layer 116. Layer 122. However, when the chemical mechanical honing method is performed, since the insulating layer 122 is softer than the silicon nitride layer 116, the insulating layer 122 on the same plane as the surface of the silicon nitride layer 116 may be slightly concave. Next, referring to FIG. 3D, the silicon nitride layer 116 is removed. The removal method is, for example, using a hot phosphoric acid solution to remove the silicon nitride layer 116, leaving the insulating layer 122 on the surface of the first polycrystalline sand layer 114. . Subsequently, for example, a portion of the insulating layer 122 above the surface of the first polycrystalline silicon layer 114 is removed by leaching uranium with hydrofluoric acid. If this semiconductor is to be made into a complementary metal-oxide-semiconductor (CMOS), ion implantation (not shown) of a threshold voltage adjustment is usually performed at this time. Next, referring to FIG. 3E, for example, a low-pressure chemical vapor deposition method is used to deposit a layer of polycrystalline silicon material, and a second polycrystalline silicon layer 124 is formed on the first polycrystalline silicon layer 114 and the insulating layer 122. Then, the gate electrode 126 is formed, and the paper size is applied to the Chinese National Standard (CNS) A4 specification (210X297 mm) (please read the precautions on the back before filling this page). Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 3 1 23twf.doc A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. The method of invention description (P), such as lithography, is used to sequentially etch part of the second polycrystalline layer 124 and part of the first polycrystalline silicon. The layer 114, and a portion of the gate oxide layer 112, the adjacent portion of the second polycrystalline silicon layer 124 and a portion of the first polycrystalline silicon layer II4 that are not etched form the gate 126. sra Referring to Figures 4A-4C, it is shown as a continuation of Figures 3A-3E, a schematic cross-sectional view of the manufacturing process of self-aligned metal silicide. First, referring to FIG. 4A, a semiconductor substrate 110 having a shallow trench isolation structure with a surface rising is provided, which includes an active region 128. The shallow trench isolation structure includes an insulating layer 122 for isolating the active region 128. The insulating layer I22 The surface is higher than the surface of the active region 128, and a gate oxide layer 112 and a gate 126 composed of a first polycrystalline sand layer U4 and a second polycrystalline silicon layer 124 have been formed on the active region 128. Examples are shown in Figures 3A-; 3E. In order to solve the hot electron effect of the short channel, the lightly doped source region 130 and the lightly doped drain region 132 are generally formed under the surface of the semiconductor substrate 110 between the sides of the gate 126 and the insulating layer 122, such as Using the ion implantation method and using the gate electrode 126 and the insulating layer 122 as a mask, the trivalent or pentavalent impurities need to be implanted according to the process. Next, please refer to FIG. 4B, a spacer 166 is formed on both sides of the gate U0, and the formation method is, for example, a low pressure chemical vapor deposition method and a dry etching method. Then, using, for example, an ion implantation method, and using the gate electrode 126, the insulating layer 122, and the spacers 34 as a mask, a high concentration of impurities is implanted under the semiconductor substrate 110 on both sides of the gate electrode 126, respectively. A heavily doped source region 136 and a heavily doped drain region 138 are formed. Perform the metal ion implantation step, using the insulating layer I22 and the spacer 134 as the cover, and implant metal materials, such as cobalt (cobalt), 12 (Please read the precautions on the back before filling this page) i-, τ r This paper size applies to Chinese National Standard (CNS) A4 specification (210X297 mm) 3 1 23 twf. doc A7 B7 V. Description of the invention ((\) Chromium, Titanium, and tungsten, etc. Then, Referring to FIG. 4C, a tempering step is performed to form a metal sanding layer 140 under the surface of the gate electrode 126, the heavily doped source region 136, and the heavily doped drain region 138. For example, according to what has been disclosed in " Coalesence of Buried CoSi2 Layers Formed by mesotaxy in Si (l 11), J. Appl. Phys. 70 (12), 15 December 1991 p.7354-7361 by Yon-Fen Hsieh, Robert Hull, Alice E. White and Ken T. Short, AT & T Bell Laboratory, Murray Hill, New Jersey 07974 ", implanted a dose of about 1.1 \ 1017 ions / cm2 of cobalt at about 1001 ^ ¥ energy and about 350 ° (:) temperature. , Then after tempering at about 56 ° C for about 1 hour, and then at about 1 to 24 hours at 1000 ° C Tempering, whether in silicon (111) or silicon (001), will form a continuous cobalt silicide (CoSi2) layer with a thickness of about 500 angstroms. In this continuous cobalt silicide layer, all cobalt silicides are connected to— The thickness and area coverage of this metal silicide layer is a function of implantation dose, and the lattice direction of the silicon substrate will affect the area coverage, as shown in Figure 5 and Figure 6 Figure 5 shows the thickness of the cobalt silicide deposit in silicon (111) as a function of the ion implantation dose, while Figure 6 shows the sand in chopping (111) and sand (〇〇1) respectively. The coverage of the area of cobalt deposits corresponds to a function of the ion implantation dose. In summary, the above-mentioned preferred embodiment of the present invention has the following features: 1. The self-aligned metal silicide process of the present invention, including surface lift High shallow trench isolation technology, ion implantation method to form shallow trench isolation. No metal removal step is required, and there is almost no leakage of current from the gate to the source / drain region. (Please read the precautions on the back before filling this page )
，1T 經濟部中央標準局員工消費合作社印製 CNS ) A4規格（210X297公釐〉 3 I23twf.doc 3 I23twf.doc 經濟部中央標準局貝工消費合作社印製 A7 -^--E______ 五、發明説明（r>) 2_氮化矽層/第一多晶矽層的堆疊層不只做爲在化學機 械硏磨法或回蝕法的蝕刻終點，也控制高於主動適域 (Active Region)塡入溝渠的絕緣層之高度。 3.高出主動區域表面的絕緣層水準是後續自行對準^ 屬矽化物之製程所必須具備的結構，其中絕緣層水準的闻 度與金屬矽化物形成的金屬離子植入能量和回火溫度相 關。 4·當進行化學機械硏磨法平坦化時，考慮硏磨絕緣層 之氧化物泥漿的選擇性(Selectivity)決定氮化矽層的厚度。 然而，在本發明中第一多晶矽層的厚度是非常重要的’因 此厚度用以控制淺溝渠隔離結構的絕緣層高出主動區域表 面的高度。在後續製程中，絕緣層的頂部將遭受金屬離子 植入的轟擊，植入後可選擇移除或保留此頂部。雖然金屬 矽化物在氧化物中的再結晶（Recrystalization)從未曾被報 導過，藉由金屬離子植入後隨即移去遭轟擊的絕緣層頂 部，將避免淺溝渠隔離結構的絕緣層隔離效能的疑慮。移 去的方式可藉由高選擇性的氣體，進行反應性離子蝕刻 (RIE)或濺擊蝕刻。 5. 不進行金屬矽化物的沉積。 6. 第二多晶矽層做爲閘極導電的基礎材料。第二多晶 矽層的厚度，由後續形成自行對準矽化物製程中金屬離子 植入的能量和回火溫度決疋。 7. 金屬離子植入的種類可以是鈷、鉻、鈦、鎢等。 8. 因爲金屬矽化物的結合（c〇alescence)程度強烈地依 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨〇><297公嫠） (請先閲讀背面之注意事項再填寫本貢), 1T CNS printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs) A4 size (210X297 mm) 3 I23twf.doc 3 I23twf.doc Printed by the Shell Standard Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economics A7-^-E______ 5. Description of the invention (R >) 2_ The stacked layer of the silicon nitride layer / the first polycrystalline silicon layer is not only used as an etching end point in a chemical mechanical honing method or an etch-back method, but is also controlled to be higher than the active region intrusion. The height of the insulation layer of the trench 3. The level of the insulation layer higher than the surface of the active area is a structure necessary for subsequent self-alignment ^ A silicide process, in which the level of the insulation layer and the metal ions formed by the metal silicide The implantation energy is related to the tempering temperature. 4. When performing chemical mechanical honing planarization, the thickness of the silicon nitride layer is determined by considering the selectivity of the oxide slurry of the honing insulating layer. However, in the present invention, The thickness of the first polycrystalline silicon layer is very important, so the thickness is used to control the height of the insulation layer of the shallow trench isolation structure above the surface of the active area. In the subsequent process, the top of the insulation layer will be subject to metal ions Implantation bombardment, the top can be removed or retained after implantation. Although metal silicide recrystallization in oxides has never been reported, it is removed by bombardment by metal ion implantation The top of the insulating layer will avoid the doubt of the insulating layer isolation performance of the shallow trench isolation structure. The removal method can be reactive ion etching (RIE) or sputtering etching with a highly selective gas. 5. No metal Deposition of silicide. 6. The second polycrystalline silicon layer is used as the base material for gate conduction. The thickness of the second polycrystalline silicon layer is determined by the energy and tempering of the metal ion implantation in the subsequent self-aligned silicide process. The temperature depends on the temperature. 7. The type of metal ion implantation can be cobalt, chromium, titanium, tungsten, etc. 8. Because the degree of coalescence of metal silicide is strongly based on the paper standard, the Chinese National Standard (CNS) is applied. A4 specifications (2 丨 〇 > < 297 gong) (Please read the precautions on the back before filling in this tribute)
、1T 3 123twf.doc 3 123twf.doc 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（（、） 賴製程的條件，源/汲極區的接合（Junction)深度可以藉由 植入能量和繼起的熱預算(Thermal Budget)操控，而源/汲 極區離子植入所導致殘留的損害也將在發展金屬矽化物中 減小。 由上述本發明較佳實施例可知，應用本發明具有下列 優點： 1·表面升高的淺溝渠隔離技術可以使得元件避免頸結 效應，而藉由堆疊的閘極氧化層/第一多晶矽層定義元件 的圖案取代習知堆疊的墊氧化層/氮化矽層。 2.以離子植入法形成在閘極和源/汲極區頂端的自行對 準金屬矽化物，取代金屬薄膜的沉積方法。 3_藉由調整離子植入條件中的能量和劑量，可以得到 最佳的金屬矽化物厚度和源/汲極區接合深度。 4.沒有金屬移除製程，因而閘極到源/汲極區的電流遺 漏會減小。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） (請先閲讀背面之注意事項再填寫本頁)1T 3 123twf.doc 3 123twf.doc Printed by A7 B7 of the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention ((,) Depending on the conditions of the process, the junction / source junction depth can be determined by planting The input energy and subsequent Thermal Budget control, and the residual damage caused by ion implantation in the source / drain region will also be reduced in the development of metal silicide. According to the above-mentioned preferred embodiment of the present invention, it can be known that the application The invention has the following advantages: 1. Shallow trench isolation technology with elevated surface can make the device avoid the neck knot effect, and replace the conventional stacked pad by the pattern of the stacked gate oxide layer / first polycrystalline silicon layer to define the component Oxide layer / silicon nitride layer. 2. Self-aligned metal silicide formed on the top of the gate and source / drain regions by ion implantation instead of the metal thin film deposition method. 3_ By adjusting the ion implantation conditions In the energy and dose, the best metal silicide thickness and source / drain region junction depth can be obtained. 4. There is no metal removal process, so the current leakage from the gate to the source / drain region will be reduced. Although this Invention has been The preferred embodiment is disclosed above, but it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be It is subject to the definition of the scope of patent application attached hereto. This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) (Please read the precautions on the back before filling this page)